TLIN1029ADRQ1 [TI]
TLIN1029A-Q1 Fault Protected LIN Transceiver with Dominant State Timeout;
| 型号： | TLIN1029ADRQ1 |
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TEXAS INSTRUMENTS |
| 描述： | TLIN1029A-Q1 Fault Protected LIN Transceiver with Dominant State Timeout |
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TLIN1029A-Q1
SLLSFK8 – DECEMBER 2020
TLIN1029A-Q1 Fault Protected LIN Transceiver with Dominant State Timeout
1 Features
2 Applications
•
AEC-Q100 (Grade 1) Qualified for automotive
applications
Compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A
and ISO/DIS 17987–4 electrical physical layer
(EPL) specification
•
•
•
•
•
Body electronics and lighting
Infotainment and cluster
Hybrid electric vehicles and power train systems
Passive safety
Appliances
•
•
Conforms to SAE J2602-1 LIN network for vehicle
applications
3 Description
•
•
•
•
Supports 12 V applications
The TLIN1029A-Q1 is a local interconnect network
(LIN) physical layer transceiver with integrated wake-
up and protection features, compliant with LIN 2.0,
LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4
standards. LIN is a single-wire bidirectional bus
typically used for in-vehicle networks using data rates
up to 20 kbps. The TLIN1029A-Q1 is designed to
support 12-V applications with wider operating voltage
and additional bus-fault protection.
LIN transmit data rate up to 20-kbps
LIN receive data rate up to 100 kbps
Wide operational supply voltage range from 4-V to
36-V
Sleep mode: ultra-low current consumption allows
wake-up event from:
•
– LIN bus
– Local wake up through EN
Power up and down glitch free operation on LIN
bus and RXD output
The LIN receiver supports data rates up to 100 kbps
for faster in-line programming. The TLIN1029A-Q1
converts the data stream on the TXD input into a LIN
bus signal using a current-limited wave-shaping driver
which reduces electromagnetic emissions (EME). The
receiver converts the data stream to logic level signals
that are sent to the microprocessor through the open-
drain RXD pin. Ultra-low current consumption is
possible using the sleep mode which allows wake-up
via LIN bus or EN pin.
•
•
Protection features:
– ±45-V LIN bus fault tolerant
– Under voltage protection on VSUP
– TXD Dominant time out protection (DTO)
– Thermal shutdown protection
– Unpowered node or ground disconnection
failsafe at system level.
•
Available in SOIC (8) and leadless VSON (8) with
wettable flanks
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
4.90 mm x 3.91 mm
3.00 mm x 3.00 mm
SOIC (D) (8)(2)
TLIN1029A-Q1
VSON (DRB) (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Product preview
VBAT
VSUP
VBAT
VSUP
VREG
VSUP
VREG
VSUP
VDD
VDD
VSUP
Commander
Node
Pullup
VDD
VDD
VSUP
NC NC
EN
8
3
7
2
VDD
NC
8
I/O
NC
3
EN
MCU w/o
pullup
I/O
2
7
VDD
MCU w/o
pullup
VDD I/O
LIN
LIN Bus
MCU
6
VDD I/O
1 kΩ
LIN Bus
MCU
LIN
LIN Controller
or
SCI/UART
1
4
6
220 pF
RXD
TXD
LIN Controller
Or
SCU/UART
1
4
220 pF
RXD
TXD
GND
5
GND
5
Simplified Schematics, Responder Mode(2)
Simplified Schematics, Commander Mode(1)
1. Commander represents industry norm 'master'.
2. Responder represents industry norm 'slave'.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLIN1029A-Q1
SLLSFK8 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 ESD Ratings - IEC ..................................................... 4
7.4 Thermal Information ...................................................4
7.5 Recommended Operating Conditions ........................5
7.6 Electrical Characteristics ............................................5
7.7 Duty Cycle Characteristics .........................................7
7.8 Switching Characteristics ...........................................9
7.9 Typical Characteristics..............................................10
8 Parameter Measurement Information..........................12
9 Detailed Description......................................................20
9.1 Overview...................................................................20
9.2 Functional Block Diagram.........................................20
9.3 Feature Description...................................................21
9.4 Device Functional Modes..........................................24
10 Application Information Disclaimer...........................26
10.1 Application Information........................................... 26
10.2 Typical Application.................................................. 26
11 Power Supply Recommendations..............................28
12 Layout...........................................................................29
12.1 Layout Guidelines................................................... 29
12.2 Layout Example...................................................... 30
13 Device and Documentation Support..........................31
13.1 Documentation Support.......................................... 31
13.2 Receiving Notification of Documentation Updates..31
13.3 Support Resources................................................. 31
13.4 Trademarks.............................................................31
13.5 Electrostatic Discharge Caution..............................32
13.6 Glossary..................................................................32
14 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
December 2020
REVISION
NOTES
*
Initial Release
5 Description (continued)
The TLIN1029A-Q1 integrates a resistor for LIN responder node applications, ESD protection, and fault
protection which allow for a reduced amount of external components in the applications. The device prevents
back-feed current through LIN to the supply input in case of a ground shift or supply voltage disconnection. The
TLIN1029A-Q1 also includes undervoltage detection, temperature shutdown protection, and loss-of-ground
protection.
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6 Pin Configuration and Functions
RXD
EN
1
2
3
4
8
7
6
5
NC
RXD
EN
1
2
3
4
8
7
6
5
NC
VSUP
LIN
V
SUP
Thermal
Pad
NC
NC
LIN
TXD
GND
TXD
GND
Not to scale
Not to scale
Figure 6-1. D Package, 8-Pin (SOIC), Top View
Figure 6-2. DRB Package, 8-Pin (VSON), Top View
Table 6-1. Pin Functions
PIN
Type
DESCRIPTION
Name
RXD
No.
1
DO
DI
RXD output (open-drain) interface reporting state of LIN bus voltage
EN
2
Enable input - High puts the device in normal operation mode and low puts the device in sleep mode
NC
3
–
Not connected
TXD
GND
LIN
4
DI
TXD input interface to control state of LIN output - Internally pulled to ground
5
GND
HV I/O
Ground
6
LIN bus single-wire transmitter and receiver
VSUP
NC
7
HV Supply Device supply voltage (connected to battery in series with external reverse blocking diode)
8
–
-
Not connected
Thermal Pad
Can be connected to the PCB ground plane to improve thermal coupling (DRB package only)
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7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
Symbol
Parameter
MIN
–0.3
–45
MAX
45
45
6
UNIT
VSUP
VLIN
Supply voltage range (ISO 17987)
LIN bus input voltage (ISO 17987)
Logic pin voltage (RXD, TXD, EN)
Digital pin output current
V
V
VLOGIC
IO
–0.3
V
8
mA
°C
TJ
Junction temperature range
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to ground terminal.
7.2 ESD Ratings
ESD Ratings
VALUE
UNIT
Human body model (HBM) classification level 3A: TXD, RXD,
EN Pins, per AEC Q100-002(1)
±4000
Human body model (HBM) classification level 3B: LIN and VSUP
Pin with respect to ground
±8000
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM)
classification level C5, per AEC All terminals
Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings - IEC
ESD and Surge Protection Ratings
VALUE
UNIT
IEC 62228-2 per ISO 10605
Contact discharge
R = 330 Ω, C = 150 pF
Electrostatic discharge, LIN, VSUP to
GND(1)
V(ESD)
±8000
V
Pulse 1
Pulse 2
Pulse 3a
Pulse 3b
–100
75
V
V
V
V
ISO 7637-2 and IEC 62228-2 per IEC
62215-3 transients according to IBEE LIN
EMC test specifications(2) (LIN , VSUP to
GND )
VTRAN
–150
100
(1) Results given here are specific to the IEC 62228-2 Integrated circuits – EMC evaluation of transceivers – Part 2: LIN transceivers.
Testing performed by OEM approved independent 3rd party, EMC report available upon request.
(2) ISO 7637 is a system level transient test. Different system level configurations may lead to diffrent results
7.4 Thermal Information
TLIN1029AD-Q1
D (SOIC)
8-PINS
115.5
TLIN1029ADRB-Q1
THERMAL METRIC(1)
DRB (VSON)
8-PINS
48.5
UNIT
RΘJA
RΘJC(top)
RΘJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
58.7
55.5
58.9
22.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
14.1
1.2
ΨJB
58.2
22.2
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7.4 Thermal Information (continued)
TLIN1029AD-Q1
D (SOIC)
TLIN1029ADRB-Q1
THERMAL METRIC(1)
DRB (VSON)
8-PINS
4.8
UNIT
8-PINS
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Recommended Operating Conditions
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER - DEFINITION
MIN
4
NOM
MAX
36
UNIT
V
VSUP
VLIN
Supply voltage
LIN Bus input voltage
0
36
V
VLOGIC
TA
Logic Pin Voltage (RXD, TXD, EN)
Ambient temperature range
Thermal shutdown temperature
Thermal shutdown hysteresis
0
5.25
125
V
-40
165
℃
°C
°C
TSD
TSD(HYS)
15
7.6 Electrical Characteristics
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4
TYP
MAX UNIT
Power Supply
Device is operational beyond the LIN
defined nominal supply voltage range
See Figure 8-1 and Figure 8-2
Operational supply voltage (ISO/DIS
17987 Param 10)
VSUP
36
36
V
V
Normal and Standby Modes: ramp VSUP
while LIN signal is a 10 kHz square
wave with 50 % duty cycle and 36V
swing. See Figure 8-1 and Figure 8-2
4
Nominal supply voltage (ISO/DIS 17987
Param 10)
VSUP
Sleep Mode
4
36
V
V
Min is falling edge and Max is rising
edge
UVSUP
UVHYS
Under voltage VSUP threshold
2.9
3.85
Delta hysteresis voltage for VSUP under
voltage threshold
0.2
1
V
Normal Mode: EN = high, bus dominant:
total bus load where RLIN > 500 Ω and
CLIN < 10 nF
5
mA
ISUP
Supply current
Standby Mode: EN = low, bus dominant:
total bus load where RLIN > 500 Ω and
CLIN < 10 nF
1
2.1
mA
Normal Mode: EN = high, bus recessive
300
10
8
650
30
µA
µA
µA
µA
(LIN = VSUP
Standby Mode: EN = low, bus recessive
(LIN = VSUP
)
)
ISUP
Supply current
Sleep Mode: 4.0 V < VSUP ≤ 14 V, LIN =
VSUP, EN = 0 V, TXD and RXD floating
12
Sleep Mode: 14 V < VSUP ≤ 36 V, LIN =
VSUP, EN = 0 V, TXD and RXD floating
20
TSD
Thermal shutdown
165
℃
℃
TSD(HYS)
Thermal shutdown hysteresis
15
RXD Output Pin (Open Drain)
VOL Output low voltage
(4)
Based upon external pull-up to VCC
0.6
V
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7.6 Electrical Characteristics (continued)
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.5
–5
TYP
MAX UNIT
IOL
Low level output current, open drain
Leakage current, high-level
LIN = 0 V, RXD = 0.4 V
LIN = VSUP, RXD = 5 V
mA
µA
IILG
0
5
TXD Input Pin
VIL
Low level input voltage
–0.3
2
0.8
5.25
5
V
V
VIH
High level input voltage
IILG
Low level input leakage current
Internal pull-down resistor value
TXD = low
–5
0
µA
kΩ
RTXD
LIN PIN
125
350
800
LIN recessive high-level output voltage TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 36
VOH
VOH
0.85
0.8
3
VSUP
VSUP
V
(3)
V
LIN recessive high-level output voltage TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 18
(1) (2)
V
LIN recessive high-level output voltage TXD = high, IO = 0 mA, 4 V ≤ VSUP < 7
VOH
(3)
V
VOL
LIN dominant low-level output voltage (3) TXD = low, 7 V ≤ VSUP ≤ 36 V
LIN dominant low-level output voltage (1)
0.2 VSUP
0.2 VSUP
VOL
TXD = low, 7 V ≤ VSUP ≤ 18 V
(2)
VOL
LIN dominant low-level output voltage (3) TXD = low, 4 V ≤ VSUP < 7 V
1.2
45
V
V
VSUP where impact of recessive LIN
TXD & RXD open LIN = 4 V to 45 V
bus < 5% (ISO/DIS 17987 Param 11)
VSUP_NON_OP
–0.3
40
Limiting current (ISO/DIS 17987 Param
TXD = 0 V, VLIN = 18 V, VSUP = 18 V
12)
IBUS_LIM
90
200
mA
mA
µA
Receiver leakage current, dominant
(ISO/DIS 17987 Param 13)
LIN = 0 V, VSUP = 12 V Driver off/
recessive Figure 8-6
IBUS_PAS_dom
IBUS_PAS_rec1
IBUS_PAS_rec2
IBUS_NO_GND
–1
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14)
LIN > VSUP, 4 V ≤ VSUP ≤ 36 V Driver
off; Figure 8-7
20
5
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14)
LIN = VSUP, Driver off; Figure 8-7
–5
–1
µA
Leakage current, loss of ground
(ISO/DIS 17987 Param 15)
GND = VSUP, VSUP = 18 V, RMeas = 1
kΩ, 0 V < VLIN < 18 V; Figure 8-8
1
mA
VSUP = 8 V, GND = open, VSUP = 18 V,
GND = open
RLeader = 1 kΩ, CL = 1 nF
RFollower = 20 kΩ, CL = 1 nF
LIN = dominant
Ileak gnd(dom)
Leakage current, loss of ground (5)
Leakage current, loss of ground (5)
-1
1
mA
VSUP = 8 V, GND = open, VSUP = 18 V,
GND = open
RLeader = 1 kΩ, CL = 1 nF
RFollower = 20 kΩ, CL = 1 nF
LIN = recessive
Ileak gnd(rec)
-100
100
5
µA
µA
Leakage current, loss of supply
(ISO/DIS 17987 Param 16)
IBUS_NO_BAT
VBUSdom
VBUSrec
LIN = 18 V, VSUP = GND; Figure 8-9
Low level input voltage (ISO/DIS 17987 LIN dominant (including LIN dominant
Param 17) (3)
for wake up) See Figure 8-4, Figure 8-3
0.4 VSUP
VSUP
High level input voltage (ISO/DIS 17987 LIN recessive See Figure 8-4, Figure
0.6
Param 18) (3)
8-3
LIN recessive high-level input voltage (1)
VIH
7 V ≤ VSUP ≤ 18 V
0.47
0.4
0.6 VSUP
0.53 VSUP
0.525 VSUP
(2)
VIL
LIN dominant low-level input voltge (1) (2) 7 V ≤ VSUP ≤ 18 V
Receiver center threshold (ISO/DIS
17987 Param 19)
VBUS_CNT = (VBUSrec + VBUSdom)/2 See
Figure 8-4, Figure 8-3
VBUS_CNT
0.475
0.5
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7.6 Electrical Characteristics (continued)
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Hysteresis voltage (ISO/DIS 17987
Param 20)
VHYS = (VBUSrec - VBUSdom) See Figure
8-4, Figure 8-3
VHYS
0.175 VSUP
VHYS = VIH - VIL See Figure 8-4, Figure
8-3
VHYS
Hysteresis voltage (SAE J2602)
0.07
0.4
0.175 VSUP
Serial diode LIN termination pull-up
path
VSERIAL_DIODE
ISERIAL_DIODE = 10 μA
0.7
45
1
V
RPU
Internal pull-up resistor to VSUP
Pull-up current source to VSUP
Capacitance of the LIN pin
Normal and standby modes
Sleep mode, VSUP = 14 V, LIN = GND
VSUP = 14 V
20
60
–2
25
kΩ
µA
pF
IRSLEEP
CLINPIN
EN Input Pin
VIL
–20
Low level input voltage
High level input voltage
Hysteresis voltage
–0.3
2
0.8
5.25
500
5
V
V
VIH
VIT
By design and characterization
EN = low
50
0
mV
µA
kΩ
IILG
Low level input current
Internal pull-down resistor
–5
REN
125
350
800
(1) SAE 2602 leader node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ
(2) SAE 2602 follower node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
(4) RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage VCC
(5) Ileak gnd = (VBAT - VLIN)/RLoad
.
7.7 Duty Cycle Characteristics
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
THREC(MAX) = 0.744 x VSUP THDOM(MAX)
= 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT
= 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
Duty Cycle 1 (ISO/DIS 17987 Param
27) (3)
D112V
0.396
THREC(MAX) = 0.625 x VSUP, THDOM(MAX)
Duty Cycle 1 (ISO/DIS 17987 Param
27) (3)
= 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT
50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
=
D112V
0.396
0.396
THREC(MAX) = 0.744 x VSUP
,
THDOM(MAX) = 0.581 x VSUP
,
D1
Duty cycle 1 (1) (2)
VSUP = 7 V to 18 V, tBIT = 52 μs
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
THREC(MIN) = 0.422 x VSUP, THDOM(MIN)
= 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT
= 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 8-10, Figure 8-11)
Duty Cycle 2 (ISO/DIS 17987 Param
28) (3)
D212V
0.581
0.581
THREC(MIN) = 0.546 x VSUP, THDOM(MIN)
= 0.4 x VSUP, VSUP = 4 V to 7 V, tBIT
=
D212V
Duty Cycle 2 (3)
50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
THREC(MIN) = 0.422 x VSUP
,
THDOM(MIN) = 0.284 x VSUP
,
D2
Duty Cycle 2 (1) (2)
VSUP = 7 V to 18 V, tBIT = 52 μs
D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
0.581
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7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
THREC(MAX) = 0.778 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT
= 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2
x tBIT) (See Figure 8-10, Figure 8-11)
Duty Cycle 3 (ISO/DIS 17987 Param
29) (3)
D312V
0.417
THREC(MAX) = 0.645 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT
96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
=
D312V
Duty Cycle 3 (3)
0.417
0.417
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 μs
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
D3
Duty Cycle 3 (1) (2)
THREC(MIN) = 0.389 x VSUP, THDOM(MIN)
= 0.251 x VSUP, VSUP = 7 V to 18 V, tBIT
= 96 µs (10.4 kbps), D4 =
tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10,
Figure 8-11)
Duty Cycle 4 (ISO/DIS 17987 Param
30) (3)
D412V
D412V
D4
0.59
0.59
0.59
THREC(MIN) = 0.422 x VSUP, THDOM(MIN)
= 0.284 x VSUP, VSUP = 4 V to 7 V, tBIT
=
Duty Cycle 4 (3)
96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 8-10, Figure 8-11)
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 μs
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
Duty Cycle 4 (1) (2)
THREC(MAX) = 0.665 x VSUP
THDOM(MAX) = 0.499 x VSUP
VSUP = 5.5 V to 7 V, tBIT = 52 μs
,
,
D1LB
D2LB
D3LB
D4LB
Duty cycle 1 at low battery (1) (2)
Duty cycle 2 at low battery (1) (2)
Duty cycle 3 at low battery (1) (2)
Duty cycle 4 at low battery (1) (2)
0.396
0.396
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 52 μs
0.581
THREC(MAX) = 0.665 x VSUP
,
THDOM(MAX) = 0.499 x VSUP
VSUP = 5.5 V to 7 V, tBIT = 96 μs
,
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 96 μs
0.581
10.8
Transmitter propagation delay timings
for
THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 52 μs
tREC(MAX)_D1 - tDOM(MIN)_D1
Tr-d max
Td-r max
Tr-d max
Td-r max
µs
µs
µs
µs
the duty cycle(1) (2)
Recessive to dominant
Transmitter propagation delay timings
for
THREC(MAX) = 0.422 x VSUP,
THDOM(MAX) = 0.284 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 52 μs
tDOM(MAX)_D2 - tREC(MIN)_D2
8.4
15.9
the duty cycle(1) (2)
Dominant to recessive
Transmitter propagation delay timings
for
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 96 μs
tREC(MAX)_D3 - tDOM(MIN)_D3
the duty cycle(1) (2)
Recessive to dominant
Transmitter propagation delay timings
for
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 96 μs
tDOM(MAX)_D4 - tREC(MIN)_D4
17.28
the duty cycle(1) (2)
Dominant to recessive
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7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Low battery transmitter propagation
delay
THREC(MAX) = 0.665 x VSUP
,
THDOM(MAX) = 0.499 x VSUP
5.5 V ≤ VSUP ≤ 7 V, tBIT = 52 μs
tREC(MAX)_low - tDOM(MIN)_low
Tr-d max_low
Td-r max_low
10.8
8.4
µs
µs
timings for the duty cycle(1) (2)
Recessive to dominant
Low battery transmitter propagation
delay
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
6.1 V ≤ VSUP ≤ 7 V, tBIT = 52 μs
tDOM(MAX)_low - tREC(MIN)_low
timings for the duty cycle(1) (2)
Dominant to recessive
(1) SAE 2602 leader node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ
(2) SAE 2602 follower node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
7.8 Switching Characteristics
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
SYMBOL
DESCRIPTION
TEST CONDITIONS
MIN
NOM
MAX UNIT
Receiver rising/falling propagation delay RRXD = 2.4 kΩ, CRXD = 20 pF
trx_pdr, trx_pdf
6
µs
µs
µs
time (ISO/DIS 17987 Param 31)
(See Figure 8-12 and Figure 8-13 )
Rising edge with respect to falling edge,
(trx_sym = trx_pdf – trx_pdr), RRXD
2.4 kΩ, CRXD = 20 pF (See Figure 8-12
and Figure 8-13 )
Symmetry of receiver propagation delay
time Receiver rising propagation delay
time
=
trs_sym
–2
25
2
LIN wakeup time (Minimum dominant
time on LIN bus for wakeup)
See Figure 8-16, Figure 9-2, and Figure
9-3
tLINBUS
65
150
Time to clear false wakeup prevention
logic if LIN bus had a bus stuck
dominant fault (recessive time on LIN
bus to clear bus stuck dominant fault)
tCLEAR
See Figure 9-3
8
20
2
25
45
50
80
15
µs
ms
µs
tDST
Dominant state time out
Time to change from standby mode to
normal mode or normal mode to sleep
mode through EN pin: (See Figure 8-14
and Figure 9-4)
tMODE_CHANGE Mode change delay time
Time for normal mode to initialize and
data on RXD pin to be valid. See Figure
8-14
tNOMINT
Normal mode initialization time
Power up time
35
µs
Upon power up time it takes for valid
data on RXD
tPWR
1.5
ms
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7.9 Typical Characteristics
40
35
30
25
20
15
10
5
1.8
1.6
1.4
1.2
1
-55°C
25°C
125°C
-55°C
25°C
125°C
0.8
0.6
0
0
5
10
15
Supply voltage (V)
20
25
30
35
40
0
5
10
15
Supply voltage (V)
20
25
30
35
40
Figure 7-1. VOH vs VSUP and Temperature
Figure 7-2. VOL vs VSUP and Temperature
2.5
2.25
2
500
450
400
350
1.75
1.5
1.25
1
-55°C
25°C
125°C
-55°C
25°C
125°C
300
250
200
150
0.75
0.5
0.25
0
5
10
15
Supply voltage (V)
20
25
30
35
40
0
5
10
15
Supply voltage (V)
20
25
30
35
40
Figure 7-3. Dominant ISUP vs VSUP and Temperature
Figure 7-4. Recessive ISUP vs VSUP and
Temperature
1
13
12
11
10
9
0.8
0.6
-55°C
25°C
125°C
-55°C
25°C
125°C
0.4
8
7
0.2
6
0
5
0
5
10
15
Supply voltage (V)
20
25
30
35
40
0
5
10
15
Supply voltage (V)
20
25
30
35
40
Figure 7-5. Standby Dominant ISUP vs VSUP and
Temperature
Figure 7-6. Standby Recessive ISUP vs VSUP and
Temperature
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13
12
11
10
9
-55°C
25°C
125°C
8
7
6
5
0
5
10
15
20
25
Supply voltage (V)
30
35
40
Figure 7-7. Sleep Current vs VSUP and Temperature
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8 Parameter Measurement Information
1
8
7
NC
RXD
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
5 V
2
VSUP
VPS
EN
NC
3
4
6
Pulse Generator
tR/tF Square Wave: < 20 ns
LIN
:
:
tR/tF Triangle Wave: < 40ns
TXD
5
GND
Frequency: 20 ppm
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8-1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
Delta t = + 5 µs
Trigger Point
(tBIT = 50 µs)
RX
2 x tBIT = 100 µs (20 kBaud)
Figure 8-2. RX Response: Operating Voltage Range
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
Figure 8-3. LIN Bus Input Signal
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1
2
3
4
8
7
NC
RXD
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
5 V
VSUP
VPS
EN
NC
6
Pulse Generator
tR/tF Square Wave: < 20 ns
LIN
:
:
tR/tF Triangle Wave: < 40ns
TXD
5
GND
Frequency: 20 ppm
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8-4. LIN Receiver Test with RX access Param 17, 18, 19, 20
1
8
7
NC
RXD
EN
Power Supply 1
Resolution: 10mV/1mA
Accuracy: 0.2%
5 V
2
VSUP
VPS1
D
Power Supply 2
Resolution: 10mV/1mA
Accuracy: 0.2%
6
5
3
4
NC
LIN
VPS2
TXD
RBUS
GND
Measurement Tools
O-scope:
DMM
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Figure 8-5. VSUP_NON_OP Param 11
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1
RXD
8
7
NC
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
2
3
VSUP
VPS
EN
NC
RMEAS = 499 Ω
6
LIN
5
4
TXD
GND
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8-6. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Param 13
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1
2
8
7
NC
RXD
EN
VPS1
VSUP
Power Supply 2
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS2
1 kΩ
6
3
4
NC
LIN
VPS2 2 V/s ramp
[8 V ‰ 36 V]
5
TXD
GND
V Drop across resistor
< 20 mV
Measurement Tools
O-scope:
DMM
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Figure 8-7. Test Circuit for IBUS_PAS_rec Param 14
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Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1
2
8
7
NC
RXD
EN
5 V
VPS1
VSUP
Power Supply 2
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS2
1 kΩ
6
5
3
4
NC
LIN
VPS2 2 V/s ramp
[0 V ‰ 36 V]
TXD
GND
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8-8. Test Circuit for IBUS_NO_GND Loss of GND
8
1
2
NC
RXD
EN
5 V
7
VSUP
Power Supply 2
Resolution: 10mV/ 1mA
10 kΩ
6
3
4
Accuracy: 0.2%
VPS
NC
LIN
VPS 2 V/s ramp
[0 V ‰ 36 V]
5
TXD
GND
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
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Figure 8-9. Test Circuit for IBUS_NO_BAT Loss of Battery
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1
2
8
7
RXD
NC
5 V
Power Supply 1
Resolution: 10mV/1mA
Accuracy: 0.2%
VSUP
EN
NC
VPS1
RMEAS
6
3
4
Power Supply 2
Resolution: 10mV/1mA
Accuracy: 0.2%
LIN
Pulse Generator
tR/tF Square Wave: < 20 ns
5
:
VPS2
TXD
GND
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8-10. Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30
TBIT
D = 50%
TXD (Input)
D112: 0.744 * VSUP
D312: 0.778 * VSUP
THREC(MAX)
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
Thresholds
RX Node 1
D112: 0.581 * VSUP
D312: 0.616 * VSUP
LIN Bus
Signal
D212: 0.422 * VSUP
D412: 0.389 * VSUP
VSUP
Thresholds
RX Node 2
D212: 0.284 * VSUP
D412: 0.251 * VSUP
tBUS_REC(MIN)
tBUS_DOM(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
Figure 8-11. Definition of Bus Timing Parameters
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VCC
2.4 kΩ
1
2
8
7
RXD
EN
NC
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
5 V
20 pF
VSUP
VPS
6
3
4
Pulse Generator
tR/tF Square Wave: < 20 ns
NC
LIN
:
:
tR/tF Triangle Wave: < 40ns
5
TXD
GND
Frequency: 20 ppm
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8-12. Propagation Delay Test Circuit; Param 31, 32
D1: 0.744 * VSUP
D3: 0.778 * VSUP
THREC(MAX)
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
Thresholds
RX Node 1
D1: 0.581 * VSUP
D3: 0.616 * VSUP
LIN Bus
Signal
D2: 0.422 * VSUP
D4: 0.389 * VSUP
VSUP
Thresholds
RX Node 2
D2: 0.284 * VSUP
D4: 0.251 * VSUP
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
Figure 8-13. Propagation Delay
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Wake Event
tMODE_CHANGE
EN
tMODE_CHANGE
tNOMINT
Transition
Sleep
Standby
Transition
Normal
Normal
MODE
Indetermin
ate Ignore
Mirrors
Bus
Wake Request
RXD = Low
RXD
Floating
Indeterminate Ignore
Mirrors Bus
Figure 8-14. Mode Transitions
EN
Weak Internal Pulldown
TXD
Weak Internal Pulldown
VSUP
LIN
RXD
Floating
Sleep
MODE
Normal
Figure 8-15. Wakeup Through EN
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0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
tLINBUS
TXD
Weak Internal Pulldown
EN
Floating
Sleep
RXD
MODE
Standby
Normal
Figure 8-16. Wakeup through LIN
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9 Detailed Description
9.1 Overview
The TLIN1029A-Q1 is a Local Interconnect Network (LIN) physical layer transceiver, compliant with LIN 2.0, LIN
2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 standards, with integrated wake-up and protection features. The
LIN bus is a single-wire bidirectional bus typically used for low speed in-vehicle networks. The device transmitter
supports data rates from 2.4-kbps to 20-kbps and the receiver works up to 100 kbps supporting in-line
programming. The LIN protocol data stream on the TXD input is converted by the TLIN1029A-Q1 into a LIN bus
signal using a current-limited wave-shaping driver as outlined by the LIN physical layer specification. The
receiver converts the data stream to logic-level signals that are sent to the microprocessor through the open-
drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage
near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a
series diode. No external pull-up components are required for responder node applications. commander node
applications require an external pull-up resistor (1 kΩ) plus a series diode per the LIN specification.
The device is designed to support 12-V applications with a wide input voltage operating range and also supports
low-power sleep mode. The device also provides two methods to wake up: EN pin and from the LIN bus.
The TLIN1029A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required
external components in the applications. In the event of a ground shift or supply voltage disconnection, the
device prevents back-feed current through LIN to the supply input. The device also includes undervoltage
detection, temperature shutdown protection, and loss-of-ground protection.
9.2 Functional Block Diagram
NC
RXD
VSUP/2
VSUP
Comp
45 kΩ
Filter
EN
NC
Wake Up
State & Control
350 kꢀ
Fault Detection
& Protection
LIN
DR/ Slope CTL
TXD
350 kꢀ
GND
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9.3 Feature Description
9.3.1 LIN (Local Interconnect Network) Bus
This high voltage input/output pin is a single-wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 45 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking
diodes, even in the event of a ground shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low-
side transistor with internal current limitation and thermal shutdown. During a thermal shut-down condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to
VSUP, so no external pull-up components are required for the LIN responder node applications. An external pull-
up resistor and series diode to VSUP must be added when the device is used for a commander node application.
9.3.1.2 LIN Receiver Characteristics
The receiver’s characteristic thresholds are proportional to the device supply pin in accordance to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the TLIN1029A-Q1 to be used for high speed downloads at the end-of-line production
or other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pull-up resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN responder node applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP
must be added when the device is used for commander node applications as per the LIN specification.
Figure 9-1 shows a commander node configuration and how the voltage levels are defined
Voltage drop across the
diodes in the pullup path
Simplified Transceiver
VSUP/2
VLIN_Bus
RXD
VSUP
VSUP
VBattery
VSUP
VLIN_Recessive
Receiver
Filter
1 kΩ
45 kΩ
LIN
Bus
LIN
TXD
350 kΩ
GND
Transmitter
with slope control
VLIN_Dominant
t
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. Commander Node Configuration with Voltage Levels
9.3.2 TXD (Transmit Input and Output)
TXD is the interface to the MCU’s LIN protocol controller or SCI and UART that is used to control the state of the
LIN output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is
recessive (near VBattery). See Figure 9-1. The TXD input structure is compatible with microcontrollers with 3.3 V
and 5 V I/O.
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9.3.3 RXD (Receive Output)
RXD is the interface to the MCU’s LIN protocol controller or SCI and UART, which reports the state of the LIN
bus voltage. LIN recessive (near VBattery) is represented by a high level on the RXD and LIN dominant (near
ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.
This allows the device to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller’s RXD pin does
not have an integrated pull-up, an external pull-up resistor to the microcontroller I/O supply voltage is required. In
standby mode the RXD pin is driven low to indicate a wake up request from the LIN bus.
9.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse-blocking diode
(Figure 9-1). If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin,
which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered
(ignition supplied) while the rest of the network remains powered (battery supplied).
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage, as well as ensuring the input and output
voltages are within their appropriate thresholds. If there is a loss of ground at the ECU level, the device has
extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in
which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered
(battery supplied).
9.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep
mode and there are no transmission paths available. The device can enter normal mode only after wake up. EN
has an internal pull-down resistor to ensure the device remains in low-power mode even if EN floats.
9.3.7 Protection Features
The TLIN1029A-Q1 has several protection features that will now be described.
9.3.8 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the
LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the
tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the device fails to a
known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no
change of stated request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and the LIN bus
pull-up termination remains on.
9.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout
The TLIN1029A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from
waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.
If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears” the bus stuck
dominant, preventing excessive current consumption. Figure 9-2 and Figure 9-3 show the behavior of this
protection.
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RXD
EN
LIN Bus
tLINBUS
< tLINBUS
< tLINBUS
Figure 9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
RXD
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
Figure 9-3. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
9.3.10 Thermal Shutdown
The LIN transmitter is protected by current limiting circuitry; however, if the junction temperature of the device
exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the
over-temperature fault condition has been removed and the junction temperature has cooled beyond the
hysteresis temperature, the transmitter is re-enabled, assuming the device remained in the normal operation
mode. During this fault, the transceiver remains in normal mode (assuming no change of state request on EN),
the transmitter is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains
on.
9.3.11 Under Voltage on VSUP
The TLIN1029A-Q1 contains a power-on reset circuit to avoid false bus messages during under voltage
conditions when VSUP is less than UVSUP
.
9.3.12 Unpowered Device and LIN Bus
In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remain powered by the battery. The TLIN1029A-Q1 has extremely low unpowered leakage current from
the bus so an unpowered node does not affect the network or load it down.
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9.4 Device Functional Modes
The TLIN1029A-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections will
describe these modes as well as how the device moves between the different modes. Figure 9-4 graphically
shows the relationship while Table 9-1 shows the state of pins.
Table 9-1. Operating Modes
LIN BUS
TERMINATION
MODE
Sleep
EN
Low
Low
RXD
Floating
Low
TRANSMITTER
COMMENT
Weak current pull-up
Off
Off
Wake-up event detected,
waiting on MCU to set EN
Standby
45 kΩ (typical)
45 kΩ (typical)
LIN bus
data
Normal
High
On
LIN transmission up to 20 kbps
Unpowered System
VSUP < UVSUP
VSUP < UVSUP
VSUP > UVSUP
EN = Low
VSUP < UVSUP
VSUP > UVSUP
EN = High
VSUP < UVSUP
Standby Mode
Driver: Off
RXD: Low
Termination: 45 kΩ
EN = High
LIN Bus Wake up
Normal Mode
Sleep Mode
Driver: On
RXD: LIN Bus Data
Termination: 45 kΩ
Driver: Off
RXD: Floating
Termination: Weak pull-up
EN = Low
EN = High
Copyright © 2017, Texas Instruments Incorporated
Figure 9-4. Operating State Diagram
9.4.1 Normal Mode
If the EN pin is high at power up, the device will power up in normal mode. If the EN pin is low, it will power up in
standby mode. The EN pin controls the mode of the device. In normal operational mode the receiver and
transmitter are active and the LIN transmission up to the LIN specified maximum of 20 kbps is supported. The
receiver detects the data stream on the LIN bus and outputs it on RXD for the LIN controller. A recessive signal
on the LIN bus is a logic high and a dominant signal on the LIN bus is a logic low. The driver transmits input data
from TXD to the LIN bus. Normal mode is entered as EN transitions high while the TLIN1029A-Q1 is in sleep or
standby mode for > tMODE_CHANGE plus tNOMINT
.
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9.4.2 Sleep Mode
Sleep mode is the power saving mode for the TLIN1029A-Q1. Sleep mode is only entered when the EN pin is
low and from normal mode. Even with extremely low current consumption in this mode, the TLIN1029A-Q1 can
still wake up from LIN bus through a wake-up signal or if EN is set high for ≥ tMODE_CHANGE. The LIN bus is
filtered to prevent false wake up events. The wake-up events must be active for the respective time periods
(tLINBUS).
The sleep mode is entered by setting EN low for longer than tMODE_CHANGE
While the device is in sleep mode, the following conditions exist:
.
•
The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events
in case an external connection to the LIN bus is lost.
•
•
The normal receiver is disabled.
EN input and LIN wake up receiver are active.
9.4.3 Standby Mode
This mode is entered whenever a wake up event occurs through LIN bus while the device is in sleep mode. The
LIN bus responder mode termination circuit is turned on when standby mode is entered. Standby mode is
signaled through a low level on RXD. See Section 10.2.2.2 for more application information.
When EN is set high for longer than tMODE_CHANGE while the device is in standby mode, the device returns to
normal mode. The normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
9.4.4 Wake Up Events
There are two ways to wake up from sleep mode:
•
Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN
bus where the dominant state is be held for tLINBUS filter time. After this tLINBUS filter time has been met and a
rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake up event,
eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
•
Local wake up through EN being set high for longer than tMODE_CHANGE
.
9.4.4.1 Wake Up Request (RXD)
When the TLIN1029A-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device
transitions to standby mode until EN is reasserted high and the device enters normal mode. Once the device
enters normal mode, the RXD pin releases the wake up request signal and the RXD pin then reflects the
receiver output from the LIN bus.
9.4.4.2 Mode Transitions
When the TLIN1029A-Q1 is transitioning from normal to sleep or standby modes the device needs the time
tMODE_CHANGE to allow the change to fully propagate from the EN pin through the device into the new state.
When transitioning from sleep or standby to normal mode the device needs tMODE_CHANGE plus tNOMINT
.
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10 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TLIN1029A-Q1 can be used as both a responder node device and a commander node device in a LIN
network. The device comes with the ability to support both remote wake up request and local wake up request.
10.2 Typical Application
The device integrates a 45 kΩ pull-up resistor and series diode for responder node applications. For commander
applications an external 1 kΩ pull-up resistor with series blocking diode can be used. Figure 10-1 shows the
device being used in both commander mode and responder mode applications.
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VSUP
COMMANDER
NODE
VREG
VSUP
VDD
VDD
VSUP
NC
8
NC
3
EN
I/O
2
7
VDD
Commander
Node
MCU w/o
pullup(2)
Pullup(3)
VDD I/O
1 kΩ
MCU
LIN
TLIN1029A-Q1
6
LIN Controller
Or
1
4
220 pF
RXD
TXD
SCU/UART(1)
GND
5
VSUP
RESPONDER
NODE
VREG
VSUP
VDD
VDD
VSUP
NC
8
NC
3
EN
7
I/O
2
VDD
MCU w/o
pullup(2)
VDD I/O
LIN
MCU
TLIN1029A-Q1
6
LIN Controller
Or
1
4
220 pF
RXD
TXD
SCU/UART(1)
GND
5
A. If RXD on MCU on LIN responder node has internal pullup; no external pullup resistor is needed.
B. If RXD on MCU or LIN responder node does not have an internal pullup requires external pullup resistor.
C. Commander node applications require and external 1 kΩ pullup resistor and serial diode.
D. Decoupling capacitor values on VSUP are system dependent but usually have 100 nF, 1 µF and ≥ 10 µF.
Figure 10-1. Typical LIN Bus
10.2.1 Design Requirements
The RXD output structure is an open-drain output stage. This allows the TLIN1029A-Q1 to be used with 3.3- V
and 5-V I/O processor. If the RXD pin of the processor does not have an integrated pull-up, an external pull-up
resistor to the processor I/O supply voltage is required. The select external pull-up resistor value should be
between 1 kΩ to 10 kΩ, depending on supply used (See IOL in electrical characteristics). The VSUP pin of the
device should be decoupled with a 100-nF capacitor by placing it close to the VSUP supply pin. The system
should include additional decoupling on the VSUP line as needed per the application requirements.
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10.2.2 Detailed Design Procedures
10.2.2.1 Normal Mode Application Note
When using the TLIN1029A-Q1 in systems which are monitoring the RXD pin for a wake up request, special
care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition
period between states as the receivers are switched. The application software should not look for an edge on the
RXD pin indicating a wake up request until tMODE_CHANGE. This is shown in Figure 8-14
10.2.2.2 Standby Mode Application Note
If the TLIN1029A-Q1 detects an under voltage on VSUP the RXD pin transitions low and would signal to the
software that the TLIN1029A-Q1 is in standby mode and should be returned to sleep mode for the lowest power
state.
10.2.3 Application Curves
The below figures show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive
and recessive to dominant edges. Device was configured in commander mode with external pull-up resistor (1
kΩ) and 680 pF bus capacitance.
Figure 10-2. Recessive to Dominant Propagation
Figure 10-3. Dominant to Recessive Propagation
11 Power Supply Recommendations
The TLIN1029A-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V
to 36 V. A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible. It is
good practice for some applications with noisier supplies to include 1 µF and 10 µF decoupling capacitor, as
well.
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12 Layout
In order for your PCB design to be successful, start with design of the protection and filtering circuitry. Because
ESD transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout
techniques must be applied during PCB design. Placement at the connector also prevents these noisy events
from propagating further into the PCB and system.
12.1 Layout Guidelines
•
Pin 1 (RXD): The pin is an open-drain output and requires an external pull-up resistor in the range of 1 kΩ to
10 kΩ to function properly. Note that the minimum value will depend on the VIO supply used. See IOL in
electrical specifications. If the microprocessor paired with the transceiver does not have an integrated pull-up,
an external resistor should be placed between RXD and the regulated voltage supply for the microprocessor.
•
Pin 2 (EN): EN is an input pin that is used to place the device in a low-power sleep mode. If this feature is not
used the pin should be pulled high to the regulated voltage supply of the microprocessor through a series
resistor between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit current on
the digital lines in the case of an over voltage fault.
•
•
Pin 3 (NC): Not Connected.
Pin 4 (TXD): The TXD pin is used to transmit the input signal from the microcontroller. A series resistor can
be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to filter noise.
•
•
Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
Pin 6 (LIN): This pin connects to the LIN bus. For responder mode applications a 220 pF capacitor to ground
is implemented. For commander mode applications an additional series resistor and blocking diode should be
placed between the LIN pin and the VSUP pin. See Figure 10-1.
•
•
Pin 7 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
Pin 8 (NC): Not Connected.
Note
All ground and power connections should be made as short as possible and use at least two vias to
minimize the total loop inductance.
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12.2 Layout Example
VDD
RXD
1
2
NC
8
7
RXD
U1
VDD
VSUP
R2
EN
EN
VSUP
C3
GND
D1
LIN
Only needed for
the commander
node
3
5
6
NC
LIN
GND
GND
GND
5
TXD
GND
TXD
R6
GND
Figure 12-1. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•
LIN Standards:
– ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
– ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
– SAEJ2602-1: LIN Network for Vehicle Applications
– LIN Specifications LIN 2.0, LIN 2.1, LIN 2.2 and LIN 2.2A
EMC requirements:
•
– SAEJ2962-1: Communication Transceivers Qualification Requirements - LIN
– ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
– ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
– ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
– ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
– IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz -
Part 4: Direct RF power injection method
– IEC 61000-4-2
– IEC 61967-4
– CISPR25
•
•
Conformance Test requirements:
– ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
– SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLIN1029ADRBRQ1
ACTIVE
SON
DRB
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
(TL029, TL029A)
TLIN1029ADRQ1
PREVIEW
ACTIVE
SOIC
SON
D
8
8
2500 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
(TL029, TL029A)
(TL029, TL029A)
TLIN1029AMDRBRQ1
DRB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLIN1029ADRBRQ1
TLIN1029AMDRBRQ1
SON
SON
DRB
DRB
8
8
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLIN1029ADRBRQ1
TLIN1029AMDRBRQ1
SON
SON
DRB
DRB
8
8
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
0.26
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
C
SYMM
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
(1.65)
8X (0.6)
8X (0.31)
SYMM
1
8
6X (0.65)
SYMM
9
(1.95) (2.4)
(0.95)
(R0.05) TYP
4
5
(Ø 0.2) VIA
TYP
(0.575)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225036/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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TLIN1039DDFRQ1
具有显性状态超时故障保护功能的局域互联网络 (LIN) 收发器 | DDF | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN1431-Q1
适用于具有集成 VREG 和看门狗的 12V 系统的汽车 LIN SBCWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN14313RGYRQ1
适用于具有集成 VREG 和看门狗的 12V 系统的汽车 LIN SBC | RGY | 20 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN14315RGYRQ1
适用于具有集成 VREG 和看门狗的 12V 系统的汽车 LIN SBC | RGY | 20 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN1441-Q1
具有集成电压稳压器和看门狗的汽车本地互联网络收发器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN14413DMTRQ1
具有集成电压稳压器和看门狗的汽车本地互联网络收发器 | DMT | 14 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN14413DMTTQ1
具有集成电压稳压器和看门狗的汽车本地互联网络收发器 | DMT | 14 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN14415DMTRQ1
具有集成电压稳压器和看门狗的汽车本地互联网络收发器 | DMT | 14 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN14415DMTTQ1
具有集成电压稳压器和看门狗的汽车本地互联网络收发器 | DMT | 14 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLIN2021A-Q1
具有抑制和唤醒功能的汽车类故障保护 LIN 收发器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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