TLIN14313RGYRQ1_技术文档

TLIN1431-Q1

ZHCSQ68A –MAY 2022 –REVISED DECEMBER 2022

带集成高侧开关和看门狗的TLIN1431-Q1 汽车类LIN SBC

1 特性

2 应用

• AEC-Q100（等级1）：符合汽车应用要求

• 功能安全型

• 车身电子装置和照明

• 混合动力、电动和动力总成系统

• 信息娱乐系统与仪表组

• 电器

– 可提供用于功能安全系统设计的文档

• 符合本地互连网络(LIN) 物理层规范LIN 2.2A、

ISO 17987–4:2016 和SAE J2602:2021 要求

• 由引脚或串行外设接口SPI 配置的集成看门狗监控

器

3 说明

TLIN1431x-Q1 是一款本地互联网络 (LIN) 系统基础芯

片(SBC)，集成了看门狗、高侧开关、跛行回家功能和

高度可配置的 WAKE 输入引脚。该器件在上电时自行

确定控制方法、引脚或串行外设接口 (SPI)。看门狗默

认为适合两种控制方法的窗口看门狗，但为了实现灵活

性，在使用 SPI 控制时，可以将器件配置为具有超过

20 个不同时间窗口的窗口看门狗或超时看门狗。

• 支持12V 应用的增强功能

– ±58V LIN 总线故障保护

– 采用12V 电源供电时支持125mA 电流的3.3V

(TLIN14313-Q1) 或5V (TLIN14315-Q1) LDO

输出

– 开路负载和短路检测由10 位PWM 或计时器控

制的高侧开关

– 可配置为高侧开关的LIMP 引脚

– 支持不同输入阈值或方法的可配置WAKE 引脚

– 睡眠模式：超低电流消耗支持以下类型的唤醒事

件：

LIN 收发器为终端编程提供 200 kbps 快速模式。为板

载 LED 提供带诊断功能的高侧开关。高度可配置的

WAKE 引脚可与高侧开关一同使用，以实现循环检

测，从而降低 ECU 睡眠电流。可为数字唤醒输出

(WKRQ) 配置 WKRQ/INH 引脚，或为外部电源配置基

于VSUP 的抑制(INH) 使能引脚。

• LIN 总线

• 通过WAKE 引脚实施的本地唤醒

器件信息

封装⁽¹⁾

– 循环和静态感测

• 保护特性：

封装尺寸（标称值）

器件型号

TLIN1431x-Q1

VQFN (RGY)(20)

4.50mm x 3.50mm

– ESD 保护

– V_SUP和V_CC欠压保护

– TXD 显性超时(DTO) 保护

– 热关断保护

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 集成式电池电压监测器

• 采用无引线QFN (20) 封装，具有改善的自动光学

检测(AOI) 功能

空白

V_BAT

V_SUP

470

V_SUP

100 nF

V_DD

For INH on WKRQ/INH pin leave

floating or

1

M

pull-down

V_SUP

100 nF

3

k

10 µF

V_DD33

SW

V_CC

V_BAT

V_DD

V_SUP

100 nF

10 µF

3

SW

k

3.3

k

V_CC

V

WAKE

B

A

T

S

U

P

V_DD

10 nF

V_DD

3.3

k

10

k

LIMP

HSS

WAKE

LIMP

10

k

nRST

10 nF

nRST

DIV_ON

PV

WKRQ

100

k

20 pF

MCU

I/O

WDT can be connect to GND,

VCC or left floating depending

upon watchdog window timing

requirements

HSS

nCS

CLK

WKRQ

WDT

SDI

SDO

nINT

FSO

MCU

100

k

Responder

Node

I/O

Responder

Node

HSSC

WDI

V_SUP

DIV_ON

PV

nWDR

V_SUP

Commander

EN

Commander

Node

Pullup

Node

Pullup

20 pF

10

k

1

k

1

k

LIN

LIN Bus

LIN Controller

Or

SCI/UART

LIN

LIN Bus

RXD

TXD

LIN Controller

Or

SCI/UART

RXD

TXD

220 pF

GND

220 pF

GND

简化版原理图，SPI 控制

简化版原理图，引脚控制

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSFE4

TLIN1431-Q1

ZHCSQ68A –MAY 2022 –REVISED DECEMBER 2022

www.ti.com.cn

Table of Contents

8.2 Functional Block Diagram.........................................23

8.3 Feature Description...................................................24

8.4 Device Functional Modes..........................................49

8.5 Programming............................................................ 65

8.6 Registers...................................................................69

9 Application and Implementation..................................90

9.1 Application Information............................................. 90

9.2 Typical Application.................................................... 91

9.3 Power Supply Recommendations.............................96

9.4 Layout....................................................................... 97

10 Device and Documentation Support..........................99

10.1 Documentation Support.......................................... 99

10.2 接收文档更新通知................................................... 99

10.3 支持资源..................................................................99

10.4 商标.........................................................................99

10.5 Electrostatic Discharge Caution............................100

10.6 术语表................................................................... 100

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 ESD Ratings, IEC Specification..................................4

6.4 Recommended Operating Conditions.........................5

6.5 Thermal Information....................................................5

6.6 Power Supply Characteristics.....................................5

6.7 Electrical Characteristics.............................................7

6.8 AC Switching Characteristics....................................11

6.9 Typical Characteristics..............................................14

7 Parameter Measurement Information..........................15

7.1 Test Circuit: Diagrams and Waveforms.....................15

8 Detailed Description......................................................22

8.1 Overview...................................................................22

Information.................................................................. 100

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (May 2022) to Revision A (December 2022)

Page

• 将数据表状态从预告信息更改为量产数据.........................................................................................................1

2

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5 Pin Configuration and Functions

V_CC

nRST

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

LIMP

HSS

WDT/CLK

nWDR/SDO

WDI/SDI

WAKE

WKRQ/INH

LIN

Thermal

Pad

PIN/nCS

GND

EN/nINT

RXD

HSSC/FSO

TXD

图5-1. RGY Package, 20-Pin QFN

(Top View)

表5-1. Pin Functions

TYPE

DESCRIPTION

NAME

V_SUP

V_CC

NO.

1

I

Device supply voltage (connected to battery in series with external reverse blocking diode)

Output voltage from integrated voltage regulator

2

O

nRST

3

I/O

Reset input/output (active low)

Pin control: WDT - Programmable watchdog window set input (3 levels)

SPI control: CLK - SPI clock input

WDT/CLK

4

5

I

Pin control: nWDR - Watchdog failure output trigger

SPI control: SDO - SPI serial data output

nWDR/SDO

O

Pin control: WDI - Watchdog timer trigger input active on both rising and falling edges (Must be driven at

WDI/SDI

PIN/nCS

6

7

I

all times)

SPI control: SDI - SPI serial data input

Pin or SPI control selection pin at power up.

Pin control: does not change

SPI control: nCS - SPI chip select (active low)

Pin control: EN - Device mode change input pin

SPI control: nINT - Device interrupt output pin

EN/nINT

8

9

I/O

Pin control: HSSC - High side switch control input pin

SPI control: FSO - Function output pin

HSSC/FSO

PV

10

11

12

13

14

15

16

17

18

19

20

O

I

Internal V_BATvoltage divider output

DIV_ON

TXD

Input to turn on the internal V_BATvoltage divider, active high

TXD input interface to control state of LIN output

RXD output interface reporting state of LIN bus voltage

Ground

I

RXD

O

GND, Pad

LIN

—

I/O

O

I

LIN bus single-wire transmitter and receiver

Digital output for wake or high voltage inhibit output depending upon state of pin at power up

High voltage local wake up (LWU) pin

WKRQ/INH

WAKE

HSS

O

I

High side switch

LIMP

Used for LIMP home, watchdog event causes this pin to switch V_SUP

Supply voltage divider sense input (connected to battery)

V_BAT

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6 Specifications

6.1 Absolute Maximum Ratings

Over recommended operating range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–24

–58

–0.3

MAX

42

UNIT

V

V_SUP

V_BAT

Supply voltage range (ISO/DIS 17987)

Battery sense input

42

V

V_LIN

LIN Bus input voltage (ISO/DIS 17987)

Regulated 5 V Output Supply

Regulated 3.3 V Output Supply

WAKE pin input voltage range

58

V

V_CC50

V_CC33

V_WAKE

6

V

4.5

42

V

42 and V_O

≤V_SUP+0.3

V_HSS

High side switch pin output voltage range

Inhibit pin output voltage range

V

–0.3

42 and V_O

≤V_SUP+0.3

V_INH

42 and V_O

≤V_SUP+0.3

V_LIMP

LIMP pin output voltage range

V_nRST

Reset output voltage

Logic input voltage

V_CC+ 0.3

V

–0.3

V_{LOGIC_INPUT}

6

V_{LOGIC_OUTPUT}

Logic output voltage

Digital pin output current

Reset output current

Junction temperature

Storage temperature range

V

I_O

8

mA

°C

I_O(nRST)

5

–5

–40

–65

T_J

160

165

Storage temperature, T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum

Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under

Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the

Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability,

functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM) classification level H2: V_BAT, V_SUP, LIN, and WAKE

with respect to ground

±10000

±4000

±750

Human body model (HBM) classification level 3A: all other pins, per AEC

Q100-002⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM) classification level

All pins

C5, per AEC Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings, IEC Specification

VALUE

UNIT

Contact discharge (VSUP, WAKE, HSS, LIMP,

±8000

Electrostatic discharge per IEC 62228-2 ⁽¹⁾

V

LIN)

V_(ESD)

Indirect ESD discharge (LIN)

Contact discharge

Air discharge

Pulse 1

±14000

±8000

±25000

-100

V_(ESD)

Powered electrostatic discharge SAE J2962-1⁽³⁾

V

Pulse 2a

75

ISO 7637-2 and IEC 62215-3 Transients

according to IBEE LIN EMC test spec⁽²⁾

Transient

Pulse 3a

-150

Pulse 3b

100

4

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6.3 ESD Ratings, IEC Specification (continued)

VALUE

UNIT

Direct coupling capacitor "slow transient pulse"

with 100 nF coupling capacitor - powered

Transient

ISO 7637-3 Slow Transients Pulse ⁽⁴⁾

±30

V

(1) IEC 62228-2 ESD testing performed at third party. Different system-level configurations may lead to different results.

(2) ISO 7637-2 according to IEC 62228-2 are system-level transient tests. Different system-level configurations may lead to different

results.

(3) SAE J2962-1 Testing performed at 3rd party US3 approved EMC test facility.

(4) ISO 7637-3 is a system-level transient test. Different system-level configurations may lead to different results.

6.4 Recommended Operating Conditions

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

MIN

5.5

0

NOM

MAX

28

UNIT

V

V_SUP

Supply voltage

V_BAT

Supply voltage

28

V

V_LIN

LIN bus input voltage

28

V

V_LOGIC5

V_LOGIC33

I_OH(DO)

I_OL(DO)

I_O(LIMP)

Logic pin voltage

0

5.25

3.465

V

Logic pin voltage

0

V

Digital terminal HIGH level output current

Digital terminal LOW level output current

LIMP output current when configured as LIMP

-2

mA

2

1

High side switch output current; LIMP output current when configured as high

side switch

I_O(HSS)

100

6

mA

I_O(INH)

C_(VSUP)

C_(VCC)

ESR_CO

Δt/ΔV

T_J

Inhibit output current

mA

nF

V_SUPsupply capacitance

100

10

V_CCsupply capacitance; no load to full load

Output ESR capacitance requirements

Input transition rise and fall rate (WDI, WDT, WDR)

Operating junction temperature range

µF

0.001

2

100

150

Ω

ns/V

°C

–40

6.5 Thermal Information

TLIN1431x

THERMAL METRIC⁽¹⁾

RGY

20 PINS

37.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

32.4

15.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JT

15.7

ψ_JB

R_θJC(bot)

4.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.6 Power Supply Characteristics

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply Voltage and Current

470 Ωseries resistor with 100nF cap to

ground

V_BAT

V_BATsense pin voltage

5.5

28

V

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6.6 Power Supply Characteristics (continued)

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

470 Ωseries resistor with 100nF cap to

ground with DIV_ON high, V_BAT= 5.5 V to

28 V

I_BAT

V_BATsense pin current

220

µA

470 Ωseries resistor with 100nF cap to

ground with DIV_ON high V_BAT= –24 V

I_BATREV

V_BATsense pin reverse current

mA

V

–1

Operational supply voltage (ISO/DIS 17987 Device is operational beyond the LIN

V_SUP

5.5

36

Param 10)

defined nominal supply voltage range

Normal⁽²⁾and Standby Modes

Sleep Mode

5.5

4.7

4

28

V

Nominal supply voltage (ISO/DIS 17987

Param 10):

V_SUP

UV_SUPR

UV_SUPF

Under voltage V_SUPthreshold

Ramp Up

5.3

4.6

Ramp Down

Delta hysteresis voltage for V_SUPunder

voltage threshold

U_VHYS

0.70

V

V_SUPpower on reset release rising

threshold

V_nPORR

V_nPORF

Ramp Up

3.5

1.9

4.2

2.9

V

V_SUPpower on reset falling threshold

Ramp down

Transceiver normal mode dominant plus

LDO output; where LDO load current is 125

mA

I_SUP

Transceiver and LDO supply current

135

5.2

mA

Normal Mode: EN = V_CC(Pin control mode

otherwise SPI enabled), bus dominant: total

2.3

1

bus load where R_LIN≥500 Ω and C_LIN

10 nF, LDO = no load

≤

I_SUPTRXDOM

Supply current

Standby Mode: EN = 0 V (Pin control mode

otherwise SPI disabled), bus dominant: total

1.9

mA

bus load where R_LIN≥500 Ω and C_LIN

10 nF, LDO = no load

≤

Normal Mode: EN = V_CC

Bus recessive: LIN = V_SUP, LDO = no load

,

I_SUPTRXREC

Normal mode recessive supply current

Standby mode recessive supply current

0.9

1.3

mA

µA

Standby Mode: EN = 0 V (Pin control mode

otherwise SPI disabled), LIN = recessive =

V_SUP, LDO = no load

I_SUPTRXREC

210

350

5.5 V < V_SUP≤14 V, LIN = V_SUP, WAKE =

GND, EN = 0 V (Pin control mode otherwise

SPI disabled), TXD and RXD floating, LDO

= no load

20

25

32

µA

I_SUPTRXSLP

Sleep mode supply current

14 V < V_SUP≤28 V, LIN = V_SUP, WAKE

=

_GND, EN = 0 V (Pin control mode

36

110

95

µA

otherwise SPI disabled), TXD and RXD

floating, LDO = no load

Additional standby mode current from high

side switch, no load.

I_SUPHSS

High side switch current - no load

WKRQ/INH current due to pull-down

Additional standby mode current due to the

pull-down resister on the WKRQ/INH pin to

determine pin function, 100 kΩ for WKRQ or

1 MΩ for INH.

I_{SUPWKRQ_INH}

Regulated Output V_CC

V_CC

Regulated output

V_SUP= 5.5 to 28 V, I_CC= 1 to 125 mA

V_SUP= 5.5 to 28 V, ΔV_CC, I_CC= 10 mA

I_CC= 1 to 125 mA, V_SUP= 14 V, ΔV_CC

-2.5

2.5

50

%

Line regulation

mV

∆V_CC(∆VSUP)

∆V_CC(∆VSUPL)

V_DROP1

Load regulation

50

Dropout voltage (5 V LDO output)

100

550

150

650

V

_SUP–V_CC, I_CC= 15 mA

_SUP–V_CC, I_CC= 125 mA

V_DROP2

V

V_CCshort circuit threshold to enter sleep

mode

V_SC

2

2.5

4.9

V

_SUP≥V_POR

UV_CC5R

UV_CC5F

UV_CC33R

Under voltage 5 V V_CCthreshold

Under voltage 3.3 V V_CCthreshold

Ramp Up

4.7

4.45

2.9

V

Ramp Down

Ramp Up

4.1

3.1

6

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6.6 Power Supply Characteristics (continued)

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

2.75

5.6

MAX

6.0

UNIT

V

UV_CC33F

OV_CC5R

OV_CC5F

OV_CC33R

OV_CC33F

I_CCOUT

Under voltage 3.3 V V_CCthreshold

Over voltage 5 V VCC threshold ⁽¹⁾

Over voltage 3.3 V VCC threshold ⁽¹⁾

Output current

Ramp Down

Ramp Up

2.5

V

Ramp Down

Ramp Up

5.28

5.5

V

3.79

3.73

3.98

V

Ramp Down

3.58

1

V

V_CCin regulation with 14V V_SUP

V_CCshort to ground

125

275

mA

I_CCOUTL

Output current limit

V_RIP= 0.5 V_PP, Load = 10 mA, ƒ= 100 Hz,

CO = 10 μF, V_SUP= 12 V and ambient

temperature = 27 ℃

PSRR

Power supply rejection ripple rejection ⁽¹⁾

60

15

dB

T_SDR

Thermal shutdown temperature ⁽¹⁾

Thermal shutdown hysteresis ⁽¹⁾

Internal junction temperature; rising

Internal junction temperature; falling

V_SUP= 12 V

160

150

185

170

°C

T_SDF

T_SDHYS

(1) Specified by design

(2) Normal Mode: Ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and 18 V swing.

6.7 Electrical Characteristics

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

0.8

TYP

MAX

UNIT

RXD Output Terminal

V_OH

High level output voltage

Low level output voltage

Unpowered leakage current

V_CC

µA

I_O= –2 mA, V_CC= Active

V_OL

I_O= 2 mA, V_CC= Active

0.2

1

I_LKG(OFF)

Outputs = 5.25/3.465 V, V_CC= V_SUP= 0 V

–1

TXD Input Terminal

V_IL

Low level input voltage

0.8

5.5

5

V

–0.3

2

V_IH

I_IH

High level input voltage

High level input leakage current

Internal pull-up resistor value

TXD = V_IH

0

µA

kΩ

–5

125

R_TXD

350

800

LIN Terminal (Referenced to V_SUP

)

LIN recessive, TXD = high, I_O= 0 mA, V_SUP

= 5.5 V to 28 V

V_OH

HIGH level output voltage⁽⁵⁾

LOW level output voltage⁽⁵⁾

0.85

V_SUP

V

LIN dominant, TXD = low, V_SUP= 5.5 V to

28 V

V_OL

0.2

45

V_SUPwhere impact of recessive LIN bus < 5%

(ISO/DIS 17987 Param 11)

V_{SUP_NON_OP}

TXD & RXD open V_LIN= 5.5 V to 45 V

–0.3

40

TXD = 0 V, V_LIN= 28 V, R_MEAS= 440 Ω,

V_SUP= 28 V,

I _{BUS_LIM}

Limiting current (ISO/DIS 17987 Param 12)

90

200

mA

V

_BUSdom≤0.251 * V_SUP

V_LIN= 0 V, V_SUP= 12 V Driver off/recessive

_LIN≥V_SUP, 5.5 V ≤V_SUP≤28 V Driver

Receiver leakage current, dominant (ISO/DIS

17987 Param 13)

I _{BUS_PAS_dom}

I _{BUS_PAS_rec1}

I _{BUS_PAS_rec2}

I _{BUS_NO_GND}

I_{BUS_NO_BAT}

V_BUSdom

mA

µA

–1

Receiver leakage current, recessive (ISO/DIS

17987 Param 14)

V

20

5

off

Receiver leakage current, recessive (ISO/DIS

17987 Param 14)

V_LIN= V_SUP, Driver off

µA

–5

–1

Leakage current, loss of ground (ISO/DIS 17987

Param 15)

GND = V_SUP, V_SUP= 12 V, 0 V ≤V_LIN≤28

V

1

mA

µA

Leakage current, loss of supply (ISO/DIS 17987

Param 16)

10

0.4

0 V ≤V_LIN≤28 V, V_SUP= GND

LIN dominant (including LIN dominant for

wake up); 图7-2

Low level input voltage (ISO/DIS 17987 Param

17)

V_SUP

High level input voltage (ISO/DIS 17987 Param

18)

V_BUSrec

0.6

LIN recessive; 图7-2

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6.7 Electrical Characteristics (continued)

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Receiver center threshold (ISO/DIS 17987 Param

19)

V_{BUS_CNT}

V_HYS

V_{SERIAL_DIODE}

R_LIN

0.475

0.5

0.525

V_SUP

V_{BUS_CNT}= (V_IL+ V_IH)/2; 图7-2

Hysteresis voltage (ISO/DIS 17987 Param 20)⁽⁶⁾

0.175

1.0

V_SUP

V

V_HYS= (V_IL- V_IH); 图7-2

(7)

Serial diode LIN term pull-up path (ISO/DIS

17987 Param 21)

By design and characterization

Normal and Standby modes

0.4

0.7

45

Internal pull-up resistor to V_SUPon LIN (ISO/DIS

17987 Param 26)

20

60

kΩ

I_RSLEEP

Pull-up current source to V_SUP

Capacitance of the LIN pin

Sleep mode, V_SUP= 12 V, LIN = GND

By design and characterization

µA

pF

–20

–2

C_LIN,PIN

25

EN Input Terminal

V_IH

V_IL

High level input voltage

Low level input voltage

Hysteresis voltage

2

5.5

0.8

500

8

V

V_HYS

I_IL

By design and characterization

EN = Low

30

–8

125

mV

µA

Low level input current

Internal pull-down resistor

R_EN

350

800

kΩ

LIMP Output Terminal (High Voltage Open-drain Output)

Hi-level voltage drop for LIMP with respect to

V_SUP

0.42

7

1.2

V

ΔV_H

I_LIMP= –60 mA

R_dson

LIMP output drain-to-source on resistance

Leakage current

20

1

I_O= –60 mA

Ω

I_LKG(LIMP)

LIMP = 0 V, Sleep Mode

µA

–1

HSS, INH high voltage open drain output pin

V_{DET_INH}

ΔV_HINH

ΔV_HHSS

R_dson

Voltage on INH/WKRQ pin during t_{DET_INH}time

VSUP = 14V

1.5

1

V

Hi-level voltage drop for INH with respect to V_SUP

Hi-level voltage drop for HSS with respect to V_SUP

HSS output drain-to-source on resistance

Output current support

0.5

0.42

7

I_INH= –6 mA

1.2

17

I_HSS= –60 mA

I_O= –60 mA

Ω

I_O(HSS)

VSUP = 14 V,

60

100

300

mA

µA

I_OC(HSS)

I_OL(HSS)

I_OLHYS(HSS)

I_lkg

HSS overcurrent limit

VSUP = 14 V

150

–2.5

0.05

–1

HSS open load current

VSUP = 14 V

HSS open load current hysteresis

Leakage current

VSUP = 14 V

0.45

1

INH, HSS = 0 V, Sleep Mode

5.5 V ≤V_SUP≤28 V, I_LOAD= 60 mA, R_L

220 Ω, 80%/20%

=

t_R/F

Output rise and fall times (HSS)

0.6

2.5

60

V/µs

µs

Switching on delay (HSS) from SPI command to V_SUP= 14 V, I_LOAD= 60 mA, V_OUT= 80% of

on V_SUP

t_{HSS_on}

t_{HSS_off}

Switching off delay (HSS) from SPI command to V_SUP= 14 V, I_LOAD= 60 mA, V_OUT= 20% of

140

µs

off

V_SUP

t_OCFLTR

t_OLFLTR

t_OCOFF

HSS overcurrent filter time⁽²⁾

HSS open load filter time⁽²⁾

HSS overcurrent shut off time

V_SUP= 14 V

I_O(HSS)> I_OC(HSS)

16

64

µs

200

4

300

WAKE Input Terminal

V_IH

V_IL

I_IL

High-level input voltage

Sleep or Standby Mode, WAKE pin enabled

WAKE = 1 V

V

Low-level input voltage

2

Low-level input leakage current

15

25

µA

Wake up hold time from a wake edge on WAKE in

standby or sleep mode for static sensing..

t_WAKE

140

µs

See 图8-44 and 图8-45

WAKE pin pulses shorter than this will be filtered

out in standby or sleep mode for static and cyclic

sensing.

t_{WAKE_INVALID}

10

WDI, SDI, CLK, nCS Input Terminal

V_IH

V_IL

High-level input voltage

Low-level input voltage

2.19

V

0.8

8

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6.7 Electrical Characteristics (continued)

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–1

TYP

MAX

UNIT

µA

I_IH

High-level input leakage current

Low-level input leakage current

Input Capacitance

Inputs = V_CC

1

I_IL

Inputs = 0 V, V_CC= Active

4 MHz

µA

–50

C_IN

10

15

1

pF

I_LKG(OFF)

R_{WDI_SDIpu}

R_CLKpu

R_nCSpu

Unpowered leakage current

Inputs = 5.25/3.465 V, V_CC= V_SUP= 0 V

µA

–1

100

Internal pull-up resistor on WDI/SDI pin

Internal pull-up resistor on WDT/CLK pin

Internal pull-up resistor on PIN/nCS pin

240

400

kΩ

SPI control only for CLK

SPI control only for nCS

WDT Input Terminal

V_IH

High-level input voltage

Inputs = V_CC

0.8

V_CC

µA

V_IL

Low-level input voltage

Inputs = V_CC

0.2

0.6

V_IM(WDT)

I_IH

WDT Mid-level input voltage⁽¹⁾

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

Inputs = V_CC

0.4

2.5

0.5

Inputs = V_CC

25

I_IL

Inputs = 0 V, V_CC= Active

Inputs = 5.25/3.465 V, V_CC= V_SUP= 0 V

µA

–25

–3

–2.5

3

I_LKG(OFF)

µA

SDO Output Terminal

V_OH

High level output voltage

0.8

–1

–5

V_CC

µA

I_O= –2 mA, V_CC= Active

V_OL

Low level output voltage

I_O= 2 mA, V_CC= Active

0.2

1

I_LKG(OFF)

Unpowered leakage current

Outputs = 5.25/3.465 V, V_CC= V_SUP= 0 V

nRST Terminal; input/output reset (Open-drain)

I_LKG

V_OL

Leakage current, high-level

Low-level output voltage

Low-level output current, open drain

Switching threshold voltage

Pull-up resistance

LIN = V_SUP, nRST = V_CC

5

µA

V_CC

mA

V_CC

kΩ

Based upon external pull up to V_CC

LIN = 0 V, nRST = 0.4 V

0.2

I_OL

1.5

0.25

30

V_th(sw)

R_PU

nINT, nWDR, WKRQ Terminal

0.75

65

45

V_OH

V_OL

High level output voltage

0.8

V_CC

I_O= –2 mA, V_CC= Active

Low-level output voltage

I_O= 2 mA, V_CC= Active

0.2

1

Unpowered leakage current (nINT and nWDR

pins)

I_LKG(OFF)

Outputs = 5.25/3.465 V, V_CC= V_SUP= 0 V

µA

–1

HSSC

V_IH

High-level input voltage

Low-level input voltage

Low-level input current

Pull-down resistor

2

5.5

0.8

1

V

V_IL

I_IL

V_IN= 0 V

µA

–1

R_HSSC

f_SW

150

350

800

400

kΩ

Switching frequency

V_HSS= 14 V, I_O(HSS)= 60 mA

Hz

WDI, WDT TIMING and SWITCHING CHARACTERISTIC (RL = 1 MΩ, CL = 50 pF and T_J= -40°C to 150°C)

t_W

Filter time to avoid false input

WDT = GND

30

32

µs

ms

s

WDI pulse width; see 图7-8

40

600

6

48

720

7.2

t_WINDOW

WDT = V_CC

480

4.8

Closed Window + Open Window; See 图7-8

WDT = Floating

DIV_ON

V_IH

High-level input voltage

Low-level input voltage

Low-level input current

Pull-down resistor

2

5.5

0.8

1

V

V_IL

I_IL

V_{DIV_ON}= 0 V

µA

–1

R_{DIV_ON}

PV

150

370

800

kΩ

Ratio

Divider ratio 5 V VCC

Divider ratio 3.3 V VCC

V_BAT= 5.5 V to 28 V

V_BAT= 5.5 V to 20 V

1:7

1:9

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6.7 Electrical Characteristics (continued)

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERR

Divider ratio error

V_BAT= 5.5 V to 28 V

2

%

–2

R_LOAD= 470 Ω± 5% and C_LOAD= 10 nF ±

10%; When capacitive load only 20 pF ±

20%, 5.5 V ≤V_BAT≤28 V

V_BATLIN5

Linear voltage range for V_BATfor 5 V LDO ⁽³⁾

0.735

0.561

4.05

2.27

5.1

V

R_LOAD= 470 Ω± 5% and C_LOAD= 10 nF ±

10%; When capacitive load only 20 pF ±

20%, 5.5 V ≤V_BAT≤20 V

Linear voltage range for V_BATfor 3.3 V LDO and

when I/O is 3.3 V with 5 V LDO ⁽⁴⁾

V_BATLIN3

28 V < V_BAT≤42 V, 470 Ω± 5% and

C_LOAD= 10 nF ± 10%; When capacitive

load only 20 pF ± 20%

V_MAX5V

Maximum V_PVOUT

20 V < V_BAT≤42 V, 470 Ω± 5% and

C_LOAD= 10 nF ± 10%; When capacitive

load only 20 pF ± 20%

Maximum V_PVOUTfor 3.3 V LDO and when I/O is

3.3 V with 5 V LDO

V_MAX3.3V

3.36

R_LOAD= 470 Ω± 5% and C_LOAD= 10 nF ±

10%; When capacitive load only 20 pF ±

20% and I/O voltage is ≤3.6 V

V_{VCC5V_VIO3V}

Voltage when VCC = 5 V and I/O is at 3.3 V

C_PIN

t_SET

Pin capacitance

12

pF

µs

470 Ω± 5% and C_LOAD= 10 nF ± 10%;

When capacitive load only 20 pF ± 20%

Settling time of the buffer

50

Duty Cycle Characteristics

TH_REC(MAX)= 0.744 x V_SUP

,

TH_DOM(MAX)= 0.581 x V_SUP

,

Duty Cycle 1 (ISO/DIS 17987 Param 27 and

V_SUP= 7 V to 18 V, t_BIT= 50/52 µs,

D1 = t_{BUS_rec(min)}/(2 x t_BIT) (See 图7-3, 图

7-4)

D1

0.396

J2602 Normal battery)^{(8) (9)}

TH_REC(MIN)= 0.422 x V_SUP

,

TH_DOM(MIN)= 0.284 x V_SUP, V_SUP= 7.6 V to

18 V,

Duty Cycle 2 (ISO/DIS 17987 Param 28 and

J2602 Normal battery)^{(8) (9)}

D2

D3

D4

0.581

t_BIT= 50/52 µs, D2 = t_{BUS_rec(MAX)}/(2 x t_BIT

)

(See 图7-3, 图7-4)

TH_REC(MAX)= 0.778 x V_SUP, TH_DOM(MAX)

=

0.616 x V_SUP, V_SUP= 7.0 V to 18 V, t_BIT= 96

µs, D3 = t_{BUS_rec(min)}/(2 x t_BIT) (See 图7-3,

图7-4)

Duty Cycle 3 (ISO/DIS 17987 Param 29 and

J2602 Normal battery)^{(8) (9)}

0.417

TH_REC(MIN)= 0.389 x V_SUP

,

TH_DOM(MIN)= 0.251 x V_SUP

,

Duty Cycle 4 (ISO/DIS 17987 Param 30 and

J2602 Normal battery)^{(8) (9)}

V_SUP= 7.6 V to 18 V, t_BIT= 96 µs,

D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See 图7-3, 图

7-4)

0.59

TH_REC(MAX)= 0.665 x V_SUP, TH_DOM(MAX)

0.499 x V_SUP, V_SUP= 5.5 V to 7 V, t_BIT

50/52 µs, D1 = t_{BUS_rec(min)/(2 x tBIT)}(See 图

7-3, 图7-4)

=

Duty Cycle 1

D1_LB

D2_LB

D3_LB

D4_LB

0.396

J2602 Low battery^{(9) (10)}

TH_REC(MIN)= 0.496 x V_SUP, TH_DOM(MIN)

=

0.361 x V_SUP, V_SUP= 6.1 V to 7.6 V, t_BIT

50/52 µs, D2 = t_{BUS_rec(MAX})/(2 x t_BIT) (See

图7-3, 图7-4)

=

Duty Cycle 2

0.581

J2602 Lowl battery^{(9) (10)}

TH_REC(MAX)= 0.665 x V_SUP, TH_DOM(MAX)

=

0.499 x V_SUP, V_SUP= 5.5 V to 7 V, t_BIT= 96

µs, D1 = t_{BUS_rec(min)/(2 x tBIT)}(See 图7-3, 图

7-4)

Duty Cycle 3

0.417

J2602 Low battery^{(9) (10)}

TH_REC(MIN)= 0.496 x V_SUP, TH_DOM(MIN)

=

0.361 x V_SUP, V_SUP= 6.1 V to 7.6 V, t_BIT

96 µs, D2 = t_{BUS_rec(MAX})/(2 x t_BIT) (See 图

7-3, 图7-4)

=

Duty Cycle 4

0.59

J2602 Lowl battery^{(9) (10)}

(1) This is the measured voltage at the WDT pin when left floating. The WDT pin should be connected directly to V_CC, GND or left floating.

(2) Specified by design

(3) V_BATLIN5= [(1/7) * V_BAT] +/- 50 mV for the linear range of the PV buffer

(4) V_BATLIN3= [(1/9) * V_BAT] +/- 50 mV for the linear range of the PV buffer

(5) SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ and for a responder node: 5.5 nF; 875 Ω

(6) V_HYSis defined for both ISO 17987 and SAE J2602-1.

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(7) V_HYS= (V_{th_rec}- V_{th_dom}) where V_{th_rec}and V_{th_dom}are the actual voltage values from V_BUSrecand V_BUSdom

(8) ISO 17987 loads include 1 nF; 1 kΩ/ 6.8nF; 660 Ω/ 10 nF; 500 Ω; with t_BITvalues of 50 µs and 96 µs

(9) SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ/ 899 pF; 20 kΩ and for a responder node: 5.5 nF; 875 Ω/ 899 pF; 900 Ω;

with t_BITvalues of 52 µs and 96 µs

(10) ISO 17987 does not have a low battery specification. Using the ISO 17987 loads these low battery duty cycle parameters are covered

for t_BITvalues of 50 µs and 96 µs

6.8 AC Switching Characteristics

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Device Switching Characteristics

t_{rx_pdr}

t_{rx_pdf}

Receiver rising/falling propagation delay time

(ISO/DIS 17987 Param 31)

R_RXD= 2.4 kΩ, C_RXD= 20 pF (See 图7-3,

图7-4)

6

2

µs

Rising edge with respect to falling edge,

Symmetry of receiver propagation delay time

Receiver rising propagation delay time (ISO/DIS (t_{rx_sym}= t_{rx_pdf}–t_{rx_pdr}), R_RXD= 2.4 kΩ,

17987 Param 32)

t_{rs_sym}

–2

C_RXD= 20 pF (See 图7-3, 图7-4)

LIN wakeup time (minimum dominant time on

LIN bus for wakeup)

t_LINBUS

25

100

45

150

See 图7-6, 图8-11 and 图8-12

Time to clear false wakeup prevention logic if

LIN bus had a bus stuck dominant fault

(recessive time on LIN bus to clear bus stuck

dominant fault)

t_CLEAR

10

60

µs

See 图8-12

t_{TXD_DTO}

t_EN

Dominant state time out

20

3

80

12

ms

µs

Time enable pin state change before

initiating mode change or sampling TXD

Enable pin deglitch time

Time to change from normal mode to sleep

mode through EN pin: See 图7-5

t_{MODE_CHANGE}

t_DETECT

Mode change delay time

100

2

µs

Time to detect Pin vs SPI and I/O voltage level

at power up⁽¹⁾

Time from coming out of UV_CCand device

determines these states

Time to detect which output INH or WKRQ at

power up

Time from coming out of UV_CCand device

determines these states

t_{DET_INH}

25

Time for normal mode to initialize and data

on RXD pin to be valid, includes

t_{MODE_CHANGE}for standby mode to normal

mode See 图7-5

t_NOMINIT

Normal mode initialization time

45

µs

Time required for V_CC≥UV_CCto leave Restart

mode

t_{RSTN_act}

t_nRSTIN

1.5

2

2.5

ms

µs

V

_CC≥UV_CC

Input pulse required on the nRST pin to

recognize a device reset.

120

reg 29h[5] = 0 (Default value in SPI

control. Value in pin control except for

watchdog failure.)

1.5

10

2

2.5

20

ms

t_{NRST_TOG}

nRST pin output toggle high to low to high time

reg 29h[5] = 1 (Value in pin control for

watchdog failure.)

15

Initial long watchdog window time required to

t_INITWD

trigger first watchdog input trigger when entering WDI input trigger or SPI write command

Standby mode or Normal mode

150

200

Timer for inactivity coming out of sleep mode

Default values and can be programmed to

and when coming out of failsafe mode to

different values in SPI control.

t_{INACT_FS}

4

5

6

min

determine if caused event has been cleared ⁽¹⁾

Time from V_SUPexceeding UV_SUPuntil INH

active

V_CC> UV_CC, INH = V_SUP, V_CCload of 50

mA @ 22 µF capacitance

3

ms

t_PWRUP

Time from V_SUPexceeding UV_{SUP and}V_CC

exceeding UV_CCuntil WKRQ active

V_CC> UV_CC, WKRQ = V_CC, V_CCload of 50

mA @ 22 µF capacitance

t_TOGGLE

t_UVFLTR

t_VSC

RXD pulse width when waking from sleep mode register 'h12[2] = 1

Undervoltage detection delay time for V_CC

5

3

15

4

µs

ms

µs

Short to ground on VCC detection delay time

75

100

130

Time LDO is on to determine if a short circuit

event is present after a previous uncleared

detection

t_LDOON

2

3

ms

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6.8 AC Switching Characteristics (continued)

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Standby to normal mode change time based

upon SPI write

t_{MODE_STBY_NOM}

70

µs

Time from SPI sleep command where LIN

transceiver is off and RXD doesn't reflect

the LIN bus

t_{MODE_NOM_SLP}

t_{MODE_NOM_STBY}

t_{WKRQ_SLP}

SPI write to go to sleep from normal

200

70

µs

SPI write to go to standby from normal mode

Dependent upon LDO turning on and ramp

time. Time provided is based upon 1 µs

ramp and LDO being at 2 V.

Time WKRQ turns on after a wake event when

device is in sleep mode

450

Time INH turns on after a wake event when

device is in sleep mode

t_{INH_SLP}

210

70

µs

SPI write to go to sleep from normal mode and

INH turns off

t_{INH_NOM_SLP}

Minimum WAKE Pin pulse width Register

8'h11[3:2] = 00b; See 图8-46

10

20

40

80

ms

Minimum WAKE Pin pulse width Register

8'h11[3:2] = 01b; See 图8-46

Minimum WAKE pin pulse width (SPI mode

only) ^{(2) (3) (4)}

t_{WK_WIDTH_MIN}

Minimum WAKE Pin pulse width Register

8'h11[3:2] = 10b; See 图8-46

Minimum WAKE Pin pulse width Register

8'h11[3:2] = 11b; See 图8-46

Maximum WAKE Pin pulse width that is

considered invalid Register 8'h11[3:2] =

00b; See 图8-46

5

10

20

40

ms

Maximum WAKE Pin pulse width that is

considered invalid Register 8'h113:2] =

01b; See 图8-46

Maximum Pulse width that is considered invalid

(SPI mode only) ^{(2) (3)}

t_{WK_WIDTH_INVALID}

Maximum WAKE Pin pulse width that is

considered invalid Register 8'h11[3:2] =

10b; See 图8-46

Maximum WAKE Pin pulse width that is

considered invalid Register 8'h11[3:2] =

11b; See 图8-46

Maximum WAKE Pin pulse window

Register 8'h11[1:0] = 00b; See 图8-46

750

1000

1500

2000

950

1250

1875

2500

ms

Maximum WAKE Pin pulse window

Register 8'h11[1:0] = 01b; See 图8-46

Maximum WAKE pin pulse width to be

considered valid (SPI mode only) ⁽²⁾

t_{WK_WIDTH_MAX}

Maximum WAKE Pin pulse window

Register 8'h11[1:0] = 10b; See 图8-46

Maximum WAKE Pin pulse window

Register 8'h11[1:0] = 11b; See 图8-46

Register 8'h12[5] = 0

Register 8'h12[5] = 1

10

60

30

75

40

90

µs

Sampling window for cyclic sensing wake;

Standby or Sleep mode; see 图8-49

t_{WK_CYC}

Fast Mode

5.5 V ≤V_SUP≤18 V, R_LIN= 500 Ωand

C_LIN(bus)= 600 pF

DR

Data Rate

200

5

kbps

µs

t_{rx_pdr}

t_{rx_pdf}

Receiver rising/falling propagation delay time

(ISO/DIS 17987 Param 31)

R_RXD= 2.4 kΩ, C_RXD= 20 pF (See 图7-3,

图7-4

5.5 V ≤V_SUP≤18 V, R_LIN= 500 Ωand

C_LIN(bus)= 600 pF, 80%/20%

t_txr/f

LIN transmitter rise and fall time

1.5

110

25

µs

Fast mode determination time for entering or

leaving

t_{FM_CHANGE}

t_FMTXD

Based upon EN and TXD voltage levels

70

5

90

Pulse must start after t_ENand finish before

t_{FM_CHANGE}

TXD pin pulse width to enter fast mode

SPI Switching Characteristics

f_SCK

SCK, SPI clock frequency ⁽¹⁾

t_SCK

SCK, SPI clock period ⁽¹⁾

4

MHz

ns

250

See 图7-7

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6.8 AC Switching Characteristics (continued)

parameters valid over –40℃≤T_J≤150 ℃range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

40

UNIT

ns

t_RSCK

t_FSCK

t_SCKH

t_SCKL

t_ACC

t_CSS

t_CSH

t_CSD

t_SISU

t_SIH

SCK rise time ⁽¹⁾

See 图7-7

SCK fall time ⁽¹⁾

40

SCK, SPI clock high ⁽¹⁾

SCK, SPI clock low ⁽¹⁾

First read access time from chip select ⁽¹⁾

Chip select setup time ⁽¹⁾

Chip select hold time ⁽¹⁾

Chip select disable time ⁽¹⁾

Data in setup time ⁽¹⁾

Data in hold time ⁽¹⁾

125

50

100

50

t_SOV

t_RSO

t_FSO

Data out valid ⁽¹⁾

80

40

SO rise time ⁽¹⁾

SO fall time ⁽¹⁾

(1) Specified by design

(2) This parameter is valid only when register 11h[7:6] = 11b

(3) This is the minimum pulse width for a WAKE pin input that device will detect as a good pulse. Values between the min t_{WK_WIDTH_MIN}

and max t_{WK_WIDTH_INVALID}is indeterminant and may or may not be considered valid.

(4) This parameter is set based upon the programmed value for t_{WK_WIDTH_INVALID}register 11h[3:2]

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6.9 Typical Characteristics

3.5

3

140

120

100

80

2.5

2

1.5

1

60

–40°C

25°C

50°C

85°C

105°C

125°C

–40°C

40

25°C

50°C

85°C

105°C

125°C

0.5

0

20

-0.5

0

5

10

15

20

V_SUP(V)

25

30

35

40

0

5

10

15

20

V_SUP(V)

25

30

35

40

V_CC= 3.3 V I_CC= 125 mA load

Temperature =

Ambient

V_CC= 3.3 V I_CC= 125 mA load

Temperature =

Ambient

Mode = Power up

to Standby

LIN = Recessive

Mode = Power up

to Standby

LIN = Recessive

图6-1. TLIN14313RGYQ1 V_CCversus V_SUPRamping Up

图6-2. TLIN14313RGYQ1 I_SUPversus V_SUPRamping Up

120

5.5

5

–40°C

25°C

50°C

85°C

105°C

100

4.5

4

125°C

80

3.5

3

60

40

20

0

2.5

2

–40°C

25°C

50°C

1.5

1

85°C

105°C

125°C

150°C

0.5

0

-20

-0.5

0

3

6

9

12

15

18

21

24

27

30

0

5

10

15

20

25

30

35

40

V_SUP(V)

V_CC= Off

I_CC= Off

Temperature =

Ambient

V_CC= 5 V I_CC= 125 mA load

Temperature =

Ambient

Mode = Sleep

LIN = Recessive

Mode = Power up

to Standby

LIN = Recessive

图6-3. TLIN14313RGYQ1 I_SUPversus V_SUPRamping Down

图6-4. TLIN14315RGYQ1 V_CCversus V_SUPRamping Up

35

140

120

100

80

30

25

20

15

60

10

25°C

50°C

85°C

105°C

125°C

40

20

0

–40°C

25°C

50°C

85°C

105°C

125°C

5

0

-5

0

5

10

15

20

25

30

35

40

0

3

6

9

12

15

18

21

24

27

30

V_SUP(V)

V_CC= 5 V I_CC= 125 mA load

Temperature =

Ambient

V_CC= Off

I_CC= Off

Temperature =

Ambient

Mode = Power up

to Standby

LIN = Recessive

Mode = Sleep

LIN = Recessive

图6-6. TLIN14315RGYQ1 I_SUPversus V_SUPRamping Down

图6-5. TLIN14315RGYQ1 I_SUPversus V_SUPRamping Up

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7 Parameter Measurement Information

7.1 Test Circuit: Diagrams and Waveforms

Delta t = + 5 µs (t_BIT

Trigger Point

= 50 µs)

RX

2 * t_BIT= 100 µs (20 kBaud)

图7-1. RX Response: Operating Voltage Range

Period T = 1/f

Amplitude

(signal range)

LIN Bus Input

Frequency: f = 20 Hz

Symmetry: 50%

图7-2. LIN Bus Input Signal

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t_BIT

RECESSIVE

D = 0.5

TXD (Input)

DOMINANT

TH_REC(MAX)

Thresholds

RX Node 1

TH_DOM(MAX)

LIN Bus

Signal

V_SUP

TH_REC(MIN)

Thresholds

RX Node 2

TH_DOM(MIN)

t_{BUS_REC(MIN)}

t_{BUS_DOM(MAX)}

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

D = t_{BUS_REC(MIN)}/(2 x t_BIT

)

t_{BUS_DOM(MIN)}

t_{BUS_REC(MAX)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

D = t_{BUS_REC(MAX)}/(2 x t_BIT

)

图7-3. Definition of Bus Timing

TH_REC(MAX)

TH_DOM(MAX)

TH_REC(MIN)

TH_DOM(MIN)

Thresholds

RX Node 1

LIN Bus

Signal

V_SUP

Thresholds

RX Node 2

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

t_{rx_pdr(1)}

t_{rx_pdf(1)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

t_{rx_pdr(2)}

t_{rx_pdf(2)}

图7-4. Propagation Delay

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t_{MODE_CHANGE}

Wake Event

t_{MODE_CHANGE}

t_NOMINT

t_EN

EN

t_EN

Can be high or low

TXD

V

_CC> UV_CC

t_{RSTN_act}

EN

Restart

VCC LDO turned on and

ramping

Filter/TXD

Sampling

Window

Enable

Filter

Transi on

Sleep

Standby

Transi on

Normal

MODE

Can be high or low

TXD

EN

Filter/TXD

Sampling

Window

Enable

Filter

Transi on

Standby

Transi on

Normal

MODE

High from normal

mode un l wake event

then low

ꢀꢁFloa ng for sleep

ꢀꢁHigh for standby ꢁ

Wake Request

RXD = Low

Mirrors

Bus

RXD

Indeterminate Ignore

Mirrors Bus

图7-5. Mode Transitions (Pin Control)

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0.6 x V_SUP

LIN

0.6 x V_SUP

V_SUP

0.4 x V_SUP

t < t_LINBUS

t_LINBUS

TXD

RXD

Weak Internal Pullup

Floa ng

t_TOGGLE

Floa ng

RXD

V_CC

UV_CC

nRST

t_{RSTN_act}

MODE

Restart

Sleep

Standby

图7-6. Wakeup through LIN

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t_CSD

nCS

t_CSH

t_FSCK

t_RSCK

t_CSS

CLK

SDI

t_SISU

t_SIH

LSB In

MSB In

t_SOV

t_ACC

t_FSO

t_RSO

SDO

MSB Out

LSB Out

图7-7. SPI AC Characteristic for Read and Write

Watchdog Window

Closed Window

Open Window

t_WDOUTmin

Watchdog Window

Closed Window

Open Window

t_WDOUTmax

t_WINDOWmin

t_WINDOWmax

Safe Trigger area

t_W

WDI state change

or SPI write

t_W- filter time for the input

WDI Trigger

Rising or Falling

Edge

to be recognized to avoid

false triggers

Standby

Mode

t_INITWD

图7-8. Watchdog Window Timing Diagram

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High

V_SUP

Normal to

Sleep CMD

SPI Mode

Change

High

V_SUP– 1V

INH

t_{INH_NOM_SLP}

V_CCoff and ramp time are

system dependent and

not specified

UV_CC

V_CC

nRST

Normal

Mode

Sleep Mode

Mode

NOM SLP

t_{MODE_NOM_SLP}

Transceiver

图7-9. Normal to Sleep via SPI

High

V_SUP

SPI Mode

Change

Normal to

Standby CMD

High

WKRQ/INH

High

V_CC

Mode

Standby Mode

Normal Mode

NOM STBY

t_{MODE_NOM_STBY}

Transceiver

图7-10. Normal to Standby via SPI

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High

V_SUP

Wake Event

WUP or LWU

t_{INH_SLP}

High

V_SUP– 1V

INH

WKRQ

WKRQ/INH

t_{WKRQ_SLP}is dependent upon LDO ramp

times which are system dependent

t_{WKRQ_SLP}

V_CCon and ramp time are system

dependent and not specified

V_CC

nRST

Mode

RXD

V_CC≥ UV_CC

t_LDOON

t_{RSTN_act}

Sleep

Mode

Restart

Mode

Standby

Mode

RXD floating

图7-11. Sleep to Restart to Standby Mode from Wake Event

备注

Throughout the document timing diagrams may have three colors associated to them.

• Red are signals on device pins

• Teal represent the WKRQ pin when configured as WKRQ

• Black will represent either internal signals or an external signal that will impact device behavior

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8 Detailed Description

8.1 Overview

The TLIN1431x-Q1 LIN transceiver is a Local Interconnect Network (LIN) physical layer transceiver, compliant to

LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, ISO 17987–4:2016, and SAE J2602:2021 with integrated wake-up and

protection features. The LIN bus is a single-wire, bi-directional bus that typically is used in low speed in-vehicle

networks with data rates that range up to 20 kbps. The device LIN receiver works up to 100 kbps supporting in-

line programming in normal mode. When the device is placed into fast mode, both the transmitter and receiver

support up to 200 kbps. The device converts the LIN protocol data stream on the TXD input into a LIN bus signal

using a current-limited wave-shaping driver which reduces electromagnetic emissions (EME). The receiver

converts the data stream to logic level signals that are sent to the microprocessor through the RXD pin. The LIN

bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the

recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode.

Ultra-low current consumption is possible using the sleep mode. The TLIN1431x-Q1 provides three methods to

wake up from sleep mode: EN pin, WAKE pin and LIN bus in pin control mode and two in SPI control mode,

WAKE pin and LIN bus. The device integrates a low dropout voltage regulator with a wide input from V_SUP

providing 5 V ±2.5% or 3.3 V ±2.5% with up to 125 mA of current depending upon system implementation.

The TLIN1431x-Q1 integrates a window-based watchdog supervisor which has a programmable delay and

window ratio determined by pin strapping or SPI communication. The device watchdog is controlled by pin

configuration or SPI depending upon the state of pin 7 at power up. During power up, if pin 7 is externally pulled

to ground, the device is configured for pin control and all digital IO voltage levels will be dependent upon V_CC. If

pin 7 is left floating or pulled up to V_CCthe device is controlled by SPI communication and the pin becomes the

nCS pin. For the 5 V V_CCversion, the digital IO voltage levels are also determined during power up when the

device is configured for SPI communication control. If pin 7 is left floating at power up, the internal pull up

configures the device for 3.3 V SPI control. This means that all the digital IO for the device will be configured for

3.3 V electrical levels. If the processor needs 5 V IO, a 500 kΩpull up resistor to the TLIN14315-Q1 V_CCpin will

configure all digital IOs 5 V electrical levels. This allows the 5 V version of the device to work with both 3.3 V

processors or 5 V processors. SPI communication is used for device configuration. This sets not only the SPI

pins but also WKRQ, nRST, FSO, nINT, TXD and RXD pins. In pin configuration, nRST is asserted high when

V_CCincreases above UV_CCand stays high as long as V_CCis above this threshold and the device is not in restart

mode.

When the watchdog is controlled by the device pins, the state of the WDT pin determines the window time. WDI

is used as the watchdog input trigger which is expected in the open window. If a watchdog error event takes

place, the nWDR pin goes low to reset the processors. When using SPI writing FFh to register 15h,

WD_INPUT_TRIG, during the open window restarts the watchdog timer. The supervised processor must trigger

the WDI pin or WD_INPUT_TRIG register within the defined window. When using SPI, the nRST pin can

become the watchdog event output trigger for the processor if programmed this way, but the nRST function is

lost. The watchdog timer has a long initial window when entering standby, normal and fast modes that a

watchdog input trigger is expected.

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8.2 Functional Block Diagram

20

1

V_SUP

19

LIMP

2

V_BAT

V_CC

3.3 V or 5 V LDO

V_INT

INH

Supply Monitors and

control

WKRQ/INH

16

WKRQ

DIV_ON

11

V_CC

PV

10

+

-

SPI and Control

V_INT

HSS

18

WAKE

17

WAKE

V_INT

CRC&

SPI

CNTL

V_INT

45 k

PIN/nCS

7

PIN/nCS

WDT/CLK

WDI/SDI

CNTL

Register

nRST

3

nRST

WDT/CLK

4

WDI/SDI

6

PWM/

Timers

WDOG

nWDR/SDO

5

nWDR/SDO

Wake

CNTL

V_INT

SWE

nINT

EN/nINT

8

EN

Mode

CNTL

350 k

V_INT

HSSC

FSO

HSSC/FSO

9

350 k

V_INT

V_SUP

TRX

CNTL

GND

14

45 k

350 k

TRX

CNTL

TXD

12

V_INT

LIN TRX

LIN

15

RXD

13

图8-1. High Level Block Diagram

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V_CC

V_SUP

V_INT

5.0 V or 3.3 V LDO

V_INT

UV

CNTL POR

DET

45 k

nRST

V_INTcan be 3.3 V or

5 V and may not be

the same as V_CC

V_SUP

LIMP

V_SUP

V_SUP/2

Comp

RXD

EN_TRX

45

k

Filter

WAKE

Wake Up

State &

LIMP CTL

Fault

V_INT

LIN

Detection

& Protection

350 k

DR/

Slope

CTL

Dominant

State

Timeout

TXD

GND

图8-2. Transceiver plus VREG Functional Block Diagram

8.3 Feature Description

8.3.1 LIN (Local Interconnect Network) Bus

This high voltage input or output pin is a single wire LIN bus transmitter and receiver. The LIN pin can survive

transient voltages up to 58 V. Reverse currents from the LIN to supply (V_SUP) are minimized with blocking

diodes, even in the event of a ground shift or loss of supply (V_SUP).

8.3.1.1 LIN Transmitter Characteristics

The transmitter meets thresholds and AC parameters according to the LIN specification. The transmitter is a low

side transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the

transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to

V_SUP, so no external pull-up components are required for the LIN responder node applications. An external pull-

up resistor and series diode to V_SUPmust be added when the device is used for a commander node application.

In fast mode, the transmitter can support 200 kbps data rates.

8.3.1.2 LIN Receiver Characteristics

The receiver characteristic thresholds are ratiometric with the device supply pin according to the LIN

specification.

The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602

specifications. This allows the TLIN1431x-Q1 to be used for high speed downloads at the end-of-line production

or other applications. The actual data rate achievable depends on system time constants (bus capacitance and

pull-up resistance) and driver characteristics used in the system. In fast mode the receiver can support 200 kbps.

8.3.1.2.1 Termination

There is an internal pull-up resistor with a serial diode structure to V_SUP, so no external pull-up components are

required for the LIN responder node applications. An external pull-up resistor (1 kΩ) and a series diode to V_SUP

must be added when the device is used for commander node applications as per the LIN specification (ISO

17987-4).

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图8-3 shows a Commander Node configuration and how the voltage levels are defined.

V_BAT

Voltage drop across the

diodes in the pullup path

Simplified Transceiver

V_{LIN_Bus}

V_SUP

V_SUP/2

V_Battery

RXD

V_SUP

V_{LIN_Recessive}

Receiver

Filter

1 kꢀ

45 kΩ

LIN

Bus

V_INT

350 kꢀ

TXD

GND

Transmitter

with slope control

V_{LIN_Dominant}

t

图8-3. Commander Node Configuration with Voltage Levels

8.3.2 TXD (Transmit Input and Output)

TXD is the interface to the node processor LIN protocol controller that is used to control the state of the LIN

output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is

recessive (near V_SUP). See 图 8-3. The TXD input structure is compatible with processors with 3.3 V and 5 V

logic I/O. TXD has an internal pull-up resistor to an internal voltage rail that either matches the processor I/O

voltage rail or the LDO output rail, V_CCwhich is determined by the state of pin 7 at power up. The LIN bus is

protected from being stuck dominant through a system failure driving TXD low through the dominant state

timeout timer. The TXD pin is also used to help determine what mode to enter in pin control mode.

8.3.3 RXD (Receive Output)

RXD is the interface to the processors LIN protocol controller or SCI and UART, which reports the state of the

LIN bus voltage. LIN recessive (near V_SUP) is represented by a high level on the RXD and LIN dominant (near

ground) is represented by a low level on the RXD pin. This device architecture allows the device to be used with

3.3 V and 5 V I/O processors. The RXD pin is a push-pull buffer and as such an external pull-up is not needed.

In restart mode, the RXD pin is driven high. When V_CC> UV_CCfor t_{RSTN_act}, the device automatically transitions

to standby mode causing RXD is then pulled low to indicate a wake-up request. The RXD pin can be

programmed to toggle low or high to indicate a wake up request with a pulse width of t_TOGGLE, see 图 7-6 as an

example of this feature.

8.3.4 WAKE (High Voltage Local Wake Up Input)

WAKE pin is used for a high voltage device local wake up (LWU). This function is explained further in Local

Wake Up (LWU) via WAKE Terminal section. The pin is both rising and falling edge trigger, meaning it

recognizes a LWU on either edge of WAKE pin transition. The pin can be configured to accept a pulse, see 图

8-46 for timing diagram of this behavior. WAKE pin is also used as part of the cyclic sensing wake, see Cyclic

Sense Wake. Registers WAKE_PIN_CONFIG1 Register (Address

=

11h) [reset

=

04h] and

WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 2h] provide the various configurations for the WAKE

pin.

8.3.5 WDT or CLK (Pin Programmable Watchdog Delay Input or SPI Clock)

When configured for pin control, the WDT or CLK pin becomes the pin programmable watchdog delay input,

WDT. This pin sets the upper boundary of the window watchdog. It can be connected to V_CC, connected to GND,

or left floating. When connected directly to V_CCor GND or left open, the window frame takes on one of three

value ranges: GND – 32 ms to 48 ms, V_CC– 480 ms to 720 ms or left open – 4.8 s to 7.2 s. The closed

versus open windows are based upon 50%/50%.

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When configured for SPI control, the WDT/CLK pin becomes the SPI input clock, CLK. When configured as the

CLK pin there is a 240 kΩpull-up to V_INTenabled.

8.3.6 WDI or SDI (Watchdog Timer Input or SPI Serial Data In)

When configured for pin control, the WDI or SDI pin becomes the watchdog timer input trigger, WDI. This resets

the timer with either a positive or negative transition from the processor. A filter time of t_Wis used to avoid false

triggers.

When configured for SPI control, the WDI/SDI pin becomes the SPI serial data input pin, SDI.

8.3.7 PIN or nCS (Pin Watchdog Select or SPI Chip Select)

This pin determines if the TLIN1431x-Q1 watchdog and mode changes are controlled by pin or SPI. At power up,

the device monitors this pin and determine which method is to be used. When tied to GND, the device is pin

programmable, see 图 8-5. When connected to a high-Z processor IO pin or pulled up, the device is set up to

support SPI, see 图 8-6. In SPI control mode, if the LDO is being used to power up circuitry other than the

processor a mismatch can take place. An example of this is using the TLIN14315-Q1 V_CCto power up a 5 V

sensor and the processor supports 3.3 V IO electrical levels. This is accomplished by letting the PIN/nCS pin

float at power up which configures the internal IO electrical levels to V_INTwhich is 3.3 V. For the IO to be 5 V, an

external 500 kΩ resistor needs to be pulled up to the 5 V V_CCpin. This makes the IO 5 V. See 图 8-4 to

understand the three ways this pin can be connected for the 5 V LDO device.

备注

The behavior of the microprocessor used must be understood if connecting to this pin to control

whether the device is to be pin controlled or SPI controlled. There is an internal pull-up that sets the

device in SPI control mode. If the processor pin drives low during power up, the device is in pin control

mode. To specify pin control mode place and external pull-down resister to ground.

V_CC

(5 V)

3.3 V

5 V SPI

PIN Mode

3.3 V SPI

PIN/nCS

GND

图8-4. PIN/nCS configuration

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V_SUP

4.7 V UV_SUPR5.3 V

3.5 V V_nPORR4.2 V

nPOR

V_CC

~ 4.7 V (5 V LDO)

~ 2.9 (3.3 V LDO)

Time for VCC to > UVCC is

system dependent

t_LDOON

Control mode

determination

(pin 7)

Determined low and

pin control mode

t_DETECT

WKRQ/INH pin state

determination

WKRQ/

INH

t_{DET_INH}

V_SUP

WKRQ/INH pin state determination:

If 1 M pulled to GND then INH pin

t_PWRUP

INH

V_{DET_INH}

V_CCor V_INT

t_PWRUP

WKRQ

WKRQ/INH pin state determination: If

100k pulled to ground then WKRQ pin

V_{DET_INH}

t_{RSTN_act}

t_PWRUP

Init

Standby

Mode

Power up

Restart

t_{RSTN_act}

nRST

RXD

Off and floating

When t_LDOONtimes out the device checks the status of VCC to determine if a

short or over-voltage is present. VCC may or may not have reached regulation

图8-5. Power up timing diagram for pin 7 connected to ground

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V_SUP

4.7 V UV_SUPR5.3 V

3.5 V V_nPORR4.2 V

nPOR

> UV_CC

V_CC

~ 4.7 V (5 V LDO)

~ 2.9 (3.3 V LDO)

Time for VCC to > UVCC is

system dependent

t_LDOON

Control mode

determination

(pin 7)

Determined high and SPI mode

t_DETECT

I/O voltage

determination

(nCS pull up)

I/O voltage set to pull up value

3.3 V or 5 V

t_DETECT

WKRQ/

INH

WKRQ/INH pin state

t_{DET_INH}

V_SUP

determination

t_PWRUP

INH

WKRQ/INH pin state determination:

If 1 M pulled to GND then INH pin

V_{DET_INH}

V_CCor V_INT

t_PWRUP

WKRQ

WKRQ/INH pin state determination: If

100k pulled to ground then WKRQ pin

V_{DET_INH}

t_PWRUP

Init

t_{RSTN_act}

Standby

Mode

Power up

Restart

t_{RSTN_act}

nRST

RXD

Off and floating

When t_LDOONtimes out the device checks the status of VCC to determine if a

short or over-voltage is present. VCC may or may not have reached regulation

图8-6. Power up timing diagram for pin 7 pulled high up

8.3.8 LIMP (Limp Home Output –High Voltage Open Drain Output)

The default configuration for the LIMP pin is used for the limp home function. When in the LIMP configuration,

the pin is connected to external circuitry for a limp home function due to various fault conditions explained in the

device functional mode sections. The LIMP pin can be configured as other functions in SPI control mode, but

only performs the limp home function in pin control mode.

8.3.8.1 LIMP in Pin Control Mode

In pin control mode, LIMP is the only function the LIMP pin can perform. The LIMP pin turns on for all faults that

cause the device to enter fail-safe mode to provide the limp home function. To exit fail-safe mode, a wake event

must take place and the fault condition is cleared or the SWE timer times out. When any non-watchdog fault

caused the device to enter fail-safe mode, the LIMP pin will turn off automatically after exiting fail-safe mode.

When exiting fail-safe mode due to a watchdog fault, the LIMP pin is still on until the device transitions to

standby mode and three correct watchdog input events take place thus turning off the LIMP pin. If this first event

is missed, the device enters fail-safe.

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8.3.8.2 LIMP in SPI Control Mode

In SPI control mode, the LIMP pin defaults to the limp home function. When fail-safe mode is enabled (default

on) the pin behaves the same as stated in pin control mode with the exception of every watchdog error causing

a reset. Programming register 8'h1A[3:2], LIMP_SEL_RESET, determines the condition for the LIMP pin to turn

off. The three modes that the LIMP pin changes state is normal, fail-safe and standby mode. When in normal

and standby mode the LIMP pin is off unless there is a watchdog failure event, which turns on the LIMP pin.

When entering these two modes, there is an initial long window requiring a watchdog input trigger. This is treated

as a WD failure and LIMP pin turns on if the window is missed. Any event that causes the device to enter fail-

safe mode also turns on the LIMP pin. LIMP is turned off once the device enters standby mode from fail-safe

mode except for a watchdog error as described previously. When fail-safe mode is disabled, a WD input failure

causes the LIMP pin to turn on, and the device enters restart mode.

If the LIMP function is not needed, this pin can be configured to support either a high side switch in SPI mode by

using register 8'h1B[7:6] = 01b or to the INH function by setting register 8'h1B[7:6] = 10b. When configured as a

high side switch, the pin can support the same load as the HSS pin, but does not have the open load and over

current detection features. When used as a high side switch, timing control is configurable using on/off, PWM or

timer based. When using PWM, PWM1 or PWM2 can be assigned. When using the timer, timer1 or timer2 and

be assigned.

8.3.9 nWDR/SDO (Watchdog Timeout Reset Output/SPI Serial Data Out)

When configured for pin control, the nWDR/SDO pin becomes the watchdog reset output pin, nWDR. When the

watchdog times out, this pin goes low for time of 15 ms and then releases back to V_CC

.

When configured for SPI control, the nWDR/SDO pin becomes the SPI serial data output pin, SDO.

8.3.10 HSS (High-side Switch)

This pin supports a high-side switch supporting up to a 100 mA load with 60 mA being typical with a 14 V V_SUP

.

In SPI mode, the HSS can be programmed to support a 200 Hz or 400 Hz 10-bit PWM. PWM1 or PWM2 can be

assigned to the HSS. The HSS can be configured to use one of two timers that allows it to work with the WAKE

pin. This supports cyclic sensing for sleep mode thus reducing sleep mode current. In pin mode this pin is

controlled by the HSSC pin.

The switch supports open load detection and over current detection. When an over current is detected, there is a

filter time, t_OCFLTR, to determine if over current is valid. If valid there is a shut off time, t_OCOFF, time for the HSS to

shut off. When the HSS shuts off due to an over current event the HSS has to be re-enabled. This is

accomplished differently depending upon whether the device is in pin control or SPI control. If in SPI control it

will also depend upon how the HSS is configured.

Pin Control:

• HSS is controlled by the input signal on the HSSC pin.

• Once the over current fault is removed a high to low transition on the HSSC pin will re-enable the HSS

output.

SPI Control and HSS_EN; 8'h1E[7] = 1b (enabled):

• When HSS is configured as On or HSSC controlled, HSS_CNTL 8'h1E[6:4] = 000b or 101b, the HSS will

have to have the HSS_EN; 8'h1E[7] set to 0b (disabled) and then reset to 1b (enabled) or will turn on when

HSSC receives the signal described above in "Pin Control."

• When HSS is configured utilizing a PWM or Timer, HSS_CNTL 8'h1E[6:4] = PWM1, PWM2, Timer1 or

Timer2, the HSS will automatically turn on.

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备注

• For resistive loads, an external capacitor to ground in not required.

• For inductive loads, an external 100 nF capacitor to ground is needed.

• When using the 10-bit PWM with the HSS or LIMP configured as a HSS, it is possible to select

values that are unrealizable due to the on and off times of the switch. An example of this would be

00 0000 0001b

8.3.11 HSSC or FSO (High-side Switch Control or Function Output)

In pin control mode, this pin is the high-side switch control pin. When in SPI control mode, the pin becomes a

function output pin that can be selected from register 8'h29[3:1]. In SPI mode this pin can be switched back to

HSSC input by using register 8'h1E[6:4] = 101b.

8.3.12 WKRQ or INH (Wake Request or Inhibit)

Upon power up, the state of this pin determines if it is WKRQ or INH. When externally pulled low with a 100 kΩ

resistor, the WKRQ function is enabled which is an active high, digital output supporting the internal voltage rail

(V_INT) or V_CCas described in PIN or nCS (Pin Watchdog Select or SPI Chip Select). When left floating or pulled

low by a 1 MΩ resistor, this pin becomes the high voltage inhibit (INH) output which is used to support the

enable pin of a power device. If a capacitor to ground is used off of this pin, it must be less than or equal to 50

pF. When WKRQ is selected, the pin behavior is based off of the LDO, so any event that causes the LDO to be

turned off will turn off the WKRQ pin.

WKRQ

100 k

INH

1 M

Floating or 1 M pull-

down make pin INH

V_SUP

GND

WKRQ/

INH

WKRQ/

INH

V_INT

Control

图8-7. WKRQ or INH Pin Select

8.3.13 PV

This output pin is the divided down value from V_BAT. The output is buffered to keep the output from exceeding

the specified values when V_BATexceeds the recommended value. It is connected directly to the ADC of the

microcontroller. It is connected by either an RC network or with just a capacitor to GND, see 图8-8. It is switched

on when a high is present on the DIV_ON pin. When off, the PV pin is in a high-Z state.

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V_BAT

DIV_ON

MCU

ADC

MCU

GND

V_CC

470

PV

20 pF

+

-

+

-

ADC

10 nF

On for 3.3 V

Off for 5 V

On for 3.3 V

Off for 5 V

GND

图8-8. PV Connections to MCU

8.3.14 DIV_ON

This is a logic input pin used to enable the voltage divider PV output. This is an active high pin and is disabled in

certain modes of operation.

8.3.15 V_BAT(Battery Voltage)

This pin is connected to the battery input prior to the reverse blocking diode. This pin is used in conjunction with

the PV and DIV_ON pins.

8.3.16 V_SUP(Supply Voltage)

V_SUPis the power supply pin. V_SUPis connected to the battery through an external reverse battery-blocking

diode (see 图 8-3). The V_SUPpin is a high-voltage-tolerant pin. Decoupling capacitors of 100 nF are

recommended to be connected close to this pin to improve the transient performance. If there is a loss of power

at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This

is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the

network remains powered (battery supplied). When V_SUPdrops low enough the regulated output drops out of

regulation. The LIN bus works with a V_SUPas low as 5.5 V, but at a lower voltage, the performance is

indeterminate and not guaranteed. If V_SUPvoltage level drops enough, it triggers the UV_SUP, and if it keeps

dropping, at some point it passes the POR threshold.

8.3.17 GND (Ground)

GND is the device ground connection. The device can operate with a ground shift as long as the ground shift

does not reduce the V_SUPbelow the minimum operating voltage. If there is a loss of ground at the ECU level, the

device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN

systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains

powered (battery supplied).

8.3.18 EN or nINT (Enable Input or Interrupt Output)

When configured as pin control, this pin becomes the transceiver enable control, EN. EN controls the operational

modes of the device. When EN is high, the device can enter normal or fast operating modes allowing a

transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device can enter standby or sleep

mode depending upon the state of the TXD pin. The device can enter normal mode only after wake up. EN has

an internal pull-down resistor to ensure the device remains in low power mode even if EN floats. EN should be

held low until V_SUPreaches the expected system voltage level.

When configured as SPI control, this pin becomes the processor interrupt pin. When the TLIN1431x-Q1 requires

the attention of the processor, this pin is pulled low.

8.3.19 nRST (Reset Input and Reset Output)

The nRST pin is a bi-directional open-drain low side driver that serves three functions, a V_CCmonitor output for

under-voltage events, restart mode indicator and a device input reset. The pin is nRST in Pin Control Mode and

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the defaulted function for SPI mode. This pin is internally pulled up to V_INTby a 45 kΩ resistor. V_INTrepresents

the TLIN1431-Q1 IO voltage level and may or may not be V_CC. It is recommended to use an external 10 kΩpull-

up to the processor IO voltage rail. The pin can determine when an input pulse of t_nRSTINis applied causing the

device to enter restart mode. When an under-voltage event takes place, the nRST is latched low after a 30 µs

filter and the device transitions to restart mode, fail-safe mode disabled, or fail-safe mode after the t_UVFLTRhas

expired. When in restart and V_CCexceeds the UV_CCRthreshold, the t_{RSTN_act}timer starts. After this timer times

out, the device transitions to standby mode, and the nRST pin is released. If a thermal shutdown event takes

place, the signal is pulled to ground. When the device is configured by SPI, the pin can be programmed to

become the watchdog output trigger to reset the processor. When the watchdog times out, this signal is pulled

low for time of t_{NRST_TOG}and then released back to V_CC. If both are needed for SPI configuration it is

recommended to add an external circuit off the LIMP pin to serve as the watchdog output trigger to reset the

processor. Note the LIMP pin output is a high voltage output based upon V_SUPand care must be taken when

connecting to a lower voltage device.

8.3.20 V_CC(Supply Output)

The V_CCterminal is the regulated output based on the applicable voltage, 3.3 V or 5 V with up to 125 mA from

12 V supply voltage. This pin is used to power external devices and when using high-k boards and thermal

management best practices full capability can be realized. The regulated voltage accuracy is ±2.5%.

When powering up the TLIN1431x-Q1, V_CCmust be above UV_CCand without any faults. V_CCis used

to determine the state of several pins that establishes several device functions, such as pin control or

SPI control. If a fault, such as V_CCSC, is present at power up the device cannot determine the state of

these pins. Fault needs to be cleared and power up performed again.

8.3.21 V_BATVoltage Divider

The voltage divider is a reverse polarity protected resistor divider connected to V_BATwith fast response times.

The divider is based upon the LDO value. For 5 V V_CC, the ratio is 1:7. For 3.3 V V_CC, the ratio is 1:9. The

voltage divider is activated by a high on the DIV_ON pin. The divided output voltage is available on the PV pin

for the microcontroller to read. See 表 8-1 for the modes that the DIV_ON functionality is enabled and disabled.

When VBAT exceeds 28 V for the 5 V LDO and 20 V for the 3.3 V LDO the voltage is clamped to prevent

damage to microcontroller. See 图8-9 and 图8-10 for the relationship between V_BATand PV output voltage.

表8-1. Voltage Divider Functionality Control by Mode

Mode of Operation

DIV_ON

PV Output State

Low

Off

On

Off

Normal/Fail-Safe/Fast/ Standby

High

Low

Sleep/Pin Init/SPI Init/Restart

High

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5

4.5

4

3.5

3

2.5

2

4−0°C

25°C

50°C

85°C

105°C

125°C

1.5

1

0.5

0

5

10

15

20

25

30

35

40

45

V_BAT(V)

图8-9. V_BATvs PV for TLIN14315RGYQ1 for Different Ambient Temperatures

3.5

3

2.5

2

1.5

1

- 40°C

25°C

50°C

85°C

105°C

125°C

0.5

0

5

10

15

20

25

30

35

40

45

V_BAT(V)

图8-10. V_BATvs PV for TLIN14315RGYQ1 for Different Ambient Temperatures

8.3.22 Protection Features

The device has several protections features that are described as follows.

8.3.22.1 Sleep Wake Error (SWE) Timer

The TLIN1431x-Q1 implements a sleep wake error timer, t_{INACT_FS}. The purpose of the SWE timer is to keep the

device and the node from being stuck in a high-power state. This timer is used to place the device into fail-safe

or sleep mode due to fault conditions. In Pin mode, the SWE timer starts automatically when entering fail-safe

and restart modes. A wake event causes the device to move from sleep mode to restart mode and if V_CCdoes

not exceed UV_CCbefore the SWE timer times out the device re-enters sleep mode. This happens in either SPI or

pin control modes.

In SPI mode, the SWE timer, when enabled, automatically starts when the device enters fail-safe, restart and

standby modes. When the device leaves restart mode and enters standby mode, the processor must initiate a

SPI transaction before the SWE timer times out or the device will enter fail-safe mode if enabled or sleep mode.

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This timer can be disabled at register 8'h1C[7] = 1. If the SWE timer duration is changed, this is accomplished

register 8'h1C[6:3]. It can be changed from default of 5 min to between 30 sec to 10 min.

8.3.22.2 Device Reset

The TLIN1431 device can be reset in various ways. In SPI mode, there are three methods to reset the device.

Two are accomplished with SPI commands –soft reset and hard reset. Soft reset and hard reset are

accomplished by writing 02h or 01h respectively to DEVICE_RST (Address 19h) register. nRST pin can also be

used to reset the device by pulling nRST low for t_nRSTINand releasing the pin. nRST pin reset works for both SPI

and PIN mode.

When performing a soft reset (SPI Mode), the following takes place:

• Device transitions to restart mode, nRST pin is pulled low for t_{NRST_TOG}and then transitions to standby mode.

• All registers are reset to default values

• All pending interrupts are cleared (unless a fault persists). PWRON interrupt is not cleared by soft reset.

• V_CCstays in the same state it was in

• INH stays ON

When performing a hard reset (SPI Mode), the following takes place:

• Similar behavior as power-up

• Device transitions to Init mode –V_CCis re-enabled, INH/WKRQ is re-sampled, SPI/PIN mode determination

is made

• All registers are reset to default values

• PWRON flag is set is with a hard reset (if previously cleared)

When pulling nRST pin low and releasing (SPI or PIN Mode), the following takes place:

• Device transitions to restart mode, nRST pin is pulled low for t_{NRST_TOG}and then transitions to standby mode.

• All registers retain the same value as before nRST reset

• V_CCstays in the same state it was in

• All pending interrupts are retained

• INH stays ON

8.3.22.3 TXD Dominant Time Out (DTO)

During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application

failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on

the TXD pin. If the low signal remains on TXD for longer than t_{TXD_DTO}, the transmitter is disabled, thus allowing

the LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and

the t_{TXD_DTO}timer is reset by a rising edge on TXD. The TXD pin has an internal pull-up to make sure the device

fails to a known recessive state if TXD is disconnected. During this fault, the transceiver remains in normal mode

(assuming no change of stated request on EN), the RXD pin reflects the LIN bus and the LIN bus pull-up

termination remains on. The TLIN1431x-Q1 can turn off TXD dominant state timeout when in SPI mode by using

register 8'h1D[5] = 1b.

8.3.22.4 Bus Stuck Dominant System Fault: False Wake Up Lockout

The device contains logic to detect bus stuck dominant system faults and prevents the device from waking up

falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus

is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears”the bus stuck dominant,

preventing excessive current use. 图8-11 and 图8-12 show the behavior of this protection.

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RXD

EN/SPI

LIN Bus

< t_LINBUS

t_LINBUS

< t_LINBUS

图8-11. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wake Up

RXD

EN/SPI

LIN Bus

t_LINBUS

t_CLEAR

< t_CLEAR

图8-12. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wake Up

8.3.22.5 Thermal Shutdown

The TLIN1431x-Q1 has multiple thermal sensors in the device to monitor the junction temperature of the die.

The V_CCLDO, LIN transmitter, and high side switch/LIMP cells are monitored. Depending upon which cell's

junction temperature are exceeded will determine the action taken by the device. Exceeding the maximum

junction temperature for the LIN transmitter or LDO will cause the LIN transmitter into the recessive state and

turns off the V_CCregulator. The nRST pin is pulled to ground during a LIN or V_CCLDO TSD event. Once the over

temperature fault condition has been removed and the junction temperature has cooled beyond the hysteresis

temperature, the transmitter can be re-enabled. Exceeding the max junction temperature of the high side switch

or LIMP cells will cause the cells to be turned off.

In pin control mode, a TSD event on the LIN transceiver or V_CCLDO causes the device enters a fail-safe mode.

Once the TSD fault has been removed and a wake event takes place, the device enters restart mode. If a wake

event takes place and the TSD fault has not cleared, the device enters sleep mode immediately. Exceeding the

max junction temperature for the high side switch and LIMP high side switch cause the switches to be turned off

until junction temperature falls below T_SDF

.

In SPI mode, there are two interrupts that can be set due to a thermal event. If the LIN transceiver or V_CCLDO

junction temperature is exceeded, the TSD_VCC_LIN interrupt is set and the devices takes the action previously

described. If the high side switch or LIMP high side switch max junction temperature is exceeded, the

TSD_HSS_LIMP interrupt is set. The device takes the action previously described. In SPI mode, the device

defaults to support fail-safe mode. The device enters fail-safe mode upon an TSD_VCC_LIN event and LIMP is

turned on (see 图 8-25). Exiting fail-safe mode is the same as when the device is pin controlled. When fail-safe

mode is disabled, the device enters sleep mode upon a TSD_VCC_LIN event.

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8.3.22.6 Under-voltage on V_SUP

The device monitors V_SUPfor two low voltage thresholds, UV_SUPand V_nPOR. When V_SUPdrops below UV_SUPF

and is above V_nPORF, the device is in an under-voltage power state. Once V_SUPramps above UV_SUPR, the

device enters restart mode and turns on the V_CCLDO, see Restart Mode. When V_SUPdrops below V_nPORF, the

device goes into a power off state. Once V_SUPramps above V_nPORR, the device prepares the digital core to wake

up. The device waits for V_SUPto rise above UV_SUPRand then turns on the V_CCLDO. Once V_SUPand V_CCare

above their under-voltage levels, the device enters Init mode, see Init Mode. The described under-voltage events

are also considered brown out events and more information can be found at Device Brownout information.

8.3.22.7 Unpowered Device and LIN Bus

In automotive applications, some LIN nodes in a system can be unpowered (ignition supplied) while others in the

network remains powered by the battery. The device has extremely low unpowered leakage current from the

bus, so an unpowered node does not affect the network or load it down.

8.3.22.8 Floating Pins

There are internal pull ups and pull downs on critical terminals to place the device into known states if the

terminal floats. See 表8-2 for details on terminal bias conditions.

表8-2. Internal Pull-ups and Pull-downs on Device Pins

TXD

Pull-up or Pull-down

Typical Value

Comment

Pull-up

350 kΩ

WDT/CLK

Pull-up

When device configured for SPI control, CLK

240 kΩ

WDI/SDI

PIN/nCS

Pull-up

240 kΩ

When device configure for SPI control, nCS

240 kΩ

DIV_ON

Pull-down

370 kΩ

LIN

Pull-up

45 kΩ

EN/nINT

HSSC/FSO

Pull-down

350 kΩ

45 kΩ

nRST

Pull-up

8.3.22.9 V_CCVoltage Regulator

The device has an integrated high-voltage input LDO that operates over a 5.5 V to 28 V input voltage range for

both 3.3 V and 5 V V_CC. The device has an output current capability of 125 mA and support fixed output voltages

of 3.3 V (TLIN14313-Q1) or 5 V (TLIN14315-Q1). It features thermal shutdown and short-circuit protection to

prevent damage during over-temperature and over current conditions

8.3.22.9.1 Under or Over Voltage and Short Circuit

The V_CCpin is the current limited regulated output based supporting an accuracy of ±2.5%. In the event that the

regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the

input voltage drops below the UV_SUPthreshold, the regulator turns off until the input voltage returns above the

UV_SUPRlevel. When 5 V LDO is used, the device uses the voltage regulator during Init mode to determine the

WKRQ/INH function, and the IO voltage. The device monitors V_CCfor under-voltage, over-voltage, short to

ground and thermal events. The device control method and whether fail-safe mode is enabled determine the

behavior of the of the device for these events. Fail-safe mode is always active when the device is in pin control.

In SPI control, the state diagram shows two paths: fail-safe mode enabled and fail-safe mode disabled. The path

followed depends on whether fail-safe mode is enabled or disabled in 8'h17[0] FSM_DIS.

For an under-voltage event, V_CCis less than or equal to UV_CCF. After a 30us filter time, the device pulls nRST

low and after the t_UVFLTRtime, the interrupt flag is set and device transitions to restart mode, if fail-safe disabled,

or fail-safe mode. When entering either mode, the SWE timer t_{INACT_FS}starts, and, in SPI control, the mode

counter increments and the appropriate interrupt flags are set. To exit fail-safe mode, the under-voltage has to

clear and a wake event takes place prior to the SWE timer timing out. If the under-voltage event has not cleared

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when the wake event takes place or if the SWE timer times out, the device enters sleep mode. 图 8-13 shows

how a UV_CCevent is handled..

Any Mode

VCC LDO on

V_CCdrops below

UV_CCthreshold >

30 µs filter

nRST latched low

t_UVFLTRtimer starts

t_UVFLTR

expires

No

V_CC< UV_CC

Current Mode

Yes

0b =

Enabled

1b =

Disabled

Fail-safe Mode

FSM CNTR + 1

nRST: low

Restart Mode

Restart CNTR +1

nRST: low

8'h17[0]

FSM_DIS

SWE starts

Yes

Execute

FSM_CNTR_ACT

8'h17[7:4]

Restart CNTR

Exceeded?

Yes

FSM CNTR

Exceeded?

No

V_CC

<

UV_CC

V_CC< UV_CC

Wake Event

V_CCUV_CC

and t_{RSTN_act}

times out

V_CC

UV_CC

<

V_CC< UV_CC

Sleep Mode

Standby Mode

V_CC

V_CCUV_CC

UV_CC

and t_{RSTN_act}

times out

Restart Mode

Restart CNTR +1

nRST: low

If the exit events do not take place before the SWE

timer timeouts the device will enter sleep mode

图8-13. UV_CCflow chart

备注

If an over-voltage or short circuit event takes place while the device is in fail-safe mode due to a

under-voltage event on V_CC, the device will behave as shown in the OV_CCand VCC_SCflow charts.

For an over-voltage event, OV_CC, the device turns off the V_CCLDO, and transitions to either sleep mode, fail-

safe mode disabled, or fail-safe mode. When a wake event takes place, the V_CCLDO is turned on for t_LDOONto

determine if the over-voltage is still present. If cleared, the device enters restart mode from either sleep or fail-

safe modes. When in fail-safe mode, if the over-voltage has not cleared when the wake event takes place the

device transitions to sleep mode.

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备注

If an over-voltage event takes place while the device is in Init mode the following will happen:

• The device will sample the pins and determine whether the device is Pin or SPI control

• The device will determine the input/output voltage level if the TLIN14315-Q1

• The device will determine if WKRQ/INH pin is WKRQ or INH

• The device will transition to fail-safe mode

Any Mode

V_CCLDO on

Yes

Current Mode

V_CC< OV_CC

No

Turn off V_CCLDO

& set interrupt

0b =

Enabled

Fail-safe Mode

FSM CNTR + 1

nRST: low

8'h17[0]

FSM_DIS

SWE starts

1b =

Disabled

Sleep Mode

nRST: low

Execute

FSM_CNTR_ACT

8'h17[7:4]

Yes

FSM CNTR

Exceeded?

No

Wake Event

Turn on V_CCt_LDOON

~ 3 ms

Yes

V_CC> OV_CCF

No

Restart Mode

nRST: low

If the exit events do not take place before the SWE timer

timeouts the device will enter sleep mode

图8-14. OV_CCflow chart

For a short to ground event, V_CCSC, the device turns off the V_CCLDO and transitions to either sleep mode, fail-

safe mode disabled, or fail-safe mode. When a wake event takes place, the V_CCLDO is turned on for t_LDOONto

determine if the short to ground is still present. If cleared, the device enters restart mode from either sleep or fail-

safe modes. When in fail-safe mode, if the short to ground has not cleared when the wake event takes place the

device will transition to sleep mode.

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备注

If a short circuit event is detected while the device is in Init mode the device will transition to sleep

mode. The device will not have determined the state of the pins and default to Pin control and will

need to be powered cycled if the default state is different than what is expected.

Any Mode

V_CCLDO on

No

Current Mode

V_CC< V_CCSC

Yes

t_VSCtimer starts

~ 100 µs

Turn off V_CCLDO

& set interrupt

0b =

Enabled

Fail-safe Mode

FSM CNTR + 1

nRST: low

8'h17[0]

FSM_DIS

SWE starts

1b =

Disabled

Sleep Mode

nRST: low

Execute

FSM_CNTR_ACT

8'h17[7:4]

Yes

FSM CNTR

Exceeded?

No

Wake Event

Yes

Turn on V_CCt_LDOON

~ 3 ms

Yes

V_CCSC

present

No

Restart Mode

nRST: low

If the exit events do not take place before the SWE timer

timeouts the device will enter sleep mode

图8-15. V_CCSC, short to ground

8.3.22.9.2 Output Capacitance Selection

For stable operation over the full temperature range and with load currents up to 125 mA on V_CC, a certain

capacitance is expected, and depends upon the minimum load current. To support no load to full load, a value of

10 µF and ESR smaller than 2 Ω is needed. For 50 µA to full load, a smaller capacitance can be used but is

system dependent and should be selected that will meet LIN to V_CCcross talk compliance during DPI testing.

The low ESR recommendation is to improve the load transient performance.

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8.3.22.9.3 Low-Voltage Tracking

At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage

based on the load current (IL) and switch resistor. This tracking allows for a smaller input capacitance and can

possibly eliminate the need for a boost converter during cold-crank conditions.

8.3.22.9.4 Power Supply Recommendation

The device is designed to operate from an input-voltage supply range between 5.5 V and 28 V. This input supply

must be well regulated, if the input supply is located more than a few inches from the device. The recommended

minimum capacitance at the pin is 100 nF. The max voltage range is for the LIN functionality. Exceeding 24 V for

the LDO reduces the effective current sourcing capability due to thermal considerations.

8.3.22.10 Watchdog

The TLIN1431x-Q1 has an integrated watchdog function. This can be programmed by pin control or SPI

communication control based upon the state of the PIN or nCS pin at power up. The device defaults to windows

based watchdog at power up. When entering normal and fast modes, the programmed watchdog timer starts

based upon the pin configuration for pin mode or register configuration in SPI control mode. When entering

standby mode from restart mode, there is a nRST transition from low to high. This transition starts the t_INITWD

timer. A WD trigger input must take place prior to this initial long window times out. If WD is disabled in standby

mode the same long window is implemented in normal mode. The LIMP pin provides a limp home capability

when connected to external circuitry. When in sleep mode, the limp pin is off. When the error counter reaches

the watchdog trigger event level, the LIMP pin turns on connecting V_SUPto the pin as described in the LIMP pin

section and the device transitions to restart mode at which time the nRST pin will be pulled low.

8.3.22.10.1 Watchdog in Pin Control Mode

The state of the WDT pin determines the window watchdog timing for three different windows. Timeout watchdog

is not available in pin control. The watchdog timer starts once the device has entered standby. The mode the

device enters is based upon other pins, EN and TXD. Fast mode can be used as a software development mode

as the WD is enabled but does not cause any action to take place. The watchdog feature cannot be disabled in

pin control mode. See 图8-16 for state diagrams on how the WD behaves.

Power up

Init Mode - Pin

Restart Mode

1^stWD trigger by

Standby Mode

t_INITWDand then based

WD = On

upon Pin program

Valid

Restart Mode

nRST = low

nWDR = low

Invalid

WD

Triggered

15 ms

t_{NRST_TOG}

times out

Normal/Fast

Mode

WD = On

Standby Mode

WD = On

1^stWD trigger by t_INITWD

and then based upon

Pin program

图8-16. Watchdog state diagram in pin mode

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8.3.22.10.2 Watchdog in SPI Control Mode

In SPI control, the window has extensive configurability including the ability to select the timeout watchdog.

Watchdog is default enabled for standby mode, but can be disabled by setting register 8'h14[0] = 1b. Register

8'h13[7:6] can be set to 00b to disable the WD. There is a WD error counter available in SPI control mode, see

Watchdog Error Counter for description of this counter. When a WD error occurs and if the WD error counter

reaches programmed count, the device transitions to restart mode and pulls nRST low for t_{NRST_TOG}. Once this

time has been met, the device transitions to standby mode and sets nRST pin high. See 图 8-17 and 图 8-18 for

state diagrams on how the WD behaves.

Power up

Init Mode

Restart Mode

SPI

CMD

Standby Mode

8'h14[0] = 0b

WD = Timeout – Long

first window, t_INITWD

After nRST

released long

window starts

Valid

WD CNTR -1

Invalid Long

First window

Invalid

WD CNTR +1

Set WD interrupt

WD Triggered

No

WD CNTR

limit met?

Standby Mode

SPI

CMD

Current Mode

WD = Timeout – Long

first window, t_INITWD

Start SWE timer

nRST = high

Normal Mode

WD = On as per

programming

Yes

Restart Mode

RSTRT CNTR +1

Start SWE mer

Restart

Mode

1b =

disabled

Sleep Mode

RSTRT CNTR

cleared

Yes

RSTRT CNTR

limit met?

FSM_DIS

8'h17[0]

0b =

enabled

No

Fail-safe

Mode

Fail-safe Mode

FSM CNTR +1

Start SWE mer

RSTRT CNTR

cleared

nRST pulled low

for t_{NRST_TOG}

Note: Fast mode WD sets flag but takes no action

Wake

event

Execute

FSM_CNTR_ACT

8'h17[7:4]

Yes

FSM CNTR

limit met?

图8-17. Watchdog state diagram in SPI mode; Standby Mode Enabled

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Power up

Init Mode - SPI

Restart Mode

SPI

CMD

Standby Mode

8'h14[0] = 0b

WD = Timeout – Long

first window, t_INITWD

After nRST

released long

window starts

Valid

WD CNTR -1

Invalid Long

First window

Invalid

WD CNTR +1

Set WD interrupt

WD Triggered

No

WD CNTR

Exceeded?

Normal Mode

SPI

CMD

Standby Mode

WD = off

Start SWE timer

nRST = high

Current Mode

WD =long first

window, t_INITWD, and

then on as per

Yes

programming

Restart Mode

RSTRT CNTR +1

Restart

Mode

1b =

disabled

Sleep Mode

RSTRT CNTR

cleared

Yes

FSM_DIS

8'h17[0]

RSTRT CNTR

limit met?

0b =

enabled

No

Fail-safe

Mode

nRST pulled low

for t_{NRST_TOG}

Fail-safe Mode

FSM CNTR +1

Start SWE mer

RSTRT CNTR

cleared

Note: Fast mode WD sets flag but takes no action

Wake

event

Execute

FSM_CNTR_ACT

8'h17[7:4]

Yes

FSM CNTR

Exceeded?

图8-18. Watchdog state diagram in SPI mode; Standby Mode Disabled

备注

• When the mode is changed while the timeout or window watchdog is running, it restarts once

entering the new mode, fast, normal and standby.

• If the watchdog configuration is changed on-the-fly while the watchdog is running, it resets the

error counter to 1 and resets the watchdog timers.

8.3.22.10.3 Watchdog Error Counter

The TLIN1431x-Q1 has a watchdog error counter used in SPI control mode. This counter is an up down counter

that increments for every missed window or incorrect input watchdog trigger event. In SPI control, the error

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counter is set at one by default. The counter decrements for every correct input trigger and increments on every

incorrect input trigger, but it never drops below zero. When the programmed counter is reached, the device

transitions to restart mode, error counter is reset back to one, and the nRST pin pulls low for t_{NRST_TOG}. At the

end of this time, the device transitions back to standby mode releasing the nRST pin to high. This counter can be

changed to 1 (every error), 5, 9, or 15 using 8'h16[7:6]. The error counter can be read at register 8'h14[4:1]. In

pin control, nWDR is pulled low for every watchdog error.

If the watchdog error count is set at one, the first input failure causes the device to transition to restart. This

allows the system to check the counter after the first input trigger to see if a valid input was sent. Every incorrect

watchdog input causes the interrupt to be set and nINT is pulled low.

8.3.22.10.4 Pin Control Mode

When using pin control for programming the watchdog, the WDT pin is used for this function. WDT sets the total

window size of the window watchdog. It can be connected to VCC, GND or left open. See 节 8.3.5 or 节 6.7 for

details on window timings. The ratio between the upper (open window) and lower (closed window) is 50/50. WDI

pin is used by the controller to trigger the watchdog input. The WDI input is an edge-triggered event and

supports both rising and falling edges. A filter time of t_Wis used to avoid noise or glitches causing a false trigger.

A pulse would be treated as a two input trigger events and cause the nWDR and nRST pins to be pulled low.

nWDR pin can connected to the controller reset pin and if a watchdog event happens this pin is pulled low. The

nRST pin may also be used for this function but includes other possible errors, like under-voltage or entering

restart mode.

8.3.22.10.5 SPI Control Programming

In SPI control, registers 8’h13 through 8’h16 control the watchdog function. The device watchdog can be set

as a timeout watchdog or window watchdog by setting 8’h13[7:6] to the method of choice. The timer is based

upon register 8’h13[5:4] WD prescaler and register 8’h14[7:5] WD timer and is in ms. See 表 8-3 for the

achievable times.

8.3.22.10.6 Watchdog Register Relationship

表8-3. Watchdog Window and Timeout Timer Configuration (ms)

WD_TIMER

Register 8'h13[5:4] WD_PRE

(ms)

Register

8'14[7:5]

00

01

10

11

000

4

8

12

96

16

128

001

32

64

010

128

256

384

512

011

256

384

512

768

100

512

1024

4096

20240

RSVD

1536

6144

RSVD

2048

8192

RSVD

101

2048

10240

RSVD

110

1111

8.3.22.10.7 Watchdog Timing

The TLIN1431x-Q1 provides two methods for setting up the watchdog when in SPI communication mode:

window watchdog or timeout watchdog. If more frequent (i.e. <16 ms) input trigger events are desired it is

suggested to use the timeout watchdog. When using timeout watchdog, the input trigger can occur anywhere

before the timeout and is not tied to an open window.

When using the window watchdog, it is important to understand the closed and open window aspects. The

device is set up with a 50%/50% open and closed window and is based on an internal oscillator with a ± 10%

accuracy range. To determine when to provide the input trigger, this variance needs to be considered. For

example, using the 64 ms nominal total window provides a closed and open window that are each 32 ms. Taking

the ±10% internal oscillator into account means the total window could range from 57.6 ms to 70.4 ms. The

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closed and open window could then range from 22.4 ms to 35.2 ms. From the 57.6 ms total window and 35.2 ms

closed window, the total open window is 22.4 ms. The trigger event needs to happen at 46.4 ms ± 11.2 ms. The

same method is used for the other window values. 图7-8 provides the above information graphically.

8.3.23 Channel Expansion

The TLIN1431x-Q1 has the ability to control an external LIN or CAN FD transceiver or a general purpose LIN or

CAN FD SBC. The processor controls the mode of the external transceiver by using the FSO pin from the

TLIN1431x-Q1 to the external transceiver. This is accomplished using the TLIN1431-Q1 SPI port, controlling the

FSO pin as an EN/STB/nSTB/S output pin to the external transceiver. This capability allows the system designer

to develop nodes with many different configurations, for example:

• Two LIN transceivers by using a simple eight pin LIN transceiver (see 图8-19)

• Two LIN transceivers with two WAKE and INH capability by using an enhanced eight pin LIN transceiver (see

图8-20)

• Two LIN transceivers with two LDO outputs by using an eight pin LIN SBC (see 图8-21)

• One LIN and one CAN FD transceiver by using a simple eight pin CAN FD transceiver (see 图8-22)

• One LIN and one CAN FD transceiver with two LDO outputs by using a CAN FD SBC (see 图8-23)

8.3.23.1 Channel Expansion for LIN

The TLIN1431x-Q1 has the ability to control an external LIN transceiver like the TLIN1039-Q1 or TLIN1021A-Q1

or a general purpose LIN SBC like the TLIN1028x-Q1. The FSO pin is configured as a general purpose output

pin. The FSO output level can be changed to meet the needs of the transceiver. The supply voltage of this

transceiver can be connected to V_SUPor controlled by the HSS pin from the TLIN1431x-Q1. To configure the

device to support an external LIN device the following registers and bits need to be configured:

• Register 8'h29[3:1] = 110b sets the FSO pin to a general-purpose output pin.

• Register 8'h29[4] sets the voltage level of the FSO pin when configured as a general-purpose output pin and

can be used to control the EN pin of an external LIN transceiver or SBC.

• To use the high-side switch (HSS) as the power to the external transceiver, turn on HSS. Note that when the

device enters sleep mode, the HSS pin is turned off.

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V_BAT

V_SUP

100 nF

470

100 nF

1 M pull-down or

leave floating for INH

3.3 V

LDO

V_DD33

V_BAT

V_SUP

1 M

INH

V_CC= 3.3V/5V

10 µ F

500 k

nCS

CLK

SDI

V_DD

WAKE

LIMP

SDO

V_DD

TLIN1431x-Q1

10 k

I/O

nRST

nINT

DIV_ON

PV

Micro

20 pF

LIN

TXD

RXD

FSO

EN

HSS

V_SUP

LIN Controller

Or

SCI/UART

TXD

RXD

LIN

TLIN1039

图8-19. Channel Expansion: LIN Transceiver

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V_BAT

V_SUP

100 nF

470

1 M pull-down or

leave floating for INH

100 nF

3.3 V

LDO

V_DD33

V_BAT

V_SUP

V_CC= 3.3V/5V

1 M

INH/

WKRQ

10 µ F

500 k

nCS

CLK

V_DD

HSS

SDI

SDO

V_DD

WAKE

LIMP

TLIN1431x-Q1

10 k

I/O

nRST

nINT

DIV_ON

PV

Micro

20 pF

LIN

TXD

RXD

V_SUP

FSO

LIN Controller

Or

SCI/UART

WAKE 2

V_SUP

WAKE EN

INH

LIN

TXD

TLIN1021A

RXD

图8-20. Channel Expansion: Enhanced LIN Transceiver

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V_BAT

V_SUP

100 nF

470

1 M pull-down or

leave floating for INH

100 nF

3.3 V

LDO

V_DD33

V_BAT

V_SUP

V_CC= 3.3V/5V

1 M

INH

10 µ F

500 k

nCS

CLK

SDI

V_DD

HSS

SDO

V_DD

WAKE

LIMP

10 k

TLIN1431x-Q1

nRST

nINT

I/O

DIV_ON

PV

Micro

20 pF

LIN

TXD

RXD

V_SUP

FSO

EN

LIN Controller

Or

SCI/UART

V_SUP

V_CC= 3.3V/5V

LIN

TXD

RXD

TLIN1028

nRST

图8-21. Channel Expansion: LIN SBC

8.3.23.2 Channel Expansion for CAN Transceiver

It is possible to add an external CAN transceiver or general purpose CAN SBC. For a simple CAN transceiver,

the 5 V VCC from the TLIN14315-Q1 can power the external transceiver. When the TLIN14315-Q1 enters sleep

mode the LDO is turned off which turns off the 5 V to the transceiver. There are other instances that this can take

place depending upon various fault conditions like thermal shut down. Using the 3.3 V version of the device can

power a 3.3 V CAN transceiver. If an external general purpose SBC is used, VCC can be used to power up other

components as the SBC will also receive its input power from V_SUP. The FSO pin when configured as a general-

purpose output pin is used as the STB/nSTB/S control pin in order to control the mode of the external CAN

transceiver or SBC.

• Register 8'h29[3:1] = 110b sets the FSO pin as a general-purpose output pin EN/STB/nSTB/S pin.

• Register 8'h29[4] sets the level of the FSO pin and can be connected to the external CAN transceiver or SBC

STB/nSTB/S pin.

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V_BAT

V_SUP

100 nF

470

1 M pull-down or

leave floating for INH

100 nF

3.3 V

LDO

V_DD33

V_BAT

V_SUP

1 M

INH/

WKRQ

500 k

nCS

CLK

SDI

HSS

V_DD

WAKE

LIMP

SDO

V_DD

TLIN14315-Q1

10 k

nRST

I/O

nINT

DIV_ON

PV

Micro

20 pF

LIN

TXD

RXD

LIN Controller

Or

SCI/UART

V_CC= 5V

10 µ F

FSO

3.3 V

100 nF

V_IO

V_CC

STB

CANH

CANL

TCAN1044VA

TXD

RXD

CAN

Controller

图8-22. Channel Expansion: CAN Transceiver

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V_BAT

V_SUP

100 nF

470

100 nF

1 M pull-down or

leave floating for INH

3.3 V

LDO

V_DD33

V_BAT

TLIN14315-Q1

FSO

V_SUP

1 M

V_CC= 3.3V/5V

10 µ F

INH

500 k

nCS

CLK

HSS

V_DD

WAKE

LIMP

SDI

SDO

V_DD

10 k

nRST

I/O

nINT

DIV_ON

PV

20 pF

Micro

LIN Controller

Or

SCI/UART

LIN

TXD

RXD

3.3 V

STB

V_IO

V_CC= 3.3V

CANH

CANL

TXD

RXD

CAN

Controller

TCAN11623

WAKE

INH

nRST

TS

图8-23. Channel Expansion: CAN SBC

8.4 Device Functional Modes

The TLIN1431x-Q1 has multiple functional modes of operation, Init, pin/SPI Init, normal, standby, sleep, restart

and fail-safe. The next sections describe these modes as well as how the device moves between the different

modes. 图 8-24 and 图 8-25 graphically shows the relationship while 表 8-4 and tables show the state of pins in

each control mode. Upon power up, and once V_CC≥ UV_CCprior to t_{INACT_FS}timing out the device enters an

initialization mode (INIT). While in this mode, V_CCis ramping, nRST ramps with V_CC, all other pins are off except

for monitoring the state of the Pin/nCS pin to determine which control method is being implemented. Once the

control method is determined, the device follows the pin control or SPI control path of the state diagram.

表8-4. Operating PIN Mode

Function

Restart Mode

Sleep Mode

Standby Mode

Normal Mode

Fail-safe Mode

Fast Mode

EN

NA

Low

High

NA

Pulse then high

Low for a wake event and

power up event otherwise

high

RXD

High

Floating

Mirrors LIN bus

Floating

Mirrors LIN bus

LIN BUS

Termination

Weak current pull-up

45 kΩ(typical)

Vbat Voltage

Divider

Off

On

Off

On

Fault dependent

Off

On

Transmitter

On (Slope control off)

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表8-4. Operating PIN Mode (continued)

Function

Watchdog

nRST Pin

WAKE Pin

Restart Mode

Sleep Mode

Standby Mode

Normal Mode

Fail-safe Mode

Fast Mode

Off

Low

Off

Low

On

On with long first pulse

On

High

Off

LDO state dependent

On

On but only sets flag

High

On

High

Off

INH - On; WKRQ - Fault

dependent

WKRQ/INH

On

Off

On

•

Same as previous

state when due to a

WD fault

Previous state prior to

entering STBY due to WD

fault

Previous state prior to

entering normal mode

due to WD fault

Previous state prior to entering

fast mode due to WD fault

Turns off when

exiting fail-safe

mode due to any

other fault

LIMP

On

On and controlled by

HSSC pin

On and controlled by

HSSC pin

On and controlled by HSSC

HSS

V_CC

Off

Ramping

On

Fault dependent

On

nRST is internally

connected to the LDO

output which in sleep

mode is off

Wake up event detected,

waiting on processors to

set EN

LIN transmission up to

20 kbps

LDO off for TSD, V_CCSC

or OV_CCevents

LIN transmission up to 200

kbps

Comment

备注

LDO state for fault dependent in fail-safe mode is as follows:

• Watchdog error - On

• Thermal shut down - Off

• UV_CC- On

• OV_CCover-voltage - Off

• V_CCSC- Off

• Restart counter exceeded - On

• SWE timer expiration - On

If TXD is held dominant when device enters normal or fast modes, the LIN transmitter does not turn on

until the TXD pin goes recessive.

If V_SUPis ≤UV_SUPWKRQ/INH is off.

WKRQ depends upon the LDO being on, so any event that causes the LDO to be turned off will turn

off WKRQ.

Any WD failure in Fast Mode will only set interrupt and not take any other action (will not set LIMP,

transition to Fail-safe or Restart or take any WD fail action)

• nRST depends upon the LDO state. When LDO is on, nRST reflects the LDO value.

– When LDO is on, nRST reflects the LDO or I/O voltage value except for a UV_CCevent where

nRST is low.

– When LDO is off, nRST is low.

表8-5. Operating SPI Mode

Function

Restart Mode

Sleep Mode

Standby Mode

Normal Mode

Fail-safe Mode

Fast Mode

Low for a wake event and

power up event otherwise

high

Fault

RXD

High

Floating

Mirrors LIN bus

dependent

LIN BUS

Termination

Weak current pull-up

45 kΩ(typical)

Vbat Voltage

Divider

Off

On

Off

On

Fault dependent

Off

On

Transmitter

On (Slope control off)

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表8-5. Operating SPI Mode (continued)

Function

Restart Mode

Sleep Mode

Standby Mode

Normal Mode

Fail-safe Mode

Fast Mode

On

If programmed off in

standby mode when

entering normal mode a

long first window is

implemented

Default on with long first

window but

programmable off

Watchdog

Off

On but only sets flag

SPI pins

nINT pin

Off

On

Fault dependent

LDO state dependent

On

nRST pin

WAKE Pin

Low

Off

Low

On

High

On

High

Off

High

Off

INH - On; WKRQ - Fault

dependent

WKRQ/INH

On

Off

On

•

Same as previous

state when due to a

WD fault

When exiting fail-

safe mode due to

any other fault how

8'h1A[3:2] is

Previous state prior to

entering STBY due to WD

fault

Previous state prior to

entering normal mode

due to WD fault

Previous state prior to entering

fast mode due to WD fault

LIMP

Off

On

programmed

determines how

LIMP is cleared

Off unless cyclic

sensing enabled

HSS

V_CC

Off

On

Off

On

Ramping

Off

Fault dependent

nRST is internally

connected to the LDO Wake up event detected, LIN transmission up to 20 LDO off for TSD, V_CCSC

LIN transmission up to 200

kbps

Comment

output which in sleep

mode is off

waiting on processors

kbps

or OV_CCevents

备注

Function status when in fail-safe mode that states fault dependent are defined in 表8-6

If TXD is held dominant when device enters normal or fast modes, the LIN transmitter does not turn on

until the TXD pin goes recessive.

If V_SUPis ≤UV_SUPWKRQ/INH is off.

WKRQ depends upon the LDO being on, so any event that causes the LDO to be turned off will turn

off WKRQ.

Any WD failure in Fast Mode will only set interrupt and not take any other action (will not set LIMP,

transition to Fail-safe or Restart or take any WD fail action)

表8-6. Fault Dependent States In Fail-safe Mode

Restart Counter

Exceeded

Function

Watchdog Error

Thermal Shutdown

UV_CC

V_CCOver Voltage

V_CCSC

LDO ⁽²⁾

INH

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On ⁽¹⁾

Programmed

On

WKRQ

SPI

On

(1) LDO is on in fail-safe mode if the restart counter causes the change when fail-safe mode is enabled.

(2) LDO is on in fail-safe mode if the SWE timer times out causing the device to enter fail-safe mode if enabled.

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Unpowered

System

V_SUP< V_nPOR

POR

UV_SUP

UV_SUP> V_SUP< V_nPOR

V_SUP> V_nPOR

V_CC> UV_CC

SPI Control Mode

Pin Control Mode

HD_RST

V_SUP> UV_SUP

Restart Mode

nCS/PIN = High

or Floating

Init Mode

nRST

nCS/PIN = GND

V_CC: Mode entrance

dependent

nRST: low

SWE timer starts

V_CC: Mode entrance

dependent

nRST: low

SWE timer starts

V_CC: on

nRST: low

Pin status determined

WD Failure Event

When Vcc UVcc and

timer (t_{RSTN_act}1.5ms to

2.5ms)

Note *

To exit fail-safe mode the fault must first be cleared then

a wake event take place prior to SWE timer timing out

SWE timer

times out

Note *

UV_CCEvents

EN = Low > t_EN

AND TXD = Low

AND nRST = High

Fail-safe Mode

Sleep Mode

Normal Mode

V_CCOvervoltage

Event

Note &

V_CC: Fault dependent

SWE timer starts

V_CC: off

nRST: low

V_CC: on

nRST: high

TSD Event

EN = High >

t_{FM_CHANGE}

AND nRST = High

Note &

V_CCSC Event

ꢀꢁSWE timer starts upon entering fail-safe mode.

This is the length of time for the fault to clear

before moving to sleep mode. If a wake event

takes place and fault still present the device will

enter sleep mode.

EN = Pulse < t_{FM_CHANGE}

AND nRST = HIGH

EN = Low > t_{FM_CHANGE}

AND TXD = High

AND nRST = High

EN = Low > t_{FM_CHANGE}

AND TXD = High

AND nRST = High

Fast Mode

Standby Mode

V_CC: on

nRST: high

LIN up to 200kbps

V_CC: on

nRST: high

EN = High > t_EN

AND TXD = Low pulse

AND nRST = High

图8-24. Pin control state diagram

备注

Normal mode can be entered from Fast mode with TXD in either state:

• TXD = high, EN = pulse < t_{FM_CHANGE}and nRST = high

• TXD = low, nRST = high and EN pulse can be any width

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Unpowered

System

POR

V_SUP< V_nPOR

UV_SUP

UV_SUP> V_SUP< V_nPOR

SPI Control Mode

V_SUP> V_nPOR

V_CC> UV_CC

Pin Control Mode

HD_RST

V_SUP> UV_SUP

Restart Mode

Init Mode

Restart Mode

nRST

nCS/PIN = High

or Floating

nCS/PIN = GND

V_CC: Mode entrance

dependent

nRST: llow

SWE timer starts

V_CC: on

V_CC: Mode entrance

dependent

nRST: low

SWE timer starts

SOFT_RST

nRST: low

Pins status

determined

Note *

To exit fail-safe mode the fault must first be

cleared then a wake event take place prior to

Note *

SWE timer timing out

TSD Event

SWE timer times out

in standby mode

Normal Mode

Restart

Mode

V_CC: on

nRST: high

Cyclic sense: on

Fail-safe Mode

FSM disabled

V_CCUV event

UV_CCEvent

V_CC: Fault Dependent

SWE timer starts

SPI CMD

WUP event

WAKE event

Faults cleared:

ꢀꢁV_CCSC event

ꢀꢁTSD event

SPI

CMD

Fast Mode

V_CCSCEvent

ꢀꢁRSRT_CNTR

V_CC: on

nRST: high

LIN up to 200kbps

SPI

CMD

SPI

CMD

V_CCOvervoltage

Event

Note &

SPI

ꢀꢁSWE timer starts upon entering fail-safe mode.

This is the length of time for the fault to clear

before moving to sleep mode. If a wake event

takes place and fault still present the device will

enter sleep mode.

CMD

SPI

CMD

SPI

CMD

Standby Mode

V_CCOvervoltage

Event

Sleep Mode

Sleep

Mode

V_CC: on

nRST: high

SWE timer starts

FSM disabled

V_CC: off

nRST: low

SPI

CMD

TSD Event

FSM disabled

Fast

Mode

Note !

V_CCSC Event

FSM disabled

SWE timer

times out

Note ! – SWE timer timing out causes the device to enter sleep mode under

these conditions

ꢀꢁFail-safe mode is disabled

ꢀꢁFail-safe mode enabled and timer times out while in fail-safe mode

图8-25. SPI control state diagram

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8.4.1 Init Mode

This is the initial mode of operation upon powering up. This is a transitional mode that is entered once V_CC

≥

UV_CC. The device is in this mode for ≤350 µs as it determines the states of pin 7, PIN/nCS and pin 16, WKRQ/

INH; see 图8-5 and 图8-6. The V_CCfault monitoring will be active to determine if there is a TSD, OV_CCor V_CCSC

faults which takes approximately 2.5 ms. If one of these faults are detected, the device will perform as described

in 节 8.3.22.5 and 节 8.3.22.9.1. If V_CC< UV_CC, The device will remain in Init mode until V_CC> UV_CC. If a fault

takes place that keeps the device from determining the state of the pins, the device will default to pin control.

Unpowered System

V_SUP< V_nPOR

POR

V_SUP> V_nPOR

V_CC> UV_CC

Init Mode

V_CCramping up and on & UV_CC

WD = Off

HD_RST

nCS/PIN = GND

Pin Restart

Mode

nRST = Low

LIN = Off

WAKE = Off

nCS/PIN = High

or Floating

SPI Restart

Mode

nCS/PIN status determination

Processor I/O voltage level determined

INH or WKRQ function determined

图8-26. Init Mode

8.4.2 Normal Mode

In normal operational mode, the receiver and transmitter are active and the LIN transmission up to the LIN

specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and outputs it

on RXD for the LIN controller. A recessive signal on the LIN bus is a digital high and a dominant signal on the

LIN bus is a digital low. The driver transmits input data from TXD to the LIN bus. When entering normal mode, it

takes t_{MODE_CHANGE}before data on RXD pin reflects the LIN bus. Normal mode can be entered from Fast mode

and standby mode. See 图8-24 for the conditions necessary to enter normal mode when in pin control.

In SPI control mode, Normal mode is entered by SPI commands at register 8'h1D[7:6] = 10b. See 图8-25 for the

conditions necessary to enter normal mode when in pin control.

Faults

Normal Mode

SPI CMD

FSM Enabled

Fail-safe Mode

V_CC= On

WD = On - Window WD (Default)

SPI = On

Normal Mode

Fast Mode

Restart Mode

WD failure

nRST = High

V_CC= On

WD = On

nRST = High

LIN = On

WAKE = Off

Sleep Mode

Faults

Fast Mode

nINT = On if enabled

LIN = On

WAKE = Off

INH or WKRQ = On

FSM Disabled

Sleep Mode

Restart Mode

WD & UV_CC

Restart Mode

WD failure

LIMP = As programmed during Norm Mode -

On if failure condition

HSS = Programming dependent

Standby Mode

INH or WKRQ = On

LIMP = Previous state prior to entering

HSS = HSSC

Standby Mode

Sleep Mode

Fail-safe Mode

图8-27. Normal Mode Pin Control

图8-28. Normal Mode SPI Control

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8.4.3 Fast Mode

Fast mode removes the slope control for the LIN transmitter allowing the LIN bus to support data rates up to 200

kbps. Fast mode is also the system software programing mode and debug mode. The watchdog is active but

only indicates a WD failure and does not cause any resets or mode changes. Fast mode can be entered in either

SPI or pin control modes. In SPI mode it is entered from normal or standby modes. In pin mode, it can be

entered from standby mode. To enter fast mode from standby, the EN pin must be high with a high-low-high

pulse on the TXD pin of duration t_FMTXDtakes place prior to t_{FM_CHANGE}timing out, see 图 8-31. In pin control

mode, to leave fast mode the enable pin and TXD pins are used. If TXD pin is high and the EN pin is pulsed from

high too low too high for t_{FM_CHANGE}, the device enters standby mode, see 图 8-32. If the EN pin is pulsed high

too low too high with the pulse being < t_{FM_CHANGE}, the device enters normal mode, see 图8-33.

Fast Mode

SPI CMD

Faults

Fast Mode

Normal

Mode

V_CC= On

WD = On but does not cause

reset

SPI = On

nRST = High

LIN = On - Slope CNTL off

WAKE = Off

INH or WKRQ = High

LIMP = Off

FSM Enabled

Fail-safe Mode

V_CC= On

WD = On but doesn’t cause

failure

nRST = High

LIN = Slope CNTL off

WAKE = Off

Normal Mode

Standby

Mode

FSM Disabled

Restart Mode

UVCC

Standby Mode

Non-WD Faults

Fail-safe

Mode

Sleep

Mode

INH or WKRQ = High

LIMP = Off

Sleep Mode

HSS = Depends on programming

HSS = HSSC

图8-29. Fast Mode Pin Control

图8-30. Fast Mode SPI Control

t_{FM_CHANGE}

t_EN

t_NOMINIT

EN

t_FMTXD

TXD = High

TXD

TXD = High

EN

Filter/TXD

Sampling

Window

Filter/TXD

Sampling

Window

Transiꢀon

Fast Mode

Standby Mode

Fast Mode

MODE

RXD

Indeterminate Ignore

Mirrors Bus

RXD

Indeterminate Ignore

Pulled Low

Mirrors Bus

图8-31. Entering Fast Mode from Standby Mode

图8-32. Exiting Fast Mode to Standby Mode

< t_{FM_CHANGE}

t_NOMINIT

EN

t_EN

EN

Filter

Transiꢀon

Normal Mode

Mirrors bus

Fast Mode

MODE

RXD

Indeterminate Ignore

Mirrors Bus

图8-33. Exiting Fast Mode to Normal Mode

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8.4.4 Sleep Mode

Sleep Mode is the power saving mode for the TLIN1431x-Q1. Even with extremely low current consumption in

this mode, the device can still wake up from the LIN bus through a wake up signal or local wake via WAKE pin.

Upon a wake event the SWE timer, t_{INACT_FS}, starts and the device enters restart mode. If UV_CCis still present

after this time, the device re-enters sleep mode. The LIN bus is filtered to prevent false wake up events. The

wake-up events must be active for the respective time periods (t_LINBUS).

In pin control mode, sleep mode is entered by setting EN low for longer than t_ENand TXD pin is low when

entered from normal mode.

In SPI control mode, setting register 8'h1D[7:6] = 01b transitions the device into sleep mode. If the reset counter

exceeds three, the device enters sleep mode from restart mode. The reset counter increments on an UV_CC

event, or a watchdog error event that causes the device to enter restart mode when fail-safe mode is disabled.

The reset counter must be cleared through a SPI command.

While the device is in sleep mode, the following conditions exist.

• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if

LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events

in case an external connection to the LIN bus is lost.

• The normal receiver is disabled.

• LIN wake up receiver is active.

• WAKE pin is active.

Sleep Mode

FSM Enabled

Sleep Mode

Fail-safe Mode

Restart Mode

V_CC= Off

WD = Off

SPI = Off

nRST = Low

nINT = Off

FSM Disabled

SWE time-out

SPI CMD

V_CC= Off

WD: Off

nRST = Low

Normal Mode

Restart Mode

Fail-safe Mode

Normal Mode

TSD

LIN = Off but WUP wake able

WAKE = On

Restart Mode

LIN = Off but WUP wake able

WAKE = Programmable but for us On

INH or WKRQ = Off

LIMP = As Programmed On or Off

HSS = Programming dependent

V_CCSC

Standby Mode

Fast Mode

INH or WKRQ = Off

LIMP = Off

OV_CC

HSS = Off

Restart counter

图8-34. Sleep Mode Pin Control

图8-35. Sleep Mode SPI Control

8.4.5 Standby Mode

This mode is entered from various other modes based upon which control method is implemented, the pin

control 图8-24 or SPI control 图8-25. The LIN bus responder node termination circuit is turned on when standby

mode is entered. Standby mode is signaled through a low level on RXD. See Standby Mode Application Note for

more application information.

When EN (in Pin Control Mode) is set high for longer than t_{FM_CHANGE}while the device is in standby mode the

device returns to normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are

enabled.

During power up, the device automatically enters standby mode from restart mode. EN has an internal pull-down

resistor ensuring EN is pulled low if the pin is left floating in the system.

In both pin and SPI modes, the watchdog is default on in standby mode. There is a long timeout initial window

that is t_INITWDthat a WD trigger event must take place. In SPI mode, watchdog can be disabled when entering

standby mode except for cases that the device has had a POR event.

The device automatically enters standby mode from restart mode when V_CC≥ UV_CCand t_{RSTN_act}time has

expired. When in SPI communication mode, the TLIN1431x-Q1 can enter standby mode by writing a 00 to

register 8'h1D[7:6] from normal or fast modes. The watchdog function is default on in standby mode. When using

SPI to configure the device, the watchdog function can be configured.

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Standby Mode

Faults

V_CC= On

WD = On (default)

SPI = On

nRST = High

nINT = On if enabled

LIN = Off

Restart Mode

FSM Enabled

Fail-safe Mode

Standby Mode

SPI CMD

V_CC= On

WD = On

nRST = High

Normal Mode

Restart Mode

Faults

Fast Mode

FSM Disabled

RXD = Indicates a wake event

WAKE = Default on

INH or WKRQ = High

LIMP = As programmed - On if failure

condition

LIN = Off

RXD = Indicates a wake event

WAKE = On

Restart Mode

WD, UVCC

Fast Mode

Restart Mode

WD

Normal Mode

INH or WKRQ = High

LIMP = Previous state

HSS = HSSC

Sleep Mode

Fail-safe Mode

Non-WD

HSS = Active

图8-36. Standby Mode Pin Control

图8-37. Standby Mode SPI Control

8.4.6 Restart Mode

Restart mode is a transitional mode. This mode can be entered from any of the other modes depending upon

whether fail-safe mode is disabled. In this mode, the LDO is ramping when coming from sleep mode or fail-safe

mode where the LDO was turned off, like a TSD event. Once V_CC≥ UV_CCfor t_{RSTN_act}(~2 ms), the device

enters standby mode. While in restart mode, the nRST pin is latched low. Each time restart mode is entered the

restart mode counter is incremented.

备注

The SWE timer starts when the device enters restart mode. If the SWE timer times out, the device

enters fail-safe mode. If fail-safe mode is disabled, the device enters sleep mode.

Faults

Restart Mode

FSM Enabled

V_CC= Ramping up (Entrance dependent)

V_CC= On (Entrance dependent)

SPI = Off

Reset counter

SWE time-out

nRST Pulse

Soft_RST

Init Mode

Restart Mode – Pin Control

WD = Off

FSM Disabled

UV_CC

nRST (Power up & Wake) = Low

nRST (other) = Pulled low for t_{NRST_TOG}

RXD = High

V_CC= Ramping up (Entrance dependent)

V_CC= On (Entrance dependent)

WD = Off

nRST (Power up & Wake event) = Low

nRST (other) = Pulled low for t_{NRST_TOG}

LIN = Off

WD Failure

nRST Pulse

Sleep Mode

Standby Mode

Faults

WD Failure

SPI = Off

nINT = High

LIN = Off

WAKE = Off

Sleep Mode

Wake Event

Sleep Mode

FSM Disabled

Sleep Mode

SWE timer

WAKE = Off

INH or WKRQ = High

LIMP = Same as previous Mode unless WD failure and

LIMP is on

Reset counter

Fail-safe Mode

INH or WKRQ = High

LIMP = Same as previous Mode

HSS = Programming dependent

Fail-safe Mode

SWE time-out

HSS = Off

图8-38. Restart Mode Pin Control

图8-39. Restart Mode SPI Control

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High

V_SUP

V_CC

High

WKRQ

/INH

Restart

Mode

Event/

Mode

WD failure

nRST, Soft reset

Standby

Mode

~200 ns

t_nRSTIN

nRST

Input

nRST

t_{NRST_TOG}

Output

RXD

Mode dependent

RXD latched low

Transceiver

备注

• A watchdog failure, soft reset or nRST event resets t_{NRST_TOG}to default value of typically 2 ms

• The typical time between the release of a nRST input pulse for device to enter restart mode is ~

200 ns

图8-40. Entering Restart Mode

8.4.6.1 Restart Counter

This counter is programed by register 8'h28[7:4] which sets the number of times restart can be entered before

transitioning to sleep or fail-safe mode, up to 14 times but should be programmed for greater than 1 to avoid

possible loops. The default value is 4. Register 8'h28[3:0] is the counter. To prevent the transition to sleep or fail-

safe mode, the counter should be cleared periodically. Entering sleep mode or fail-safe mode due to a meeting

the restart counter automatically clears the restart counter.

8.4.6.2 nRST Behavior in Restart Mode

The nRST output pin behavior depends upon the reason the device entered restart mode. When entered from

other modes due to a watchdog failure, soft reset or an external nRST toggle, the nRST pin is pulled low for

t_{nRST_TOG}which is a default pulse width of 2 ms. This pulse width can be configured to 15 ms by changing

register 8'h29[5] = 1b. In pin control, the pulse width on nRST is always nominally 15 ms for a watchdog failure.

Once the timer expires, the device enters standby mode. From power up, sleep and certain fail-safe modes, the

nRST behaves like the UV_CCevent, pulling nRST low until V_CC> UV_CCand t_{RSTN_act}times out. See 图 8-41 on

how the nRST pin behaves when entering restart mode.

The nRST pin is also a TLIN1431x-Q1 reset input which transitions the device into restart mode when the pin is

pulled low for t_nRSTIN

.

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Event

Restart Mode

SWE timer starts

Restart counter + 1

FSM

disabled

FSM

enabled

Yes

Fail-safe Mode

RSTRT CNTR

cleared

Sleep Mode

RSTRT CNTR

cleared

Counter

limit met?

No

Power or

Wake event

WD, soft reset,

nRST toggle

Reason

Entered

nRST pulled low

for t_{NRST_TOG}

nRST held low

V_CCUV_CCand

t_{RSTN_act}times out

Standby Mode

nRST: high

Note:

1. Wake event means entered from sleep or fail-safe modes

2. If SWE timer times out device will enter sleep or fail-safe mode

3. nRST toggle reason is an external toggle of nRST pin to reset device

4. A soft reset or external nRST toggle will reset t_{NRST_TOG}to default value, typically 2 ms

图8-41. nRST Behavior in Restart Mode

8.4.7 Fail-safe Mode

When the TLIN1431x-Q1 has certain fault conditions, the device enters a fail-safe mode (FSM). This feature can

be disabled in SPI control mode, but is always on in pin control mode. This mode turns on LIMP and brings all

other function into lower power mode states. Fault conditions are over-voltage on V_CC, thermal shutdown, V_CC

under-voltage events and reaching restart counter limit in SPI control mode. When entering FSM, a fail-safe

mode counter is incremented. The counter limit is set at register 8'h18[7:4], FSM_CNTR_SET and should be set

to greater than 1. To avoid unwanted actions the counter should be cleared by writing 0h to 8'h18[3:0]. If the limit

is reached a programmed action will be executed, register 8'h17[7:4], FSM_CNTR_ACT. Once the fault

conditions are cleared, the device can be put back into restart mode from a wake event. If a fault condition is still

in effect after the wake event the device enters sleep. If no wake event takes place, the device enters sleep

mode after the programmed SWE timer, t_{INACT_FS}, times out.

Fail-Safe Mode

Faults

Standby Mode

SWE timer expires

UV_CCunder-voltage

Fail-Safe Mode

V_CC= Fault dependent

Driver = Off

RXD = Fault dependent

Termination = Weak pullup

WD = Off

INH = On

WKRQ = Fault dependent

LIMP = On

Restart Mode

Faults cleared

& Wake event

V_CC= Fault dependent

Driver = Off

RXD = Floating

Termination = Weak pullup

WD = Off

INH = On

WKRQ = Fault dependent

LIMP = On

Restart Mode

Faults cleared

& Wake event

SWE timer expires

OV_CCover-voltage

V_CCSCSC Event

UV_CC

V_CCovervoltage

V_CCSC Event

Sleep Mode

Wake event &

Faults not cleared

or SWE time-out

Sleep Mode

Wake event &

Faults not cleared

or SWE time-out

TSD

WD Failure

Restart counter

TSD

HSS = Off

图8-42. Fail-safe Mode Pin Control

图8-43. Fail-safe Mode SPI Control

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备注

When the device enters fail-safe mode, the SWE timer automatically starts.

• If SWE timer times out, the device enters sleep mode

• If a wake event takes place prior to the SWE timer timing out, the device determines if fault is still

present.

– If fault is present, the device enters sleep mode.

– If fault has cleared, the device enters restart mode.

When fail-safe mode is entered due to a thermal shutdown (TSD), V_CCover-voltage (OV_CC) or a V_CC

short circuit (V_CCSC) event the following takes place:

• LDO is turned off

• If the device receives a wake event, the LDO is turned on for t_LDOONto determine if the TSD, OV_CC

or V_CCSCevent is still present.

– During this window, if a TSD or OV_CCis detected the device immediately enters sleep mode.

– At the end of t_LDOONwindow, if a V_CCSCis detected the device enters sleep mode.

• If fault is cleared, the device enters restart mode.

If the device enters fail-safe mode and V_CCis on, the t_LDOONtimer is started and expires before the

device transitions to restart mode.

8.4.8 Wake Up Events

There are three ways to wake-up from sleep mode depending upon control mode, pin or SPI:

1. Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on the

LIN bus where the dominant state is held for t_LINBUSfilter time. After this t_LINBUSfilter time has been met and

a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake-up event

eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground. Active for

both pin and SPI control modes.

2. Local wake up through EN being set high for longer than t_{MODE_CHANGE}. Active for pin control mode.

3. Local wake up through WAKE pin

• Being set high or low for longer than t_{MODE_CHANGE}. Active for both pin and SPI mode.

• Only active during on-time cyclic sense period. Active for SPI mode.

备注

• Remote and local wake up are also valid wake events when the device enters fail-safe mode. The

EN pin will not wake the device if it has entered fail-safe mode.

• When a wake event takes place and INH is selected, it is turned on with in t_{INH_SLP}

.

• When WKRQ is used, a wake event requires the LDO to be on and the voltage level to exceed 2 V.

Once this happens, the WKRQ pin ramps with V_CCuntil it expected voltage level.

8.4.8.1 Wake Up Request (RXD)

When the TLIN1431x-Q1 encounters a wake up event from the LIN bus the device transitions to restart mode. In

restart mode, the LDO is turned on and ramps until V_CC> UV_CCat which time the device enters either Normal

mode, Fast mode or Standby mode depending upon the device control method. In Restart mode, RXD is pulled

high. After V_CChas exceeded UV_CCfor t_{RSTN_act}, the device transitions to standby mode and RXD is latched low.

Once the device enters normal mode, the RXD pin releases the wake up request signal and the RXD pin then

reflects the receiver output from the LIN bus. RXD can be programmed to toggle low or high when in standby

mode from a wake event.

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8.4.8.2 Local Wake Up (LWU) via WAKE Terminal

The WAKE terminal is a ground referenced input terminal supporting high voltage wake inputs used for local

wake up (LWU) request via a voltage transition. The terminal triggers an LWU event on either a low to high or

high to low transition as it has bi-directional input thresholds. This terminal may be used with a switch to VSUP

or ground. If the terminal is not used it should be pulled to ground to avoid unwanted parasitic wake up events.

There are two methods for using the WAKE pin:

1. Static wake

2. Cyclic sensing wake

8.4.8.2.1 Static WAKE

The WAKE terminal defaults to bi-directional input but can be configured for rising edge and falling edge

transitions by using register 8'h11[7:6] WAKE_CONFIG (see 图 8-44 and 图 8-45). Once the device enters sleep

mode the WAKE terminal voltage level needs to be at either a low state or high state for t_WAKEbefore a state

transition for a WAKE input can be determined. A pulse width less than t_{WAKE_INVALID}is filtered out.

The LWU circuitry is active in sleep mode, standby and fail-safe modes. If a valid LWU event occurs, the device

transitions to restart mode. The LWU circuitry is not active in normal, fast and restart modes. To minimize system

level current consumption, the internal bias voltages of the terminal follows the state on the terminal with a delay

of t_WAKE. A constant low level on WAKE has an internal pull-down to ground. On power up, this may look like a

LWU event and could be flagged as such. The device provides a WAKE pin status change update using register

8'h11[5:4]. The status change will lock in a change in the WAKE pin and needs to be cleared.

t

t_WAKE

Wake

Threshold

Not Crossed

t

t_{WAKE_INVALID}

No Wake

UP

Local Wake Request

Wake UP

Wake

Local Wake Request

UV_CC

Cleared

WKRQ/INH

t_{RSTN_act}

RXD latched low

RXD is off and floating

RXD

t_{RSTN_act}

RXD is off and floating

RXD

RXD programmed to toggle

t_TOGGLE

Mode

nRST

Sleep Mode

Restart Mode

Standby Mode

t_{RSTN_act}

图8-44. Local Wake Up (LWU) - Rising Edge

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Wake

Threshold

Not Crossed

t

t_WAKE

t ≤ t_{WAKE_INVALID}

No Wake

UP

Local Wake Request

Wake UP

WAKE

Local Wake Request

UV_CC

Cleared

WKRQ/INH

t_{RSTN_act}

RXD latched low

RXD is off and floating

RXD

t_{RSTN_act}

RXD is off and floating

RXD programmed to toggle

t_TOGGLE

Mode

nRST

Sleep Mode

Restart Mode

Standby Mode

t_{RSTN_act}

图8-45. Local Wake Up (LWU) - Falling Edge

备注

These figures show the state of the RXD pin after a WAKE pin event. The transition to standby mode

is shown in the state diagrams but is based upon the following:

• PIN Mode: All must take place

– WAKE pin event recognized

– V_CCgoes above UV_CCfor > t_{RSTN_act}

– EN pin is High for > t_EN

• SPI Mode: All must take place

– WAKE pin event recognized

– V_CCgoes above UV_CCfor > t_{RSTN_act}

The WAKE terminal can be configured for a pulse, see 图 8-46, by using WAKE_CONFIG register 11h[7:6]. The

terminal can be configured to work off a pulse only. The pulse must be between t_{WK_WIDTH_MIN}and

t_{WK_WIDTH_MAX}, see 图 8-46. This figure provides three examples of pulses and whether the device will wake or

not wake. t_{WK_WIDTH_MIN}is determined by the value for t_{WK_WIDTH_INVALID}is set to in register 8'h11[3:2]. There

are two regions where

a

pulse may or may not be detected. By using register 8'h1B[1],

WAKE_WIDTH_MAX_DIS, the pulse mode can be configured as a filtered wake input. Writing a 1b to this bit

disables t_{WK_WIDTH_MAX}, and the WAKE input is based upon the configuration of register 8'h11[3:2] which selects

a t_{WK_WIDTH_INVALID}and t_{WK_WIDTH_MIN}value. A WAKE input of less than t_{WK_WIDTH_INVALID}is filtered out, and if

longer than t_{WK_WIDTH_MIN}INH turns on and device enters standby mode. The region between the two may or

may not be counted, see 图 8-47. Register 8'h12[7] determines the direction of the pulse or filter edge that is

recognized. The status of the WAKE pin can be determined from register 8'h11[5:4]. When a WAKE pin change

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takes place, the device registers the change as a rising edge or falling edge. This is latched until a 00b is written

to the bits.

t_{WK_WIDTH_MAX}

t_{WK_WIDTH_MIN}

Case 1

t_{WK_WIDTH_INVALID}

No

Detect

Pulse not

detected

May

Pulse detected

WAKE PIN

0ms

Wake pulse detected

t_{WK_WIDTH_MAX}

Case 2

t_{WK_WIDTH_MIN}

t_{WK_WIDTH_INVALID}

No

Detect

Pulse not

detected

May

Pulse detected

WAKE PIN

0ms

Wake pulse not detected

t_{WK_WIDTH_MAX}

Case 3

t_{WK_WIDTH_MIN}

t_{WK_WIDTH_INVALID}

No

Detect

Pulse not

detected

May

Pulse detected

WAKE PIN

0ms

Wake pulse not detected

图8-46. WAKE Pin Pulse Behavior

WAKE PIN

t_{WK_WIDTH_MIN}

t_{WK_WIDTH_INVALID}

INH PIN

Case 1

No

Detect

May

Wake detection

0ms

Filtered wake detected

WAKE PIN

INH PIN

Case 2

t_{WK_WIDTH_MIN}

t_{WK_WIDTH_INVALID}

No

Detect

May

Wake detecion

0ms

Filtered wake not detected

图8-47. WAKE Pin Filtered Behavior

8.4.8.2.2 Cyclic Sense Wake

Cyclic sense wake is a method using the high-side switch with the WAKE input pin to periodically check for a

WAKE pin state change in standby and sleep modes. In sleep mode, cyclic sense wake reduces the quiescent

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current of the device by reducing the WAKE circuitry to be active only during the on time of the HSS pin, see 图

8-48 as an example for this. Periodically, the HSS pin turns on applying V_SUPto the external local wake circuitry

and the device samples the state of the WAKE pin. Each time the WAKE pin is sampled, the current state is

compared to the previous state. If there has been a state change, the device wakes up and transitions to restart

mode; otherwise, it remains in sleep mode. See 图 8-49 for the timing diagram. In standby mode, the same

process is followed for determining a state change on the WAKE pin. A state change on the WAKE pin causes

the device to initiate an interrupt and the RXD pin is latched low. When entering standby or sleep mode, this

process is reset with the first HSS on time being the initial WAKE pin state and does not cause a wake event.

The wake time is based upon t_{WK_CYC}, which is the sampling window, as shown in Static WAKE. This HSS

period and on time are determined by setting timer1 register, 8'h25[7:0] or timer 2 register 8'h26[7:0]. The

sampling window, t_{WK_CYC}, is determined by register 8'h12[5].

V_BAT

V_SUP

470

Pull down on WKRQ/INH pin

100 nF

for digital level output

V_SUP

otherwise leave floating

V_DD33

100 nF

10 µF

V_CC

V_BATV_SUP

V_DD

WKRQ

100 k

HSS

3 k

SW

nCS

CLK

3.3 k

WAKE

LIMP

I/O

10 nF

SDI

SDO

Cyclic

sensing

configuration

nINT

MCU

V_DD

Responder

Node

10 k

nRST

V_SUP

Commander

Node

Pullup

FSO

DIV_ON

PV

1 k

LIN Bus

20 pF

LIN

LIN Controller

Or

SCI/UART

RXD

TXD

220 pF

GND

图8-48. Application Cyclic Sense Configuration

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High

V_SUP

HSS

t_{WK_CYC}

High

Switch

3^rdwake = high

State change

1^stwake = low

Low stored

2^ndwake = low

No change

WAKE

V_CC

Wakes up device

High

UV_CC

t_{RSTN_act}

High

nRST

Mode

Sleep

Mode

Restart

Mode

Standby

Mode

图8-49. Cyclic Sensing Timing

备注

When the device enters fail-safe mode and turns off the HSS pin, the WAKE pin reverts to static

mode, and must be reprogrammed for cyclic sensing when the device enters standby or normal mode.

8.4.9 Mode Transitions

When the device is transitioning between modes, the device needs the time t_{MODE_CHANGE}and t_NOMINITto allow

the change to fully propagate from the EN pin through the device into the new state.

8.5 Programming

The TLIN1431x-Q1 is 7-bit address access SPI communication port.

表8-9 shows a list of the registers in the device along with their respective addresses.

8.5.1 SPI Communication

The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip Select

Not), SDI (SPI Data In), SDO (SPI Data Out) and CLK (SPI Clock). Each SPI transaction is initiated by a seven

bit address with a R/W bit.

The SPI data input data on SDI is sampled on the low to high edge of CLK. The SPI output data on SDO is

changed on the high to low edge of CLK.

See 图8-50 and 图8-51 for read and write method.

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nCS

CLK

SDI

R/W

= 1

ADDRESS [6:0]

DATA [7:0]

SDO

图8-50. SPI Write

nCS

CLK

SDI

R/W

= 0

ADDRESS [6:0]

SDO

Filler byte

00h

DATA [7:0]

图8-51. SPI Read

8.5.1.1 Cyclic Redundancy Check

The TLIN1431x supports cyclic redundancy check (CRC) for SPI transactions and is default disabled. Register

8'h0A[0] can be used to enable this feature. The default polynomial supports AutoSAR CRC8H2F, X⁸+ X⁵+ X³+

X²+ X + 1, see 表 8-7. CRC8 according to SAE J1850 is also supported and can be selected at register

8'h0B[0].

When CRC is enabled, a filler byte of 00h is used to calculate the CRC value during a read/write operation, see

图8-52 and 图8-53.

表8-7. CRC8H27

SPI Transactions

CRC result width

Polynomial

8 bits

2Fh

FFh

No

Initial value

Input data reflected

Result data reflected

XOR value

No

FFh

DFh

42h

Check

Magic Check

表8-8. CRC8 SAE J1850

SPI Transactions

CRC result width

8 bits

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表8-8. CRC8 SAE J1850 (continued)

SPI Transactions

Polynomial

1Dh

FFh

No

Initial value

Input data reflected

Result data reflected

XOR value

No

FFh

4Bh

C4h

Check

Magic Check

nCS

CLK

SDI

R/W

= 1

8-bit CRC of Address

+ R/W + Data

ADDRESS [6:0]

DATA [7:0]

SDO

图8-52. CRC SPI Write

nCS

CLK

SDI

R/W

= 0

Filler Byte

Value = 00h

8-bit CRC of Address

+ R/W + Filler Byte

ADDRESS [6:0]

SDO

Filler Byte

Value = 00h

8-bit CRC of Filler

Byte + Data

DATA [7:0]

图8-53. CRC SPI Read

8.5.1.2 Chip Select Not (nCS)

This input pin is used to select the device for a SPI transaction. The pin is active low, so while nCS is high the

SPI Data Output (SDO) pin of the device is high impedance allowing an SPI bus to be designed. When nCS is

low, the SDO driver is activated and communication may be started. The nCS pin is held low for a SPI

transaction.

8.5.1.3 Serial Clock Input (CLK)

This input pin is used to input the clock for the SPI to synchronize the input and output serial data bit streams.

The SPI Data Input is sampled on the rising edge of CLK and the SPI Data Output is changed on the falling

edge of the CLK. See 图8-54 .

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ACTIONs: C = data capture, S = data shi ,

L = load data out, P = process captured data

SPI CLOCKING

MODE 0 (CPOL = 0, CPHA = 0)

nCS

CLK

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SDI, SDO

ACTION

L

C

S

C

S

C

S

C

S

C

S

C

S

C

S

C

L

C

S

C

S

C

S

C

S

C

S

C

S

C

S

C

P

INTERNAL

CLK

INTERNAL_CLK = !CS xor CLK

图8-54. SPI Clocking

8.5.1.4 Serial Data Input (SDI)

This input pin is used to shift data into the device. Once the SPI is enabled by a low on nCS, the SDI samples

the input shifted data on each rising edge of the SPI clock (SCK). The data is shifted into an 8-bit shift register.

After eight (8) clock cycles and shifts, the addressed register is read giving the data to be shifted out on SDO.

After eight clock cycles, the shift register is full and the SPI transaction is complete. If the command code is a

write, the new data is written into the addressed register. When nCS has a falling edge, there will be 16-bits

(CRC disabled) or 24-bits (CRC enabled) shifted in by CLK, at which time the nCS has a rising edge to deselect

the device. 16 Clock cycles are required to shift 16-bits (CRC disabled) and 24 clock cycles for 24-bits (CRC

enabled) during one SPI transaction (nCS is low). If more or less clock cycles than these are used, the SPIERR

flag will be set. If CRC was enabled the CRCERR flag will be set. When writing to the device, any transaction

other than 16 or 24 clock cycles could result in behavior that is outside of the specification.

8.5.1.5 Serial Data Output (SDO)

This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on nCS

and a read command given, on the first falling edge of CLK, the shifting out of the data with each falling edge on

CLK until all 8 bits have been shifted out the shift register.

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8.6 Registers

The following tables contain the registers that the device use during SPI communication.

表 8-9 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in 表

8-9 should be considered as reserved locations and the register contents should not be modified.

表8-9. Device Registers

Address

Acronym

Register Name

Section

Go

0h + formula DEVICE_ID_y

Device Part Number

8h

REV_ID_MAJOR

REV_ID_MINOR

CRC_CNTL

Major Revision

9h

Minor Revision

Ah

SPI CRC control

Bh

CRC_POLY_SET

Scratch_Pad_SPI

WAKE_PIN_CONFIG1

WAKE_PIN_CONFIG2

WD_CONFIG_1

WD_CONFIG_2

WD_INPUT_TRIG

WD_RST_PULSE

FSM_CONFIG

FSM_CNTR

Sets SPI CRC polynomial

Read and Write Test Register SPI

WAKE pin configuration 1

WAKE pin configuration 2

Watchdog configuration 1

Watchdog configuration 2

Watchdog input trigger

Fh

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

28h

29h

50h

51h

52h

53h

56h

57h

58h

5Ah

5Eh

Watchdog output pulse width

Fail safe mode configuration

Fail safe mode counter

DEVICE_RST

DEVICE_CONFIG1

DEVICE_CONFIG2

SWE_TIMER

LIN_CNTL

Device reset

Device configuration 1

Device configuration 2

Sleep wake error timer configuration

LIN transceiver control

HSS_CNTL

High side switch 1 and 2 control

Pulse width modulation frequency select

Pulse width modulation duty cycle two MSB select

Pulse width modulation duty cycle eight LSB select

Pulse width modulation frequency select

Pulse width modulation duty cycle two MSB select

Pulse width modulation duty cycle eight LSB select

High side switch timer 1 configuration

High side switch timer 2configuration

Restart counter configuration

nRST and FSO pin control

Global Interrupts

PWM1_CNTL1

PWM1_CNTL2

PWM1_CNTL3

PWM2_CNTL1

PWM2_CNTL2

PWM2_CNTL3

TIMER1_CONFIG

TIMER2_CONFIG

RSRT_CNTR

nRST_CNTL

INT_GLOBAL

INT_1

Interrupts

INT_2

Interrupts

INT_3

Interrupts

INT_EN_1

Interrupt enable for INT_1

Interrupt enable for INT_2

Interrupt enable for INT_3

Interrupts

INT_EN_2

INT_EN_3

INT_4

INT_EN_4

Interrupt enable for INT_4

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Complex bit access types are encoded to fit into small table cells. 表 8-10 shows the codes that are used for

access types in this section.

表8-10. Device Access Type Codes

Access Type

Code

Description

Read Type

R

Read

RH

H

R

Set or cleared by hardware

Read

Write Type

H

Set or cleared by hardware

Write

W

W1C

1C

W

1 to clear

Write

Reset or Default Value

-n

Value after reset or the default

value

Register Array Variables

i,j,k,l,m,n

When these variables are used in

a register name, an offset, or an

address, they refer to the value of

a register array where the register

is part of a group of repeating

registers. The register groups

form a hierarchical structure and

the array is represented with a

formula.

y

When this variable is used in a

register name, an offset, or an

address it refers to the value of a

register array.

8.6.1 DEVICE_ID_y Register (Address = 0h + formula) [reset = 0h]

DEVICE_ID_y is shown in 图8-55 and described in 表8-11.

Return to Summary Table.

Device Part Number

Offset = 0h + y; where y = 0h to 7h

图8-55. DEVICE_ID_y Register

7

6

5

4

3

2

1

0

DEVICE_ID

R-0b

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表8-11. DEVICE_ID_y Register Field Descriptions

Bit

Field

DEVICE_ID

Type

Reset

Description

7-0

R

0b

The DEVICE_ID[1:8] registers determine the part number of the

device.

The reset values and value of each DEVICE_ID register are listed for

the corresponding register address

Address 00h = 54h = T

Address 01h = 4Ch = L

Address 02h = 49h = I

Address 03h = 31h = 1

Address 04h = 34h = 4

Address 05h = 33h = 3

Address 06h = 31h = 1

Address 07h = 33h = 3 for 3.3 V LDO

Address 07h = 35h = 5 for 5 V LDO

8.6.2 REV_ID_MAJOR Register (Address = 8h) [reset = 01h]

REV_ID_MAJOR is shown in 图8-56 and described in 表8-12.

Return to Summary Table.

Major Revision

图8-56. REV_ID_MAJOR Register

7

6

5

4

3

2

1

0

Major_Revision

R-01h

表8-12. REV_ID_MAJOR Register Field Descriptions

Bit

7-0

Field

Major_Revision

Type

Reset

Description

R

01h

Major die revision

8.6.3 REV_ID_MINOR Register (Address = 9h) [reset = 0h]

REV_ID_MINOR is shown in 图8-57 and described in 表8-13.

Return to Summary Table.

Minor Revision

图8-57. REV_ID_MINOR Register

7

6

5

4

3

2

0

Minor_Revision

R-0b

表8-13. REV_ID_MINOR Register Field Descriptions

Bit

7-0

Field

Minor_Revision

Type

Reset

Description

R

0b

Minor die revision

8.6.4 CRC_CNTL Register (Address = Ah) [reset = 0h]

CRC_CNTL is shown in 图8-58 and described in 表8-14.

Return to Summary Table.

SPI CRC register controls the CRC function. CRC_DIS bit can disable the CRC function.

图8-58. CRC_CNTL Register

7

6

5

4

3

2

0

CRC_CNTL_RSVD

CRC_EN

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图8-58. CRC_CNTL Register (continued)

R-0b

R/W-0b

表8-14. CRC_CNTL Register Field Descriptions

Bit

7-1

0

Field

Type

Reset

Description

CRC_CNTL_RSVD

CRC_EN

R

0b

CRC control reserved bits

R/W

0b

CRC enable

0b = Disable

1b = Enable

8.6.5 CRC_POLY_SET (Address = Bh) [reset = 00h]

CRC_POLY_SET is shown 图8-59 and described in 表8-15.

Return to Summary Table.

This register will set which polynomial will be set for CRC. Defaults to AutoSAR 8-bit 0x2F.

图8-59. CRC_POLY_SET Register

7

6

5

4

RSVD

R

3

2

1

0

POLY_8_SET

R/W-0b

表8-15. CRC_POLY_SET Register Field Description

Bit

Field

Type

Reset

00h

0b

Description

7-1

0

RSVD

R

Reserved

POLY_8_SET

R/W

CRC polynomial select

0b = X^8 + X^5 + X^3 + X^2 + X + 1 (0x2F)

1b = X^8 + X^4 + X^3 + X^2 + 1 (0x1D SAE J1850)

8.6.6 Scratch_Pad_SPI Register (Address = Fh) [reset = 0h]

Scratch_Pad_SPI is shown in 图8-60 and described in 表8-16.

Return to Summary Table.

Read and Write Test Register SPI

图8-60. Scratch_Pad_SPI Register

7

6

5

4

3

2

1

0

Scratch_Pad

R/W-0b

表8-16. Scratch_Pad_SPI Register Field Descriptions

Bit

7-0

Field

Scratch_Pad

Type

Reset

Description

R/W

0b

Read and Write Test Register SPI

8.6.7 WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 04h]

WAKE_PIN_CONFIG1 is shown in 图8-61 and described in 表8-17.

Return to Summary Table.

Register to configure the behavior of the WAKE pin.

图8-61. WAKE_PIN_CONFIG1 Register

7

6

5

4

3

2

1

0

WAKE_CONFIG

WAKE_STAT

WAKE_WIDTH_INVALID

WAKE_WIDTH_MAX

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图8-61. WAKE_PIN_CONFIG1 Register (continued)

R/W-00b

R/W0C/H-00b

R/W-01b

R/W-00b

表8-17. WAKE_PIN_CONFIG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

WAKE_CONFIG

R/W

00b

Wake pin configuration: Note: Pulse requires more programming

00b = Bi-directional - either edge

01b = Rising edge

10b = Falling edge

11b = Pulse

5-4

3-2

1-0

WAKE_STAT

R/W0C/H

00b

01b

00b

Wake pin status

00b = No change

01b = Rising edge

10b = Falling edge

11b = Pulse

WAKE_WIDTH_INVALID R/W

Pulses less than or equal to these pulses are considered invalid

00b = 5 ms and sets t_{WAKE_WIDTH_MIN}to 10 ms

01b = 10 ms and sets t_{WAKE_WIDTH_MIN}to 20 ms

10b = 20 ms and sets t_{WAKE_WIDTH_MIN}to 40 ms

11b = 40 ms and sets t_{WAKE_WIDTH_MIN}to 80 ms

WAKE_WIDTH_MAX

R/W

Maximum WAKE pin input pulse width to be considered valid.

00b = 750 ms

01b = 1000 ms

10b = 1500 ms

11b = 2000 ms

8.6.8 WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 2h]

WAKE_PIN_CONFIG2 is shown in 图8-62 and described in 表8-18.

Return to Summary Table.

Device wake configuration register

图8-62. WAKE_PIN_CONFIG2 Register

7

6

5

4

3

2

1

0

WAKE_PULSE WAKE_SENSE TWK_CYC_SE

nINT_SEL

R/W-0b

RXD_WK_CON

FIG

WAKE_LEVEL

R/W-10b

_CONFIG

T

R/W-0b

R/W/H-0b

R/W-0b

表8-18. WAKE_PIN_CONFIG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

WAKE_PULSE_CONFIG R/W

0b

Set WAKE pin expected pulse direction

0b = Low –> High –> Low

1b = High –> Low –> High

6

WAKE_SENSE

R/W/H

0b

WAKE pin configured for static or cyclic sensing wake

0b = Static

1b = Cyclic

备注

When Cyclic sensing is selected and the device goes to

fail-safe mode it will automatically change to static

sensing. If cyclic sensing is needed it will have to be

reprogrammed.

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表8-18. WAKE_PIN_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

TWK_CYC_SET

R/W

0b

Sets the t_{WK_CYC}time (µs) for sampling the WAKE pin status (used

for cyclic sensing)

0b = 30

1b = 75

备注

NOTE: t_{WK_CYC_SET}works with timer1 and timer2. When

using 75 µs t_{WK_CYC}, 100 µs TIMER1/2_ON_WIDTH

cannot be used.

4-3

nINT_SEL

R/W

00b

nINT configuration selection: active low

00b = Global interrupt

01b = Watchdog failure output

10b = Reserved

11b = Wake request

2

RXD_WK_CONFIG

WAKE_LEVEL

R/W

0b

Configures RXD pin behavior from a wake event

0b = Pulled low

1b = Toggle

1-0

10b

WAKE pin threshold level; Mid-point value in 2 V window.

00b = 2.5 V

01b = 2.8 V

10b = 3 V

11b = 3.3 V

8.6.9 WD_CONFIG_1 Register (Address = 13h) [reset = 90h]

WD_CONFIG_1 is shown in 图8-63 and described in 表8-19.

Return to Summary Table.

Watchdog configuration register.

图8-63. WD_CONFIG_1 Register

7

6

5

4

3

2

1

0

WD_CONFIG

R/W-10b

WD_PRE

R/W-01b

RSVD

R-0000b

表8-19. WD_CONFIG_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-4

3-0

WD_CONFIG

WD_PRE

RSVD

R/W

10b

Watchdog configuration

00b = Disabled

01b = Timeout

10b = Window

11b = Reserved

R/W

R

01b

Watchdog prescalar

00b = Factor 1

01b = Factor 2

10b = Factor 3

11b = Factor 4

0000b

Reserved

8.6.10 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]

WD_CONFIG_2 is shown in 图8-64 and described in 表8-20.

Return to Summary Table.

Watchdog timer and error counter register.

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图8-64. WD_CONFIG_2 Register

7

6

5

4

3

2

1

0

WD_TIMER

R/W-000b

WD_ERR_CNT

RH-0001b

WD_STBY_DIS

R/W-0b

表8-20. WD_CONFIG_2 Register Field Descriptions

Bit

Field

WD_TIMER

Type

Reset

Description

7-5

R/W

000b

Sets window or timeout times based upon the WD_PRE setting

See WD_TIMER table

4-1

0

WD_ERR_CNT

WD_STBY_DIS

RH

0001b

0b

Watchdog error counter

Running count of errors up to 15 errors

R/W

Watchdog disable in standby mode

0b = Enabled

1b = Disabled

8.6.11 WD_INPUT_TRIG Register (Address = 15h) [reset = 0h]

WD_INPUT_TRIG is shown in 图8-65 and described in 表8-21.

Return to Summary Table.

Writing FFh resets WD timer if accomplished at appropriate time.

图8-65. WD_INPUT_TRIG Register

7

6

5

4

3

2

1

0

WD_INPUT

R/W1C-00h

表8-21. WD_INPUT_TRIG Register Field Descriptions

Bit

7-0

Field

WD_INPUT

Type

Reset

Description

R/W1C

00h

Write FFh to trigger WD

8.6.12 WD_RST_PULSE Register (Address = 16h) [reset = 40h]

WD_RST_PULSE is shown in 图8-66 and described in 表8-22.

Return to Summary Table.

Sets the watchdog error counter value.

图8-66. WD_RST_PULSE Register

7

6

5

4

3

2

1

0

WD_ERR_CNT_SET

R/W-01b

RSVD

R-000000b

表8-22. WD_RST_PULSE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

WD_ERR_CNT_SET

R/W

01b

Sets the watchdog event error counter that upon reaching the count

value, will cause the watchdog action.

00b = Immediate trigger on each WD fail

01b = Triggers when counter reaches 5

10b = Triggers when counter reaches 9

11b = Triggers when counter reaches 15

5-0

RSVD

R

000000b

Reserved

8.6.13 FSM_CONFIG Register (Address = 17h) [reset = 0h]

FSM_CONFIG is shown in 图8-67 and described in 表8-23.

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Return to Summary Table.

Configures the fail-safe mode

图8-67. FSM_CONFIG Register

7

6

5

4

3

2

1

0

FS_CNTR_ACT

R/W-0000b

FS_STAT

RH-000b

FSM_DIS

R/W-0b

表8-23. FSM_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

FSM_CNTR_ACT

R/W

0000b

Action if fail safe counter exceeds programmed value

000b = Disabled

0001b = Pull WKRQ/INH low for 1 s

0010b = Perform soft reset

0011b = Perform hard reset - POR

0100b = Stop responding to wake events and go to sleep until power

cycle reset

0101b = Reserved

0110b = Reserved

0111b = Reserved

1001b = Turn off VCC for 300 ms and set interrupt

备注

•

If LIMP is configured as INH then 0001b will impact

cause the LIMP pin to go low for 1 s.

All other values reserved

3-1

FSM_STAT

RH

000b

Reason for entering failsafe mode

000b = Not in FS mode

001b = Thermal shut down event

010b = Reserved

011b = UV_CC

100b = OV_CC

101b = V_CCSC

110b = Watchdog failure

111b = Restart counter exceeded

These values are held until cleared by writing 0h to

FSM_CNTR_STAT

0

FSM_DIS

R/W

0b

Fail safe mode disable: Excludes power up fail safe

0b = Enabled

1b = Disabled

8.6.14 FSM_CNTR Register (Address = 18h) [reset = 0h]

FSM_CNTR is shown in 图8-68 and described in 表8-24.

Return to Summary Table.

Set fail safe counter and status

图8-68. FSM_CNTR Register

7

6

5

4

3

2

1

0

FSM_CNTR_SET

R/W-0h

FSM_CNTR_STAT

RH-0h

表8-24. FSM_CNTR Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

FSM_CNTR_SET

R/W

0h

Sets the number of times FS mode enters before action taken. Value

is one less than the number of times FS mode is entered. Range is

0-15, representing entering fail-safe mode 1-16 times.

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表8-24. FSM_CNTR Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

FSM_CNTR_STAT

RH

0h

Reads back the number of time FSM has been entered in a row up

to 15. Can be cleared by writing 0h.

8.6.15 DEVICE_RST Register (Address = 19h) [reset = 0h]

DEVICE_RST is shown in 图8-69 and described in 表8-25.

Return to Summary Table.

Forces a soft or hard reset.

图8-69. DEVICE_RST Register

7

6

5

4

3

2

1

0

RESERVED

R-00h

SF_RST

R/W1C-0b

HD_RST

R/W1C-0b

表8-25. DEVICE_RST Register Field Descriptions

Bit

Field

Type

Reset

00h

0b

Description

7-2

1

RESERVED

SF_RST

R

Reserved

R/W1C

Soft Reset: Writing a 1 causes a soft reset. Device registers return to

default values while keeping INH on.

0

HD_RST

R/W1C

0b

Hard Reset: Forces a power on reset when writing a 1.

备注

NOTE: This will set the PWRON interrupt flag.

8.6.16 DEVICE_CONFIG (Address = 1Ah) [reset = 80h]

DEVICE_CONFIG is shown in 图8-70 and described in 表8-26

Return to Summary Table.

Enables SPI to work in sleep mode if V_IOis available.

WKRQ/INH and LIMP pin configuration.

图8-70. DEVICE_CONFIG Register

7

6

5

4

3

2

1

0

WKRQ_POL_S WKRQ_INH_DI INH_LIMP_SEL

LIMP_DIS

LIMP_SEL_RESET

R/W - 00b

LIMP_RESET

RSVD

EL

S

R/W-1b

R/W-0b

R/W - 0b

R/W1C - 0b

R - 0b

表8-26. DEVICE_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

WKRQ_POL_SEL

WKRQ_INH_DIS

INH_LIMP_SEL

R/W

1b

Selects the polarity for the WKRQ pin

0b = Low

1b = High

6

5

R/W

0b

WKRQ/INH pin disable

0b = Enabled

1b = Disabled

Pin function select function of INH pin

0b = INH

1b = LIMP

Note: This only works if WKRQ/INH pin is configured for INH at

power-up. If pin is WKRQ writing to this bit will be ignored.

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表8-26. DEVICE_CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4

LIMP_DIS

R/W

0b

LIMP pin disable

0b = Enabled

1b = Disabled

3-2

LIMP_SEL_RESET

R/W

0b

Selects the method to reset/turnoff the LIMP pin

00b = On third successful input trigger the error counter receives

01b = First correct input trigger

10b = SPI write to 8'h1A[1] = 1

11b = Reserved

1

0

LIMP_RESET

RSVD

R/W1C

R

0b

LIMP reset

Writing a one to this location resets the LIMP pin to off state and bit

automatically clears

Reserved

8.6.17 DEVICE_CONFIG2 (Address = 1Bh) [reset = 0h]

DEVICE_CONFIG2 is shown in 图8-71 and described in 表8-27

Return to Summary Table.

LIMP pin configuration and control.

图8-71. DEVICE_CONFIG2 Register

7

6

5

4

3

2

1

0

LIMP_HSS_SEL

LIMP_HSS_CNTL

R/W-000b

LIMP_HSS_ON WAKE_WIDTH

_MAX_DIS

RSVD

R/W-00b

R/W-0b

R-0b

表8-27. DEVICE_CONFIG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

LIMP_HSS_SEL

R/W

00b

Selects LIMP pin function

00b = LIMP

01b = High side switch

10b = INH

11b = Reserved

5-3

LIMP_HSS_CNTL

R/W

000b

Selects the method of control for the LIMP pin when configured as a

high side switch

000b = On/Off

001b = PWM1

010b = PWM2

011b = Timer1

100b = Timer2

101b - 111b = Reserved

2

1

0

LIMP_HSS_ON

R/W

R

0b

When LIMP is configured as HSS and control is On/Off this bit turns

on or off the LIMP pin.

0b = Off

1b = On

WAKE_WIDTH

_MAX_DIS

Disables the Max limit, t_{WK_PULSE_WIDTH_MAX}detection when pulse is

selected for WAKE pin wake up.

0b = Enabled

1b = Disabled

RSVD

Reserved

8.6.18 SWE_TIMER (Address = 1Ch) [reset = 30h]

SWE_TIMER is shown in 图8-72 and described in 表8-28

Return to Summary Table.

Sleep wake error timer configuration. Power up always sets to default value.

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图8-72. SWE_TIMER Register

7

6

5

4

3

2

1

RSVD

R

0

SWE_DIS

R/W-0b

SWE_TIMER_SET

R/W-0110b

表8-28. SWE_TIMER Register Field Descriptions

Bit

Field

SWE_DIS

Type

Reset

Description

7

R/W

0b

Sleep wake error disable: NOTE: This disables the device from

starting the t_{INACT_FS}timer. If enabled, a SPI read or write must take

place within this window or the device will go back to sleep.

0b = Enabled

1b = Disabled

6-3

SWE_TIMER_SET

R/W

0110b

Sets the timer used for t_{INACT_FS}(minutes)

0000b = 2

0001b = 2.5

0010b = 3

0011b = 3.5

0100b = 4

0101b = 4.5

0110b = 5 (default)

0111b = 5.5

1000b = 6

1001b = 6.5

1010b = 8

1011b = 8.5

1100b = 10

1101b = 0.5

1111b = 1

2-0

RSVD

R

0b

Reserved

8.6.19 LIN_CNTL (Address = 1Dh) [reset = 00h]

LIN_CNTL is shown in 图8-73 and described in 表8-29

Return to Summary Table.

LIN transceiver mode and DTO control. Port 1 is the TLIN1431x-Q1 LIN control.

图8-73. LIN_CNTL Register

7

6

5

4

3

2

1

0

LIN_MODE

R/W/H-00b

LIN_DTO_DIS

R/W - 0b

LIN_RSVD

R - 00000b

表8-29. LIN_CNTL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

LIN_MODE

R/W/H

00b

Port 1 LIN mode control

00b = Standby mode

01b = Sleep Mode

10b = Normal Mode

11b = Fast Mode

5

LIN_DTO_DIS

LIN_RSVD

R/W

R

0b

Port 1 LIN dominant state timeout disable

0b = Enabled

1b = Disabled

4-0

00000b

Reserved

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8.6.20 HSS_CNTL (Address = 1Eh) [reset = 0h]

HSS_CNTL is shown in 图8-74 and described in 表8-30

Return to Summary Table.

HSS high side switch control.

图8-74. HSS_CNTL Register

7

6

5

4

3

2

1

0

HSS_EN

R/W-0b

HSS_CNTL

R/W-000b

HSS_RSVD

R-0000b

表8-30. HSS_CNTL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

HSS_EN

R/W

0b

High side switch, HSS, enable

0b = Disabled

1b = Enabled

6-4

HSS_CNTL

R/W

000b

Control for HSS

000b = On/Off

001b = PWM1

010b = PWM2

011b = Timer1

100b = Timer2

101b = HSSC

110b - 111b = Reserved

Note: selecting HSSC control disables FSO output capability

3-0

HSS_RSVD

R/W

0000b

Reserved

8.6.21 PWM1_CNTL1 (Address = 1Fh) [reset = 0h]

PWM1_CNTL1 is shown in 图8-75 and described in 表8-31

Return to Summary Table.

Sets the pulse width modulation frequency, PWM1.

图8-75. PWM1_CNTL1 Register

7

6

5

4

3

2

1

0

PWM1_FREQ

R/W-0b

PWM1_FREQ_RSVD

R-0b

表8-31. PWM1_CNTL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PWM1_FREQ

R/W

0b

PWM frequency select (Hz)

0b = 200

1b = 400

6-0

PWM1_FREQ_RSVD

R

0b

Reserved

8.6.22 PWM1_CNTL2 (Address = 20h) [reset = 0h]

PWM1_CNTL2 is shown in 图8-76 and described in 表8-32

Return to Summary Table.

Set the two most significant bit for the 10-bit PWM1. These work with register h'21 PWM1_CNTL3.

图8-76. PWM1_CNTL2 Register

7

6

5

4

3

2

1

0

PWM1_RSVD

PWM1_DC_MSB

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图8-76. PWM1_CNTL2 Register (continued)

R-0b

R/W-00b

表8-32. PWM1_CNTL2L Register Field Descriptions

Bit

7-2

1-0

Field

Type

Reset

Description

PWM1_RSVD

R

0b

Reserved

PWM1_DC_MSB

R/W

00b

Most significant two bits for 10-bit PWM1 duty cycle select. Works

with 'h21[7:0]

00b = 100% off when used with 'h21[7:0] and it is 00h

xxb = on time with an increase of ~ 0.1% when used with 'h21[7:0]

11b = 100% of when used with 'h21[7:0] and it is FFh

备注

Minimum on-time during PWM is limited to the on and off-time of the high side switch. This will make

certain PWM values unusable like 00 0000 0001.

8.6.23 PWM1_CNTL3 (Address = 21h) [reset = 00h]

PWM1_CNTL3 is shown in 图8-77 and described in 表8-33

Return to Summary Table.

Bits 0 - 7 of the 10-bit PWM1. Used with register h'20[1:0] PWM1_CNTL2.

图8-77. PWM1_CNTL3 Register

7

6

5

4

3

2

1

0

PWM1_DC

R/W-00h

表8-33. PWM1_CNTL3 Register Field Descriptions

Bit

Field

PWM1_DC

Type

Reset

Description

7

R/W

00h

Bits 0 - 7 of the 10-bit PWM1

00h = 100% off when used with 'h20[1:0] = 00b

xxh = On time with an increase of ~ 0.1% when used with 'h20[1:0]

FFh = 100% on when used with 'h20[1:0] = 11b

8.6.24 PWM2_CNTL1 (Address = 22h) [reset = 0h]

PWM2_CNTL1 is shown in 图8-78 and described in 表8-34

Return to Summary Table.

Sets the pulse width modulation frequency, PWM2.

图8-78. PWM2_CNTL1 Register

7

6

5

4

3

2

1

0

PWM2_FREQ

R/W-0b

PWM2_FREQ_RSVD

R-0b

表8-34. PWM2_CNTL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PWM2_FREQ

R/W

0b

PWM frequency select (Hz)

0b = 200

1b = 400

6-0

PWM2_FREQ_RSVD

R

0b

Reserved

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8.6.25 PWM2_CNTL2 (Address = 23h) [reset = 0h]

PWM2_CNTL2 is shown in 图8-79 and described in 表8-35

Return to Summary Table.

Set the two most significant bit for the 10-bit PWM2. These work with register h'24 PWM2_CNTL3.

图8-79. PWM2_CNTL2 Register

7

6

5

4

3

2

1

0

PWM2_RSVD

R-0b

PWM2_DC_MSB

R/W-00b

表8-35. PWM2_CNTL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1-0

PWM2_RSVD

R

0b

Reserved

PWM2_DC_MSB

R/W

00b

Most significant two bits for 10-bit PWM2 duty cycle select. Works

with 'h24[7:0]

00b = 100% off when used with 'h24[7:0] and it is 00h

xxb = on time with an increase of ~ 0.1% when used with 'h24[7:0]

11b = 100% of when used with 'h24[7:0] and it is FFh

8.6.26 PWM2_CNTL3 (Address = 24h) [reset = 0h]

PWM2_CNTL3 is shown in 图8-80 and described in 表8-36

Return to Summary Table.

Bits 0 - 7 of the 10-bit PWM2. Used with register h'23[1:0] PWM2_CNTL2.

图8-80. PWM2_CNTL3 Register

7

6

5

4

3

2

1

0

PWM2_DC

R/W-00h

表8-36. PWM2_CNTL3 Register Field Descriptions

Bit

7-0

Field

PWM2_DC

Type

Reset

Description

R/W

00h

Bits 0 - 7 of the 10-bit PWM2

00h = 100% off when used with 'h23[1:0] = 00b

xxh = On time with an increase of ~ 0.1% when used with 'h23[1:0]

FFh = 100% on when used with 'h23[1:0] = 11b

备注

Minimum on-time during PWM is limited to the on and off-time of the high side switch. This will make

certain PWM values unusable like 00 0000 0001.

8.6.27 TIMER1_CONFIG (Address = 25h) [reset = 00h]

TIMER1_CONFIG is shown in 图8-81 and described in 表8-37

Return to Summary Table.

Sets timer 1 period and on time. Careful selection is important as selecting a 200ms on width and a 10ms period

is not possible.

图8-81. TIMER1_CONFIG Register

7

6

5

4

3

2

1

0

TIMER1_ON_WIDTH

TIMER1_RSVD

TIMER1_PERIOD

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图8-81. TIMER1_CONFIG Register (continued)

R/W-0h

R-0b

R/W-000b

表8-37. TIMER1_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

TIMER1_ON_WIDTH

R/W

0b

Sets the high side switch on time (ms) for timer 1

0000b = Off (HSS is high impedance)

0001b = 0.1

0010b = 0.3

0011b = 0.5

0100b = 1

0101b = 10

0110b = 20

0111b = 30

1000b = 40

1001b = 50

1010b = 60

1011b = 80

1100b = 100

1101b = 150

1110b = 200

1111b = On (HSS is on 100%)

备注

NOTE: t_{WK_CYC}which is set by t_{WK_CYC_SET}works with

these times to determine if a state change has taken

place on the WAKE pin. When t_{WK_CYC}is set at 65 µs

the 100 µs on width time cannot be used.

3

TIMER1_RSVD

R

0b

Reserved

2-0

TIMER1_PERIOD

R/W

Sets the timer period (ms) for timer 1

000b = 10

001b = 20

010b = 50

011b = 100

100b = 200

101b = 500

110b = 1000

111b = 2000

8.6.28 TIMER2_CONFIG (Address = 26h) [reset = 00h]

TIMER2_CONFIG is shown in 图8-82 and described in 表8-38

Return to Summary Table.

Sets timer 2 period and on time. Careful selection is important as selecting a 200ms on width and a 10ms period

is not possible.

图8-82. TIMER2_CONFIG Register

7

6

5

4

3

2

1

0

TIMER2_ON_WIDTH

R/W-0h

TIMER2_RSVD

R-0b

TIMER2_PERIOD

R/W-000b

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表8-38. TIMER2_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

TIMER2_ON_WIDTH

R/W

0b

Sets the high side switch on time (ms) for timer 2

0000b = Off (HSS is high impedance)

0001b = 0.1

0010b = 0.3

0011b = 0.5

0100b = 1

0101b = 10

0110b = 20

0111b = 30

1000b = 40

1001b = 50

1010b = 60

1011b = 80

1100b = 100

1101b = 150

1110b = 200

1111b = On (HSS is on 100%)

备注

NOTE: t_{WK_CYC}which is set by t_{WK_CYC_SET}works with

these times to determine if a state change has taken

place on the WAKE pin. When t_{WK_CYC}is set at 65 µs

the 100 µs on width time cannot be used.

3

TIMER2_RSVD

R

0b

Reserved

2-0

TIMER2_PERIOD

R/W

Sets the timer period (ms) for timer 2

000b = 10

001b = 20

010b = 50

011b = 100

100b = 200

101b = 500

110b = 1000

111b = 2000

8.6.29 RSRT_CNTR (Address = 28h) [reset = 40h]

RSRT_CNTR is shown in 图8-83 and described in 表8-39

Return to Summary Table.

Restart mode counter set and counter. Determines the number of times the device has entered restart mode and

when it will transition to sleep mode once programmed counter value has been reached. Counter should be

reset often to avoid this transition.

图8-83. RSRT_CNTR Register

7

6

5

4

3

2

1

0

RSRT_CNTR_SEL

R/W-4h

RSRT_CNTR

R/W1C-0h

表8-39. RSRT_CNTR Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RSRT_CNTR_SEL

R/W

4h

Selects the number of times the device can enter restart mode prior

to device entering sleep mode. Range is 0-15, representing entering

restart mode 1-16 times.

3-0

RSRT_CNTR

R/W1C

0h

Provides the number of times the device has entered restart mode

and should be cleared prior to reaching the RSRT_CNTR_SEL value

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8.6.30 nRST_CNTL (Address = 29h) [reset = 00h]

nRST_CNTL is shown in 图8-84 and described in 表8-40

Return to Summary Table.

Configures nRST pin and FSO pin.

图8-84. nRST_CNTL Register

7

6

5

4

3

2

1

0

RSVD

R-00b

nRST_PULSE_ FSO_POL_SEL

WIDTH

FSO_SEL

RSVD

R/W-0b

R/W/H-000b

R-0b

表8-40. nRST_CNTL Register Field Descriptions

Bit

Field

Type

Reset

00b

0b

Description

7-6

5

RSVD

R

Reserved

nRST_PULSE_WIDTH

R/W

Sets the pulse width for toggling nRST from high-->low-->high when

device enters restart mode (ms)

0b = 2

1b = 15

4

FSO_POL_SEL

R/W

0b

Selects the polarity for the FSO pin

0b = Active low

1b = Active high

备注

Selects the output level when register 8'h29[3:1] = 110b

making the pin a general-purpose output pin; 0 = Low

and 1 = High

3-1

FSO_SEL

R/W/H

000b

Selects the information that will cause this pin to be pulled to the

state selected by 'h29[4]

000b = V_CCInterrupt (overvoltage, undervoltage or short)

001b = WD interrupt event

010b = Reserved

011b = Local wake request (LWU)

100b = Bus wake request (WUP)

101b = Fail-safe mode entered

110b = General purpose output

111b = Reserved

0

RSVD

R

0b

Reserved

8.6.31 INT_GLOBAL Register (Address = 50h) [reset = A0h]

INT_GLOBAL is shown in 图8-85 and described in 表8-41.

Return to Summary Table.

Logical OR of all to certain interrupts.

图8-85. INT_GLOBAL Register

7

6

5

4

3

2

1

0

GLOBALERR

RH-1b

INT_1

RH-0b

INT_2

RH-1b

INT_3

RH-0b

RSVD

RH-0b

INT_4

RH-0b

RSVD

R-0b

RSVD

R-0b

表8-41. INT_GLOBAL Register Field Descriptions

Bit

7

Field

Type

Reset

Description

GLOBALERR

INT_1

RH

1b

Logical OR of all interrupts

Logical OR of INT_1 register

Logical OR of INT_2 register

6

RH

0b

5

INT_2

RH

1b

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表8-41. INT_GLOBAL Register Field Descriptions (continued)

Bit

4

Field

Type

RH

Reset

Description

INT_3

RSVD

INT_4

RSVD

0b

Logical OR of INT_3 register

Reserved

3

0b

2

0b

Logical OR of INT_4 register

Reserved

1

0b

0

0b

Reserved

8.6.32 INT_1 Register (Address = 51h) [reset = 0h]

INT_1 is shown in 图8-86 and described in 表8-42.

Return to Summary Table.

图8-86. INT_1 Register

7

6

5

4

3

2

1

0

WD

RSVD

R-0b

LWU

WKERR

RSVD

R-0b

R/W1C-0b

表8-42. INT_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

WD

R/W1C

0b

Watchdog event interrupt.

NOTE: This interrupt bit will be set for every watchdog error event

and does not rely upon the Watchdog error counter

6

5

4

RSVD

LWU

R

0b

Reserved

R/W1C

Local wake up

WKERR

Wake error bit is set when the SWE timer has expired and the state

machine has returned to Sleep mode

3-0

RSVD

R

0b

Reserved

8.6.33 INT_2 Register (Address = 52h) [reset = 40h]

INT_2 is shown in 图8-87 and described in 表8-43.

Return to Summary Table.

图8-87. INT_2 Register

7

6

5

4

3

2

1

0

SMS

PWRON

OVCC

UVSUP

R/W1C-0b

RSVD

R-0b

UVCC

TSD_VCC_LIN TSD_HSS_LIM

P

R/W1C-0b

R/W1C-1b

R/W1C-0b

表8-43. INT_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SMS

R/W1C

0b

Sleep mode status flag. Only sets when sleep mode is entered by a

fault

6

5

4

3

2

1

0

PWRON

R/W1C

R

1b

0b

Power on

OVCC

V_CCovervoltage

UVSUP

V_SUPundervoltage

RSVD

Reserved

UVCC

R/W1C

V_CCundervoltage

TSD_VCC_LIN

TSD_HSS_LIMP

Thermal Shutdown due to VCC or LIN

Thermal Shutdown due to HSS or LIMP

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8.6.34 INT_3 Register (Address 53h) [reset = 0h]

INT_3 is shown in 图8-88 and described in 表8-44.

Return to Summary Table.

图8-88. INT_3 Register

7

6

5

4

3

2

1

0

SPIERR

R/W1C-0b

RSVD

R-0b

FSM

CRCERR

R/W1C/U-0b

VCCSC

RSRT_CNT

R/W1C/U-0b

RSVD

R-0b

R/W1C-0b

R/W1C/U-0b

表8-44. INT_3 Register Field Descriptions

Bit

7

Field

Type

Reset

Description0b

SPIERR

RSVD

FSM

R/W1C

R

0b

Sets when SPI status bit sets

Reserved

6

0b

5

R/W1C

R/W1C/U

R

0b

Entered fail-safe mode. Can be cleared while in failsafe mode.

SPI CRC error detected

4

CRCERR

VCCSC

0b

3

0b

V_CCshort detected

2

RSRT_CNT

RSVD

0b

Restart counter exceeded programmed count

Reserved

1-0

0b

8.6.35 INT_EN_1 Register (Address = 56h) [reset = B0h]

INT_EN_1 is shown in 图8-89 and described in 表8-45.

Return to Summary Table.

Interrupt mask for INT_1.

图8-89. INT_EN_1 Register

7

6

5

4

3

2

1

0

WD_EN

R/W-1b

RSVD

R-0b

LWU_EN

R/W-1b

WKERR_EN

R/W-1b

RSVD

R-0000b

表8-45. INT_EN_1 Register Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

WD_EN

RSVD

1b

Watchdog event interrupt enable

Reserved

6

0b

5

LWU_EN

WKERR_EN

RSVD

1b

Local wake up enable

Wake error enable

Reserved

4

1b

3-0

0000b

8.6.36 INT_EN_2 Register (Address = 57h) [reset = 37h]

INT_EN_2 is shown in 图8-90 and described in 表8-46.

Return to Summary Table.

Interrupt mask for INT_2.

图8-90. INT_EN_2 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

OVCC_EN

UVSUP_EN

RSVD

UVCC_EN

TSD_VCC_LIN TSD_HSS_LMI

_EN

P_EN

R/W-1b

R-0b

R/W-1b

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表8-46. INT_EN_2 Register Field Descriptions

Bit

7-6

5

Field

Type

Reset

Description

RSVD

R

0b

Reserved

OVCC_EN

UVSUP_EN

RSVD

R/W

R

1b

V_CCover voltage enable

V_SUPundervoltage enable

Reserved

4

1b

3

0b

2

UVCC_EN

TSD_VCC_LIN_EN

TSD_HSS_LIMP_EN

R/W

1b

V_CCundervoltage enable

Thermal shutdown enable for VCC and LIN

Thermal shutdown due to HSS or LIMP enable

1

1b

0

1b

8.6.37 INT_EN_3 Register (Address =58h) [reset = BCh]

INT_EN_3 is shown in 图8-91 and described in 表8-47.

Return to Summary Table.

Interrupt mask for INT_3.

图8-91. INT_EN_3 Register

7

6

5

4

3

2

1

0

SPIERR_EN

RSVD

FSM_EN

CRCERR_EN

VCCSC_EN

RSRT_CNT_E

N

RSVD

R-0b

R/W-1b

R-0b

R/W-1b

表8-47. INT_EN_3 Register Field Descriptions

Bit

7

Field

SPIERR_EN

Type

R/W

R

Reset

Description

1b

SPI error interrupt enable

Reserved

6

RSVD

0b

5

FSM_EN

R/W

R

1b

Fail-safe mode interrupt enable

SPI CRC error interrupt enable

VCC short circuit interrupt enable

4

CRCERR_EN

VCCSC_EN

RSRT_CNT_EN

RSVD

1b

3

1b

2

1b

Exceeding programmed restart counter interrupt enable

Reserved

1-0

0b

8.6.38 INT_4 Register (Address = 5Ah) [reset = 0h]

INT_4 is shown in 图8-92 and described in 表8-48.

Return to Summary Table.

Interrupt for LIN and high side switch.

图8-92. INT_4 Register

7

6

5

4

3

2

1

0

LIN_WUP

R/W1C-0b

LIN_DTO

R/W1C-0b

RSVD

R-00b

HSSOC

HSSOL

R/W1C-0b

RSVD

R-00b

R/W1C-0b

表8-48. INT_4 Register Field Descriptions

Bit

7

Field

Type

Reset

Description

LIN_WUP

LIN_DTO

RSVD

R/W1C

R

0b

LIN bus wake

6

0b

LIN dominant state timeout

Reserved

5-4

3

00b

0b

HSSOC

HSSOL

R/W1C

High side switch over current

High side switch open load

2

0b

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表8-48. INT_4 Register Field Descriptions (continued)

Bit

Field

RSVD

Type

Reset

Description

1-0

R

00b

Reserved

8.6.39 INT_EN_4 Register (Address = 5Eh) [reset = CCh]

INT_EN_4 is shown in 图8-93 and described in 表8-49.

Return to Summary Table.

Interrupt mask for INT_4.

图8-93. INT_EN_4 Register

7

6

5

4

3

2

1

0

LIN_WUP_EN

R/W-1b

LIN_DTO_EN

R/W-1b

RSVD

R-00b

HSSOC_EN

R/W-1b

HSSOL_EN

R/W-1b

RSVD

R-00b

表8-49. INT_EN_4 Register Field Descriptions

Bit

7

Field

LIN_WUP_EN

Type

R/W

R

Reset

Description

1b

LIN bus wake interrupt enable

6

LIN_DTO_EN

RSVD

1b

LIN dominant state timeout interrupt enable

Reserved

5-4

3

00b

1b

HSSOC_EN

HSSOL_EN

RSVD

R/W

R

High side switch over current interrupt enable

High side switch open load interrupt enable

Reserved

2

1b

1-0

00b

8.6.40 Reserved Registers

All other registers not provided up to 'h7F are reserved.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TLIN1431x-Q1 can be used in both responder node and commander node applications in a LIN network.

The device comes with the ability to support remote wake up request and local wake up request. It can provide

the power to the local processor as well as providing watchdog supervision for the processor.

9.1.1 Device Brownout Information

During a brownout condition where V_SUPstays above V_nPORF, the device pin and mode behavior is as per 图

9-1. When V_SUPfalls below V_nPORF, the device enters power-on reset as per 图9-2

High

V_SUP

4.7 V UV_SUPR5.4 V

4.0 V UV_SUPF4.6 V

3.5 V V_nPORR4.2 V

3.1 V

3.0 V V_nPORF2.5 V

> V_nPORF

WKRQ/INH

UV_CCF

UV_CCR

t_LDOON

V_CC

t_{RSTN_act}

nRST

Mode

FSM

enabled

Normal, Fast, Standby

Mode dependent

UV_SUP

Restart

Standby

Set high but if no Vcc

will be indeterminate

RXD

图9-1. Brownout Above V_nPORF

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High

V_SUP

WKRQ/INH

V_CC

4.7 V UV_SUPR5.4 V

3.5 V V_nPORR4.2 V

4.0 V UV_SUPF4.6 V

3.0 V V_nPORF2.5 V

Below

V_nPORF

V_{DET_INH}

UV_CCR

UV_CCF

t_LDOON

t_{RSTN_act}

nRST

Mode

UV_SUP

Init

Normal, Fast, Standby

Mode dependent

Off

Restart

Standby

RXD

Floating

图9-2. Brownout Below V_nPORF

9.2 Typical Application

The device comes with an integrated 45 kΩ pull-up resistor and series diode for responder node applications.

For commander node applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. 图

9-3 shows the device in SPI control mode in a responder node application. 图9-4 shows the device in pin control

mode for a responder node application.

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V_BAT

V_SUP

470

Pull down on WKRQ/INH pin

for digital level output

otherwise leave floating

100 nF

V_SUP

V_DD33

100 nF

10 µF

V_CC

V_BATV_SUP

V_DD

WKRQ

100 k

HSS

3 k

SW

nCS

CLK

3.3 k

WAKE

LIMP

I/O

10 nF

SDI

SDO

Cyclic

sensing

configuration

nINT

MCU

V_DD

Responder

Node

10 k

nRST

V_SUP

Commander

Node

Pullup

FSO

DIV_ON

PV

1 k

LIN Bus

20 pF

LIN

LIN Controller

Or

SCI/UART

RXD

TXD

220 pF

GND

图9-3. Typical LIN Responder Node in SPI Control Mode

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V_BAT

V_SUP

470

V_SUP

100 nF

V_DD

100 nF

3 k

10 µF

SW

V_CC

V_BAT

V_DD

V_SUP

3.3 k

WAKE

LIMP

V_DD

10 nF

10 k

nRST

DIV_ON

PV

HSS

20 pF

MCU

WDT can be connect to GND,

VCC or left floating depending

upon watchdog window timing

requirements

WKRQ

WDT

100 k

I/O

Responder

Node

HSSC

WDI

nWDR

V_SUP

EN

Commander

Node

10 k

Pullup

1 k

LIN

LIN Bus

LIN Controller

Or

SCI/UART

RXD

TXD

220 pF

GND

图9-4. Typical LIN Responder Node in Pin Control Mode

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9.2.1 Design Requirements

9.2.1.1 Normal Mode Application Note

When using the TLIN1431x-Q1 in systems which are monitoring the RXD pin for a wake-up request, special care

should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period

between states as the receivers are switched. The application software should not look for an edge on the RXD

pin indicating a wake-up request until t_{MODE_CHANGE}. This is shown in 图 7-5. When transitioning to normal

mode, there is an initialization period shown as t_NOMINIT

.

9.2.1.2 Standby Mode Application Note

If the TLIN1431x-Q1 detects an under-voltage on V_SUP, the RXD pin transitions low, and signals to the software

that the device is in standby mode and should be returned to sleep mode for the lowest power state.

9.2.1.3 TXD Dominant State Timeout Application Note

The minimum dominant TXD time allowed by the minimum t_{TXD_DTO}limits the minimum possible data rate of the

device. The LIN protocol has different constraints for commander and responder node applications. Thus, there

are different maximum consecutive dominant bits for each application case and thus different minimum data

rates.

9.2.2 Detailed Design Procedures

Commander node applications require and external 1 kΩ pull-up resistor and serial diode.

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9.2.3 Application Curves

The characteristic curves show the LDO performance between 0 V and 5.5 V when ramping up and ramping

down.

3.6

3.3

3

5

4.5

4

-40°C

25°C

85°C

105°C

125°C

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

3.5

3

2.5

2

1.5

1

-40°C

25°C

85°C

105°C

125°C

0.5

0

-0.3

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

D029

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

D012

V_SUP(V)

V_CC= 3.3 V

I_CCLoad = 125 mA Ramp Up

V_CC= 5 V

I_CCLoad = 125 mA Ramp Down

图9-5. V_CCvs V_SUPAcross Temperature

图9-6. V_CCvs V_SUPAcross Temperature

3.6

3.3

3

120

110

100

90

80

70

60

50

40

30

20

10

0

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

-40°C

25°C

85°C

105°C

125°C

-40°C

25°C

85°C

105°C

125°C

-0.3

-10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

D027

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

D016

V_SUP(V)

V_CC= 3.3 V

I_CCLoad = 125 mA Ramp Down

V_CC= 5 V

I_CCLoad = 125 mA Ramp Up

图9-7. V_CCvs V_SUPAcross Temperature

图9-8. I_SUPvs V_SUPAcross Temperature

140

120

100

80

9

8

7

6

5

60

4

3

40

2

20

-40°C

25°C

85°C

105°C

125°C

-40°C

25°C

85°C

105°C

125°C

1

0

-20

-1

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

D025

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

D045

V_SUP(V)

V_CC= 3.3 V

I_CCLoad = 125 mA Ramp Up

V_CC= 5 V

Sleep Mode

Ramp Down

图9-9. I_SUPvs V_SUPAcross Temperature

图9-10. I_SUPvs V_SUPAcross Temperature

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图9-11. LIN Bus Performance

图9-12. Recessive to Dominant Propagation Delay

图9-13. Dominant to Recessive Propagation Delay

9.3 Power Supply Recommendations

The TLIN1431x-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 5.5 V

to 28 V. A 100 nF decoupling capacitor should be placed as close to the V_SUPpin of the device as possible.

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9.4 Layout

PCB design should start with design of the protection and filtering circuitry because ESD and EFT have a wide

frequency bandwidth from approximately 3 MHz to 3 GHz. High frequency layout techniques must be applied

during PCB design. Placement at the connector also prevents these noisy events from propagating further into

the PCB and system.

9.4.1 Layout Guidelines

The layout example and information below are for a responder node with the following configuration: See 图

9-14.

• Responder node

• SPI control

• WKRQ

• WAKE and High-side switch configured for cyclic sensing

The following are the layout guidelines based upon the provided configuration:

• Pin 1 (V_SUP): This is the supply pin for the device. A 100 nF decoupling capacitor (C1) should be placed as

close to the device as possible. Other bulk decoupling capacitance should be considered.

• Pin 2 (V_CC): Output source, either 3.3 V or 5 V depending upon the version of the device and has a 10 μF

decoupling capacitor (C2) to ground as close to the device as possible. This pin is connected to external

circuitry for a limp home mode if the watchdog has timed out causing a reset

• Pin 3 (nRST): This pin connects to the processors and functions in one of two manners; as a reset pin for the

TLIN1431x-Q1 or an indicator to the processor of an under-voltage and watchdog failure event. The pin has a

10 kΩresistor (R1) pulled up to the processor I/O voltage rail.

• Pin 4 (WDT/CLK): In SPI control mode, this pin (CLK) is connected directly to the processor as the SPI CLK

input to the TLIN1431x-Q1.

• Pin 5 (nWDR/SDO): In SPI control mode, this pin (SDO) is connected directly to the processor as the SPI

serial data output from the TLIN1431x-Q1.

• Pin 6 (WDI/SDI): In SPI control mode, this pin (SDI) is connected directly to the processor as the SPI serial

data input into the TLIN1431x-Q1.

• Pin 7 (PIN/nCS): For SPI control mode, this pin (nCS) should be connected directly to the processor as the

SPI chip select to the TLIN1431x-Q1.

• Pin 8 (EN/nINT): In SPI control mode, this pin becomes an output interrupt pin that is provided to the

processor.

• Pin 9 (HSSC/FSO): In SPI control mode, this pin (FSO) is connected directly to the processor, external

transceiver or general purpose SBC as a selectable interrupt or control pin.

• Pin 10 (PV): This pin is connected directly to a processor ADC and has a 20 pF capacitor (C3) to GND.

• Pin 11 (DIV_ON): The pin is connected to a processor which controls when the V_BATmonitoring in the

TLIN1431x-Q1 is enabled.

• Pin 12 (TXD): The TXD pin is the LIN transceiver input from the processors. A series resistor can be placed

to limit the input current to the device in the event of an over-voltage on this pin. A capacitor to ground can be

placed close to the input pin of the device to filter noise. These are system level dependent and not covered

here as usually not needed.

• Pin 13 (RXD): The RXD is the LIN transceiver receive output to the processor. The pin is a push-pull output

and can be connected directly to the processor without external pull-ups.

• Pin 14 (GND): This is the ground connection for the device. This pin should be tied to the ground plane

through a short trace with the use of two vias to limit total return inductance.

• Pin 15 (LIN): This pin connects to the LIN bus. For responder nodes, a 220 pF capacitor (C4) to ground is

implemented. For commander nodes, an additional series resistor and blocking diode should be placed

between the LIN pin and the V_SUPpin.

• Pin 16 (WKRQ/INH): This pin can be the high-voltage inhibit output pin or the digital wake output pin. The

example shows the pin configured as WKRQ which requires a 100 kΩresistor (R2) to ground at power up.

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• Pin 17 (WAKE): This pin connects to V_SUPthrough a resistor divider (R3 and R4) with the center tap

connected to a switch to ground or V_SUPand is used as the local wake up pin. A 10 nF capacitor (C5) to

ground should be placed at this center tap as shown in the application drawings. In the layout example, the

pin is configured to work with the HSS pin using the cyclic sensing wake capability of the device.

• Pin 18 (HSS): This pin is the high-side switch output

• Pin 19 (LIMP): This pin as a high-side switch that is used for a limp home function that provides V_SUPto an

external circuit which is not shown.

• Pin 20 (VBAT): This pin is used for battery monitoring is comes from the battery prior to the blocking diode. It

has a 470 Ωresistor (R5) in series and a 100 nF capacitor (C6) to GND.

备注

All ground and power connections should be made as short as possible and use at least two vias to

minimize the total loop inductance.

9.4.2 Layout Example

This is a layout example for the TLIN1431x-Q1 configured for SPI control supporting following:

• Cyclic Sensing using the WAKE pin and HSS pin

• Digital wake output, WKRQ pin.

V_BAT

V_SUP

R5

C1

C6

GND

C2

R1

V_CC

19

2

LIMP

Processor

I/O Vrail

HSS

nRST

R4

C5

WAKE

CLK

To Switch

R3

GND

SDO

WKRQ

LIN

R2

C4

GND

SDI

nCS

GND

RXD

TXD

nINT

FSO

9

12

GND

C3

图9-14. Layout Example

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

• LIN Standards:

– ISO 17987-1: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and use

case definition

– ISO 17987-4:2016: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer

(EPL) specification 12V/24V

– SAEJ2602-1:2021: LIN Network for Vehicle Applications

– LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification

• EMC requirements:

– SAE J2962-2:

– HW Requirements for CAN, LIN, FR V1.3: German OEM requirements for LIN

– ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge

– ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband

radiated electromagnetic energy - Part 4: Harness excitation methods

– ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:

Definitions and general considerations

– ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical

transient transmission by capacitive and inductive coupling via lines other than supply lines

– IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz -

Part 4: Direct RF power injection method

– IEC 61000-4-2

– IEC 61967-4

– CISPR25

• Conformance Test requirements:

– ISO 17987-7: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer (EPL)

conformance test specification

– SAE J2602-2:2021: LIN Network for Vehicle Applications Conformance Test

Application Notes:

TLINx441 LDO Performance, SLLA427

10.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 商标

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

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10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLIN14313RGYRQ1
厂家：	TEXAS INSTRUMENTS
描述：	适用于具有集成 VREG 和看门狗的 12V 系统的汽车 LIN SBC \| RGY \| 20 \| -40 to 125
文件：	总103页 (文件大小：3754K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLIN14313RGYRQ1 [TI]

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