TLIN2021A-Q1_技术文档

TLIN2021A-Q1

ZHCSMB3A –MARCH 2021 –REVISED APRIL 2022

TLIN2021A-Q1 故障保护LIN 收发器，配备抑制和唤醒功能

1 特性

2 应用

• 符合面向汽车应用的AEC-Q100（1 级）标准

• 符合LIN 2.0、LIN 2.1、LIN 2.2、LIN 2.2A 和ISO

17987–4 电气物理层(EPL) 规格标准

• 符合SAE J2602-1 面向汽车应用的LIN 网络标准

• 提供功能安全

• 车身电子装置和照明

• 汽车信息娱乐系统和仪表组

• 混合动力电动汽车和动力总成系统

• 工业运输

3 说明

– 可帮助进行功能安全系统设计的文档

• 支持12V 和24V 应用

• 宽工作输入电压范围：

– VSUP 范围为4.5V 至45V

• LIN 传输数据速率高达20kbps

• LIN 接收数据速率高达100kbps

• 工作模式：正常、待机和睡眠

• 通过源识别提供低功耗模式唤醒支持：

TLIN2021A-Q1 是一款本地互连网络 (LIN) 物理层收发

器。LIN 是支持汽车车载网络的低速通用异步收发器

(UART) 通信协议。

TLIN2021A-Q1 发送器支持高达 20 kbps 的数据速

率。收发器通过 TXD 引脚控制 LIN 总线的状态，并通

过其开漏 RXD 输出引脚报告总线的状态。该器件具有

限流波形整形驱动器，用于降低电磁发射(EME)。

– 通过LIN 总线实现远程唤醒

– 通过WAKE 引脚实现本地唤醒

– 通过EN 引脚实现本地唤醒

TLIN2021A-Q1 旨在为 12V 和 24V 应用提供支持，具

有宽输入工作电压范围。该器件支持低功耗睡眠模式，

并可通过LIN、WAKE 引脚或EN 引脚唤醒功能从低功

耗模式唤醒。该器件可以通过器件 INH 输出引脚选择

性地启用节点上会存在的各种电源，从而在整个系统级

别减少电池电流消耗。

• 集成45kΩLIN 上拉电阻器

• 使用INH 引脚控制系统级功耗

• 在LIN 总线和RXD 输出上实现上电/断电无干扰运

行

器件信息

封装⁽¹⁾

• 保护特性：±60V LIN 总线容错、58V 负载突降支

持、VSUP 上的欠压保护、TXD 显性状态超时、热

关断、系统级未供电节点或接地断开失效防护

• 结温范围为-40°C 至150°C

• 可采用8 引脚SOIC、具有可湿性侧面的VSON 和

SOT23 封装

封装尺寸（标称值）

4.90mm x 3.91mm

3.00mm x 3.00mm

2.90mm x 1.60mm

器件型号

SOIC (D) (8)⁽²⁾

VSON (DRB) (8)

SOT23 (DDF) (8)⁽²⁾

TLIN2021A

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 产品预发布

V_BAT

= 24 V

V_BAT

= 24 V

SW

3 kꢀ

SW

INH

3 kΩ

V_IN

Voltage Regulator

EN

V_DD

Commander

Node

Pullup

INH

WAKE V_SUP

7

WAKE V_SUP

7

8

3

8

3

V_DD

EN

2

I/O

2

I/O

V_DD

1 k

LIN

6

TLIN2021A

MCU

LIN Controller

or

SCI/UART

6

TLIN2021A

MCU

LIN Controller

1

4

1

4

or

RXD

220 pF

SCI/UART

TXD

5

GND

5

GND

简化版响应者节点原理图

简化版指挥官节点原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSFK7

TLIN2021A-Q1

ZHCSMB3A –MARCH 2021 –REVISED APRIL 2022

www.ti.com.cn

Table of Contents

9.2 Functional Block Diagram.........................................21

9.3 Feature Description...................................................21

9.4 Device Functional Modes..........................................24

10 Application Information Disclaimer...........................29

10.1 Application Information........................................... 29

10.2 Typical Application.................................................. 29

11 Power Supply Recommendations..............................31

12 Layout...........................................................................31

12.1 Layout Guidelines................................................... 31

12.2 Layout Example...................................................... 32

13 Device and Documentation Support..........................33

13.1 Documentation Support.......................................... 33

13.2 接收文档更新通知................................................... 33

13.3 支持资源..................................................................33

13.4 Trademarks.............................................................33

13.5 Electrostatic Discharge Caution..............................33

13.6 术语表..................................................................... 33

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................2

6 Pin Configuration and Functions...................................3

7 Specification.................................................................... 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 ESD Ratings - IEC Specification.................................4

7.4 Thermal Information....................................................5

7.5 Recommended Operating Conditions.........................5

7.6 Power Supply Characteristics.....................................6

7.7 Electrical Characteristics.............................................6

7.8 AC Switching Characteristics....................................10

7.9 Typical Curves...........................................................11

8 Parameter Measurement Information..........................13

9 Detailed Description......................................................20

9.1 Overview...................................................................20

Information.................................................................... 33

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (January 2021) to Revision A (April 2022)

Page

• 删除了原理图后面的注释.................................................................................................................................... 1

• Changed the WAKE I_ILparameter description from "Ligh-level input leakage current" to "Low-level input

leakage current"..................................................................................................................................................6

5 说明（续）

TLIN2021A-Q1 集成了适用于LIN 响应者节点应用的电阻器，还集成了ESD 保护和故障保护功能，这些功能有助

于减少应用中的外部元件数量。一旦发生接地漂移或电源电压断开，该器件可防止反馈电流经 LIN 流向电源输

入。

TLIN2021A-Q1 还包含欠压检测、过热关断保护和接地失效保护功能。一旦发生故障情况，此发送器便会立即关

闭并在故障被排除之前一直保持关闭状态。

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6 Pin Configuration and Functions

RXD

EN

1

2

3

4

8

7

6

5

INH

RXD

EN

1

2

3

4

8

7

6

5

INH

V

SUP

V_SUP

LIN

Thermal

Pad

WAKE

TXD

LIN

WAKE

TXD

GND

Not to scale

图6-1. D Package, 8-Pin (SOIC), and DDF Package,

8-Pin (SOT23) Top View

图6-2. DRB Package, 8-Pin (VSON), Top View

表6-1. Pin Functions

TYPE

DESCRIPTION

NAME

RXD

EN

NO.

1

Digital

LIN receive data output, open-drain

2

Sleep mode control input, integrated pull-down

Local wake-up input, high voltage

WAKE

TXD

GND

LIN

3

High Voltage

Digital

4

LIN transmit data input, integrated pulled down - active low after a local wake-up event

Ground connection

5

GND

6

Bus IO

LIN bus input/output line

V_SUP

INH

7

Supply

High-voltage supply from the battery

8

High Voltage

Inhibit output to control system voltage regulators and supplies, high voltage

Thermal

Pad

Electrically connected to GND, connect the thermal pad to the printed circuit board

(PCB) ground plane for thermal relief

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7 Specification

7.1 Absolute Maximum Ratings

(1) (2)

MIN

–0.3

–60

–0.3

MAX

60

UNIT

V_SUP

V_LIN

Supply voltage range (ISO 17987)

LIN Bus input voltage (ISO 17987)

WAKE pin input voltage

V

60

V_WAKE

60

60 and V_O≤

V_INH

INH pin output voltage

V

–0.3

V_SUP+0.3

V_{LOGIC_INPUT}

V_{LOGIC_OUTPUT}

I_O

Logic input voltage

6

8

4

V

–0.3

Logic output voltage

Digital pin output current

Inhibit output current

mA

I_O(INH)

WAKE output current due to ground shift

(V_WAKE≤V_GND) –0.3 V thus current out of the

WAKE pin must be limited

I_O(WAKE)

3

mA

T_J

Junction Temp

165

150

°C

–55

T_stg

Storage temperature

-65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to the ground terminal.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM) classification level 3B: V_SUP, INH, and WAKE with respect to

ground

±8000

Human body model (HBM) classification level 3B: LIN with respect to ground

±10000

±4000

V_ESDElectrostatic discharge

V

Human body model (HBM) classification level 3A: all other pins, per AEC Q100-002⁽¹⁾

Charged device model (CDM) classification

All pins

±750

level C5, per AEC Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 ESD Ratings - IEC Specification

VALUE

UNIT

IEC 62228-2 per ISO 10605

Contact discharge

R = 330 Ω, C = 150 pF (IEC 61000-4-2)

LIN, V_SUP, WAKE terminal to GND⁽¹⁾

LIN terminal to GND⁽¹⁾

±8000

V_ESDElectrostatic discharge

V

IEC 62228-2 per ISO 10605

Indirect contact discharge

R = 330 Ω, C = 150 pF (IEC 61000-4-2)

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7.3 ESD Ratings - IEC Specification (continued)

VALUE

UNIT

IEC 62228-2 per IEC 62215-3

12 V electrical systems

Pulse 1

-100

IEC 62215-3

24 V electrical systems ⁽³⁾

Pulse 1

-450

75

IEC 62228-2 per IEC 62215-3

12 V electrical systems

24 V electrical systems ⁽³⁾

Pulse 2

Non-synchronous transient

LIN, V_SUP, WAKE terminal to GND⁽¹⁾

injection

IEC 62228-2 per IEC 62215-3

12 V electrical systems

Pulse 3a

-150

-225

150

V_TRAN

V

IEC 62215-3

24 V electrical systems ⁽³⁾

Pulse 3a

IEC 62228-2 per IEC 62215-3

12 V electrical systems

Pulse 3b

IEC 62215-3

24 V electrical systems ⁽³⁾

Pulse 3b

225

±30

SAE J2962-1 per ISO 7637-3

DCC - Slow transient pulse

Direct capacitor coupling

LIN terminal to GND⁽²⁾

(1) Results given here are specific to the IEC 62228-2 Integrated circuits –EMC evaluation of transceivers –Part 2: LIN transceivers.

Testing performed by OEM approved independent 3^rdparty, EMC report available upon request.

(2) Results given here are specific to the SAE J2962-1 Communication Transceivers Qualification Requirements - LIN. Testing performed

by OEM approved independent 3^rdparty, EMC report available upon request.

(3) Verified during characterization

7.4 Thermal Information

TLIN2021A-Q1

THERMAL METRIC⁽¹⁾

D (SOIC)

8 PINS

126.2

66.4

DRB (VSON)

8 Pins

54.4

DDF(SOT)

8 PINS

120.7

60.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

61.1

69.6

26.8

42.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

18.7

2.3

2.4

Ψ_JT

68.9

26.7

41.9

Ψ_JB

R_θJC(bot)

10.8

–

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Recommended Operating Conditions

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

MIN

4.5

0

NOM

MAX

45

UNIT

V

V_SUP

V_LIN

Supply Voltage

LIN Bus input voltage

45

V

V_LOGIC

T_J

Logic Pin Voltage

0

5.25

150

V

Operating virtual junction temperature range

Thermal shutdown rising

Thermal shutdown falling

Thermal shutdown hysteresis

-40

160

°C

T_SDR

T_SDF

T_SD(HYS)

150

10

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7.6 Power Supply Characteristics

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply Voltage and Current

Device is operational beyond the LIN

defined nominal supply voltage range

See Figure 8-1

Operational supply voltage

Nominal supply voltage

4.5

45

V

See Figure 8-2

V_SUP

Normal and standby modes⁽¹⁾

See Figure 8-1

See Figure 8-2

4.5

45

V

Sleep mode

Normal mode

1.8

1

7.5

mA

EN = V_CC,R_LIN≥500 Ω, C_LIN≤10 nF, INH

= WAKE = V_SUP

Supply current

Bus dominant

Standby mode

EN = 0 V, R_LIN≥500 Ω, C_LIN≤10 nF, INH

=WAKE = V_SUP

2.1

mA

Normal mode

EN = V_CC, INH = WAKE = V_SUP

400

20

850

55

µA

Supply current

Bus recessive

I_SUP

Standby mode

EN = 0 V, INH = WAKE = V_SUP

4.5 V < V_SUP≤27 V, T_J= 125℃

EN = 0 V, LIN = WAKE = V_SUP, TXD and

RXD floating

12

20

µA

Supply current

Sleep mode

27 V < V_SUP≤45 V, T_J= 125℃

EN = 0 V, LIN = WAKE = V_SUP, TXD and

RXD floating

26

UV_SUPR

UV_SUPF

U_VHYS

Under voltage V_SUPthreshold

Ramp up

4.15

4

4.45

V

Ramp down

3.5

Delta hysteresis voltage for V_SUPunder voltage threshold

0.13

(1) Normal mode ramp V_SUPwhile LIN signal is a 10 kHz square wave with 50% duty cycle and 36 V swing.

7.7 Electrical Characteristics

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.6

5

UNIT

RXD Output Terminal

(4)

V_OL

I_OL

Low-level voltage

Based upon external pull-up to V_CC

LIN = 0 V, RXD = 0.4 V

V

Low-level output current, open drain

Leakage current, high-level

1.5

mA

µA

I_LKG

LIN = V_SUP, RXD = V_CC

–5

TXD Input Terminal

V_IL

Low-level input voltage

0.8

V

V_IH

I_LKG

High-level input voltage

2

Low-level input leakage current

TXD = 0 V

5

8

µA

–5

Standby mode after a local wake-up event

V_LIN= V_SUP, WAKE = 0 V or V_SUP, TXD = 1

V

I_TXD(WAKE)

Local wake-up source recognition TXD

Internal pull-down resistor value

1.3

mA

R_TXD

EN Input Terminal

125

350

800

kΩ

V_IL

Low-level input voltage

0.8

5.25

500

5

V

–0.3

2

V_IH

V_HYS

I_IL

High-level input voltage

Hysteresis voltage

By design and characterization

EN = 0 V

30

mV

µA

Low-level input current

Internal pull-down resistor

–5

125

R_EN

350

800

kΩ

LIN Terminal (Referenced to V_SUP

)

6

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7.7 Electrical Characteristics (continued)

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TXD = V_CC, I_O= 0 mA

7 V ≤V_SUP≤45 V

V_OH

V_OL

LIN recessive high-level output voltage⁽³⁾

0.85

V_SUP

TXD = V_CC, I_O= 0 mA

7 V ≤V_SUP≤18 V

LIN recessive high-level output voltage^{(1) (2)}

LIN recessive high-level output voltage⁽³⁾

LIN dominant low-level output voltage⁽³⁾

LIN dominant low-level output voltage^{(1) (2)}

LIN dominant low-level output voltage⁽³⁾

0.8

3

V_SUP

TXD = V_CC, I_O= 0 mA

4.5 V ≤V_SUP≤7 V

V

TXD = 0 V

7 V ≤V_SUP≤45 V

0.2

1.2

V_SUP

V

TXD = 0 V

7 V ≤V_SUP≤18 V

TXD = 0 V

4.5 V ≤V_SUP≤7 V

LIN dominant (including LIN dominant for

wake up)

See Figure 8-3

V_BUSdom

Low-level input voltage⁽³⁾

0.4

V_SUP

See Figure 8-4

LIN recessive

See Figure 8-3

See Figure 8-4

V_BUSrec

High-level input voltage⁽³⁾

0.6

V_SUP

V_IH

V_IL

LIN recessive high-level input voltage^{(1) (2)}

LIN dominant low-level input voltge^{(1) (2)}

0.47

0.4

0.6

V_SUP

7 V ≤V_SUP≤18 V

0.53

TXD & RXD open

4.5 V ≤V_LIN≤60 V

V_{SUP_NON_OP}

V_SUPwhere impact of recessive LIN bus < 5%⁽³⁾

60

V

–0.3

V_{BUS_CNT}= (V_BUSrec+ V_BUSdom)/2

See Figure 8-3

V_{BUS_CNT}

Receiver center threshold⁽³⁾

0.475

0.5

0.525

V_SUP

See Figure 8-4

V_HYS= V_BUSrec- V_BUSdom

See Figure 8-3

See Figure 8-4

V_HYS

Hysteresis voltage (ISO 17987)

Hysteresis voltage (SAE J2602)

0.175

V_SUP

V_HYS= V_IH- V_IL

See Figure 8-3

See Figure 8-4

V_HYS

0.07

0.4

75

0.175

1.0

V_SUP

V

V_{SERIAL_DIODE}

I_BUS(LIM)

Serial diode LIN termination pull-up path

Limiting current

I_{SERIAL_DIODE}= 10 µA

0.7

TXD = 0 V, V_LIN= 36 V, R_Meas= 480 Ω

V_SUP= 36 V, V_BUSdom< 10.224 V

120

300

mA

Driver off/recessive, LIN = 0 V

V_SUP= 24 V

I_{BUS_PAS_dom}

Receiver leakage current, dominant

mA

–1

See Figure 8-6

Driver off/recessive, LIN ≥V_SUP

4.5 V ≤V_SUP≤45 V

See Figure 8-7

I_{BUS_PAS_rec1}

Receiver leakage current, recessive

20

5

µA

Driver off/recessive, LIN = V_SUP

See Figure 8-7

I_{BUS_PAS_rec2}

–5

GND_Device= V_SUP= 24 V

R_Meas= 1 kΩ

I_{BUS_NO_GND}

Leakage current, loss of ground

Leakage current, loss of ground⁽⁵⁾

1.5

mA

–1.5

0 V < V_LIN< 36 V

V_SUP= 8 V, GND = open, V_SUP= 18 V, GND

= open

R_Commander= 1 kΩ, C_L= 1 nF

R_Responder= 20 kΩ, C_L= 1 nF

LIN = dominant

I_{leak gnd(dom)}

1

–1

V_SUP= 8 V, GND = open, V_SUP= 18 V, GND

= open

R_Commander= 1 kΩ, C_L= 1 nF

R_Responder= 20 kΩ, C_L= 1 nF

LIN = recessive

I_{leak gnd(rec)}

Leakage current, loss of ground⁽⁵⁾

100

µA

–100

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7.7 Electrical Characteristics (continued)

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µA

V_SUP= GND

0 V ≤V_LIN≤36 V

I_{BUS_NO_BAT}

Leakage current, loss of supply

5

I_RSLEEP

R_PU

Pull-up current source to V_SUPsleep mode

Pull-up resistor to V_SUP

V_SUP= 27 V, LIN = GND

Normal and standby modes

V_SUP= 14 V

µA

–20

–1.5

60

20

45

kΩ

C_LIN

Capacitance of the LIN pin

25

pF

INH Output Terminal

High level voltage drop INH with respect to V_SUP

Leakage current sleep mode

I_INH= - 0.5 mA

INH = 0 V

0.5

1

V

ΔV_H

I_LKG(INH)

0.5

µA

–0.5

WAKE Input Terminal

V_SUP

–

V_IH

V_IL

High-level input voltage

Standby and sleep mode

V

1.8

V_SUP

–

Low-level input voltage

3.85

I_IH

High-level input leakage current

Low-level input leakage current

WAKE hold time

WAKE = V_SUP- 1 V

WAKE = 1 V

µA

µs

–25

–12.5

I_IL

15

25

50

t_WAKE

Wake up time from sleep mode

5

Duty Cycle Characteristics

TH_REC(MAX)= 0.744 x V_SUP

TH_DOM(MAX)= 0.581 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 50 µs

D1 = t_{BUS_rec(min)}/(2 x t_BIT

See Figure 8-8 and Figure 8-9

,

Duty cycle 1⁽³⁾

D1_12V

0.396

ISO 17987 Param 27

)

TH_REC(MAX)= 0.665 x V_SUP

,

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 4.5 V to 7 V, t_BIT= 50 µs

D1_12V

D2_12V

D3_12V

Duty cycle 1^{(3) (6)}

D1 = t_{BUS_rec(min)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MAX)= 0.744 x V_SUP

TH_DOM(MAX)= 0.581 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 52 µs

D1 = t_{BUS_rec(min)}/(2 x t_BIT

See Figure 8-8 and Figure 8-9

,

Duty cycle 1^{(1) (2) (6)}

)

TH_REC(MIN)= 0.422 x V_SUP

TH_DOM(MIN)= 0.284 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 50 µs

D2 = t_{BUS_rec(MAX)}/(2 x t_BIT

See Figure 8-8 and Figure 8-9

,

Duty cycle 2⁽³⁾

ISO 17987 Param 28

0.581

)

TH_REC(MIN)= 0.496 x V_SUP

TH_DOM(MIN)= 0.361 x V_SUP

V_SUP= 4.5 V to 7 V, t_BIT= 50 µs

D2 = t_{BUS_rec(MAX)}/(2 x t_BIT

See Figure 8-8 and Figure 8-9

,

Duty cycle 2^{(3) (6)}

)

TH_REC(MIN)= 0.422 x V_SUP

TH_DOM(MIN)= 0.284 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 52 µs

D2 = t_{BUS_rec(MAX)}/(2 x t_BIT

,

Duty cycle 2^{(1) (2) (6)}

)

See Figure 8-8 and Figure 8-9

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 µs

Duty cycle 3⁽³⁾

ISO 17987 Param 29

0.417

D3 = t_{BUS_rec(min)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MAX)= 0.665 x V_SUP

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 4.5 V to 7 V, t_BIT= 96 µs

Duty cycle 3^{(3) (6)}

D3 = t_{BUS_rec(min)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

8

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7.7 Electrical Characteristics (continued)

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 µs

Duty cycle 3^{(1) (2) (6)}

D3_12V

D4_12V

D1_24V

D2_24V

D3_24V

D4_24V

0.417

D3 = t_{BUS_rec(min)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 µs

Duty cycle 4⁽³⁾

ISO 17987 Param 30

0.59

D4 = t_{BUS_rec(MAX)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

V_SUP= 4.5 V to 7 V, t_BIT= 96 µs

Duty cycle 4^{(3) (6)}

D4 = t_{BUS_rec(MAX)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 µs

Duty cycle 4^{(1) (2) (6)}

D4 = t_{BUS_rec(MAX)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MAX)= 0.710 x V_SUP

TH_DOM(MAX)= 0.554 x V_SUP

V_SUP= 15 V to 36 V, t_BIT= 50 µs

D1 = t_{BUS_rec(min)}/(2 x t_BIT

See Figure 8-8 and Figure 8-9

,

Duty cycle 1

ISO 17987 Param 72

0.330

)

TH_REC(MIN)= 0.446 x V_SUP

TH_DOM(MIN)= 0.302 x V_SUP

V_SUP= 15.6 V to 36 V, t_BIT= 50 µs

D2 = t_{BUS_rec(MAX)}/(2 x t_BIT

,

Duty cycle 2

ISO 17987 Param 73

0.642

)

See Figure 8-8 and Figure 8-9

TH_REC(MAX)= 0.744 x V_SUP

TH_DOM(MAX)= 0.581 x V_SUP

V_SUP= 7 V to 36 V, t_BIT= 96 µs

Duty cycle 3

ISO 17987 Param 74

0.386

D3 = t_{BUS_rec(min)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MAX)= 0.645 x V_SUP

TH_DOM(MAX)= 0.581 x V_SUP

V_SUP= 4.5 V to 7 V, t_BIT= 96 µs

Duty cycle 3 ⁽⁶⁾

D3 = t_{BUS_rec(min)}/(2 x t_BIT

)

See Figure 8-8 and Figure 8-9

TH_REC(MIN)= 0.422 x V_SUP

TH_DOM(MIN)= 0.284 x V_SUP

V_SUP= 4.5 V to 36 V, t_BIT= 96 µs

D2 = t_{BUS_rec(MAX)}/(2 x t_BIT

See Figure 8-8 and Figure 8-9

,

Duty cycle 2 ⁽⁶⁾

ISO 17987 Param 75

0.591

0.581

)

TH_REC(MAX)= 0.665 x V_SUP

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 5.5 V to 7 V, t_BIT= 52 µs

,

D1_LB

D2_LB

D3_LB

D_4LB

Duty cycle 1 at low battery^{(1) (2) (6)}

Duty cycle 2 at low battery^{(1) (2) (6)}

Duty cycle 3 at low battery^{(1) (2) (6)}

Duty cycle 4 at low battery^{(1) (2) (6)}

0.396

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

V_SUP= 6.1 V to 7 V, t_BIT= 52 µs

TH_REC(MAX)= 0.665 x V_SUP

,

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 5.5 V to 7 V, t_BIT= 96 µs

,

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

V_SUP= 6.1 V to 7 V, t_BIT= 96 µs

0.581

10.8

TH_REC(MAX)= 0.744 x V_SUP

,

Transmitter propagation delay timings for the duty

cycle^{(1) (2) (6)}

Recessive to dominant

TH_DOM(MAX)= 0.581 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 52 µs

t_{REC(MAX)_D1}- t_{DOM(MIN)_D1}

T_{r-d max_D1}

µs

TH_REC(MAX)= 0.422 x V_SUP

,

Transmitter propagation delay timings for the duty

cycle^{(1) (2) (6)}

Dominant to recessive

TH_DOM(MAX)= 0.284 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 52 µs

t_{DOM(MAX)_D2}- t_{REC(MIN)_D2}

T_{d-r max_D2}

8.4

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7.7 Electrical Characteristics (continued)

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 96 µs

t_{REC(MAX)_D3}- t_{DOM(MIN)_D3}

Transmitter propagation delay timings for the duty

cycle^{(1) (2) (6)}

Recessive to dominant

T_{r-d max_D3}

T_{d-r max_D4}

T_{r-d max_low}

T_{d-r max_low}

15.9

µs

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 96 µs

t_{DOM(MAX)_D4}- t_{REC(MIN)_D4}

Transmitter propagation delay timings for the duty

cycle^{(1) (2) (6)}

Dominant to recessive

17.28

10.8

8.4

µs

TH_REC(MAX)= 0.665 x V_SUP

,

Low battery transmitter propagation delay timings

for the duty cycle^{(1) (2) (6)}

Recessive to dominant

TH_DOM(MAX)= 0.499 x V_SUP

5.5 V ≤V_SUP≤7 V, t_BIT= 52 µs

t_{REC(MAX)_low}- t_{DOM(MIN)_low}

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

6.1 V ≤V_SUP≤7 V, t_BIT= 52 µs

t_{DOM(MAX)_low}- t_{REC(MIN)_low}

Low battery transmitter propagation delay timings

for the duty cycle^{(1) (2) (6)}

Dominant to recessive

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C_LINBUS, R_LINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.

(4) RXD uses open drain output structure therefore V_OLlevel is based upon microcontroller supply voltage.

(5) I_{leak gnd}= (V_BAT- V_LIN)/R_Load

(6) Specified by design

7.8 AC Switching Characteristics

parameters valid across -40℃≤T_J≤150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Device Switching Characteristics

Receiver rising propagation delay time

ISO 17987 Param 31

t_{rx_pdr}

t_{rx_pdf}

t_{rx_pdr}

t_{rx_pdf}

6

5

µs

4.5 V ≤VSUP < 5.5 V, R_RXD= 2.4 kΩ,

C_RXD= 20 pF

See Figure 8-10 and Figure 8-11

Receiver falling propagation delay time

ISO 17987 Param 31

Receiver rising propagation delay time

ISO 17987 Param 31

5.5 V ≤VSUP, R_RXD= 2.4 kΩ, C_RXD= 20

pF

See Figure 8-10 and Figure 8-11

Receiver falling propagation delay time

ISO 17987 Param 31

Rising edge with respect to falling edge

t_{rx_sym}= t_{rx_pdf}–t_{rx_pdr}),

R_RXD= 2.4 kΩ, C_RXD= 20 pF

See Figure 8-10 and Figure 8-11

Symmetry of receiver propagation delay time

Receiver rising propagation delay time

ISO 17987 Param 32

t_{rs_sym}

2

µs

–2

t_LINBUS

t_CLEAR

Minimum dominant time on LIN bus for wake-up

See Figure 8-14, Figure 9-2 and Figure 9-3

25

8

65

25

150

50

µs

Time to clear false wake-up prevention logic if LIN

bus had a bus stuck dominant fault (recessive

time on LIN bus to clear bus stuck dominant fault)

See Figure 9-3

Time to change from normal mode to sleep

mode through EN pin

See Figure 8-12

t_{MODE_CHANGE}Mode change delay time

2

15

45

µs

Time for normal mode to initialize and data

on RXD pin to be valid, includes

t_{MODE_CHANGE}for standby to normal mode.

See Figure 8-12

t_NOMINT

Normal mode initialization time⁽¹⁾

Time it takes for valid data on RXD upon

power-up

t_PWR

Power-up time

1.5

80

ms

t_{TXD_DTO}

Dominant state time out

20

50

(1) The transition time from sleep mode to normal mode includes both t_{MODE_CHANGE}and t_NOMINT

.

10

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7.9 Typical Curves

40

35

30

25

20

15

10

5

1.8

1.6

1.4

1.2

1

-55°C

25°C

125°C

150°C

-55°C

25°C

125°C

150°C

0.8

0.6

0

5

10

15

Supply Voltage (V)

20

25

30

35

40

0

5

10

15

Supply Voltage (V)

20

25

30

35

40

D001

D002

图7-1. VOH vs VSUP vs Temperature

图7-2. VOL vs VSUP vs Temperature

3

2.5

2

500

450

400

350

300

250

200

150

1.5

1

-55°C

25°C

125°C

150°C

-55°C

25°C

125°C

150°C

0.5

0

5

10

15

Supply Voltage (V)

20

25

30

35

40

0

5

10

15

Supply Voltage (V)

20

25

30

35

40

D003

D004

图7-3. ISUP (DOM) vs VSUP vs Temperature

图7-4. ISUP (REC) vs VSUP vs Temperature

1.2

1

1.2

1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

-55°C

25°C

125°C

150°C

-55°C

25°C

125°C

150°C

5

10

15

Supply Voltage (V)

20

25

30

35

40

0

5

10

15

Supply Voltage (V)

20

25

30

35

40

D005

图7-5. ISUP(STBY_DOM) vs VSUP vs Temperature

图7-6. ISUP(STBY_REC) vs VSUP vs Temperature

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7.9 Typical Curves (continued)

16

14

12

10

8

-55°C

25°C

125°C

150°C

6

0

5

10

15

20

25

Supply Voltage (V)

30

35

40

D007

图7-7. ISUP(SLP) vs VSUP vs Temperature

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8 Parameter Measurement Information

1

RXD

8

7

INH

5 V

Power Supply

Resolution: 10mV/ 1mA

Accuracy: 0.2%

2

V_SUP

EN

3

WAKE

6

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

LIN

4

TXD

5

Jitter: < 25 ns

GND

Measurement Tools

O-scope:

DMM

图8-1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10

Trigger Point

Delta t = + 5 µs (t_BIT= 50 µs)

RX

2 * t_BIT= 100 µs (20 kBaud)

图8-2. RX Response: Operating Voltage Range

A

Period T = 1/f

Amplitude

(signal range)

LIN Bus Input

Frequency: f = 20 Hz

Symmetry: 50%

图8-3. LIN Bus Input Signal

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1

RXD

INH

8

7

5 V

Power Supply

Resolution: 10mV/ 1mA

Accuracy: 0.2%

2

V_SUP

EN

6

5

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

3

4

WAKE

TXD

LIN

Jitter: < 25 ns

GND

Measurement Tools

O-scope:

DMM

图8-4. LIN Receiver Test with RX access Param 17, 18, 19, 20

8

7

RXD

EN

1

2

INH

5 V

Power Supply 1

Resolution: 10mV/ 1mA

V_SUP

V_PS1

Accuracy: 0.2%

D

6

5

3

4

WAKE

TXD

LIN

Power Supply 2

Resolution: 10mV/ 1mA

V_PS2

Accuracy: 0.2%

R_BUS

GND

Measurement Tools

O-scope:

DMM

图8-5. V_{SUP_NON_OP}Param 11

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8

7

RXD

EN

1

2

INH

5 V

Power Supply

Resolution: 10mV/ 1mA

Accuracy: 0.2%

V_SUP

R_MEAS= 499 Ω

6

3

4

LIN

WAKE

TXD

5

GND

Measurement Tools

O-scope:

DMM

图8-6. Test Circuit for I_{BUS_PAS_dom}; TXD = Recessive State V_BUS= 0 V, Param 13

Power Supply 1

Resolution: 10mV/ 1mA

1

2

8

7

INH

RXD

EN

5 V

V_PS1

Accuracy: 0.2%

V_SUP

Power Supply 2

Resolution: 10mV/ 1mA

1 kΩ

6

Accuracy: 0.2%

V_PS2

LIN

3

4

WAKE

TXD

V_PS22 V/s ramp [8 V < 18 V]

V_DROPR< 20 mV

5

GND

Measurement Tools

O-scope:

DMM

图8-7. Test Circuit for I_{BUS_PAS_rec}Param 14

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8

7

INH

1

2

RXD

5 V

Power Supply 1

Resolution: 10mV/ 1mA

V_SUP

EN

V_PS1

Accuracy: 0.2%

R_MEAS

6

3

4

WAKE

LIN

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

Power Supply 2

Resolution: 10mV/ 1mA

V_PS2

5

Accuracy: 0.2%

TXD

GND

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-8. Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30

T_BIT

D = 50%

TXD (Input)

D1₂₄: 0.710 * V_SUP

D3₂₄: 0.744 * V_SUP

D1₁₂: 0.744 * V_SUP

D3₁₂: 0.778 * V_SUP

TH_REC(MAX)

TH_DOM(MAX)

TH_REC(MIN)

TH_DOM(MIN)

Thresholds

RX Node 1

D1₁₂: 0.581 * V_SUP

D3₁₂: 0.616 * V_SUP

D1₂₄: 0.554 * V_SUP

D3₂₄: 0.581 * V_SUP

LIN Bus

Signal

D2₁₂: 0.422 * V_SUP

D4₁₂: 0.389 * V_SUP

D2₂₄: 0.446 * V_SUP

D4₂₄: 0.422 * V_SUP

V_SUP

Thresholds

RX Node 2

D2₁₂: 0.284 * V_SUP

D4₁₂: 0.251 * V_SUP

D2₂₄: 0.302 * V_SUP

D4₂₄: 0.284 * V_SUP

t_{BUS_REC(MIN)}

t_{BUS_DOM(MAX)}

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

t_{BUS_DOM(MIN)}

t_{BUS_REC(MAX)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

图8-9. Definition of Bus Timing Parameters

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8

7

INH

1

2

RXD

5 V

Power Supply 1

Resolution: 10mV/ 1mA

V_SUP

EN

V_PS1

Accuracy: 0.2%

R_MEAS

6

3

4

WAKE

LIN

Pulse Generator

Power Supply 2

Resolution: 10mV/ 1mA

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

V_PS2

5

Accuracy: 0.2%

TXD

GND

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-10. Propagation Delay Test Circuit; Param 31, 32

D1: 0.744 * V_SUP

D3: 0.778 * V_SUP

D1₂₄: 0.710 * V_SUP

D3₂₄: 0.744 * V_SUP

TH_REC(MAX)

Thresholds

RX Node 1

D1: 0.581 * V_SUP

D3: 0.616 * V_SUP

D1₂₄: 0.554 * V_SUP

D3₂₄: 0.581 * V_SUP

TH_DOM(MAX)

LIN Bus

Signal

D2: 0.422 * V_SUP

D4: 0.389 * V_SUP

D2₂₄: 0.446 * V_SUP

D4₂₄: 0.422 * V_SUP

V_SUP

TH_REC(MIN)

Thresholds

RX Node 2

D2: 0.284 * V_SUP

D4: 0.251 * V_SUP

D2₂₄: 0.302 * V_SUP

D4₂₄: 0.284 * V_SUP

TH_DOM(MIN)

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

t_{rx_pdr(1)}

t_{rx_pdf(1)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

t_{rx_pdr(2)}

t_{rx_pdf(2)}

图8-11. Propagation Delay

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Wake Event

t_{MODE_CHANGE}

t_NOMINT

t_{MODE_CHANGE}

EN

Transition

Sleep

Standby

Transition

Normal

MODE

Indeterminate

Ignore

Mirrors

Bus

Wake Request

RXD = Low

RXD

Floating

Indeterminate Ignore

Mirrors Bus

图8-12. Mode Transitions

EN

Weak Internal Pulldown

TXD

Weak Internal Pulldown

V_SUP

LIN

RXD

Floating

Sleep

MODE

Normal

图8-13. Wake-up Through EN

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0.6 x V_SUP

LIN

0.6 x V_SUP

V_SUP

0.4 x V_SUP

t < t_LINBUS

t_LINBUS

TXD

Weak Internal Pull-down

EN

Floating

RXD

MODE

Sleep

Standby

Normal

图8-14. Wake-up through LIN

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9 Detailed Description

9.1 Overview

The TLIN2021A-Q1 is a local interconnect network (LIN) physical layer transceiver, compliant to LIN 2.0, LIN 2.1,

LIN 2.2, LIN 2.2A, SAE J2602-1, SAE J2602-2, ISO 17987–4, and ISO 17987–7 standards. LIN is a low-speed

universal asynchronous receiver transmitter (UART) communication protocol focused on automotive in-vehicle

networking.

The device transmitter supports data rates from 2.4-kbps to 20-kbps and the receiver supports data rates up to

100-kbps for end-of-line programming. The device controls the state of the LIN bus through the TXD pin and

reports the state of the bus through its open-drain RXD output pin. The LIN protocol data stream on the TXD

input is converted by the device into a LIN bus signal using an optimized electromagnetic emissions current-

limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the data

stream to logic-level signals that are sent to the microcontroller through the open-drain RXD pin. The LIN bus

has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive

state, the LIN bus is pulled high by the transceivers internal pull-up resistor (45-kΩ) and a series diode. No

external pull-up components are required for responder node applications. Commander node applications

require an external pull-up resistor (1-kΩ) as well as a series diode per the LIN specification.

The device is designed to support 12-V and 24-V applications with a wide input voltage operating range and also

supports low-power sleep mode. The device supports wake-up from low-power mode through wake over LIN,

the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by

selectively enabling the various power supplies that may be present on a node through the INH output pin.

The TLIN2021A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required

external components in the applications. In the event of a ground shift or supply voltage disconnection, the

device prevents back-feed current through LIN to the supply input.

The TLIN2021A-Q1 also includes undervoltage detection, temperature shutdown protection, and loss-of-ground

protection. In the event of a fault condition, the transmitter is immediately switched off and remains off until the

fault condition is removed.

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9.2 Functional Block Diagram

INH

V_SUP/2

RXD

V_SUP

Comp

Filter

EN

45 kΩ

350 kΩ

Wake Up

State & Control

V_SUP

Fault Detection

& Protection

LIN

WAKE

DR/

Slope

CTL

Dominant

State

Time-Out

TXD

350 kΩ

GND

9.3 Feature Description

9.3.1 LIN

This high voltage input/output pin is the single-wire LIN bus transmitter and receiver. The LIN pin can survive

transient voltages up to 60-V. Reverse currents from the LIN to supply (V_SUP) are minimized with blocking

diodes, even in the event of a ground shift or loss of supply (V_SUP).

9.3.1.1 LIN Transmitter Characteristics

The LIN transmitter has thresholds and AC switching parameters according to the LIN specification. The

transmitter is a low-side transistor with internal current limitation and thermal shutdown. During a thermal

shutdown condition, the transmitter is disabled to protect the device. There is an internal pull-up resistor with a

serial diode structure to V_SUP, so no external pull-up components are required for LIN responder node

applications. An external pull-up resistor and series diode to V_SUPmust be added when the device is used in a

commander node application per the LIN specification.

9.3.1.2 LIN Receiver Characteristics

The receiver characteristic thresholds are proportional to the device supply pin in accordance to the LIN

specification.

The receiver is capable of receiving higher data rates, > 100 kbps, than supported by LIN or SAEJ2602

specifications. This allows the TLIN2021A-Q1 to be used for high-speed downloads at the end-of-line production

or other applications. The actual data rate achievable depends on system time constants (bus capacitance and

pull-up resistance) and driver characteristics used in the system.

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9.3.1.2.1 Termination

There is an internal pull-up resistor with a serial diode structure to V_SUP, so no external pull-up components are

required for the LIN responder node applications. An external pull-up resistor (1-kΩ) and a series diode to V_SUP

must be added when the device is used for commander node applications as per the LIN specification.

图9-1 shows a commander node configuration and how the voltage levels are defined

Voltage drop across the

Simplified Transceiver

V_{LIN_Bus}

diodes in the pull-up path

V_SUP

V_SUP/2

RXD

V_Battery

V_SUP

V_{LIN_Recessive}

Receiver

Filter

1 kQ

45 kQ

LIN Bus

LIN

TXD

350 kQ

GND

Transmitter

with slope control

V_{LIN_Dominant}

t

图9-1. Commander Node Configuration with Voltage Levels

9.3.2 TXD

TXD is the interface to the MCU LIN protocol controller or SCI and UART that is used to control the state of the

LIN output. When TXD is low the LIN output is dominant (near ground) and when TXD is high the LIN output is

recessive (near V_SUP), see 图9-1.

The TXD input structure is compatible with 3.3-V and 5-V microcontrollers and integrates a weak pull-down

resistor. The LIN bus is protected from being stuck dominant through a system failure driving TXD low through

the dominant state time-out timer. When a change of state on the WAKE pin initiates a local wake-up event, the

TXD pin is pulled hard to ground indicating a local wake-up event. The hard pull to ground is released upon the

rising edge on the EN pin. If an external pull-up resistor is added to the TXD pin to the microcontroller's IO

voltage then TXD is pulled high to indicate a remote wake-up event.

9.3.3 RXD

RXD is the interface to the MCU’s LIN protocol controller or SCI and UART, which reports the state of the LIN

bus voltage. LIN recessive (near V_SUP) is represented by a high level on the RXD and LIN dominant (near

ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.

This allows the device to be used with 3.3-V and 5-V microcontrollers. If the microcontroller's RXD pin does not

have an integrated pull-up, an external pull-up resistor to the microcontroller's IO supply voltage is required. In

standby mode, the RXD pin is driven low to indicate a wake-up request.

9.3.4 V_SUP

V_SUPis the power supply pin. V_SUPis connected to the battery through an external reverse-blocking diode, see

图9-1. If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which

does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition

supplied) while the rest of the network remains powered (battery supplied).

9.3.5 GND

GND is the device ground connection. The device can operate with a ground shift as long as the ground shift

does not reduce the V_SUPbelow the minimum operating voltage. If there is a loss of ground at the ECU level, the

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device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN

systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains

powered (battery supplied).

9.3.6 EN

EN controls the operational modes of the device. When EN is high the device is in normal operating mode

allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep

mode and there are no transmission paths available. The device can enter normal mode only after wake-up. EN

has an internal pull-down resistor to ensure the device remains in low power mode even if EN floats.

9.3.7 WAKE

The WAKE pin is a high-voltage input used for the local wake-up (LWU) function. This function is explained

further in 节 9.4.4.1 section. The pin is defaulted to bidirectional edge trigger, meaning it recognizes a local

wake-up (LWU) on a rising or falling edge of WAKE pin transition.

9.3.8 INH

The TLIN2021A-Q1 inhibit, INH, output pin can be used to control the enable of system power-management

devices allowing for a significant reduction in battery quiescent current consumption while the application is in

sleep mode. The INH pin has two states: driven high and high impedance. When the INH pin is driven high, the

terminal shows V_SUPminus a diode voltage drop. In the high impedance state the output is left floating. The INH

pin is high in the normal and standby modes and is low when in sleep mode. A 100 kΩload can be added to the

INH output to ensure a fast transition time from the driven high state to the low state and to also force the pin low

when left floating.

The INH terminal should be considered a high-voltage logic terminal and not a power output. Thus should be

used to drive the EN terminal of the systems power-management device and not used as a switch for the power-

management supply itself. This terminal is not reverse battery protected and thus should not be connected

outside the system module.

9.3.9 Local Faults

The TLIN2021A-Q1 has several protection features that are described as follows.

9.3.10 TXD Dominant Time-Out (DTO)

While the LIN driver is in active mode a TXD DTO circuit prevents the local node from blocking network

communication in the event of a hardware or software failure where TXD is held dominant longer than the time-

out period t_{TXD_DTO}. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before

the time-out constant of the circuit, t_{TXD_DTO}, expires the LIN driver is disabled releasing the bus line to the

recessive level. This keeps the bus free for communication between other nodes on the network. The LIN driver

is re-activated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time-

out. During this fault, the transceiver remains in normal mode, the integrated LIN bus pull-up termination remains

on, and the LIN receiver and RXD terminal remain active reflecting the LIN bus data.

The TXD pin has an internal pull-down to ensure the device fails to a known state if TXD is disconnected. If EN

pin is high at power-up, the TLIN2021A-Q1 enters normal mode. With the internal TXD connected low, the DTO

timer starts. To avoid a t_{TXD_DTO}fault, a recessive signal should be put onto the TXD pin before the t_{TXD_DTO}

timer expires, or the device should be into sleep mode by connecting EN pin low.

9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout

The TLIN2021A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from

waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.

If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus clears the bus stuck

dominant fault, preventing excessive current use, see 图9-2 and 图9-3.

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RXD

EN

LIN Bus

t_LINBUS

< t_LINBUS

图9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wake-up

RXD

EN

t_LINBUS

LIN Bus

t_CLEAR

< t_CLEAR

图9-3. Bus Fault: Entering Sleep Mode With Bus Stuck Dominant Fault, Clearing, and Wake-up

9.3.12 Thermal Shutdown

The TLIN2021A-Q1 transmitter is protected by limiting the current. If the junction temperature, T_J, of the device

exceeds the thermal shutdown threshold, T_J> T_SDR, the device puts the LIN transmitter into the recessive state.

Once the over temperature fault condition has been removed and the junction temperature has cooled beyond

the hysteresis temperature, the transmitter is re-enabled. During this fault, the transceiver remains in normal

mode, the integrated LIN bus pull-up termination remains on, the LIN receiver and RXD terminal remain active

reflecting the LIN bus data.

9.3.13 Under Voltage on V_SUP

The device contains a power on reset circuit to avoid false bus messages during under voltage conditions when

V_SUPis less than UV_SUP

.

9.3.14 Unpowered Device

In automotive applications, some LIN nodes in a system can be unpowered, ignition supplied, while others in the

network remains powered by the battery. The device has extremely low unpowered leakage current from the bus

so an unpowered node does not affect the network or load it down.

9.4 Device Functional Modes

The TLIN2021A-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections

describe these modes and how the device transitions between the different modes. 图 9-4 graphically shows the

relationship while 表9-1 shows the state of pins.

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表9-1. Operating Modes

LIN BUS

TERMINATION

TRANSMITTE

R

MODE

EN

TXD

RXD

INH

COMMENT

Weak current

pull-up

Sleep

Low

High

Weak pull-down

Floating

Off

On

Weak pull-down if LIN bus wake-

up; Strong pull-down if a local

wake-up event (WAKE pin)

Wake-up event detected,

waiting on MCU to set

EN

Standby

Normal

Low

High

45-kΩ

High: recessive state

Low: dominant state

LIN transmission up to 20

kbps

LIN Bus Data

Unpowered System

V_SUP< UV_SUP

V_SUP> UV_SUP

EN = Low

V_SUP< UV_SUP

V_SUP> UV_SUP

EN = High

Standby Mode

Driver: Off

RXD: Low

TXD:

V_SUP< UV_SUP

weak pull-down for LIN bus wake

Hard pull-down for WAKE pin wake

INH: On

Normal Mode

LIN termination: 45 kΩ

Driver: On

RXD: LIN Bus Data

TXD:

High for recessive

Low for dominant

INH: On

Sleep Mode

EN = High

LIN bus wake up or

WAKE pin wake up

Driver: Off

RXD: Floating

TXD: Weak pull-down

INH: Off

LIN termination: Weak pull-up

EN = Low

EN = High

LIN termination: 45 kΩ

图9-4. Operating State Diagram

9.4.1 Normal Mode

The EN pin controls the mode of the device. If the EN pin is high at power-up the device powers up in normal

mode, if the EN is low at power-up the device powers up in standby mode. In normal mode the receiver and

transmitter fully operational. The LIN transmitter transmits data from the LIN controller to the LIN bus up to the

LIN specified maximum data rate of 20-kbps. The LIN receiver detects the data stream on the LIN bus up to data

rates of 100-kbps and outputs the data on RXD output for the LIN controller. Upon an EN pin transition from low

to high the TLIN2021A-Q1 transitions from sleep mode to normal mode in t ≥t_NOMINT

.

9.4.2 Sleep Mode

Sleep mode is the lowest power mode of the TLIN2021A-Q1 and is only entered from normal mode when the EN

pin transitions from high to low for t > t_{MODE_CHANGE}. In sleep mode, the LIN driver and receiver are switched off,

the LIN bus is weakly pulled up, and the transceiver cannot send or receive data. The INH pin is switched to a

floating output in sleep mode causing any system power elements controlled by the INH pin to be switched off

thus reducing the system power consumption. While the device is in sleep mode, the following conditions exist:

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• The LIN bus driver is disabled and the internal LIN bus termination is switched off to minimize power loss if

LIN is short circuited to ground.

• A weak current pull-up is active to prevent false wake-up events in case an external connection to the LIN

bus is lost.

• The normal receiver is disabled.

• EN input, WAKE pin and LIN wake-up receiver are active.

The TLIN2021A-Q1 supports three methods for wake-up from sleep mode:

• Wake-up over the LIN bus via the LIN wake-up receiver.

• Local wake-up via the WAKE pin.

• Local wake-up via the EN pin. The EN pin must be set high for t > t_NOMINTin order for the device to wake-up.

9.4.3 Standby Mode

Standby mode is entered whenever a wake-up event occurs through LIN bus or the WAKE pin while the device

is in sleep mode. In standby mode, the LIN bus responder termination circuit, 45-kΩ, is on. When a wake-up

event occurs and the TLIN2021A-Q1 enters standby mode the RXD pin is driven low signaling the wake-up

event to the LIN controller.

The TLIN2021A-Q1 exits standby mode and transitions to normal mode when the EN pin is set high for longer

than t_{MODE_CHANGE}where the normal LIN transmitter and receiver are fully operational and bi-directional

communication is possible.

9.4.4 Wake-Up Events

There are three ways to wake-up the TLIN2021A-Q1 from sleep mode:

• Remote wake-up initiated by the falling edge of a recessive-to-dominant state transition on the LIN bus where

the dominant state is held longer than t_LINBUSfilter time. After the t_LINBUSfilter time has been met a rising

edge on the LIN bus going from dominant-to-recessive initiates a remote wake-up event. The pattern and

t_LINBUSfilter time used for the LIN wake-up prevents noise and bus stuck dominant faults from causing false

wake requests.

• A local wake-up event due to the EN pin being set high for t > t_{MODE_CHANGE}

.

• A local wake-up event due to a change in voltage level on the WAKE pin for t > t_WAKE

9.4.4.1 Local Wake-Up (LWU) via WAKE Input Terminal

The WAKE terminal is a bi-directional high-voltage input which can be used for local wake-up (LWU) requests via

a voltage transition. A LWU event is triggered on either a low-to-high or high-to-low transition since it has bi-

directional input thresholds. The WAKE pin could be used with a switch to V_SUPor to ground. If the terminal is

unused it should be pulled to V_SUPor ground to avoid unwanted parasitic wake-up events. When a LWU event

takes place the TXD pin is pulled hard to GND letting the LIN controller know that the wake-up event was due to

the WAKE pin and not a wake over LIN event.

The LWU circuitry is active in standby mode and sleep mode. If a valid LWU event occurs in standby mode, the

device remains in standby mode and drive the RXD output low. If a valid LWU event occurs in sleep mode, the

device transitions to standby mode and drives the RXD output low. The LWU circuitry is not active in normal

mode. To minimize system-level current consumption, the internal bias voltages of the terminal follows the state

on the terminal with a delay of t_WAKE(MIN). A constant high level on WAKE has an internal pull-up to V_SUP, and a

constant low level on WAKE has an internal pull-down to GND.

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Wake

Threshold

Not Crossed

t ≤ t_WAKE

No Wake

UP

t ≥ t_WAKE

Wake UP

Wake

Local Wake Request

INH

Pull-down

Latched Low

TXD

RXD

*

Mode

Sleep Mode

Standby Mode

图9-5. Local Wake-Up –Rising Edge

Wake

Threshold

Not Crossed

t ≤ t_WAKE

No Wake

UP

t ≥ t_WAKE

Wake UP

Wake

Local Wake Request

INH

Pull-down

Latched Low

TXD

RXD

*

Mode

Sleep Mode

Standby Mode

图9-6. Local Wake-Up –Falling Edge

9.4.4.2 Wake-Up Request (RXD)

When the TLIN2021A-Q1 encounters a wake-up event from the WAKE pin or the LIN bus, the RXD output is

driven low until EN is asserted high, the device enters normal mode. Once the device enters normal mode, the

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wake-up event is cleared, and the RXD output is released. The RXD output is fully operational and reflects the

receiver output from the LIN bus.

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10 Application Information Disclaimer

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The TLIN2021A-Q1 can be used in both a responder node application and a commander node application in a

LIN network.

10.2 Typical Application

The device integrates a 45-kΩ pull-up resistor and series diode for responder node applications. For commander

node applications, an external 1-kΩ pull-up resistor with series blocking diode can be used. 图 10-1 shows the

device being used in both commander node and responder node applications.

V_SUP

Commander

Node

VREG

V_SUP

SW

GND

3 kꢀ

EN

V_DD

V_SUP

INH

2

WAKE

(4)

EN

8

3

7

I/O

V_DD

Commander

Node

MCU w/o

pull-up⁽²⁾

Pullup⁽³⁾

V_DDI/O

1 kΩ

LIN

MCU

TLIN2021A

6

LIN Controller

Or

1

4

220 pF

RXD

TXD

SCI/UART⁽¹⁾

GND

5

V_SUP

Responder

Node

VREG

V_SUP

SW

3 kꢀ

GND

EN

V_DD

V_SUP

INH

2

WAKE

3

(4)

EN

8

7

I/O

V_DD

MCU w/o

pull-up⁽²⁾

V_DDI/O

LIN

MCU

TLIN2021A

6

LIN Controller

Or

1

4

220 pF

RXD

TXD

SCI/UART⁽¹⁾

GND

5

(1) If RXD on MCU or LIN responder node has internal pull-up; no external pull-up resistor is needed.

(2) If RXD on MCU or LIN responder node does not have an internal pull-up requires external pull-up resistor.

(3) Commander node applications require and external 1 kΩ pull-up resistor and serial diode.

(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥10 µF

图10-1. Typical LIN Bus

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10.2.1 Design Requirements

The RXD output structure is an open-drain output stage which allows the TLIN2021A-Q1 to be used with 3.3-V

and 5-V controllers. If the RXD pin of the controller does not have an integrated pull-up, an external pull-up

resistor to the controller's IO voltage is required. The external pull-up resistor value should be between 1-kΩ to

10-kΩ. The V_SUPpin of the device should be decoupled with a 100-nF capacitor by placing it close to the V_SUP

supply pin. The system should include additional decoupling on the V_SUPline as needed per the application

requirements.

10.2.2 Detailed Design Procedures

10.2.2.1 Normal Mode Application Note

When using the TLIN2021A-Q1 in systems which are monitoring the RXD pin for a wake-up request, special

care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition

period between states as the receivers are switched. The application software should not look for an edge on the

RXD pin indicating a wake-up request until t_{MODE_CHANGE}has been met. This is shown in 图8-12

10.2.2.2 TXD Dominant State Time-Out Application Note

The maximum dominant TXD time allowed by the TXD dominant state time-out limits the minimum possible data

rate of the device. The LIN protocol has different constraints for commander node and responder node

applications thus there are different maximum consecutive dominant bits for each application case thus different

minimum data rates.

10.2.2.3 Standby Mode Application Note

If the TLIN2021A-Q1 detects an under voltage on V_SUPthe RXD pin transitions low signaling to the controller

that the TLIN2021A-Q1 is in standby mode. The transceiver should be returned to sleep mode for the lowest

power state.

10.2.3 Application Curves

图 10-2 and 图 10-3 show the propagation delay from the TXD pin to the LIN pin for the dominant to recessive

and recessive to dominant edges. Device was configured in commander mode with external pull-up resistor (1

kΩ) and 680 pF bus capacitance.

图10-2. Dominant To Recessive Propagation Delay 图10-3. Recessive to Dominant Propagation Delay

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11 Power Supply Recommendations

The TLIN2021A-Q1 was designed to operate directly from a car battery, or any other DC supply ranging from

4.5-V to 45-V. The V_SUPpin of the device should be decoupled with a 100-nF capacitor by placing it close to the

V_SUPsupply pin. The system should include additional decoupling on the V_SUPline as needed per the application

requirements. Device has been designed and tested to support supply ramp rates equal to or slower than 0.5

V/µs.

12 Layout

For the PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD

transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz, high-frequency layout

techniques must be applied during PCB design. Placement at the connector also prevents these noisy events

from propagating further into the PCB and system.

12.1 Layout Guidelines

• Pin 1(RXD): The RXD pin is an open-drain output and requires and external pull-up resistor in the range of 1-

kΩ and 10-kΩ to function properly. If the controller paired with the transceiver does not have an integrated

pull-up, an external resistor should be placed between RXD and the supply voltage for the controller.

• Pin 2 (EN): EN is an input pin that is used to place the device in low-power sleep mode. If this feature is not

used, the pin should be connected to the supply voltage for the controller through a series resistor using a

pull-up value between 1-kΩ and 10-kΩ. Additionally, a series resistor may be placed on the pin to limit current

on the digital lines in the case of an over voltage fault.

• Pin 3 (WAKE): SW1 is oriented in a low-side configuration which is used to implement a local WAKE event.

The series resistor R5 is needed for protection against over current conditions as it limits the current into the

WAKE pin when the ECU has lost its ground connection. The pull-up resistor R4 is required to provide

sufficient current during stimulation of a WAKE event. In this layout example R4 is set to 3-kΩand R5 is set

to 33-kΩ.

• Pin 4 (TXD): The TXD pin is the transmit input signal to the device from the controller. A series resistor can

be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to

ground can be placed close to the input pin of the device to help filter noise.

• Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane

through a short trace with the use of two vias to limit total return inductance.

• Pin 6 (LIN): The LIN pin connects to the TLIN2021A-Q1 to the LIN bus. For responder node applications a

220 pF capacitor to ground is implemented. For commander node applications an additional series resistor

and blocking diode should be placed between the LIN pin and the V_SUPpin, see Typical LIN Bus.

• Pin 7 (V_SUP): This is the supply pin for the device. A 100-nF capacitor should be placed close to the V_SUP

supply pin for local power supply decoupling.

• Pin 8 (INH):The INH pin is used for system power-management. A 100-kΩload can be added to the INH

output to ensure a fast transition time from the driven high state to the low state and to also force the pin low

when left floating.

备注

All ground and power connections should be made as short as possible and use at least two vias to

minimize the total loop inductance.

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12.2 Layout Example

GND

RXD

EN

INH

V_SUP

LIN

R3

INH

V_SUP

C2

V_SUP

WAKE

TXD

R1

To Switch

R2

LIN

C1

GND

图12-1. Layout Example

32

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TLIN2021A-Q1

ZHCSMB3A –MARCH 2021 –REVISED APRIL 2022

www.ti.com.cn

13 Device and Documentation Support

13.1 Documentation Support

13.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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33

Product Folder Links: TLIN2021A-Q1

PACKAGE OUTLINE

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

1.75

1.55

(0.2) TYP

6X 0.65

(0.19)

4

5

SYMM

9

2.5

2.3

1.95

1

8

0.36

0.26

8X

PIN 1 ID

(OPTIONAL)

0.1

0.05

C A B

C

SYMM

0.5

0.3

8X

4225036/A 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)

(1.65)

8X (0.6)

8X (0.31)

SYMM

1

8

6X (0.65)

SYMM

9

(1.95) (2.4)

(0.95)

(R0.05) TYP

4

5

(Ø 0.2) VIA

TYP

(0.575)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

METAL

NON- SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225036/A 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)

2X

(1.51)

8X (0.6)

8X (0.31)

SYMM

1

8

2X

(1.06)

6X (0.65)

SYMM

(1.95)

(0.63)

9

(R0.05) TYP

4

5

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

81% PRINTED COVERAGE BY AREA

SCALE: 20X

4225036/A 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLIN2021A-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有抑制和唤醒功能的汽车类故障保护 LIN 收发器
文件：	总41页 (文件大小：2120K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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