TLIN2021ADRBRQ1 [TI]
具有抑制和唤醒功能的汽车类故障保护 LIN 收发器 | DRB | 8 | -40 to 125;型号: | TLIN2021ADRBRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有抑制和唤醒功能的汽车类故障保护 LIN 收发器 | DRB | 8 | -40 to 125 |
文件: | 总41页 (文件大小:2120K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLIN2021A-Q1
ZHCSMB3A –MARCH 2021 –REVISED APRIL 2022
TLIN2021A-Q1 故障保护LIN 收发器,配备抑制和唤醒功能
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100(1 级)标准
• 符合LIN 2.0、LIN 2.1、LIN 2.2、LIN 2.2A 和ISO
17987–4 电气物理层(EPL) 规格标准
• 符合SAE J2602-1 面向汽车应用的LIN 网络标准
• 提供功能安全
• 车身电子装置和照明
• 汽车信息娱乐系统和仪表组
• 混合动力电动汽车和动力总成系统
• 工业运输
3 说明
– 可帮助进行功能安全系统设计的文档
• 支持12V 和24V 应用
• 宽工作输入电压范围:
– VSUP 范围为4.5V 至45V
• LIN 传输数据速率高达20kbps
• LIN 接收数据速率高达100kbps
• 工作模式:正常、待机和睡眠
• 通过源识别提供低功耗模式唤醒支持:
TLIN2021A-Q1 是一款本地互连网络 (LIN) 物理层收发
器。LIN 是支持汽车车载网络的低速通用异步收发器
(UART) 通信协议。
TLIN2021A-Q1 发送器支持高达 20 kbps 的数据速
率。收发器通过 TXD 引脚控制 LIN 总线的状态,并通
过其开漏 RXD 输出引脚报告总线的状态。该器件具有
限流波形整形驱动器,用于降低电磁发射(EME)。
– 通过LIN 总线实现远程唤醒
– 通过WAKE 引脚实现本地唤醒
– 通过EN 引脚实现本地唤醒
TLIN2021A-Q1 旨在为 12V 和 24V 应用提供支持,具
有宽输入工作电压范围。该器件支持低功耗睡眠模式,
并可通过LIN、WAKE 引脚或EN 引脚唤醒功能从低功
耗模式唤醒。该器件可以通过器件 INH 输出引脚选择
性地启用节点上会存在的各种电源,从而在整个系统级
别减少电池电流消耗。
• 集成45kΩLIN 上拉电阻器
• 使用INH 引脚控制系统级功耗
• 在LIN 总线和RXD 输出上实现上电/断电无干扰运
行
器件信息
封装(1)
• 保护特性:±60V LIN 总线容错、58V 负载突降支
持、VSUP 上的欠压保护、TXD 显性状态超时、热
关断、系统级未供电节点或接地断开失效防护
• 结温范围为-40°C 至150°C
• 可采用8 引脚SOIC、具有可湿性侧面的VSON 和
SOT23 封装
封装尺寸(标称值)
4.90mm x 3.91mm
3.00mm x 3.00mm
2.90mm x 1.60mm
器件型号
SOIC (D) (8)(2)
VSON (DRB) (8)
SOT23 (DDF) (8)(2)
TLIN2021A
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
(2) 产品预发布
VBAT
= 24 V
VBAT
= 24 V
SW
3 kꢀ
SW
INH
3 kΩ
VIN
VIN
Voltage Regulator
Voltage Regulator
EN
EN
VDD
VDD
VDD
VDD
Commander
Node
Pullup
INH
WAKE VSUP
7
WAKE VSUP
7
8
3
8
3
VDD
VDD
EN
EN
2
I/O
2
I/O
VDD
VDD
1 k
LIN
LIN
6
TLIN2021A
MCU
LIN Controller
or
SCI/UART
6
TLIN2021A
MCU
LIN Controller
1
4
1
4
or
RXD
RXD
220 pF
220 pF
SCI/UART
TXD
TXD
5
GND
5
GND
简化版响应者节点原理图
简化版指挥官节点原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLLSFK7
TLIN2021A-Q1
ZHCSMB3A –MARCH 2021 –REVISED APRIL 2022
www.ti.com.cn
Table of Contents
9.2 Functional Block Diagram.........................................21
9.3 Feature Description...................................................21
9.4 Device Functional Modes..........................................24
10 Application Information Disclaimer...........................29
10.1 Application Information........................................... 29
10.2 Typical Application.................................................. 29
11 Power Supply Recommendations..............................31
12 Layout...........................................................................31
12.1 Layout Guidelines................................................... 31
12.2 Layout Example...................................................... 32
13 Device and Documentation Support..........................33
13.1 Documentation Support.......................................... 33
13.2 接收文档更新通知................................................... 33
13.3 支持资源..................................................................33
13.4 Trademarks.............................................................33
13.5 Electrostatic Discharge Caution..............................33
13.6 术语表..................................................................... 33
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................2
6 Pin Configuration and Functions...................................3
7 Specification.................................................................... 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 ESD Ratings - IEC Specification.................................4
7.4 Thermal Information....................................................5
7.5 Recommended Operating Conditions.........................5
7.6 Power Supply Characteristics.....................................6
7.7 Electrical Characteristics.............................................6
7.8 AC Switching Characteristics....................................10
7.9 Typical Curves...........................................................11
8 Parameter Measurement Information..........................13
9 Detailed Description......................................................20
9.1 Overview...................................................................20
Information.................................................................... 33
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (January 2021) to Revision A (April 2022)
Page
• 删除了原理图后面的注释.................................................................................................................................... 1
• Changed the WAKE IIL parameter description from "Ligh-level input leakage current" to "Low-level input
leakage current"..................................................................................................................................................6
5 说明(续)
TLIN2021A-Q1 集成了适用于LIN 响应者节点应用的电阻器,还集成了ESD 保护和故障保护功能,这些功能有助
于减少应用中的外部元件数量。一旦发生接地漂移或电源电压断开,该器件可防止反馈电流经 LIN 流向电源输
入。
TLIN2021A-Q1 还包含欠压检测、过热关断保护和接地失效保护功能。一旦发生故障情况,此发送器便会立即关
闭并在故障被排除之前一直保持关闭状态。
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6 Pin Configuration and Functions
RXD
EN
1
2
3
4
8
7
6
5
INH
RXD
EN
1
2
3
4
8
7
6
5
INH
V
SUP
VSUP
LIN
Thermal
Pad
WAKE
TXD
LIN
WAKE
TXD
GND
GND
Not to scale
Not to scale
图6-1. D Package, 8-Pin (SOIC), and DDF Package,
8-Pin (SOT23) Top View
图6-2. DRB Package, 8-Pin (VSON), Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
RXD
EN
NO.
1
Digital
Digital
LIN receive data output, open-drain
2
Sleep mode control input, integrated pull-down
Local wake-up input, high voltage
WAKE
TXD
GND
LIN
3
High Voltage
Digital
4
LIN transmit data input, integrated pulled down - active low after a local wake-up event
Ground connection
5
GND
6
Bus IO
LIN bus input/output line
VSUP
INH
7
Supply
High-voltage supply from the battery
8
High Voltage
Inhibit output to control system voltage regulators and supplies, high voltage
Thermal
Pad
Electrically connected to GND, connect the thermal pad to the printed circuit board
(PCB) ground plane for thermal relief
—
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7 Specification
7.1 Absolute Maximum Ratings
(1) (2)
MIN
–0.3
–60
–0.3
MAX
60
UNIT
VSUP
VLIN
Supply voltage range (ISO 17987)
LIN Bus input voltage (ISO 17987)
WAKE pin input voltage
V
V
V
60
VWAKE
60
60 and VO ≤
VINH
INH pin output voltage
V
–0.3
VSUP+0.3
VLOGIC_INPUT
VLOGIC_OUTPUT
IO
Logic input voltage
6
6
8
4
V
V
–0.3
–0.3
Logic output voltage
Digital pin output current
Inhibit output current
mA
mA
IO(INH)
WAKE output current due to ground shift
(VWAKE ≤VGND) –0.3 V thus current out of the
WAKE pin must be limited
IO(WAKE)
3
mA
TJ
Junction Temp
165
150
°C
°C
–55
Tstg
Storage temperature
-65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to the ground terminal.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM) classification level 3B: VSUP, INH, and WAKE with respect to
ground
±8000
Human body model (HBM) classification level 3B: LIN with respect to ground
±10000
±4000
VESD Electrostatic discharge
V
Human body model (HBM) classification level 3A: all other pins, per AEC Q100-002(1)
Charged device model (CDM) classification
All pins
±750
level C5, per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings - IEC Specification
VALUE
UNIT
IEC 62228-2 per ISO 10605
Contact discharge
R = 330 Ω, C = 150 pF (IEC 61000-4-2)
LIN, VSUP, WAKE terminal to GND(1)
LIN terminal to GND(1)
±8000
±8000
VESD Electrostatic discharge
V
IEC 62228-2 per ISO 10605
Indirect contact discharge
R = 330 Ω, C = 150 pF (IEC 61000-4-2)
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7.3 ESD Ratings - IEC Specification (continued)
VALUE
UNIT
IEC 62228-2 per IEC 62215-3
12 V electrical systems
Pulse 1
-100
IEC 62215-3
24 V electrical systems (3)
Pulse 1
-450
75
IEC 62228-2 per IEC 62215-3
12 V electrical systems
24 V electrical systems (3)
Pulse 2
Non-synchronous transient
LIN, VSUP, WAKE terminal to GND(1)
injection
IEC 62228-2 per IEC 62215-3
12 V electrical systems
Pulse 3a
-150
-225
150
VTRAN
V
IEC 62215-3
24 V electrical systems (3)
Pulse 3a
IEC 62228-2 per IEC 62215-3
12 V electrical systems
Pulse 3b
IEC 62215-3
24 V electrical systems (3)
Pulse 3b
225
±30
SAE J2962-1 per ISO 7637-3
DCC - Slow transient pulse
Direct capacitor coupling
LIN terminal to GND(2)
(1) Results given here are specific to the IEC 62228-2 Integrated circuits –EMC evaluation of transceivers –Part 2: LIN transceivers.
Testing performed by OEM approved independent 3rd party, EMC report available upon request.
(2) Results given here are specific to the SAE J2962-1 Communication Transceivers Qualification Requirements - LIN. Testing performed
by OEM approved independent 3rd party, EMC report available upon request.
(3) Verified during characterization
7.4 Thermal Information
TLIN2021A-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.2
66.4
DRB (VSON)
8 Pins
54.4
DDF(SOT)
8 PINS
120.7
60.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
61.1
69.6
26.8
42.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.7
2.3
2.4
ΨJT
68.9
26.7
41.9
ΨJB
RθJC(bot)
10.8
–
–
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Recommended Operating Conditions
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
MIN
4.5
0
NOM
MAX
45
UNIT
V
VSUP
VLIN
Supply Voltage
LIN Bus input voltage
45
V
VLOGIC
TJ
Logic Pin Voltage
0
5.25
150
V
Operating virtual junction temperature range
Thermal shutdown rising
Thermal shutdown falling
Thermal shutdown hysteresis
-40
160
°C
°C
°C
°C
TSDR
TSDF
TSD(HYS)
150
10
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7.6 Power Supply Characteristics
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage and Current
Device is operational beyond the LIN
defined nominal supply voltage range
See Figure 8-1
Operational supply voltage
Nominal supply voltage
4.5
45
V
See Figure 8-2
VSUP
Normal and standby modes(1)
See Figure 8-1
See Figure 8-2
4.5
4.5
45
45
V
V
Sleep mode
Normal mode
1.8
1
7.5
mA
EN = VCC, RLIN ≥500 Ω, CLIN ≤10 nF, INH
= WAKE = VSUP
Supply current
Bus dominant
Standby mode
EN = 0 V, RLIN ≥500 Ω, CLIN ≤10 nF, INH
=WAKE = VSUP
2.1
mA
Normal mode
EN = VCC, INH = WAKE = VSUP
400
20
850
55
µA
µA
Supply current
Bus recessive
ISUP
Standby mode
EN = 0 V, INH = WAKE = VSUP
4.5 V < VSUP ≤27 V, TJ = 125℃
EN = 0 V, LIN = WAKE = VSUP, TXD and
RXD floating
12
20
µA
µA
Supply current
Sleep mode
27 V < VSUP ≤45 V, TJ = 125℃
EN = 0 V, LIN = WAKE = VSUP, TXD and
RXD floating
26
UVSUPR
UVSUPF
UVHYS
Under voltage VSUP threshold
Under voltage VSUP threshold
Ramp up
4.15
4
4.45
V
V
V
Ramp down
3.5
Delta hysteresis voltage for VSUP under voltage threshold
0.13
(1) Normal mode ramp VSUP while LIN signal is a 10 kHz square wave with 50% duty cycle and 36 V swing.
7.7 Electrical Characteristics
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.6
5
UNIT
RXD Output Terminal
(4)
VOL
IOL
Low-level voltage
Based upon external pull-up to VCC
LIN = 0 V, RXD = 0.4 V
V
Low-level output current, open drain
Leakage current, high-level
1.5
mA
µA
ILKG
LIN = VSUP, RXD = VCC
–5
TXD Input Terminal
VIL
Low-level input voltage
0.8
V
V
VIH
ILKG
High-level input voltage
2
Low-level input leakage current
TXD = 0 V
5
8
µA
–5
Standby mode after a local wake-up event
VLIN = VSUP, WAKE = 0 V or VSUP, TXD = 1
V
ITXD(WAKE)
Local wake-up source recognition TXD
Internal pull-down resistor value
1.3
mA
RTXD
EN Input Terminal
125
350
800
kΩ
VIL
Low-level input voltage
0.8
5.25
500
5
V
V
–0.3
2
VIH
VHYS
IIL
High-level input voltage
Hysteresis voltage
By design and characterization
EN = 0 V
30
mV
µA
Low-level input current
Internal pull-down resistor
–5
125
REN
350
800
kΩ
LIN Terminal (Referenced to VSUP
)
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7.7 Electrical Characteristics (continued)
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXD = VCC, IO = 0 mA
7 V ≤VSUP ≤45 V
VOH
VOH
VOH
VOL
VOL
VOL
LIN recessive high-level output voltage(3)
0.85
VSUP
TXD = VCC, IO = 0 mA
7 V ≤VSUP ≤18 V
LIN recessive high-level output voltage(1) (2)
LIN recessive high-level output voltage(3)
LIN dominant low-level output voltage(3)
LIN dominant low-level output voltage(1) (2)
LIN dominant low-level output voltage(3)
0.8
3
VSUP
TXD = VCC, IO = 0 mA
4.5 V ≤VSUP ≤7 V
V
TXD = 0 V
7 V ≤VSUP ≤45 V
0.2
0.2
1.2
VSUP
VSUP
V
TXD = 0 V
7 V ≤VSUP ≤18 V
TXD = 0 V
4.5 V ≤VSUP ≤7 V
LIN dominant (including LIN dominant for
wake up)
See Figure 8-3
VBUSdom
Low-level input voltage(3)
0.4
VSUP
See Figure 8-4
LIN recessive
See Figure 8-3
See Figure 8-4
VBUSrec
High-level input voltage(3)
0.6
VSUP
VIH
VIL
LIN recessive high-level input voltage(1) (2)
LIN dominant low-level input voltge(1) (2)
0.47
0.4
0.6
VSUP
VSUP
7 V ≤VSUP ≤18 V
7 V ≤VSUP ≤18 V
0.53
TXD & RXD open
4.5 V ≤VLIN ≤60 V
VSUP_NON_OP
VSUP where impact of recessive LIN bus < 5%(3)
60
V
–0.3
VBUS_CNT = (VBUSrec + VBUSdom)/2
See Figure 8-3
VBUS_CNT
Receiver center threshold(3)
0.475
0.5
0.525
VSUP
See Figure 8-4
VHYS = VBUSrec - VBUSdom
See Figure 8-3
See Figure 8-4
VHYS
Hysteresis voltage (ISO 17987)
Hysteresis voltage (SAE J2602)
0.175
VSUP
VHYS = VIH - VIL
See Figure 8-3
See Figure 8-4
VHYS
0.07
0.4
75
0.175
1.0
VSUP
V
VSERIAL_DIODE
IBUS(LIM)
Serial diode LIN termination pull-up path
Limiting current
ISERIAL_DIODE = 10 µA
0.7
TXD = 0 V, VLIN = 36 V, RMeas = 480 Ω
VSUP = 36 V, VBUSdom < 10.224 V
120
300
mA
Driver off/recessive, LIN = 0 V
VSUP = 24 V
IBUS_PAS_dom
Receiver leakage current, dominant
mA
–1
See Figure 8-6
Driver off/recessive, LIN ≥VSUP
4.5 V ≤VSUP ≤45 V
See Figure 8-7
IBUS_PAS_rec1
Receiver leakage current, recessive
Receiver leakage current, recessive
20
5
µA
µA
Driver off/recessive, LIN = VSUP
See Figure 8-7
IBUS_PAS_rec2
–5
GNDDevice = VSUP = 24 V
RMeas = 1 kΩ
IBUS_NO_GND
Leakage current, loss of ground
Leakage current, loss of ground(5)
1.5
mA
mA
–1.5
0 V < VLIN < 36 V
VSUP = 8 V, GND = open, VSUP = 18 V, GND
= open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = dominant
Ileak gnd(dom)
1
–1
VSUP = 8 V, GND = open, VSUP = 18 V, GND
= open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = recessive
Ileak gnd(rec)
Leakage current, loss of ground(5)
100
µA
–100
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7.7 Electrical Characteristics (continued)
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
VSUP = GND
0 V ≤VLIN ≤36 V
IBUS_NO_BAT
Leakage current, loss of supply
5
IRSLEEP
RPU
Pull-up current source to VSUP sleep mode
Pull-up resistor to VSUP
VSUP = 27 V, LIN = GND
Normal and standby modes
VSUP = 14 V
µA
–20
–1.5
60
20
45
kΩ
CLIN
Capacitance of the LIN pin
25
pF
INH Output Terminal
High level voltage drop INH with respect to VSUP
Leakage current sleep mode
IINH = - 0.5 mA
INH = 0 V
0.5
1
V
ΔVH
ILKG(INH)
0.5
µA
–0.5
WAKE Input Terminal
VSUP
–
VIH
VIL
High-level input voltage
Standby and sleep mode
Standby and sleep mode
V
V
1.8
VSUP
–
Low-level input voltage
3.85
IIH
High-level input leakage current
Low-level input leakage current
WAKE hold time
WAKE = VSUP - 1 V
WAKE = 1 V
µA
µA
µs
–25
–12.5
IIL
15
25
50
tWAKE
Wake up time from sleep mode
5
Duty Cycle Characteristics
THREC(MAX) = 0.744 x VSUP
THDOM(MAX) = 0.581 x VSUP
VSUP = 7 V to 18 V, tBIT = 50 µs
D1 = tBUS_rec(min)/(2 x tBIT
See Figure 8-8 and Figure 8-9
,
,
Duty cycle 1(3)
D112V
0.396
0.396
0.396
ISO 17987 Param 27
)
THREC(MAX) = 0.665 x VSUP
,
THDOM(MAX) = 0.499 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 50 µs
D112V
D112V
D212V
D212V
D212V
D312V
D312V
Duty cycle 1(3) (6)
D1 = tBUS_rec(min)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MAX) = 0.744 x VSUP
THDOM(MAX) = 0.581 x VSUP
VSUP = 7 V to 18 V, tBIT = 52 µs
D1 = tBUS_rec(min)/(2 x tBIT
See Figure 8-8 and Figure 8-9
,
,
Duty cycle 1(1) (2) (6)
)
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP
VSUP = 7 V to 18 V, tBIT = 50 µs
D2 = tBUS_rec(MAX)/(2 x tBIT
See Figure 8-8 and Figure 8-9
,
,
Duty cycle 2(3)
ISO 17987 Param 28
0.581
0.581
0.581
)
THREC(MIN) = 0.496 x VSUP
THDOM(MIN) = 0.361 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 50 µs
D2 = tBUS_rec(MAX)/(2 x tBIT
See Figure 8-8 and Figure 8-9
,
,
Duty cycle 2(3) (6)
)
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP
VSUP = 7 V to 18 V, tBIT = 52 µs
D2 = tBUS_rec(MAX)/(2 x tBIT
,
,
Duty cycle 2(1) (2) (6)
)
See Figure 8-8 and Figure 8-9
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
Duty cycle 3(3)
ISO 17987 Param 29
0.417
0.417
D3 = tBUS_rec(min)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MAX) = 0.665 x VSUP
THDOM(MAX) = 0.499 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 96 µs
Duty cycle 3(3) (6)
D3 = tBUS_rec(min)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
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7.7 Electrical Characteristics (continued)
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
Duty cycle 3(1) (2) (6)
D312V
D412V
D412V
D412V
D124V
D224V
D324V
D324V
D424V
0.417
D3 = tBUS_rec(min)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
Duty cycle 4(3)
ISO 17987 Param 30
0.59
0.59
0.59
D4 = tBUS_rec(MAX)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 96 µs
Duty cycle 4(3) (6)
D4 = tBUS_rec(MAX)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
Duty cycle 4(1) (2) (6)
D4 = tBUS_rec(MAX)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MAX) = 0.710 x VSUP
THDOM(MAX) = 0.554 x VSUP
VSUP = 15 V to 36 V, tBIT = 50 µs
D1 = tBUS_rec(min)/(2 x tBIT
See Figure 8-8 and Figure 8-9
,
,
Duty cycle 1
ISO 17987 Param 72
0.330
)
THREC(MIN) = 0.446 x VSUP
THDOM(MIN) = 0.302 x VSUP
VSUP = 15.6 V to 36 V, tBIT = 50 µs
D2 = tBUS_rec(MAX)/(2 x tBIT
,
,
Duty cycle 2
ISO 17987 Param 73
0.642
)
See Figure 8-8 and Figure 8-9
THREC(MAX) = 0.744 x VSUP
THDOM(MAX) = 0.581 x VSUP
VSUP = 7 V to 36 V, tBIT = 96 µs
Duty cycle 3
ISO 17987 Param 74
0.386
0.386
D3 = tBUS_rec(min)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MAX) = 0.645 x VSUP
THDOM(MAX) = 0.581 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 96 µs
Duty cycle 3 (6)
D3 = tBUS_rec(min)/(2 x tBIT
)
See Figure 8-8 and Figure 8-9
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP
VSUP = 4.5 V to 36 V, tBIT = 96 µs
D2 = tBUS_rec(MAX)/(2 x tBIT
See Figure 8-8 and Figure 8-9
,
,
Duty cycle 2 (6)
ISO 17987 Param 75
0.591
0.581
)
THREC(MAX) = 0.665 x VSUP
THDOM(MAX) = 0.499 x VSUP
VSUP = 5.5 V to 7 V, tBIT = 52 µs
,
,
D1LB
D2LB
D3LB
D4LB
Duty cycle 1 at low battery(1) (2) (6)
Duty cycle 2 at low battery(1) (2) (6)
Duty cycle 3 at low battery(1) (2) (6)
Duty cycle 4 at low battery(1) (2) (6)
0.396
0.396
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 52 µs
THREC(MAX) = 0.665 x VSUP
,
THDOM(MAX) = 0.499 x VSUP
VSUP = 5.5 V to 7 V, tBIT = 96 µs
,
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 96 µs
0.581
10.8
THREC(MAX) = 0.744 x VSUP
,
Transmitter propagation delay timings for the duty
cycle(1) (2) (6)
Recessive to dominant
THDOM(MAX) = 0.581 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 52 µs
tREC(MAX)_D1 - tDOM(MIN)_D1
Tr-d max_D1
µs
µs
THREC(MAX) = 0.422 x VSUP
,
Transmitter propagation delay timings for the duty
cycle(1) (2) (6)
Dominant to recessive
THDOM(MAX) = 0.284 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 52 µs
tDOM(MAX)_D2 - tREC(MIN)_D2
Td-r max_D2
8.4
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7.7 Electrical Characteristics (continued)
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 96 µs
tREC(MAX)_D3 - tDOM(MIN)_D3
Transmitter propagation delay timings for the duty
cycle(1) (2) (6)
Recessive to dominant
Tr-d max_D3
Td-r max_D4
Tr-d max_low
Td-r max_low
15.9
µs
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 96 µs
tDOM(MAX)_D4 - tREC(MIN)_D4
Transmitter propagation delay timings for the duty
cycle(1) (2) (6)
Dominant to recessive
17.28
10.8
8.4
µs
µs
µs
THREC(MAX) = 0.665 x VSUP
,
Low battery transmitter propagation delay timings
for the duty cycle(1) (2) (6)
Recessive to dominant
THDOM(MAX) = 0.499 x VSUP
5.5 V ≤VSUP ≤7 V, tBIT = 52 µs
tREC(MAX)_low - tDOM(MIN)_low
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
6.1 V ≤VSUP ≤7 V, tBIT = 52 µs
tDOM(MAX)_low - tREC(MIN)_low
Low battery transmitter propagation delay timings
for the duty cycle(1) (2) (6)
Dominant to recessive
(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ
(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
(4) RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage.
(5) Ileak gnd = (VBAT - VLIN)/RLoad
(6) Specified by design
7.8 AC Switching Characteristics
parameters valid across -40℃≤TJ ≤150℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device Switching Characteristics
Receiver rising propagation delay time
ISO 17987 Param 31
trx_pdr
trx_pdf
trx_pdr
trx_pdf
6
6
5
5
µs
µs
µs
µs
4.5 V ≤VSUP < 5.5 V, RRXD = 2.4 kΩ,
CRXD = 20 pF
See Figure 8-10 and Figure 8-11
Receiver falling propagation delay time
ISO 17987 Param 31
Receiver rising propagation delay time
ISO 17987 Param 31
5.5 V ≤VSUP, RRXD = 2.4 kΩ, CRXD = 20
pF
See Figure 8-10 and Figure 8-11
Receiver falling propagation delay time
ISO 17987 Param 31
Rising edge with respect to falling edge
trx_sym = trx_pdf –trx_pdr),
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 8-10 and Figure 8-11
Symmetry of receiver propagation delay time
Receiver rising propagation delay time
ISO 17987 Param 32
trs_sym
2
µs
–2
tLINBUS
tCLEAR
Minimum dominant time on LIN bus for wake-up
See Figure 8-14, Figure 9-2 and Figure 9-3
25
8
65
25
150
50
µs
µs
Time to clear false wake-up prevention logic if LIN
bus had a bus stuck dominant fault (recessive
time on LIN bus to clear bus stuck dominant fault)
See Figure 9-3
Time to change from normal mode to sleep
mode through EN pin
See Figure 8-12
tMODE_CHANGE Mode change delay time
2
15
45
µs
µs
Time for normal mode to initialize and data
on RXD pin to be valid, includes
tMODE_CHANGE for standby to normal mode.
See Figure 8-12
tNOMINT
Normal mode initialization time(1)
Time it takes for valid data on RXD upon
power-up
tPWR
Power-up time
1.5
80
ms
ms
tTXD_DTO
Dominant state time out
20
50
(1) The transition time from sleep mode to normal mode includes both tMODE_CHANGE and tNOMINT
.
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7.9 Typical Curves
40
35
30
25
20
15
10
5
1.8
1.6
1.4
1.2
1
-55°C
25°C
125°C
150°C
-55°C
25°C
125°C
150°C
0.8
0.6
0
0
0
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
D001
D002
图7-1. VOH vs VSUP vs Temperature
图7-2. VOL vs VSUP vs Temperature
3
2.5
2
500
450
400
350
300
250
200
150
1.5
1
-55°C
25°C
125°C
150°C
-55°C
25°C
125°C
150°C
0.5
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
D003
D004
图7-3. ISUP (DOM) vs VSUP vs Temperature
图7-4. ISUP (REC) vs VSUP vs Temperature
1.2
1
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-55°C
25°C
125°C
150°C
-55°C
25°C
125°C
150°C
5
10
15
Supply Voltage (V)
20
25
30
35
40
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
D005
D005
图7-5. ISUP(STBY_DOM) vs VSUP vs Temperature
图7-6. ISUP(STBY_REC) vs VSUP vs Temperature
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7.9 Typical Curves (continued)
16
14
12
10
8
-55°C
25°C
125°C
150°C
6
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
D007
图7-7. ISUP(SLP) vs VSUP vs Temperature
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8 Parameter Measurement Information
1
RXD
8
7
INH
5 V
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
2
VSUP
EN
3
WAKE
6
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
LIN
4
TXD
5
Jitter: < 25 ns
GND
Measurement Tools
O-scope:
DMM
Copyright © 2019, Texas Instruments Incorporated
图8-1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
Trigger Point
Delta t = + 5 µs (tBIT = 50 µs)
RX
2 * tBIT = 100 µs (20 kBaud)
Copyright © 2019, Texas Instruments Incorporated
图8-2. RX Response: Operating Voltage Range
A
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
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图8-3. LIN Bus Input Signal
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1
RXD
INH
8
7
5 V
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
2
VSUP
EN
6
5
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
3
4
WAKE
TXD
LIN
Jitter: < 25 ns
GND
Measurement Tools
O-scope:
DMM
Copyright © 2019, Texas Instruments Incorporated
图8-4. LIN Receiver Test with RX access Param 17, 18, 19, 20
8
7
RXD
EN
1
2
INH
5 V
Power Supply 1
Resolution: 10mV/ 1mA
VSUP
VPS1
Accuracy: 0.2%
D
6
5
3
4
WAKE
TXD
LIN
Power Supply 2
Resolution: 10mV/ 1mA
VPS2
Accuracy: 0.2%
RBUS
GND
Measurement Tools
O-scope:
DMM
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图8-5. VSUP_NON_OP Param 11
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8
7
RXD
EN
1
2
INH
5 V
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VSUP
RMEAS = 499 Ω
6
3
4
LIN
WAKE
TXD
5
GND
Measurement Tools
O-scope:
DMM
Copyright © 2019, Texas Instruments Incorporated
图8-6. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Param 13
Power Supply 1
Resolution: 10mV/ 1mA
1
2
8
7
INH
RXD
EN
5 V
VPS1
Accuracy: 0.2%
VSUP
Power Supply 2
Resolution: 10mV/ 1mA
1 kΩ
6
Accuracy: 0.2%
VPS2
LIN
3
4
WAKE
TXD
VPS2 2 V/s ramp [8 V < 18 V]
VDROPR < 20 mV
5
GND
Measurement Tools
O-scope:
DMM
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图8-7. Test Circuit for IBUS_PAS_rec Param 14
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8
7
INH
1
2
RXD
5 V
Power Supply 1
Resolution: 10mV/ 1mA
VSUP
EN
VPS1
Accuracy: 0.2%
RMEAS
6
3
4
WAKE
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Power Supply 2
Resolution: 10mV/ 1mA
VPS2
5
Accuracy: 0.2%
TXD
GND
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2019, Texas Instruments Incorporated
图8-8. Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30
TBIT
D = 50%
TXD (Input)
D124: 0.710 * VSUP
D324: 0.744 * VSUP
D112: 0.744 * VSUP
D312: 0.778 * VSUP
THREC(MAX)
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
Thresholds
RX Node 1
D112: 0.581 * VSUP
D312: 0.616 * VSUP
D124: 0.554 * VSUP
D324: 0.581 * VSUP
LIN Bus
Signal
D212: 0.422 * VSUP
D412: 0.389 * VSUP
D224: 0.446 * VSUP
D424: 0.422 * VSUP
VSUP
Thresholds
RX Node 2
D212: 0.284 * VSUP
D412: 0.251 * VSUP
D224: 0.302 * VSUP
D424: 0.284 * VSUP
tBUS_REC(MIN)
tBUS_DOM(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
图8-9. Definition of Bus Timing Parameters
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8
7
INH
1
2
RXD
5 V
Power Supply 1
Resolution: 10mV/ 1mA
VSUP
EN
VPS1
Accuracy: 0.2%
RMEAS
6
3
4
WAKE
LIN
Pulse Generator
Power Supply 2
Resolution: 10mV/ 1mA
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
VPS2
5
Accuracy: 0.2%
TXD
GND
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2019, Texas Instruments Incorporated
图8-10. Propagation Delay Test Circuit; Param 31, 32
D1: 0.744 * VSUP
D3: 0.778 * VSUP
D124: 0.710 * VSUP
D324: 0.744 * VSUP
THREC(MAX)
Thresholds
RX Node 1
D1: 0.581 * VSUP
D3: 0.616 * VSUP
D124: 0.554 * VSUP
D324: 0.581 * VSUP
THDOM(MAX)
LIN Bus
Signal
D2: 0.422 * VSUP
D4: 0.389 * VSUP
D224: 0.446 * VSUP
D424: 0.422 * VSUP
VSUP
THREC(MIN)
Thresholds
RX Node 2
D2: 0.284 * VSUP
D4: 0.251 * VSUP
D224: 0.302 * VSUP
D424: 0.284 * VSUP
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
图8-11. Propagation Delay
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Wake Event
tMODE_CHANGE
tNOMINT
tMODE_CHANGE
EN
Transition
Sleep
Standby
Transition
Normal
Normal
MODE
Indeterminate
Ignore
Mirrors
Bus
Wake Request
RXD = Low
RXD
Floating
Indeterminate Ignore
Mirrors Bus
图8-12. Mode Transitions
EN
Weak Internal Pulldown
TXD
Weak Internal Pulldown
VSUP
LIN
RXD
Floating
Sleep
MODE
Normal
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图8-13. Wake-up Through EN
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0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
tLINBUS
TXD
Weak Internal Pull-down
EN
Floating
RXD
MODE
Sleep
Standby
Normal
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图8-14. Wake-up through LIN
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9 Detailed Description
9.1 Overview
The TLIN2021A-Q1 is a local interconnect network (LIN) physical layer transceiver, compliant to LIN 2.0, LIN 2.1,
LIN 2.2, LIN 2.2A, SAE J2602-1, SAE J2602-2, ISO 17987–4, and ISO 17987–7 standards. LIN is a low-speed
universal asynchronous receiver transmitter (UART) communication protocol focused on automotive in-vehicle
networking.
The device transmitter supports data rates from 2.4-kbps to 20-kbps and the receiver supports data rates up to
100-kbps for end-of-line programming. The device controls the state of the LIN bus through the TXD pin and
reports the state of the bus through its open-drain RXD output pin. The LIN protocol data stream on the TXD
input is converted by the device into a LIN bus signal using an optimized electromagnetic emissions current-
limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the data
stream to logic-level signals that are sent to the microcontroller through the open-drain RXD pin. The LIN bus
has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive
state, the LIN bus is pulled high by the transceivers internal pull-up resistor (45-kΩ) and a series diode. No
external pull-up components are required for responder node applications. Commander node applications
require an external pull-up resistor (1-kΩ) as well as a series diode per the LIN specification.
The device is designed to support 12-V and 24-V applications with a wide input voltage operating range and also
supports low-power sleep mode. The device supports wake-up from low-power mode through wake over LIN,
the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by
selectively enabling the various power supplies that may be present on a node through the INH output pin.
The TLIN2021A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required
external components in the applications. In the event of a ground shift or supply voltage disconnection, the
device prevents back-feed current through LIN to the supply input.
The TLIN2021A-Q1 also includes undervoltage detection, temperature shutdown protection, and loss-of-ground
protection. In the event of a fault condition, the transmitter is immediately switched off and remains off until the
fault condition is removed.
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9.2 Functional Block Diagram
INH
VSUP/2
RXD
VSUP
Comp
Filter
EN
45 kΩ
350 kΩ
Wake Up
State & Control
VSUP
Fault Detection
& Protection
LIN
WAKE
WAKE
DR/
Slope
CTL
Dominant
State
Time-Out
TXD
350 kΩ
GND
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9.3 Feature Description
9.3.1 LIN
This high voltage input/output pin is the single-wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 60-V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking
diodes, even in the event of a ground shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The LIN transmitter has thresholds and AC switching parameters according to the LIN specification. The
transmitter is a low-side transistor with internal current limitation and thermal shutdown. During a thermal
shutdown condition, the transmitter is disabled to protect the device. There is an internal pull-up resistor with a
serial diode structure to VSUP, so no external pull-up components are required for LIN responder node
applications. An external pull-up resistor and series diode to VSUP must be added when the device is used in a
commander node application per the LIN specification.
9.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are proportional to the device supply pin in accordance to the LIN
specification.
The receiver is capable of receiving higher data rates, > 100 kbps, than supported by LIN or SAEJ2602
specifications. This allows the TLIN2021A-Q1 to be used for high-speed downloads at the end-of-line production
or other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pull-up resistance) and driver characteristics used in the system.
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9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN responder node applications. An external pull-up resistor (1-kΩ) and a series diode to VSUP
must be added when the device is used for commander node applications as per the LIN specification.
图9-1 shows a commander node configuration and how the voltage levels are defined
Voltage drop across the
Simplified Transceiver
VLIN_Bus
diodes in the pull-up path
VSUP
VSUP
VSUP/2
RXD
VBattery
VSUP
VLIN_Recessive
Receiver
Filter
1 kQ
45 kQ
LIN Bus
LIN
TXD
350 kQ
GND
Transmitter
with slope control
VLIN_Dominant
t
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图9-1. Commander Node Configuration with Voltage Levels
9.3.2 TXD
TXD is the interface to the MCU LIN protocol controller or SCI and UART that is used to control the state of the
LIN output. When TXD is low the LIN output is dominant (near ground) and when TXD is high the LIN output is
recessive (near VSUP), see 图9-1.
The TXD input structure is compatible with 3.3-V and 5-V microcontrollers and integrates a weak pull-down
resistor. The LIN bus is protected from being stuck dominant through a system failure driving TXD low through
the dominant state time-out timer. When a change of state on the WAKE pin initiates a local wake-up event, the
TXD pin is pulled hard to ground indicating a local wake-up event. The hard pull to ground is released upon the
rising edge on the EN pin. If an external pull-up resistor is added to the TXD pin to the microcontroller's IO
voltage then TXD is pulled high to indicate a remote wake-up event.
9.3.3 RXD
RXD is the interface to the MCU’s LIN protocol controller or SCI and UART, which reports the state of the LIN
bus voltage. LIN recessive (near VSUP) is represented by a high level on the RXD and LIN dominant (near
ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.
This allows the device to be used with 3.3-V and 5-V microcontrollers. If the microcontroller's RXD pin does not
have an integrated pull-up, an external pull-up resistor to the microcontroller's IO supply voltage is required. In
standby mode, the RXD pin is driven low to indicate a wake-up request.
9.3.4 VSUP
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse-blocking diode, see
图9-1. If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which
does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition
supplied) while the rest of the network remains powered (battery supplied).
9.3.5 GND
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
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device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
9.3.6 EN
EN controls the operational modes of the device. When EN is high the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep
mode and there are no transmission paths available. The device can enter normal mode only after wake-up. EN
has an internal pull-down resistor to ensure the device remains in low power mode even if EN floats.
9.3.7 WAKE
The WAKE pin is a high-voltage input used for the local wake-up (LWU) function. This function is explained
further in 节 9.4.4.1 section. The pin is defaulted to bidirectional edge trigger, meaning it recognizes a local
wake-up (LWU) on a rising or falling edge of WAKE pin transition.
9.3.8 INH
The TLIN2021A-Q1 inhibit, INH, output pin can be used to control the enable of system power-management
devices allowing for a significant reduction in battery quiescent current consumption while the application is in
sleep mode. The INH pin has two states: driven high and high impedance. When the INH pin is driven high, the
terminal shows VSUP minus a diode voltage drop. In the high impedance state the output is left floating. The INH
pin is high in the normal and standby modes and is low when in sleep mode. A 100 kΩload can be added to the
INH output to ensure a fast transition time from the driven high state to the low state and to also force the pin low
when left floating.
The INH terminal should be considered a high-voltage logic terminal and not a power output. Thus should be
used to drive the EN terminal of the systems power-management device and not used as a switch for the power-
management supply itself. This terminal is not reverse battery protected and thus should not be connected
outside the system module.
9.3.9 Local Faults
The TLIN2021A-Q1 has several protection features that are described as follows.
9.3.10 TXD Dominant Time-Out (DTO)
While the LIN driver is in active mode a TXD DTO circuit prevents the local node from blocking network
communication in the event of a hardware or software failure where TXD is held dominant longer than the time-
out period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before
the time-out constant of the circuit, tTXD_DTO, expires the LIN driver is disabled releasing the bus line to the
recessive level. This keeps the bus free for communication between other nodes on the network. The LIN driver
is re-activated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time-
out. During this fault, the transceiver remains in normal mode, the integrated LIN bus pull-up termination remains
on, and the LIN receiver and RXD terminal remain active reflecting the LIN bus data.
The TXD pin has an internal pull-down to ensure the device fails to a known state if TXD is disconnected. If EN
pin is high at power-up, the TLIN2021A-Q1 enters normal mode. With the internal TXD connected low, the DTO
timer starts. To avoid a tTXD_DTO fault, a recessive signal should be put onto the TXD pin before the tTXD_DTO
timer expires, or the device should be into sleep mode by connecting EN pin low.
9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
The TLIN2021A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from
waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.
If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus clears the bus stuck
dominant fault, preventing excessive current use, see 图9-2 and 图9-3.
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RXD
EN
LIN Bus
tLINBUS
< tLINBUS
< tLINBUS
图9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wake-up
RXD
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
图9-3. Bus Fault: Entering Sleep Mode With Bus Stuck Dominant Fault, Clearing, and Wake-up
9.3.12 Thermal Shutdown
The TLIN2021A-Q1 transmitter is protected by limiting the current. If the junction temperature, TJ, of the device
exceeds the thermal shutdown threshold, TJ > TSDR, the device puts the LIN transmitter into the recessive state.
Once the over temperature fault condition has been removed and the junction temperature has cooled beyond
the hysteresis temperature, the transmitter is re-enabled. During this fault, the transceiver remains in normal
mode, the integrated LIN bus pull-up termination remains on, the LIN receiver and RXD terminal remain active
reflecting the LIN bus data.
9.3.13 Under Voltage on VSUP
The device contains a power on reset circuit to avoid false bus messages during under voltage conditions when
VSUP is less than UVSUP
.
9.3.14 Unpowered Device
In automotive applications, some LIN nodes in a system can be unpowered, ignition supplied, while others in the
network remains powered by the battery. The device has extremely low unpowered leakage current from the bus
so an unpowered node does not affect the network or load it down.
9.4 Device Functional Modes
The TLIN2021A-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections
describe these modes and how the device transitions between the different modes. 图 9-4 graphically shows the
relationship while 表9-1 shows the state of pins.
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表9-1. Operating Modes
LIN BUS
TERMINATION
TRANSMITTE
R
MODE
EN
TXD
RXD
INH
COMMENT
Weak current
pull-up
Sleep
Low
Low
High
Weak pull-down
Floating
Floating
Off
Off
On
Weak pull-down if LIN bus wake-
up; Strong pull-down if a local
wake-up event (WAKE pin)
Wake-up event detected,
waiting on MCU to set
EN
Standby
Normal
Low
High
High
45-kΩ
45-kΩ
High: recessive state
Low: dominant state
LIN transmission up to 20
kbps
LIN Bus Data
Unpowered System
VSUP < UVSUP
VSUP < UVSUP
VSUP > UVSUP
EN = Low
VSUP < UVSUP
VSUP > UVSUP
EN = High
Standby Mode
Driver: Off
RXD: Low
TXD:
VSUP < UVSUP
weak pull-down for LIN bus wake
Hard pull-down for WAKE pin wake
INH: On
Normal Mode
LIN termination: 45 kΩ
Driver: On
RXD: LIN Bus Data
TXD:
High for recessive
Low for dominant
INH: On
Sleep Mode
EN = High
LIN bus wake up or
WAKE pin wake up
Driver: Off
RXD: Floating
TXD: Weak pull-down
INH: Off
LIN termination: Weak pull-up
EN = Low
EN = High
LIN termination: 45 kΩ
图9-4. Operating State Diagram
9.4.1 Normal Mode
The EN pin controls the mode of the device. If the EN pin is high at power-up the device powers up in normal
mode, if the EN is low at power-up the device powers up in standby mode. In normal mode the receiver and
transmitter fully operational. The LIN transmitter transmits data from the LIN controller to the LIN bus up to the
LIN specified maximum data rate of 20-kbps. The LIN receiver detects the data stream on the LIN bus up to data
rates of 100-kbps and outputs the data on RXD output for the LIN controller. Upon an EN pin transition from low
to high the TLIN2021A-Q1 transitions from sleep mode to normal mode in t ≥tNOMINT
.
9.4.2 Sleep Mode
Sleep mode is the lowest power mode of the TLIN2021A-Q1 and is only entered from normal mode when the EN
pin transitions from high to low for t > tMODE_CHANGE. In sleep mode, the LIN driver and receiver are switched off,
the LIN bus is weakly pulled up, and the transceiver cannot send or receive data. The INH pin is switched to a
floating output in sleep mode causing any system power elements controlled by the INH pin to be switched off
thus reducing the system power consumption. While the device is in sleep mode, the following conditions exist:
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• The LIN bus driver is disabled and the internal LIN bus termination is switched off to minimize power loss if
LIN is short circuited to ground.
• A weak current pull-up is active to prevent false wake-up events in case an external connection to the LIN
bus is lost.
• The normal receiver is disabled.
• EN input, WAKE pin and LIN wake-up receiver are active.
The TLIN2021A-Q1 supports three methods for wake-up from sleep mode:
• Wake-up over the LIN bus via the LIN wake-up receiver.
• Local wake-up via the WAKE pin.
• Local wake-up via the EN pin. The EN pin must be set high for t > tNOMINT in order for the device to wake-up.
9.4.3 Standby Mode
Standby mode is entered whenever a wake-up event occurs through LIN bus or the WAKE pin while the device
is in sleep mode. In standby mode, the LIN bus responder termination circuit, 45-kΩ, is on. When a wake-up
event occurs and the TLIN2021A-Q1 enters standby mode the RXD pin is driven low signaling the wake-up
event to the LIN controller.
The TLIN2021A-Q1 exits standby mode and transitions to normal mode when the EN pin is set high for longer
than tMODE_CHANGE where the normal LIN transmitter and receiver are fully operational and bi-directional
communication is possible.
9.4.4 Wake-Up Events
There are three ways to wake-up the TLIN2021A-Q1 from sleep mode:
• Remote wake-up initiated by the falling edge of a recessive-to-dominant state transition on the LIN bus where
the dominant state is held longer than tLINBUS filter time. After the tLINBUS filter time has been met a rising
edge on the LIN bus going from dominant-to-recessive initiates a remote wake-up event. The pattern and
tLINBUS filter time used for the LIN wake-up prevents noise and bus stuck dominant faults from causing false
wake requests.
• A local wake-up event due to the EN pin being set high for t > tMODE_CHANGE
.
• A local wake-up event due to a change in voltage level on the WAKE pin for t > tWAKE
9.4.4.1 Local Wake-Up (LWU) via WAKE Input Terminal
The WAKE terminal is a bi-directional high-voltage input which can be used for local wake-up (LWU) requests via
a voltage transition. A LWU event is triggered on either a low-to-high or high-to-low transition since it has bi-
directional input thresholds. The WAKE pin could be used with a switch to VSUP or to ground. If the terminal is
unused it should be pulled to VSUP or ground to avoid unwanted parasitic wake-up events. When a LWU event
takes place the TXD pin is pulled hard to GND letting the LIN controller know that the wake-up event was due to
the WAKE pin and not a wake over LIN event.
The LWU circuitry is active in standby mode and sleep mode. If a valid LWU event occurs in standby mode, the
device remains in standby mode and drive the RXD output low. If a valid LWU event occurs in sleep mode, the
device transitions to standby mode and drives the RXD output low. The LWU circuitry is not active in normal
mode. To minimize system-level current consumption, the internal bias voltages of the terminal follows the state
on the terminal with a delay of tWAKE(MIN). A constant high level on WAKE has an internal pull-up to VSUP, and a
constant low level on WAKE has an internal pull-down to GND.
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Wake
Threshold
Not Crossed
t ≤ tWAKE
No Wake
UP
t ≥ tWAKE
Wake UP
Wake
Local Wake Request
INH
Pull-down
Latched Low
TXD
RXD
*
Mode
Sleep Mode
Standby Mode
图9-5. Local Wake-Up –Rising Edge
Wake
Threshold
Not Crossed
t ≤ tWAKE
No Wake
UP
t ≥ tWAKE
Wake UP
Wake
Local Wake Request
INH
Pull-down
Latched Low
TXD
RXD
*
Mode
Sleep Mode
Standby Mode
Copyright © 2019, Texas Instruments Incorporated
图9-6. Local Wake-Up –Falling Edge
9.4.4.2 Wake-Up Request (RXD)
When the TLIN2021A-Q1 encounters a wake-up event from the WAKE pin or the LIN bus, the RXD output is
driven low until EN is asserted high, the device enters normal mode. Once the device enters normal mode, the
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wake-up event is cleared, and the RXD output is released. The RXD output is fully operational and reflects the
receiver output from the LIN bus.
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10 Application Information Disclaimer
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
The TLIN2021A-Q1 can be used in both a responder node application and a commander node application in a
LIN network.
10.2 Typical Application
The device integrates a 45-kΩ pull-up resistor and series diode for responder node applications. For commander
node applications, an external 1-kΩ pull-up resistor with series blocking diode can be used. 图 10-1 shows the
device being used in both commander node and responder node applications.
VSUP
Commander
Node
VREG
VSUP
SW
GND
3 kꢀ
EN
VDD
VDD
VSUP
INH
2
WAKE
(4)
EN
8
3
7
I/O
VDD
Commander
Node
MCU w/o
pull-up(2)
Pullup(3)
VDD I/O
1 kΩ
LIN
MCU
TLIN2021A
6
LIN Controller
Or
1
4
220 pF
RXD
TXD
SCI/UART(1)
GND
5
VSUP
Responder
Node
VREG
VSUP
SW
3 kꢀ
GND
EN
VDD
VDD
VSUP
INH
2
WAKE
3
(4)
EN
8
7
I/O
VDD
MCU w/o
pull-up(2)
VDD I/O
LIN
MCU
TLIN2021A
6
LIN Controller
Or
1
4
220 pF
RXD
TXD
SCI/UART(1)
GND
5
(1) If RXD on MCU or LIN responder node has internal pull-up; no external pull-up resistor is needed.
(2) If RXD on MCU or LIN responder node does not have an internal pull-up requires external pull-up resistor.
(3) Commander node applications require and external 1 kΩ pull-up resistor and serial diode.
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥10 µF
图10-1. Typical LIN Bus
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10.2.1 Design Requirements
The RXD output structure is an open-drain output stage which allows the TLIN2021A-Q1 to be used with 3.3-V
and 5-V controllers. If the RXD pin of the controller does not have an integrated pull-up, an external pull-up
resistor to the controller's IO voltage is required. The external pull-up resistor value should be between 1-kΩ to
10-kΩ. The VSUP pin of the device should be decoupled with a 100-nF capacitor by placing it close to the VSUP
supply pin. The system should include additional decoupling on the VSUP line as needed per the application
requirements.
10.2.2 Detailed Design Procedures
10.2.2.1 Normal Mode Application Note
When using the TLIN2021A-Q1 in systems which are monitoring the RXD pin for a wake-up request, special
care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition
period between states as the receivers are switched. The application software should not look for an edge on the
RXD pin indicating a wake-up request until tMODE_CHANGE has been met. This is shown in 图8-12
10.2.2.2 TXD Dominant State Time-Out Application Note
The maximum dominant TXD time allowed by the TXD dominant state time-out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for commander node and responder node
applications thus there are different maximum consecutive dominant bits for each application case thus different
minimum data rates.
10.2.2.3 Standby Mode Application Note
If the TLIN2021A-Q1 detects an under voltage on VSUP the RXD pin transitions low signaling to the controller
that the TLIN2021A-Q1 is in standby mode. The transceiver should be returned to sleep mode for the lowest
power state.
10.2.3 Application Curves
图 10-2 and 图 10-3 show the propagation delay from the TXD pin to the LIN pin for the dominant to recessive
and recessive to dominant edges. Device was configured in commander mode with external pull-up resistor (1
kΩ) and 680 pF bus capacitance.
图10-2. Dominant To Recessive Propagation Delay 图10-3. Recessive to Dominant Propagation Delay
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11 Power Supply Recommendations
The TLIN2021A-Q1 was designed to operate directly from a car battery, or any other DC supply ranging from
4.5-V to 45-V. The VSUP pin of the device should be decoupled with a 100-nF capacitor by placing it close to the
VSUP supply pin. The system should include additional decoupling on the VSUP line as needed per the application
requirements. Device has been designed and tested to support supply ramp rates equal to or slower than 0.5
V/µs.
12 Layout
For the PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD
transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz, high-frequency layout
techniques must be applied during PCB design. Placement at the connector also prevents these noisy events
from propagating further into the PCB and system.
12.1 Layout Guidelines
• Pin 1(RXD): The RXD pin is an open-drain output and requires and external pull-up resistor in the range of 1-
kΩ and 10-kΩ to function properly. If the controller paired with the transceiver does not have an integrated
pull-up, an external resistor should be placed between RXD and the supply voltage for the controller.
• Pin 2 (EN): EN is an input pin that is used to place the device in low-power sleep mode. If this feature is not
used, the pin should be connected to the supply voltage for the controller through a series resistor using a
pull-up value between 1-kΩ and 10-kΩ. Additionally, a series resistor may be placed on the pin to limit current
on the digital lines in the case of an over voltage fault.
• Pin 3 (WAKE): SW1 is oriented in a low-side configuration which is used to implement a local WAKE event.
The series resistor R5 is needed for protection against over current conditions as it limits the current into the
WAKE pin when the ECU has lost its ground connection. The pull-up resistor R4 is required to provide
sufficient current during stimulation of a WAKE event. In this layout example R4 is set to 3-kΩand R5 is set
to 33-kΩ.
• Pin 4 (TXD): The TXD pin is the transmit input signal to the device from the controller. A series resistor can
be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to help filter noise.
• Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
• Pin 6 (LIN): The LIN pin connects to the TLIN2021A-Q1 to the LIN bus. For responder node applications a
220 pF capacitor to ground is implemented. For commander node applications an additional series resistor
and blocking diode should be placed between the LIN pin and the VSUP pin, see Typical LIN Bus.
• Pin 7 (VSUP): This is the supply pin for the device. A 100-nF capacitor should be placed close to the VSUP
supply pin for local power supply decoupling.
• Pin 8 (INH):The INH pin is used for system power-management. A 100-kΩload can be added to the INH
output to ensure a fast transition time from the driven high state to the low state and to also force the pin low
when left floating.
备注
All ground and power connections should be made as short as possible and use at least two vias to
minimize the total loop inductance.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: TLIN2021A-Q1
TLIN2021A-Q1
ZHCSMB3A –MARCH 2021 –REVISED APRIL 2022
www.ti.com.cn
12.2 Layout Example
GND
GND
RXD
EN
INH
VSUP
LIN
R3
INH
VSUP
C2
VSUP
WAKE
TXD
R1
To Switch
R2
LIN
C1
GND
图12-1. Layout Example
Copyright © 2022 Texas Instruments Incorporated
32
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TLIN2021A-Q1
ZHCSMB3A –MARCH 2021 –REVISED APRIL 2022
www.ti.com.cn
13 Device and Documentation Support
13.1 Documentation Support
13.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLIN2021ADRBRQ1
ACTIVE
SON
DRB
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL021A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLIN2021ADRBRQ1
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DRB
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TLIN2021ADRBRQ1
8
3000
Pack Materials-Page 2
PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
0.26
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
C
SYMM
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
(1.65)
8X (0.6)
8X (0.31)
SYMM
1
8
6X (0.65)
SYMM
9
(1.95) (2.4)
(0.95)
(R0.05) TYP
4
5
(Ø 0.2) VIA
TYP
(0.575)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225036/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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