TLIN2022ADRQ1_技术文档

TLIN2022A-Q1

ZHCSNE3 –JUNE 2021

TLIN2022A-Q1 具有显性状态超时的双路本地互连网络(LIN) 收发器

1 特性

2 应用

• 符合面向汽车应用的AEC-Q100（1 级）标准

• 符合LIN 2.0、LIN 2.1、LIN 2.2、LIN 2.2 A 和

ISO/DIS 17987–4 电气物理层(EPL) 规格标准

• 符合面向汽车应用的SAE J2602-1 LIN 网络标准

• 提供功能安全

• 车身电子装置和照明

• 混合动力电动汽车和动力总成系统

• 信息娱乐系统与仪表组

• 电器

3 说明

– 可帮助进行功能安全系统设计的文档

• 支持12V 和24V 电池应用

• LIN 传输数据速率高达20kbps

• LIN 接收数据速率高达100kbps

• 宽工作电源电压范围：4V 至48V

• 休眠模式：超低电流消耗允许以下类型的唤醒事

件：

TLIN2022A-Q1 是一款双路本地互连网络 (LIN) 物理层

收发器，集成了唤醒和保护功能，符合 LIN 2.0、LIN

2.1、LIN 2.2、LIN 2.2A 和 ISO/DIS 17987–4 标准。

LIN 是一根单线制双向总线，通常用于低速车载网络，

数据传输速率高达 20kbps。TLIN2022A-Q1 旨在为

12V 和 24V 应用提供支持，具有更宽的工作电压范围

和额外的总线故障保护。

– LIN 总线

LIN 接收器支持高达 100kbps 的数据传输速率，从而

更快速地执行内联编程TLIN2022A-Q1 使用一个可降

低电磁辐射 (EME) 的限流波形整形驱动器将 TXD 输入

上的 LIN 协议数据流转化为 LIN 总线信号。接收器将

数据流转化为逻辑电平信号，此信号通过开漏 RXD 引

脚发送到微处理器。休眠模式可实现超低电流消耗，该

模式允许通过LIN 总线或EN 引脚实现唤醒。

– 通过EN 引脚的本地唤醒

• 在LIN 总线和RXD 输出上实现上电和断电无干扰

运行

• 保护特性：

– ±60V LIN 总线容错

– V_SUP欠压保护

– TXD 显性超时(DTO) 保护

– 热关断保护

器件信息

封装⁽¹⁾

– 系统级未供电节点或接地断开失效防护。

• 可提供具有可湿性侧面的SOIC (14) 和无引线

VSON (14) 封装

封装尺寸（标称值）

5.00mm x 8.65mm

3.00mm x 4.50mm

器件型号

SOIC (14) (D)

TLIN2022A-Q1

VSON (14) (DMT)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V_BAT

V_SUP

V_BAT

V_SUP

COMMANDER

NODE

VREG

V_SUP

VREG

V_SUP

RESPONDER

NODE

V_DD

V_SUP

V_DD

NC

14

NC

14

NC

6

NC

6

EN1

Commander Node

Pullup

10

V_DD

I/O

V_DD

I/O

2

V_DDI/O

1 kΩ

MCU w/o

pullup⁽²⁾

MCU w/o

pullup⁽²⁾

LIN1

LIN Bus

MCU

13

LIN Bus

220 pF

1

3

1

3

RXD1

TXD1

RXD1

TXD1

TLIN2022A

LIN Controller

Or

SCI/UART⁽¹⁾

LIN Controller

Or

SCI/UART⁽¹⁾

V_DDI/O

LIN Bus

MCU w/o

pullup⁽²⁾

LIN2

MCU w/o

pullup⁽²⁾

LIN2

9

220 pF

4

7

4

7

RXD2

TXD2

RXD2

TXD2

12 NC

11 NC

12 NC

11 NC

EN2

5

I/O

GND

8

GND

8

简化版原理图，指挥官模式

简化版原理图，响应者模式

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSFM6

TLIN2022A-Q1

ZHCSNE3 –JUNE 2021

www.ti.com.cn

Table of Contents

9.2 Functional Block Diagram.........................................23

9.3 Feature Description...................................................23

9.4 Device Functional Modes..........................................26

10 Application Information Disclaimer...........................29

10.1 Application Information........................................... 29

10.2 Typical Application.................................................. 29

11 Layout...........................................................................32

11.1 Layout Guidelines................................................... 32

11.2 Layout Example...................................................... 33

12 Device and Documentation Support..........................34

12.1 Documentation Support.......................................... 34

12.2 接收文档更新通知................................................... 34

12.3 支持资源..................................................................34

12.4 Trademarks.............................................................34

12.5 Electrostatic Discharge Caution..............................35

12.6 Glossary..................................................................35

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 说明（续）.........................................................................3

5 Revision History.............................................................. 3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 ESD Ratings - IEC ..................................................... 5

7.4 Thermal Information ...................................................6

7.5 Recommended Operating Conditions ........................6

7.6 Electrical Characteristics ............................................7

7.7 Duty Cycle Characteristics .........................................9

7.8 Switching Characteristics .........................................11

7.9 Typical Characteristics..............................................12

8 Parameter Measurement Information..........................14

9 Detailed Description......................................................22

9.1 Overview...................................................................22

Information.................................................................... 35

2

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4 说明（续）

TLIN2022A-Q1 集成了一个用于LIN 响应节点应用、ESD 保护和故障保护的电阻器，可减少应用中的外部元件数

量一旦发生接地漂移或电源电压断开，该器件可防止反馈电流经LIN 流向电源输入。器件还包含欠压保护、过热

关断保护和接地失效保护功能。

5 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

June 2021

*

Initial release

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6 Pin Configuration and Functions

RXD1

EN1

1

2

3

4

5

6

7

14

13

12

11

10

9

NC

RXD1

EN1

1

2

3

4

5

6

7

14

13

12

11

10

9

NC

LIN1

NC

LIN1

NC

TXD1

RXD2

EN2

TXD1

RXD2

EN2

Thermal

Pad

NC

VSUP

LIN2

GND

VSUP

LIN2

GND

NC

TXD2

8

TXD2

8

Not to scale

图6-2. DMT Package, 14-Pin (VSON), Top View

图6-1. D Package, 14-Pin (SOIC), Top View

表6-1. Pin Functions

NAME

Type

DESCRIPTION

NO.

1

RXD1

EN1

O

I

Channel 1 RXD Output (open-drain) interface reporting state of LIN bus voltage

Channel 1 Enable Input- High puts the channel 1 in normal operation mode and low puts it in

sleep mode

2

3

4

TXD1

RXD2

I

Channel 1 TXD input interface to control state of LIN output

O

Channel 2 RXD Output (open-drain) interface reporting state of LIN bus voltage

Channel 2 Enable Input- High puts the channel 2 in normal operation mode and low puts it in

sleep mode

5

EN2

I

7

8

TXD2

GND

LIN2

V_SUP

LIN1

I

Channel 2 TXD input interface to control state of LIN output

Ground

GND

9

HV I/O

Supply

HV I/O

Channel 2 High voltage LIN bus single-wire transmitter and receiver

Device Supply Voltage (connected to battery in series with external reverse blocking diode)

Channel 1 High voltage LIN bus single-wire transmitter and receiver

10

13

6, 11, 12,

14

NC

Not Connected

–

Can be connected to the PCB ground plane to improve thermal coupling (DMT package

only)

Thermal Pad

4

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7 Specifications

7.1 Absolute Maximum Ratings

(1) (2)

Symbol

Parameter

MIN

–0.3

–60

–0.3

MAX

60

6

UNIT

V

V_SUP

V_LIN

Supply voltage range (ISO/DIS 17987 Param 10)

LIN bus input voltage (ISO/DIS 17987 Param 82)

Logic pin voltage (RXD, TXD, EN)

Logic pin output current

V

V_LOGIC

I_O

V

8

mA

°C

T_J

Junction temperature range

150

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to ground terminal.

7.2 ESD Ratings

ESD Ratings

VALUE

UNIT

Human body model (HBM) classification level 3A: TXD, RXD,

EN Pins, per AEC Q100-002⁽¹⁾

±4000

Human body model (HBM) classification level 3B: LIN and V_SUP

Pin with respect to ground

±8000

±1500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM)

classification level C5, per AEC All pins

Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 ESD Ratings - IEC

ESD and Surge Protection Ratings

VALUE

UNIT

IEC 62228-2 per ISO 10605

Contact discharge

R = 330 Ω, C = 150 pF

Electrostatic discharge, LIN, V_SUPto

GND⁽¹⁾

V_(ESD)

±8000

V

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UNIT

7.3 ESD Ratings - IEC (continued)

ESD and Surge Protection Ratings

VALUE

IEC 62228-2 per IEC 62215-3

12 V electrical systems

Pulse 1

–100

IEC 62215-3

24 V electrical systems ⁽²⁾

Pulse 1

–450

IEC 62228-2 per IEC 62215-3

12 V electrical systems

24 V electrical systems ⁽²⁾

Pulse 2

75

ISO 7637-2 and IEC 62228-2 per IEC

62215-3 transients according to IBEE LIN IEC 62228-2 per IEC 62215-3

V_TRAN

V

EMC test specifications ⁽²⁾(LIN , V_SUPto 12 V electrical systems

–150

-225

100

GND )

Pulse 3a

IEC 62215-3

24 V electrical systems ⁽²⁾

Pulse 3a

IEC 62228-2 per IEC 62215-3

12 V electrical systems

Pulse 3b

IEC 62215-3

24 V electrical systems ⁽²⁾

Pulse 3b

225

(1) Results given here are specific to the IEC 62228-2 Integrated circuits –EMC evaluation of transceivers –Part 2: LIN transceivers.

Testing performed by OEM approved independent 3rd party, EMC report available upon request.

(2) Verified during characterization

7.4 Thermal Information

TLIN2022AD-Q1

TLIN2022ADMT-Q1

THERMAL METRIC⁽¹⁾

D (SOIC)

14-PINS

82.3

DMT (VSON)

14-PINS

35.5

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_ΘJC(top)

R_ΘJB

41.5

18.1

38.4

13.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

8.9

0.6

Ψ_JT

38.1

13.1

Ψ_JB

R_ΘJC(bot)

n/a

2.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Recommended Operating Conditions

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER - DEFINITION

MIN

4

NOM

MAX

48

UNIT

V

V_SUP

V_LIN

Supply voltage

LIN Bus input voltage

0

48

V

V_LOGIC

T_A

Logic Pin Voltage (RXD, TXD, EN)

Ambient temperature range

Thermal shutdown edge

Thermal shutdown hysteresis

0

5.25

125

V

-40

165

°C

TSD

TSD_(HYS)

15

6

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7.6 Electrical Characteristics

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

4

TYP

MAX UNIT

Power Supply

Device is operational beyond the LIN

defined nominal supply voltage range

See Figure 8-1 and Figure 8-2

Operational supply voltage (ISO/DIS

17987 Param 10, 53)

V_SUP

48

V

Normal and Standby Modes: ramp V_SUP

while LIN signal is a 10 kHZ square

wave with 50 % duty cycle and 36V

swing. See Figure 8-1 and Figure 8-2

Nominal supply voltage (ISO/DIS 17987

Param 10, 53)

4

V_SUP

Sleep Mode

4

48

V

UV_SUP

UV_HYS

Undervoltage V_SUPthreshold

2.9

3.85

Delta hysteresis voltage for V_SUP

undervoltage threshold

0.2

1.2

V

Normal Mode: EN = High, bus

dominant: total bus load where R_LIN

500 Ωand C_LIN< 10 nF

>

8.5

mA

I_SUP

Supply current

Standby Mode: EN = Low, bus

dominant: total bus load where R_LIN

500 Ωand C_LIN< 10 nF

1.1

3.75

mA

Normal Mode: EN = High, Bus

Recessive: LIN = V_SUP

670

20

1600

40

µA

Standby Mode: EN = Low, Bus

Recessive LIN = V_SUP

I_SUP

Supply current

Sleep Mode: 4.0 V < V_SUP< 14 V, LIN =

V_SUP, EN = 0 V, TXD and RXD Floating

10

20

Sleep Mode: 14 V < V_SUP< 36 V, LIN =

V_SUP, EN = 0 V, TXD and RXD floating

30

RXD1/RXD2 OUTPUT PIN (OPEN DRAIN)

(4)

V_OL

I_OL

Output Low voltage

Based upon external pull-up to V_CC

0.6

5

V

Low-level output current, open-drain

Leakage current, high-level

LIN = 0 V, RXD = 0.4 V

LIN = V_SUP, RXD = 5 V

1.5

mA

µA

I_ILG

0

–5

TXD1/TXD2 INPUT PIN

V_IL

V_IH

Low-level input voltage

0.8

V

–0.3

High-level input voltage

2

5.25

Input threshold voltage, normal modes&

selective wake modes

V_HYS

50

500

mV

I_ILG

Low-level input leakage current

Internal pull-down resitor value

TXD = Low

0

5

µA

–5

R_TXD

125

350

800

kΩ

EN1/EN2 INPUT PIN

V_IL

Low-level input voltage

0.8

5.25

500

5

V

–0.3

V_IH

High-level input voltage

Hysteresis voltage

2

V_HYS

By design and characterization

EN = Low

50

0

mV

µA

I_ILG

Low-level input current

Internal pull-down resistor

–5

R_EN

125

350

800

kΩ

LIN1/LIN2 PIN

LIN recessive, TXD = high, I_O= 0 mA, 7

V ≤V_SUP≤48 V

V_OH

HIGH level output voltage ⁽³⁾

0.85

0.8

V_SUP

LIN recessive high-level output voltage

TXD = high, IO = 0 mA, 7 V ≤V_SUP

≤

(1) (2)

18 V

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7.6 Electrical Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LIN recessive, TXD = high, I_O= 0 mA, 4

V ≤V_SUP< 7 V

V_OH

HIGH level output voltage⁽³⁾

3

V

LIN dominant, TXD = low, 7 V ≤V_SUP

≤48 V

V_OL

LOW level output voltage⁽³⁾

0.2 V_SUP

LIN dominant low- level output voltage

V_OL

TXD = low, 7 V ≤V_SUP≤18 V

(1) (2)

LIN dominant, TXD = low, 4 V ≤

V_SUP< 7 V

V_OL

LOW level output voltage⁽³⁾

1.2

58

V

VSUP where impact of recessive LIN

bus < 5% (ISO/DIS 17987 Param 56)

V_{SUP_NON_OP}

I_{BUS_LIM}

I_{BUS_PAS_dom}

I_{BUS_PAS_rec1}

I_{BUS_PAS_rec2}

I_{BUS_NO_GND}

TXD & RXD open LIN = 4 V to 58 V

V

–0.3

75

Limiting current (ISO/DIS 17987 Param

57)

TXD = 0 V, V_LIN= 48 V, R_MEAS= 440 Ω,

V_SUP= 48 V, V_BUSdom< 4.518 V

120

300

mA

µA

mA

Receiver leakage current, dominant

(ISO/DIS 17987 Param 58)

LIN = 0 V, V_SUP= 24 V Driver off/

recessive; See Figure 8-6

–2

Receiver leakage current, recessive

(ISO/DIS 17987 Param 59)

LIN > V_SUP, 8 V ≤V_SUP≤48 V Driver

off; See Figure 8-7

20

5

Receiver leakage current, recessive

(ISO/DIS 17987 Param 59)

LIN = V_SUP, Driver off; See Figure 8-7

–5

–2

Leakage current, loss of ground

(ISO/DIS 17987 Param 60)

GND = V_SUP, 0 V ≤V_LIN= 36 V, V_SUP

24 V; See Figure 8-8

=

2

V_SUP= 8 V, GND = open, V_SUP= 18 V,

GND = open

R_Commander= 1 kΩ, C_L= 1 nF

R_Responder= 20 kΩ, C_L= 1 nF

LIN = dominant

I_{leak gnd(dom)}

Leakage current, loss of ground ⁽⁵⁾

-1

1

mA

V_SUP= 8 V, GND = open, V_SUP= 18 V,

GND = open

R_Commander= 1 kΩ, C_L= 1 nF

R_Responder= 20 kΩ, C_L= 1 nF

LIN = recessive

I_{leak gnd(rec)}

-100

100

5

µA

Leakage current, loss of supply

(ISO/DIS 17987 Param 61)

0 V ≤V_LIN≤48 V, V_SUP= GND; See

Figure 8-9

I_{BUS_NO_BAT}

LIN dominant (including LIN dominant

for wake up); See Figure 8-3 and Figure

8-4

Low-level input voltage (ISO/DIS 17987

Param , 62)

V_BUSdom

0.4 V_SUP

High-level input voltage (ISO/DIS 17987 LIN recessive; See Figure 8-3 and

V_BUSrec

V_IH

0.6

0.47

0.4

V_SUP

0.6 V_SUP

Param , 63)

Figure 8-4

LIN recessive high-level input voltage ⁽¹⁾

7 V ≤V_SUP≤18 V

(2)

LIN dominant low-level input voltage ⁽¹⁾

V_IL

0.53 V_SUP

0.525 V_SUP

0.175 V_SUP

7 V ≤V_SUP≤18 V

(2)

Receiver center threshold (ISO/DIS

17987 Param , 64)

V_{BUS_CNT}= ( V_BUSdom+ V_BUSrec)/2; See

Figure 8-3 and Figure 8-4

V_{BUS_CNT}

V_HYS

0.475

0.5

Hysteresis voltage (ISO/DIS 17987

Param , 65)

V_HYS= (V_BUSrec- V_BUSdom); See Figure

8-3 and Figure 8-4

V_HYS= V_IH- V_IL; See Figure 8-3 and

Figure 8-4

V_HYS

Hysteresis voltage (SAE J2602)

0.07

0.4

Serial diode LIN termination pullup path

(ISO/DIS 17987 Param , 66)

V_{SERIAL_DIODE}

0.7

45

1

V

I_{SERIAL_DIODE}= 10 μA

Pull-up resistor to V_SUP(ISO/DIS 17987

Param , 71)

R_PU

Normal and Standby modes

20

60

kΩ

I_RSLEEP

Pull-up current source to V_SUP

Sleep mode, V_SUP= 27 V, LIN = GND

µA

–20

–2

8

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7.6 Electrical Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

25 pF

C_LINPIN

Capacitance of the LIN pin

V_SUP= 14 V

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩand 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ωand 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C_LINBUS, R_LINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.

(4) RXD uses open drain output structure therefore V_OLlevel is based upon microcontroller supply voltage V_CC

(5) I_{leak gnd}= (V_BAT- V_LIN)/R_Load

.

7.7 Duty Cycle Characteristics

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TH_REC(MAX)= 0.744 x V_SUPTH_DOM(MAX)

= 0.581 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 50 µs (20 kbps), D1 = t_{BUS_rec(min)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11 )

Duty Cycle 1 (ISO/DIS 17987 Param

27) ⁽³⁾

D1_12V

0.396

TH_REC(MAX)= 0.625 x V_SUP, TH_DOM(MAX)

Duty Cycle 1 (ISO/DIS 17987 Param

27) ^{(3) (4)}

= 0.581 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

50 µs (20 kbps), D1 = t_{BUS_rec(min)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11 )

=

D1_12V

0.396

TH_REC(MAX)= 0.744 x V_SUP

TH_DOM(MAX)= 0.581 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 52 μs

,

D1

Duty cycle 1 ^{(1) (2) (4)}

D1 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11 )

TH_REC(MIN)= 0.422 x V_SUP, TH_DOM(MIN)

= 0.284 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 50 µs (20 kbps), D2 = t_{BUS_rec(MAX)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11 )

Duty Cycle 2 (ISO/DIS 17987 Param

28)⁽³⁾

D2_12V

0.581

TH_REC(MIN)= 0.546 x V_SUP, TH_DOM(MIN)

= 0.4 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

=

D2_12V

Duty Cycle 2 ^{(3) (4)}

50 µs (20 kbps), D2 = t_{BUS_rec(MAX)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11 )

TH_REC(MIN)= 0.422 x V_SUP

,

TH_DOM(MIN)= 0.284 x V_SUP

,

D2

Duty Cycle 2 ^{(1) (2) (4)}

0.581

V_SUP= 7 V to 18 V, t_BIT= 52 μs

D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11 )

TH_REC(MAX)= 0.778 x V_SUP, TH_DOM(MAX)

= 0.616 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 96 µs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11 )

Duty Cycle 3 (ISO/DIS 17987 Param

29)⁽³⁾

D3_12V

0.417

TH_REC(MAX)= 0.645 x V_SUP, TH_DOM(MAX)

= 0.616 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

=

D3_12V

Duty Cycle 3^{(3) (4)}

96 µs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11 )

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 μs

D3 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11 )

D3

Duty Cycle 3 ^{(1) (2) (4)}

0.417

TH_REC(MIN)= 0.389 x V_SUP, TH_DOM(MIN)

= 0.251 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 96 µs (10.4 kbps), D4 =

t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11 )

Duty Cycle 4 (ISO/DIS 17987 Param

30)⁽³⁾

D4_12V

0.59

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7.7 Duty Cycle Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TH_REC(MIN)= 0.422 x V_SUP, TH_DOM(MIN)

= 0.284 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

96 µs (10.4 kbps), D4 = t_{BUS_rec(MAX)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11 )

=

D4_12V

Duty Cycle 4^{(3) (4)}

0.59

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 μs

D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11 )

D4

Duty Cycle 4 ^{(1) (2) (4)}

0.59

TH_REC(MAX)= 0.710 x V_SUP, TH_DOM(MAX)

= 0.544 x V_SUP, V_SUP= 15 V to 36 V,

t_BIT= 50 µs (20 kbps), D1 =

t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11 )

Duty Cycle 1 (ISO/DIS 17987 Param

27)⁽¹⁾

D1_24V

0.33

TH_REC(MIN)= 0.446 x V_SUP, TH_DOM(MIN)

= 0.302 x V_SUP, V_SUP= 15.6 V to 36 V,

t_BIT= 50 µs (20 kbps), D2 =

t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11 )

Duty Cycle 2 (ISO/DIS 17987 Param

28)

D2_24V

D3_24V

D4_24V

0.642

TH_REC(MAX)= 0.744 x V_SUP, TH_DOM(MAX)

= 0.581 x V_SUP, V_SUP= 7 V to 36 V, t_BIT

= 96 µs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11 )

Duty Cycle 3 (ISO/DIS 17987 Param

29)

0.386

TH_REC(MIN)= 0.422 x V_SUP, TH_DOM(MIN)

= 0.284 x V_SUP, V_SUP= 7.6 V to 36 V,

t_BIT= 96 µs (10.4 kbps), D4 =

t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11 )

Duty Cycle 4 (ISO/DIS 17987 Param

30) ⁽⁴⁾

0.591

TH_REC(MAX)= 0.665 x V_SUP

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 5.5 V to 7 V, t_BIT= 52 μs

,

D1_LB

D2_LB

D3_LB

D4_LB

Duty cycle 1 at low battery ^{(1) (2) (4)}

Duty cycle 2 at low battery ^{(1) (2) (4)}

Duty cycle 3 at low battery ^{(1) (2) (4)}

Duty cycle 4 at low battery ^{(1) (2) (4)}

0.396

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

V_SUP= 6.1 V to 7 V, t_BIT= 52 μs

0.581

TH_REC(MAX)= 0.665 x V_SUP

,

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 5.5 V to 7 V, t_BIT= 96 μs

,

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

V_SUP= 6.1 V to 7 V, t_BIT= 96 μs

TH_REC(MAX)= 0.744 x V_SUP

,

Transmitter propagation delay timings

for

TH_DOM(MAX)= 0.581 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 52 μs

t_{REC(MAX)_D1}- t_{DOM(MIN)_D1}

Tr-d max

Td-r max

Tr-d max

Td-r max

10.8

8.4

µs

the duty cycle^{(1) (2) (4)}

Recessive to dominant

TH_REC(MAX)= 0.422 x V_SUP

,

Transmitter propagation delay timings

for

TH_DOM(MAX)= 0.284 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 52 μs

t_{DOM(MAX)_D2}- t_{REC(MIN)_D2}

the duty cycle^{(1) (2) (4)}

Dominant to recessive

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 96 μs

t_{REC(MAX)_D3}- t_{DOM(MIN)_D3}

Transmitter propagation delay timings

for

15.9

17.28

the duty cycle^{(1) (2) (4)}

Recessive to dominant

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 96 μs

t_{DOM(MAX)_D4}- t_{REC(MIN)_D4}

Transmitter propagation delay timings

for

the duty cycle^{(1) (2) (4)}

Dominant to recessive

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7.7 Duty Cycle Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TH_REC(MAX)= 0.665 x V_SUP

,

Low battery transmitter propagation

delay

TH_DOM(MAX)= 0.499 x V_SUP

5.5 V ≤V_SUP≤7 V, t_BIT= 52 μs

t_{REC(MAX)_low}- t_{DOM(MIN)_low}

Tr-d max_low

Td-r max_low

10.8

8.4

µs

timings for the duty cycle^{(1) (2) (4)}

Recessive to dominant

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

6.1 V ≤V_SUP≤7 V, t_BIT= 52 μs

t_{DOM(MAX)_low}- t_{REC(MIN)_low}

Low battery transmitter propagation

delay

timings for the duty cycle^{(1) (2) (4)}

Dominant to recessive

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩand 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ωand 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C_LINBUS, R_LINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.

(4) Specified by design

7.8 Switching Characteristics

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

SYMBOL

DESCRIPTION

TEST CONDITIONS

MIN

NOM

MAX UNIT

Receiver rising propagation delay time

(ISO/DIS 17987 Param 31)

t_{rx_pdr}

6

µs

R_RXD= 2.4 kΩ, C_RXD= 20 pF (See

Figure 8-12 and Figure 8-13 )

Receiver falling propagation delay time

(ISO/DIS 17987 Param 31)

t_{rx_pdf}

Rising edge with respect to falling edge,

Symmetry of receiver propagation delay (trx_sym = trx_pdf –trx_pdr), R_RXD

time

=

2.4 kΩ_,C_RXD= 20 pF (See Figure 8-12

and Figure 8-13 )

t_{rs_sym}

2

µs

–2

LIN wakeup time (Minimum dominant

time on LIN bus for wakeup)

See Figure 8-16, Figure 9-2 and Figure

9-3

t_LINBUS

25

100

150

Time to clear false wakeup prevention

logic if LIN bus had a bus stuck

dominant fault (recessive time on LIN

bus to clear bus stuck dominant fault)

t_CLEAR

See Figure 9-3

8

20

2

17

34

50

80

15

µs

ms

µs

t_DST

Dominant state time out

Time to change from standby mode to

normal mode or normal mode to sleep

mode through EN pin; See Figure 8-14

and Figure 9-4

t_{MODE_CHANGE}Mode change delay time

Time for normal mode to initialize and

data on RXD pin to be valid; See Figure

8-14

t_NOMINT

Normal mode initialization time

Power up time

35

µs

Upon power up time it takes for valid

data on RXD

t_PWR

1.5

ms

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7.9 Typical Characteristics

图7-1. V_OHvs V_SUPand Temperature

图7-2. V_OLvs V_SUPand Temperature

Normal Mode (Dominant)

Normal Mode (Recessive)

图7-3. Supply Current vs Voltage Supply Across Temperature

图7-4. Supply Current vs Voltage Supply Across Temperature

Standby Mode (Dominant)

Standby Mode (Recessive)

图7-5. Supply Current vs Voltage Supply and Temperature

图7-6. Supply Current vs Voltage Supply and Temperature

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7.9 Typical Characteristics (continued)

Sleep Mode

图7-7. Supply Current vs Voltage Supply and Temperature

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8 Parameter Measurement Information

1, 4

NC 11, 12, 14

10

RXD1/2

Power Supply

Resolution: 10mV/ 1mA

Accuracy: 0.2%

5 V

2, 5

V_SUP

V_PS

EN1/2

NC

6

9, 13

LIN1/2

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

TXD1/2

3, 7

8

GND

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10

Delta t = + 5 µs

(t_BIT= 50 µs)

Trigger Point

RX

2 x t_BIT= 100 µs (20 kBaud)

图8-2. RX Response: Operating Voltage Range

Period T = 1/f

Amplitude

(signal range)

LIN Bus Input

Frequency: f = 20 Hz

Symmetry: 50%

图8-3. LIN Bus Input Signal

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1, 4

NC

RXD1/2

11, 12, 14

10

Power Supply

Resolution: 10 mV / 1 mA

Accuracy: 0.2%

5 V

2, 5

6

V_SUP

V_PS

EN1/2

NC

9, 13

8

LIN1/2

GND

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40 ns

Frequency: 20 ppm

3, 7 TXD1/2

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-4. LIN Receiver Test with RX access Parameters 17, 18, 19, 20

Power Supply 1

Resolution: 10 mV / 1mA

Accuracy: 0.2%

NC

RXD1/2

11, 12, 14

10

1, 4

2, 5

5 V

V_PS1

V_SUP

EN1/2

NC

D

6

Power Supply 2

Resolution: 10 mV / 1mA

Accuracy: 0.2%

9, 13

LIN1/2

GND

3, 7

TXD1/2

8

V_PS2

R_BUS

Measurement Tools

O-scope:

DMM

图8-5. V_{SUP_NON_OP}Parameters 11

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11, 12, 14

10

NC

Power Supply

Resolution: 10mV/ 1mA

Accuracy: 0.2%

1, 4 RXD1/2

V_PS

V_SUP

2, 5

6

EN1/2

NC

R_MEAS= 499 Ω

9, 13

8

LIN1/2

GND

TXD1/2

3, 7

Measurement Tools

O-scope:

DMM

图8-6. Test Circuit for I_{BUS_PAS_dom}; TXD = Recessive State V_BUS= 0 V, Parameters 13

Power Supply 1

Resolution: 10mV/ 1mA

Accuracy: 0.2%

1, 4

RXD1/2

NC 11, 12, 14

V_PS1

10

2, 5 EN1/2

V_SUP

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

TLINx022

1 kΩ

6

NC

9, 13

V_PS2

LIN1/2

GND

V_PS22 V/s ramp

[8 V à 27 V]

3, 7

TXD1/2

8

V Drop across resistor

< 20 mV

Measurement Tools

O-scope:

DMM

图8-7. Test Circuit for I_{BUS_PAS_rec}Param 14

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Power Supply 1

Resolution: 10mV/ 1mA

Accuracy: 0.2%

11, 12, 14

10

NC

RXD1/2

1, 4

2, 5

5 V

V_PS1

V_SUP

EN1/2

NC

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

1 kΩ

6

9, 13

8

LIN1/2

GND

V_PS2

V_PS22 V/s ramp

[0 V à 27 V]

3, 7 TXD1/2

V Drop across resistor

< 1V

Measurement Tools

O-scope:

DMM

图8-8. Test Circuit for I_{BUS_NO_GND}Loss of GND

11, 12, 14

NC

RXD1/2

1, 4

5 V

2, 5

10

V_SUP

EN1/2

NC

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

10 kΩ

6

9, 13

V_PS

LIN1/2

V_PS2 V/s ramp

[0 V à 27 V]

3, 7

TXD1/2

8

GND

V Drop across resistor

< 1V

Measurement Tools

O-scope:

DMM

图8-9. Test Circuit for I_{BUS_NO_BAT}Loss of Battery

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NC 11, 12, 14

10

RXD1/2

1, 4

2, 5

5 V

Power Supply 1

Resolution: 10 mV / 1mA

Accuracy: 0.2%

V_SUP

EN1/2

NC

V_PS1

R_MEAS

6

9, 13

8

LIN1/2

GND

Power Supply 2

Resolution: 10 mV / 1mA

Accuracy: 0.2%

Pulse Generator

V_PS2

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40 ns

Frequency: 20 ppm

3, 7

TXD1/2

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-10. Test Circuit Slope Control and Duty Cycle Parameters 27, 28, 29, 30

T_BIT

D = 50%

TXD (Input)

D1₁₂: 0.744 * V_SUP

D3₁₂: 0.778 * V_SUP

TH_REC(MAX)

TH_DOM(MAX)

TH_REC(MIN)

TH_DOM(MIN)

Thresholds

RX Node 1

D1₁₂: 0.581 * V_SUP

D3₁₂: 0.616 * V_SUP

LIN Bus

Signal

D2₁₂: 0.422 * V_SUP

D4₁₂: 0.389 * V_SUP

V_SUP

Thresholds

RX Node 2

D2₁₂: 0.284 * V_SUP

D4₁₂: 0.251 * V_SUP

t_{BUS_REC(MIN)}

t_{BUS_DOM(MAX)}

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

t_{BUS_DOM(MIN)}

t_{BUS_REC(MAX)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

图8-11. Definition of Bus Timing Parameters

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V_CC

2.4 kΩ

1, 4

2, 5

NC 11, 12, 14

RXD1/2

Power Supply

Resolution: 10 mV / 1mA

Accuracy: 0.2%

5 V

20 pF

10

V_SUP

EN1/2

NC

V_PS

6

9, 13

8

LIN1/2

GND

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40 ns

Frequency: 20 ppm

3, 7

TXD1/2

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-12. Propagation Delay Test Circuit; Parameters 31, 32

D1: 0.744 * V_SUP

D3: 0.778 * V_SUP

TH_REC(MAX)

Thresholds

RX Node 1

D1: 0.581 * V_SUP

D3: 0.616 * V_SUP

TH_DOM(MAX)

TH_REC(MIN)

TH_DOM(MIN)

LIN Bus

Signal

D2: 0.422 * V_SUP

D4: 0.389 * V_SUP

V_SUP

Thresholds

RX Node 2

D2: 0.284 * V_SUP

D4: 0.251 * V_SUP

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

t_{rx_pdr(1)}

t_{rx_pdf(1)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

t_{rx_pdr(2)}

t_{rx_pdf(2)}

图8-13. Propagation Delay

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Wake Event

t_{MODE_CHANGE}

EN

t_{MODE_CHANGE}

t_NOMINT

Transition

Sleep

Standby

Transition

Normal

MODE

Indetermin

ate Ignore

Mirrors

Bus

Wake Request

RXD = Low

RXD

Floating

Indeterminate Ignore

Mirrors Bus

图8-14. Mode Transitions

EN1/2

Weak Internal Pulldown

TXD1/2

Weak Internal Pulldown

V_SUP

LIN1/2

RXD1/2

MODE

Floating

Sleep

Normal

图8-15. Wakeup Through EN

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0.6 x

V_SUP

0.6 x

V_SUP

LIN1/2

0.4 x V_SUP

V_SUP

0.4 x

V_SUP

t < t_LINBUS

t_LINBUS

TXD1/2

Weak Internal Pulldown

EN1/2

Floating

Sleep

RXD1/2

MODE

Standby

Normal

图8-16. Wakeup through LIN

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9 Detailed Description

9.1 Overview

The TLIN2022A-Q1 device is a Dual Local Interconnect Network (LIN) physical layer transceiver, compliant to

LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 standards, with integrated wake-up and protection

features. The LIN bus is a single wire bidirectional bus typically used for low speed in-vehicle networks. The

device transmitter supports data rates from 2.4 kbps to 20 kbps. The device receiver works up to 100 kbps

supporting in-line programming. The LIN protocol data stream on the TXD input is converted by the TLIN2022A-

Q1 into a LIN bus signal using a current-limited wave-shaping driver as outlined by the LIN physical layer

specification. The receiver converts the data stream to logic-level signals that are sent to the microprocessor

through the open-drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and

recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up

resistor (45 kΩ) and a series diode. No external pull-up components are required for responder node

applications. Commander node applications require an external pull-up resistor (1 kΩ) plus a series diode per

the LIN specification.

The device is designed to support 12-V and 24-V applications with a wide input voltage operating range and also

supports low-power sleep mode. The device also provides two methods to wake up: EN pin and from the LIN

bus.

The TLIN2022A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required

external components in end applications. In the event of a ground shift or supply voltage disconnection, the

device prevents back-feed current through LIN to the supply input. The device also includes undervoltage

detection, temperature shutdown protection, and loss-of-ground protection.

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9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 LIN (Local Interconnect Network) Bus

This high voltage input/output pin is a single wire LIN bus transmitter and receiver. The LIN pin can survive

transient voltages up to 45 V. Reverse currents from the LIN to supply (V_SUP) are minimized with blocking

diodes, even in the event of a ground shift or loss of supply (V_SUP).

9.3.1.1 LIN Transmitter Characteristics

The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low-

side transistor with internal current limitation and thermal shutdown. During a thermal shut-down condition, the

transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to

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V_SUP, so no external pull-up components are required for the LIN responder node applications. An external pull-

up resistor and series diode to V_SUPmust be added when the device is used for a commander node application.

9.3.1.2 LIN Receiver Characteristics

The receiver characteristic thresholds are proportional to the device supply pin according to the LIN

specification.

The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602

specifications. This allows the TLIN2022A-Q1 to be used for high speed downloads at the end-of-line production

or other applications. The actual data rate achievable depends on system time constants (bus capacitance and

pull-up resistance) and driver characteristics used in the system.

9.3.1.2.1 Termination

There is an internal pull-up resistor with a serial diode structure to V_SUP, so no external pull-up components are

required for the LIN responder node applications. An external pull-up resistor (1 kΩ) and a series diode to V_SUP

must be added when the device is used for commander node applications as per the LIN specification.

图9-1 shows a commander node configuration and how the voltage levels are defined

Voltage drop across the

Simplified Transceiver

V_{LIN_Bus}

diodes in the pullup path

RXD

V_SUP

V_SUP/2

V_Battery

V_SUP

V_{LIN_Recessive}

Receiver

Filter

1 kΩ

45 kΩ

LIN

Bus

TXD

350 kΩ

GND

Transmitter

with slope control

V_{LIN_Dominant}

t

图9-1. Commander Node Configuration with Voltage Levels

9.3.2 TXD

TXD is the interface to the MCUs LIN protocol controller or SCI / UART that is used to control the state of the LIN

output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is

recessive (near V_Battery). See 图 9-1. The TXD input structure is compatible with processors using 3.3 V and 5 V

I/O. TXD has an internal pull-down resistor. The LIN bus is protected from being stuck dominant through a

system failure driving TXD low through the dominant state timeout timer.

9.3.3 RXD (Receive Output)

RXD is the interface to the MCU's LIN protocol controller or SCI / UART, which reports the state of the LIN bus

voltage. LIN recessive (near V_Battery) is represented by a high level on the RXD and LIN dominant (near ground)

is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This

allows the device to be used with 3.3 V and 5 V I/O processors. If the microcontroller’s RXD pin does not have

an integrated pull-up, an external pull-up resistor to the processors I/O supply voltage is required. In standby

mode the RXD pin is driven low to indicate a wake up request from the LIN bus.

9.3.4 V_SUP(Supply Voltage)

V_SUPis the power supply pin. V_SUPis connected to the battery through an external reverse battery blocking

diode (see 图 9-1). If there is a loss of power at the ECU level, the device has low leakage from the LIN pin,

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which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered

(ignition supplied) while the rest of the network remains powered (battery supplied).

9.3.5 GND (Ground)

GND is the device ground connection. The device can operate with a ground shift as long as the ground shift

does not reduce the V_SUPbelow the minimum operating voltage, as well as ensuring the input and output

voltages are within their appropriate thresholds. If there is a loss of ground at the ECU level, the device has

extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in

which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered

(battery supplied).

9.3.6 EN (Enable Input)

EN1 and EN2 control the operational modes of the respective LIN channel . When EN1/EN2 is high the LIN1/

LIN2 channel is in normal operating mode allowing a transmission path from TXD to respective LIN bus and from

LIN to RXD. When EN1/EN2 is low the LIN1/LIN2 channel is put into sleep mode and there is no transmission

path available. The channel can enter normal mode only after wake up. EN has an internal pull-down resistor to

ensure the channel remains in low power mode even if EN floats.

9.3.7 Protection Features

The TLIN2022A-Q1 has several protection features.

9.3.8 TXD Dominant Time Out (DTO)

During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application

failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on

the TXD pin. If the low signal remains on TXD for longer than t_DST, the transmitter is disabled, thus allowing the

LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the

t_DSTtimer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the LIN channel

fails to a known state if TXD is disconnected. During this fault, the LIN channel remains in normal mode

(assuming no change of state request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and

the LIN bus pull-up termination remains on.

9.3.9 Bus Stuck Dominant System Fault: False Wake-Up Lockout

The TLIN2022A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from

waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.

If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears”the bus stuck

dominant, preventing excessive current use. 图9-2 and 图9-3 show the behavior of this protection.

RXD

EN

LIN Bus

t_LINBUS

< t_LINBUS

图9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wake-up

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RXD

EN

t_LINBUS

LIN Bus

t_CLEAR

< t_CLEAR

图9-3. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wake-up

9.3.10 Thermal Shutdown

The LIN transmitter is protected by limiting the current; however if the junction temperature of the device

exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the

over-temperature fault condition has been removed and the junction temperature has cooled beyond the

hysteresis temperature, the transmitter is re-enabled, assuming the device remained in the normal operation

mode. During this fault, the transceiver remains in normal mode (assuming no change of state request on EN),

the transmitter is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains

on.

9.3.11 Undervoltage on V_SUP

The TLIN2022A-Q1 contains a power on reset circuit to avoid false bus messages during undervoltage

conditions when V_SUPis less than UV_SUP

.

9.3.12 Unpowered Device and LIN Bus

In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the

network remains powered by the battery. The TLIN2022A-Q1 has a low unpowered leakage current from the bus

so an unpowered node does not affect the network or load it down.

9.4 Device Functional Modes

The TLIN2022A-Q1 has three functional modes of operation; normal, sleep, and standby. The next sections

describe these modes as well as how the device moves between the different modes. 图 9-4 graphically shows

the relationship while 表9-1 shows the state of pins.

表9-1. Operating Modes

LIN BUS

TERMINATION

MODE

Sleep

EN

Low

RXD

Floating

Low

TRANSMITTER

COMMENT

Weak Current Pullup

Off

Wake up event detected,

waiting on MCU to set EN

Standby

45 kΩ (typical)

LIN Bus

Data

Normal

High

Off

LIN transmission up to 20 kbps

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Unpowered System

V_SUP< V_{SUP_UNDER}

V_SUP> V_{SUP_UNDER}

EN = Low

V_SUP< V_{SUP_UNDER}

V_SUP> V_{SUP_UNDER}

EN = High

V_SUP< V_{SUP_UNDER}

Standby Mode

Driver: Off

RXD: Low

Termination: 45 kΩ

EN = High

LIN Bus Wake up

Normal Mode

Driver: On

RXD: LIN Bus Data

Sleep Mode

Driver: Off

RXD: Floating

Termination: Weak pullup

EN = Low

EN = High

Termination: 45 kΩ

图9-4. Operating State Diagram

9.4.1 Normal Mode

If the EN1 or EN2 pin is high at power up, the channel powers up in normal mode. If EN1 or EN2 is low, the

channel powers up in standby mode. The EN pin controls the mode of the channel. In normal operational mode,

the receiver and transmitter are active and the LIN transmission up to the LIN specified maximum of 20 kbps is

supported. The receiver detects the data stream on the LIN bus and outputs it on RXD for the LIN controller. A

recessive signal on the LIN bus is a logic high and a dominant signal on the LIN bus is a logic low. The driver

transmits input data from TXD to the LIN bus. Normal mode is entered as EN transitions high while the LIN

channel is in sleep or standby mode for > t_{MODE_CHANGE}plus t_NOMINT

.

9.4.2 Sleep Mode

Sleep Mode is the power saving mode for the TLIN2022A-Q1. Even with extremely low current consumption in

this mode, the LIN channel can still wake-up from LIN bus through a wake-up signal or if EN is set high for

≥t_{MODE_CHANGE}. The LIN bus is filtered to prevent false wake-up events. The wake-up events must be active for

the respective time periods (t_LINBUS).

Sleep mode is entered by setting EN low for longer than t_{MODE_CHANGE}

While the channel is in sleep mode, the following conditions exist.

.

• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if

LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake-up events

in case an external connection to the LIN bus is lost.

• The normal receiver is disabled.

• EN input and LIN wake-up receiver are active.

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9.4.3 Standby Mode

This mode is entered whenever a wake-up event occurs through the LIN bus while the channel is in sleep mode.

The LIN bus responder termination circuit is turned on when standby mode is entered. Standby mode is signaled

through a low level on RXD. See Standby Mode Application Note for more application information.

When EN is set high for longer than t_{MODE_CHANGE}while the channel is in standby mode, the device returns to

normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.

9.4.4 Wake-Up Events

There are two ways to wake-up from sleep mode:

• Remote wake-up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN

bus where the dominant state is held for t_LINBUSfilter time. After this t_LINBUSfilter time has been met and a

rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake-up event,

eliminating false wake-ups from disturbances on the LIN bus or if the bus is shorted to ground.

• Local wake-up through EN being set high for longer than t_{MODE_CHANGE}

.

9.4.4.1 Wake-Up Request (RXD)

When the TLIN2022A-Q1 encounters a wake-up event from the LIN bus, RXD goes low and the channel

transitions to standby mode until EN is reasserted high and the channel enters normal mode. Once the LIN

channel enters normal mode, the RXD pin releases the wake-up request signal and the RXD pin then reflects

the receiver output from the correponding LIN bus.

9.4.4.2 Mode Transitions

When any of the LIN channel of TLIN2022A-Q1 is transitioning between modes, the device needs the time,

t_{MODE_CHANGE}, to allow the change to fully propagate from the EN pin through the channel into the new state.

When transitioning from sleep or standby mode to normal mode, the transition time is the sum of t_{MODE_CHANGE}

and t_NOMINT

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10 Application Information Disclaimer

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The TLIN2022A-Q1 can be used as both a responder node device and a commander node device in a LIN

network. The device comes with the ability to support both remote wake-up request and local wake-up request.

10.2 Typical Application

The device comes with an integrated 45 kΩ pull-up resistor and series diode for responder node applications.

For commander node applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. 图

10-1 shows the device being used in both commander mode and responder mode applications.

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COMMANDER NODE

V_BAT

V_SUP

VREG

V_SUP

V_DD

V_SUP

V_DD

NC NC NC

11 12 14

(4)

Commander

Node

Pullup⁽³⁾

1 kΩ

EN1

10

V_DD

I/O

2

V_DDI/O

MCU w/o

pullup⁽²⁾

LIN1

MCU

13

1

3

220 pF

RXD1

TXD1

TLIN2022A

LIN Controller

Or

SCI/UART⁽¹⁾

V_DDI/O

LIN2

MCU w/o

pullup⁽²⁾

9

220 pF

4

7

RXD2

TXD2

EN2

5

I/O

GND

6

8

NC

RESPONDER NODE

V_BAT

V_SUP

VREG

V_SUP

V_DD

V_SUP

V_DD

NC NC NC

11 12 14

(4)

EN1

10

V_DD

I/O

2

V_DDI/O

MCU w/o

pullup⁽²⁾

LIN1

MCU

13

220 pF

1

3

RXD1

TXD1

TLIN2022A

LIN Controller

Or

SCI/UART⁽¹⁾

V_DDI/O

LIN2

MCU w/o

pullup⁽²⁾

9

220 pF

4

7

RXD2

TXD2

EN2

5

I/O

GND

6

8

NC

A. If RXD on MCU or LIN responder has internal pullup; no external pullup resistor is needed.

B. If RXD on MCU or LIN responder does not have an internal pullup requires external pullup resistor

C. Commander node applications require and external 1 kΩ pullup resistor and serial diode.

D. Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥10 µF

图10-1. Typical LIN Bus

10.2.1 Design Requirements

The RXD output structure is an open-drain output stage. This allows the TLIN2022A-Q1 to be used with 3.3-V

and 5-V I/O processor. If the RXD pin of the processor does not have an integrated pull-up, an external pull-up

resistor to the processor I/O supply voltage is required. The select external pull-up resistor value should be

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between 1 kΩ to 10 kΩ, depending on supply used (See I_OLin electrical characteristics). The V_SUPpin of the

device should be decoupled with a 100 nF capacitor by placing it close to the V_SUPsupply pin. The system

should include additional decoupling on the V_SUPline as needed per the application requirements.

10.2.2 Detailed Design Procedures

10.2.2.1 Normal Mode Application Note

When using the TLIN2022A-Q1 in systems which are monitoring the RXD pin for a wake up request, special

care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition

period between states as the receivers are switched. The application software should not look for an edge on the

RXD pin indicating a wake up request until t when going from normal to sleep mode or t_{MODE_CHANGE}plus

t_NOMINTwhen going from sleep or standby to normal mode. This is shown in 图8-14.

10.2.2.2 Standby Mode Application Note

If the TLIN2022A-Q1 detects an undervoltage on V_SUPthe RXD pin transitions low, and signals to the software

that the TLIN2022A-Q1 is in standby mode and should be returned to sleep mode for the lowest power state.

10.2.2.3 TXD Dominant State Timeout Application Note

The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data

rate of the device. The LIN protocol has different constraints for commander and responder applications thus

there are different maximum consecutive dominant bits for each application case and thus different minimum

data rates.

10.2.3 Application Curves

图 10-2 and 图 10-3 show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive

and recessive to dominant edges.

图10-2. Dominant to Recessive Propagation

图10-3. Recessive to Dominant Propagation

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Power Supply Recommendations

The TLIN2022A-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V

to 48 V. A 100 nF decoupling capacitor should be placed as close to the V_SUPpin of the device as possible. It is

good practice for some applications with noisier supplies to include 1 μF and 10 μF decoupling capacitor.

11 Layout

In order for the PCB design to be successful, start with the design of the protection and filtering circuitry.

Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high

frequency layout techniques must be applied during PCB design. Placement at the connector also prevents

these noisy events from propagating further into the PCB and system.

11.1 Layout Guidelines

• Pin 1, 4 (RXD1/2): The pin is an open-drain outputs and require an external pull-up resistor in the range of 1

kΩ and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an

integrated pull-up, an external resistor should be placed between RXD and the regulated voltage supply for

the microprocessor.

• Pin 2, 5 (EN1/2): EN is an input pin that is used to place the device in a low power sleep mode. If this feature

is not used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a

series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to

limit current on the digital lines in the event of an over voltage fault.

• Pin 6 (NC): Not Connected.

• Pin 3, 7 (TXD1/2): The TXD pins are the transmitter input signals to the device from the processor. A series

resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A

capacitor to ground can be placed close to the input pin of the device to filter noise.

• Pin 8 (GND): This is the ground connection for the device. This pin should be tied to the ground plane

through a short trace with the use of two vias to limit total return inductance.

• Pin 9, 13 (LIN1/2): This pin connects to the LIN bus. For responder node applications, a 220 pF capacitor to

ground is implemented. For commander node applications and additional series resistor, a blocking diode

should be placed between the LIN pin and the V_SUPpin. See 图10-1.

• Pin 10 (V_SUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close

to the device as possible.

• Pin 11, 12 and 14 (NC): Not Connected.

Note

All ground and power connections should be made as short as possible and use at least two vias to

minimize the total loop inductance.

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11.2 Layout Example

V_DD

V_SUP

RXD1

NC 14

1

2

3

4

5

6

7

RXD1

Only needed for

the Commander

node

U1

V_DD

LIN1

R2

EN1

LIN1 13

EN1

TXD1

RXD2

EN2

GND

R4

TXD1

RXD2

EN2

NC

12

V_DD

11

NC

V_DD

V_SUP

R6

10

C5

V_SUP

LIN2

GND

Only needed for

the Commander

node

D1

LIN2

NC

9

GND

TXD2

8

TXD2

R8

GND

图11-1. Layout Example

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12 Device and Documentation Support

This device will conform to the following LIN standards. The core of what is needed is covered within this system

spec, however reference should be made to these standards and any discrepancies pointed out and discussed.

This document should provide all the basics of what is needed.

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• LIN Standards:

– ISO/DIS 17987-1: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and

use case definition

– ISO/DIS 17987-4: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer

(EPL) specification 12V/24V

– SAEJ2602-1: LIN Network for Vehicle Applications

– LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification

• EMC requirements:

– SAEJ2962-1

– ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge

– ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband

radiated electromagnetic energy - Part 4: Harness excitation methods

– ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:

Definitions and general considerations

– ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical

transient transmission by capacitive and inductive coupling via lines other than supply lines

– IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz -

Part 4: Direct RF power injection method

– IEC 61000-4-2

– IEC 61967-4

– CISPR25

• Conformance Test requirements:

– ISO/DIS 17987-7: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer

(EPL) conformance test specification

– SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test

•

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

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12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

DMT 14

3 x 4.5, 0.65 mm pitch

VSON - 0.9 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225088/A

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PACKAGE OUTLINE

DMT0014A

VSON - 0.9 mm max height

SCALE 3.200

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

A

B

PIN 1 INDEX AREA

4.6

4.4

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

C

0.9 MAX

SEATING PLANE

0.08 C

0.05

0.00

1.6 0.1

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

7

8

A

2X

3.9

15

SYMM

4.2 0.1

14

1

12X 0.65

0.35

0.25

14X

0.45

0.35

14X

PIN 1 ID

0.1

C A B

C

(OPTIONAL)

0.05

4223033/B 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DMT0014A

VSON - 0.9 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.6)

14X (0.6)

14X (0.3)

SYMM

1

14

2X

(1.85)

12X (0.65)

SYMM

15

(4.2)

(0.69)

TYP

(

0.2) VIA

TYP

8

7

(R0.05) TYP

(0.55) TYP

(2.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223033/B 10/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DMT0014A

VSON - 0.9 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.47)

15

14X (0.6)

1

14

14X (0.3)

(1.18)

12X (0.65)

SYMM

(1.38)

(R0.05) TYP

METAL

TYP

8

7

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 15

77.4% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4223033/B 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TLIN2022ADRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有显性状态超时故障保护功能的双路本地互连网络 (LIN) 收发器 \| D \| 14 \| -40 to 125
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