TLV5624IDRG4 [TI]

2.7-V TO 5.5-V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN; ？ 2.7 V至5.5 V低功耗的8位数字 - 模拟转换器，具有内部基准和掉电


型号：	TLV5624IDRG4
厂家：	TEXAS INSTRUMENTS
描述：	2.7-V TO 5.5-V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN ？ 2.7 V至5.5 V低功耗的8位数字 - 模拟转换器，具有内部基准和掉电转换器数模转换器光电二极管
文件：	总22页 (文件大小：941K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLAS235B − JULY 1999 − REVISED APRIL 2004

D OR DGK PACKAGE

(TOP VIEW)

features

8-Bit Voltage Output DAC

DIN

OUT

Programmable Internal Reference

SCLK

Programmable Settling Time:

1 µs in Fast Mode,

REF

AGND

3.5 µs in Slow Mode

Compatible With TMS320 and SPI Serial

Ports

Differential Nonlinearity . . . <0.2 LSB

Monotonic Over Temperature

applications

Digital Servo Control Loops

Digital Offset and Gain Adjustment

Industrial Process Control

Machine and Motion Control Devices

Mass Storage Devices

description

The TLV5624 is a 8-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows

glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit

serial string containing 4 control and 8 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling

time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable

precision voltage reference, the TLV5624 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented

with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in

an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial

temperature ranges.

AVAILABLE OPTIONS

PACKAGE

SOIC

(D)

MSOP

(DGK)

0°C to 70°C

TLV5624CD

TLV5624ID

TLV5624CDGK

TLV5624IDGK

−40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

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SLAS235B − JULY 1999 − REVISED APRIL 2004

functional block diagram

REF

PGA With

Output Enable

Voltage

Bandgap

Power

and Speed

Control

Power-On

Reset

2-Bit

Control

Latch

DIN

Serial

SCLK

Interface

and

Control

OUT

8-Bit

DAC

Latch

Terminal Functions

TERMINAL

I/O/P

DESCRIPTION

NAME

NO.

AGND

Ground

Chip select. Digital input active low, used to enable/disable inputs

Digital serial data input

DIN

Frame sync input

OUT

REF

SCLK

I/O

DAC A analog voltage output

Analog reference voltage input/output

Digital serial clock input

Positive power supply

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SLAS235B − JULY 1999 − REVISED APRIL 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (V

to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V

+ 0.3 V

Operating free-air temperature range, T : TLV5624C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

TLV5624I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

4.5

2.7

0.55

NOM

MAX

5.5

3.3

UNIT

= 5 V

= 3 V

Supply voltage, V

Power on reset, POR

= 2.7 V

High-level digital input voltage, V

= 5.5 V

= 2.7 V

= 5.5 V

2.4

0.6

Low-level digital input voltage, V

Reference voltage, V to REF terminal

ref

= 5 V (see Note 1)

= 3 V (see Note 1)

AGND

2.048

1.024

−1.5

Reference voltage, V to REF terminal

ref

Load resistance, R

kΩ

Load capacitance, C

100

Clock frequency, f

MHz

CLK

TLV5624C

TLV5624I

Operating free-air temperature, T

°C

−40

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (V −0.4 V)/2 causes clipping of the transfer function. The output buffer of the

internal reference must be disabled, if an external reference is used.

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SLAS235B − JULY 1999 − REVISED APRIL 2004

electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

No load,

Fast

2.3

3.3

All inputs = AGND or V

DAC latch = 0x800

Power supply current

Slow

1.5

1.9

Power down supply current

Power supply rejection ratio

See Figure 8

0.01

−65

µA

Zero scale, See Note 2

Full scale, See Note 3

PSRR

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying V

and is given by:

PSRR = 20 log [(E (V max) − E (V min))/V max]

ZS DD ZS DD DD

3. Power supply rejection ratio at full scale is measured by varying V

and is given by:

PSRR = 20 log [(E (V max) − E (V min))/V max]

DD DD DD

static DAC specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

bits

Resolution

INL

Integral nonlinearity, end point adjusted

Differential nonlinearity

See Note 4

See Note 5

See Note 6

See Note 7

0.3

0.5

0.2

LSB

DNL

0.07

LSB

Zero-scale error (offset error at zero scale)

TC Zero-scale-error temperature coefficient

ppm/°C

% full

scale V

Gain error

See Note 8

0.6

Gain error temperature coefficient

See Note 9

ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 255.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1

LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains

constant) as a change in the digital input code. Tested from code 10 to code 255.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: E

TC = [E

) − E

)]/V × 10 /(T

ref max

− T ).

min

ZS max

ZS min

8. Gain error is the deviation from the ideal output (2V − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

ref

9. Gain temperature coefficient is given by: E TC = [E (T

) − E (T

)]/V × 10 /(T

− T ).

min

max

min

ref

max

output specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

0.10

MAX

UNIT

Output voltage

= 10 kΩ

−0.4

% full

scale V

Output load regulation accuracy

= 4.096 V, 2.048 V

R = 2 kΩ

0.25

reference pin configured as output (REF)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low reference voltage

High reference voltage

Output source current

Output sink current

1.003 1.024 1.045

ref(OUTL)

> 4.75 V

2.027 2.048 2.069

ref(OUTH)

ωF

ref(source)

ref(sink)

−1

Load capacitance

PSRR

Power supply rejection ratio

−65

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SLAS235B − JULY 1999 − REVISED APRIL 2004

electrical characteristics over recommended operating conditions (unless otherwise noted)

(Continued)

reference pin configured as input (REF)

PARAMETER

Input voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DD−1.5

Input resistance

MΩ

Input capacitance

Fast

1.3

MHz

Reference input bandwidth

Reference feedthrough

REF = 0.2 V + 1.024 V dc

Slow

525

−80

kHz

REF = 1 V at 1 kHz + 1.024 V dc (see Note 10)

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER

High-level digital input current

TEST CONDITIONS

V = V

MIN

TYP

MAX

UNIT

µA

Low-level digital input current

Input capacitance

V = 0 V

−1

µA

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast

Slow

Fast

Slow

Fast

Slow

= 10 kΩ,

See Note 11

= 100 pF,

Output settling time, full scale

Output settling time, code to code

Slew rate

µs

s(FS)

3.5

0.5

1.5

= 10 kΩ,

See Note 12

µs

s(CC)

= 10 kΩ,

V/µs

See Note 13

1.5

DIN = 0 to 1,

CS = V

= 100 kHz,

CLK

Glitch energy

nV−S

SNR

Signal-to-noise ratio

S/(N+D) Signal-to-noise + distortion

= 480 kSPS,

= 1 kHz,

= 100 pF

out

= 10 kΩ,

THD

Total harmonic distortion

−50

−48

Spurious free dynamic range

NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change

of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

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SLAS235B − JULY 1999 − REVISED APRIL 2004

digital input timing requirements

MIN NOM

MAX

UNIT

Setup time, CS low before FS falling edge

Setup time, FS low before first negative SCLK edge

su(CS−FS)

su(FS-CK)

Setup time, 16 negative SCLK edge after FS low on which bit D0 is sampled before rising

edge of FS

su(C16-FS)

su(C16-CS)

Setup time, 16 positive SCLK edge (first positive after D0 is sampled) before CS rising

edge. If FS is used instead of 16 positive edge to update DAC, then setup time between

FS rising edge and CS rising edge.

SCLK pulse duration high

SCLK pulse duration low

Setup time, data ready before SCLK falling edge

Hold time, data held valid after SCLK falling edge

FS pulse duration high

su(D)

H(D)

wH(FS)

PARAMETER MEASUREMENT INFORMATION

SCLK

DIN

5 15

su(D) h(D)

D15

D14

D13

D12

su(C16-CS)

su(CS-FS)

wH(FS)

su(FS-CK)

su(C16-FS)

Figure 1. Timing Diagram

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SLAS235B − JULY 1999 − REVISED APRIL 2004

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE

LOAD CURRENT

OUTPUT VOLTAGE

LOAD CURRENT

2.071

2.0705

2.07

4.135

4.134

4.133

4.132

4.131

4.13

= 3 V, REF = Int. 1 V, Input Code = 255

= 5 V, REF = Int. 2 V, Input Code = 255

Fast

2.0695

2.0698

2.0685

2.068

Fast

Slow

2.0675

2.067

2.0665

2.066

4.129

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

Source Current − mA

Figure 2

Figure 3

OUTPUT VOLTAGE

LOAD CURRENT

2.5

= 3 V, REF = Int. 1 V,

Input Code = 0

= 5 V, REF = Int. 2 V,

Input Code = 0

4.5

3.5

Fast

1.5

2.5

1.5

0.5

Slow

3.5

0.5

1.5

2.5

3.5

0.5

1.5

2.5

Sink Current − mA

Figure 4

Figure 5

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SLAS235B − JULY 1999 − REVISED APRIL 2004

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

TEMPERATURE

2.5

= 5 V, REF = 2 V,

= 3 V, REF = 1 V,

Input Code = 255

Fast Mode

Slow Mode

1.5

Slow Mode

0.5

−40−30 −20−10 0 10 20 30 40 50 60 70 80 90

−40−30−20 −10 0 10 20 30 40 50 60 70

t − Temperature − °C

Figure 6

Figure 7

POWER DOWN SUPPLY CURRENT

TOTAL HARMONIC DISTORTION AND NOISE

TIME

FREQUENCY

1.8

1.6

1.4

1.2

−10

−20

−30

−40

−50

−60

−70

−80

= 5 V

ref

= 1 V dc + 1 V p/p Sinewave

Output Full Scale

0.8

0.6

0.4

Slow Mode

Fast Mode

0.2

−90

−100

100

1000

10000

100000

t − Time − µs

f − Frequency − Hz

Figure 8

Figure 9

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ꢊ

ꢕ

ꢂ

ꢍ

ꢎ

ꢀ

ꢑ

ꢀ

ꢑ

ꢕ

ꢍ

ꢎ

ꢍ

ꢎ

ꢒ

ꢊꢋ

ꢕ

SLAS235B − JULY 1999 − REVISED APRIL 2004

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

FREQUENCY

−10

−20

−30

−40

−50

−60

−70

−80

= 5 V

ref

= 1 V dc + 1 V p/p Sinewave

Output Full Scale

Slow Mode

Fast Mode

−90

−100

100

1000

10000

100000

f − Frequency − Hz

Figure 10

DIFFERENTIAL NONLINEARITY

DIGITAL OUTPUT CODE

0.20

0.15

0.10

0.05

−0.00

−0.05

−0.10

−0.15

−0.20

128

160

192

224

256

Digital Output Code

Figure 11

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ꢅꢇ ꢈꢉꢂ ꢀꢊ ꢃ ꢇꢃ ꢉꢂ ꢁ ꢊꢋ ꢌ ꢊꢋ ꢍ ꢎ ꢏ ꢉꢐꢑ ꢀ ꢒꢑ ꢓ ꢑꢀꢔꢁ ꢉꢀꢊ ꢉꢔꢕꢔꢁ ꢊ ꢓ

ꢖ ꢊꢕ ꢂꢍꢎ ꢀ ꢍꢎ ꢋ ꢑ ꢀꢗ ꢑ ꢕꢀ ꢍ ꢎꢕꢔ ꢁ ꢎꢍ ꢘꢍ ꢎꢍ ꢕꢖꢍ ꢔꢕꢒ ꢌꢊ ꢋ ꢍꢎ ꢒꢊ ꢋ ꢕ

SLAS235B − JULY 1999 − REVISED APRIL 2004

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

DIGITAL OUTPUT CODE

0.50

0.25

0.00

−0.25

−0.50

128

160

192

224

256

Digital Output Code

Figure 12

APPLICATION INFORMATION

general function

The TLV5624 is an 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial

interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a

rail-to-rail output buffer.

The output voltage (full scale determined by reference) is given by:

CODE

2 REF

[V]

n−1

where REF is the reference voltage and CODE is the digital input value within the range 0 to 2 , where

n = 8 (bits). The 16-bit word, consisting of control bits and a new DAC value, is illustrated in the data format

section. A power on reset initially resets the internal latches to a defined state (all bits zero).

serial interface

The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting

with the MSB) to the internal register on high-low transitions of SCLK. After 16 bits have been transferred or

FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new

level.

The serial interface of the TLV5624 can be used in two basic modes:

Four wire (with chip select)

Three wire (without chip select)

Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of

the data source (DSP or microcontroller). Figure 13 shows an example with two TLV5624s connected directly

to a TMS320 DSP.

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ꢅ ꢇꢈ ꢉꢂ ꢀ ꢊ ꢃ ꢇꢃ ꢉꢂ ꢁ ꢊꢋ ꢌꢊ ꢋ ꢍꢎ ꢏ ꢉꢐꢑ ꢀ ꢒꢑ ꢓꢑ ꢀꢔꢁ ꢉꢀꢊ ꢉꢔ ꢕ ꢔꢁ ꢊꢓ

ꢖꢊ ꢕꢂ ꢍ ꢎꢀ ꢍꢎ ꢋ ꢑꢀ ꢗ ꢑꢕ ꢀꢍ ꢎꢕꢔꢁ ꢎꢍꢘ ꢍ ꢎꢍꢕꢖꢍ ꢔꢕꢒ ꢌꢊ ꢋꢍ ꢎ ꢒ ꢊꢋ ꢕ

SLAS235B − JULY 1999 − REVISED APRIL 2004

APPLICATION INFORMATION

serial interface (continued)

TLV5624

FS DIN SCLK

CS FS DIN SCLK

TMS320

XF0

DSP

XF1

FSX

CLKX

Figure 13. TMS320 Interface

If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows

an example of how to connect the TLV5624 to TMS320, SPI or Microwire using only three pins.

TMS320

DSP

TLV5624

SPI

TLV5624

Microwire

I/O

TLV5624

FSX

I/O

MOSI

SCK

DIN

CLKX

SCLK

Figure 14. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a

falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write

operations must be performed to program the TLV5624. After the write operation(s), the DAC output is updated

automatically on the next positive clock edge following the 16 falling clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

+ 20 MHz

sclkmax

) t

whmin

wlmin

The maximum update rate is:

+ 1.25 MHz

updatemax

₁₆ǒ_t

wlmin

) t

whmin

Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the

TLV5624 has to be considered, too.

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ꢅꢇ ꢈꢉꢂ ꢀꢊ ꢃ ꢇꢃ ꢉꢂ ꢁ ꢊꢋ ꢌ ꢊꢋ ꢍ ꢎ ꢏ ꢉꢐꢑ ꢀ ꢒꢑ ꢓ ꢑꢀꢔꢁ ꢉꢀꢊ ꢉꢔꢕꢔꢁ ꢊ ꢓ

ꢖ ꢊꢕ ꢂꢍꢎ ꢀ ꢍꢎ ꢋ ꢑ ꢀꢗ ꢑ ꢕꢀ ꢍ ꢎꢕꢔ ꢁ ꢎꢍ ꢘꢍ ꢎꢍ ꢕꢖꢍ ꢔꢕꢒ ꢌꢊ ꢋ ꢍꢎ ꢒꢊ ꢋ ꢕ

SLAS235B − JULY 1999 − REVISED APRIL 2004

APPLICATION INFORMATION

data format

The 16-bit data word for the TLV5624 consists of two parts:

Program bits

New data

(D15..D12)

(D11..D0)

D15

D14

D13

D12

D11

D10

SPD

PWR

8 Data bits

SPD: Speed control bit

PWR: Power control bit

1 → fast mode

1 → power down

0 → slow mode

0 → normal operation

The following table lists the possible combination of the register select bits:

Write data to DAC

Reserved

Write data to control register

The meaning of the 12 data bits depends on the selected register. For the DAC register, bits D11...D4 determine

the new DAC output value:

data bits: DAC

D11

D10

New DAC Value

If the control register is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:

data bits: CONTROL

D11

D10

REF1

REF2

X: don’t care

REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.

reference bits

REF1

REF0

REFERENCE

External

1.024 V

2.048 V

External

NOTE: A 0.1µF bypass capacitor must be installed on

the reference pin (pin 6). If internal reference is used a

10 µF capacitor must also be installed for reference

voltage stability.

CAUTION:

If external reference voltage is applied to the REF pin, external reference MUST be selected.

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ꢀꢁꢂ ꢃꢄ ꢅꢆ

ꢅ ꢇꢈ ꢉꢂ ꢀ ꢊ ꢃ ꢇꢃ ꢉꢂ ꢁ ꢊꢋ ꢌꢊ ꢋ ꢍꢎ ꢏ ꢉꢐꢑ ꢀ ꢒꢑ ꢓꢑ ꢀꢔꢁ ꢉꢀꢊ ꢉꢔ ꢕ ꢔꢁ ꢊꢓ

ꢖꢊ ꢕꢂ ꢍ ꢎꢀ ꢍꢎ ꢋ ꢑꢀ ꢗ ꢑꢕ ꢀꢍ ꢎꢕꢔꢁ ꢎꢍꢘ ꢍ ꢎꢍꢕꢖꢍ ꢔꢕꢒ ꢌꢊ ꢋꢍ ꢎ ꢒ ꢊꢋ ꢕ

SLAS235B − JULY 1999 − REVISED APRIL 2004

APPLICATION INFORMATION

Example:

Set DAC output, select fast mode, select internal reference at 2.048 V:

1. Set reference voltage to 2.048 V (CONTROL register):

D15

D14

D13

D12

D11

D10

2. Write new DAC value and update DAC output:

D15

D14

D13

D12

D11

D10

New DAC output value

The DAC output is updated on the rising clock edge after D0 is sampled.

To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage

may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 15.

Output

Voltage

0 V

DAC Code

Negative

Offset

Figure 15. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code after offset and full

scale are adjusted out or accounted for in some way. However, single supply operation does not allow for

adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured

between full-scale code and the lowest code that produces a positive output voltage.

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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

ꢅꢇ ꢈꢉꢂ ꢀꢊ ꢃ ꢇꢃ ꢉꢂ ꢁ ꢊꢋ ꢌ ꢊꢋ ꢍ ꢎ ꢏ ꢉꢐꢑ ꢀ ꢒꢑ ꢓ ꢑꢀꢔꢁ ꢉꢀꢊ ꢉꢔꢕꢔꢁ ꢊ ꢓ

ꢖ ꢊꢕ ꢂꢍꢎ ꢀ ꢍꢎ ꢋ ꢑ ꢀꢗ ꢑ ꢕꢀ ꢍ ꢎꢕꢔ ꢁ ꢎꢍ ꢘꢍ ꢎꢍ ꢕꢖꢍ ꢔꢕꢒ ꢌꢊ ꢋ ꢍꢎ ꢒꢊ ꢋ ꢕ

SLAS235B − JULY 1999 − REVISED APRIL 2004

APPLICATION INFORMATION

power-supply bypassing and ground management

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.

Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected

together at the low-impedance power-supply source. The best ground connection may be achieved by

connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground

currents are well managed and there are negligible voltage drops across the ground plane.

A 0.1-µF ceramic-capacitor bypass should be connected between V and AGND and mounted with short leads

as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the

digital power supply.

Figure 16 shows the ground plane layout and bypassing technique.

Analog Ground Plane

0.1 µF

Figure 16. Power-Supply Bypassing

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum

deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale

errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the

measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage

changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (E

)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (E )

Gain error is the error in slope of the DAC transfer function.

total harmonic distortion (THD)

THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal.

The value for THD is expressed in decibels.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below

the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of

the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

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PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TLV5624CD

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

5624C

TLV5624CDG4

TLV5624CDGK

TLV5624CDGKG4

TLV5624CDGKR

TLV5624CDGKRG4

TLV5624ID

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

0 to 70

5624C

ADR

5624I

ADS

VSSOP

SOIC

DGK

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

0 to 70

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

0 to 70

2500

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

0 to 70

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

TLV5624IDG4

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLV5624IDGK

VSSOP

SOIC

DGK

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

TLV5624IDGKG4

TLV5624IDGKR

TLV5624IDGKRG4

TLV5624IDR

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

ADS

2500

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

ADS

Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

ADS

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

5624I

TLV5624IDRG4

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV5624CDGKR

TLV5624IDGKR

TLV5624IDR

VSSOP

SOIC

DGK

2500

330.0

12.4

5.3

6.4

3.4

5.2

1.4

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV5624CDGKR

TLV5624IDGKR

TLV5624IDR

VSSOP

SOIC

DGK

2500

367.0

35.0

Pack Materials-Page 2

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TLV5624IDRG4 [TI]

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