TMP175AQDGKRQ1 [TI]
具有27 个 I2C/SMBus 地址、采用业界通用 LM75 外形尺寸和引脚排列的汽车类温度传感器 | DGK | 8 | -40 to 125;
| 型号： | TMP175AQDGKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有27 个 I2C/SMBus 地址、采用业界通用 LM75 外形尺寸和引脚排列的汽车类温度传感器 | DGK | 8 | -40 to 125 温度传感 输出元件 传感器 换能器 温度传感器 |
| 文件： | 总33页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
TMPx75-Q1 具有 I2C 和 SMBus 接口的汽车级温度传感器，采用行业标准
LM75 尺寸和引脚
1 特性
3 说明
1
•
具有符合 AEC-Q100 标准的以下结果：
TMP75-Q1 和 TMP175-Q1 器件属于数字温度传感
器，是负温度系数 (NTC) 和正温度系数 (PTC) 热敏电
阻的理想替代产品。该器件无需校准或外部组件信号调
节即可提供典型值为 ±1°C 的精度。器件温度传感器为
高度线性化产品，无需复杂计算或查表即可得知温度。
片上 12 位模数转换器 (ADC) 提供低至 0.0625°C 的分
辨率。这两款器件采用行业标准 LM75 8 引脚 SOIC
和 VSSOP 封装。
–
–
–
温度 1 级：-40°C 至 +125°C 的工作环境温度范
围
人体放电模式 (HBM) 静电放电 (ESD) 分类等级
2
组件充电模式 (CDM) ESD 分类等级 C6
•
•
TMP175-Q1 精度：
–
–
–40°C 至 125°C 范围内为 ±1°C（典型值）
–40°C 至 +125°C 范围内为 ±2°C（最大值）
TMP175-Q1 和 TMP75-Q1 与 SMBus、两线制和 I2C
接口兼容。TMP175-Q1 器件允许一条总线上最多连接
27 个器件。TMP75-Q1 允许一条总线上最多连接 8 个
器件。TMP175-Q1 和 TMP75-Q1 均具备 SMBus 报
警功能。
TMP75-Q1 精度：
–
–
–40°C 至 125°C 范围内为 ±1°C（典型值）
–40°C 至 +125°C 范围内为 ±3°C（最大值）
•
•
TMP175-Q1：27 个地址
TMP75-Q1：8 个地址，美国国家标准与技术研究
所 (NIST) 可追溯
数字输出： SMBus™、两线制和 I2C 接口兼容性
TMP175-Q1 和 TMP75-Q1 器件是各种通信、计算
机、消费类产品、环境、工业和仪器应用中扩展温度测
量的理想选择。TMP75-Q1 生产单元已完全通过可追
溯 NIST 的传感器测试，并且已借助可追溯 NIST 的设
备使用 ISO/IEC 17025 标准认可的校准进行验证。
•
•
•
•
•
分辨率：9 至 12 位，用户可选
低静态电流：50μA，0.1μA 待机电流
宽电源电压范围：2.7V 至 5.5V
小型 8 引脚超薄小外形尺寸 (VSSOP) 封装和 8 引
脚小外形集成电路 (SOIC) 封装
TMP175-Q1 和 TMP75-Q1 器件的额定工作温度范围
为 －40℃ 至 +125℃。
2 应用
器件信息(1)
•
•
•
•
•
•
•
•
•
汽车空调
器件型号
TMPx75-Q1
封装
SOIC (8)
VSSOP (8)
封装尺寸（标称值）
4.90mm x 3.91mm
3.00mm x 3.00mm
信息娱乐处理器管理
空气流量传感器
电池控制单元
引擎控制单元
UREA 传感器
抽水机
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
TMP175-Q1 和 TMP75-Q1 内部框图
Temperature
Diode
Temp.
1
2
Control
Logic
8
7
V+
A0
SDA
SCL
HID 灯
Sensor
安全气囊控制单元
ΔΣ
简化电路原理图
Serial
ADC
Interface
2.7-V to 5.5-V
Supply Voltage
3
4
6
5
ALERT
GND
A1
A2
0.01-µF
Supply Bypass
Capacitor
Config.
and Temp.
Register
5-kꢀ
Pullup Resistors
OSC
1
8
Two-Wire
Host
Controller
V+
A0
A1
A2
SDA
2
7
SCL
3
6
5
ALERT
4
GND
TMP175-Q1,
TMP75-Q1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS759
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 15
7.5 Programming .......................................................... 16
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
Power Supply Recommendations...................... 23
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1 相关链接................................................................ 24
11.2 社区资源................................................................ 24
11.3 商标....................................................................... 24
11.4 静电放电警告......................................................... 24
11.5 Glossary................................................................ 24
12 机械、封装和可订购信息....................................... 24
7
4 修订历史记录
日期
修订版本
注释
2015 年 11 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
5 Pin Configuration and Functions
DGK, D Packages
8-Pin VSSOP, SOIC
Top View
1
2
3
4
8
7
6
5
SDA
SCL
V+
A0
A1
A2
ALERT
GND
NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram.
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
SDA
SCL
ALERT
GND
A2
1
2
3
4
5
6
7
8
I/O
I
Serial data. Open-drain output; requires a pullup resistor.
Serial clock. Open-drain output; requires a pullup resistor.
Overtemperature alert. Open-drain output; requires a pullup resistor.
Ground
O
—
A1
I
I
Address select. Connect to GND, V+, or (for the TMP175-Q1 device only) leave these pins floating.
Supply voltage, 2.7 V to 5.5 V
A0
V+
Copyright © 2015, Texas Instruments Incorporated
3
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–55
–60
MAX
7
UNIT
V
Power supply, V+
Input voltage(2)
7
V
Input current
10
mA
°C
°C
°C
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
127
150
130
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input voltage rating applies to all TMP175-Q1 and TMP75-Q1 input voltages.
6.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
5.5
UNIT
Supply voltage
V
Operating free-air temperature, TA
–40
125
°C
6.4 Thermal Information
TMP175-Q1, TMP75-Q1
THERMAL METRIC(1)
DGK (SOIC), D (VSSOP)
UNIT
8 PINS
185
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
76.1
106.4
14.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
104.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
6.5 Electrical Characteristics
at TA = –40°C to +125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE INPUT
Range
–40
125
°C
TMP175-Q1
±0.5
±0.5
±1
±1.5
±2
–25°C to +85°C
TMP75-Q1
TMP175-Q1
TMP75-Q1
Accuracy (temperature error)
°C
±2
–40°C to +125°C
Selectable
±1
±3
Accuracy (temperature error) vs supply
Resolution(1)
0.2
±0.5
°C/V
°C
0.0625
DIGITAL INPUT/OUTPUT
Input capacitance
3
pF
V
VIH
VIL
IIN
High-level input logic
Low-level input logic
Leakage input current
Input voltage hysteresis
0.7 (V+)
–0.5
6
0.3 (V+)
1
V
0 V ≤ VIN ≤ 6 V
SCL and SDA pins
IOL = 3 mA
IOL = 4 mA
Selectable
9 bits
µA
mV
500
0.15
0.15
9 to 12
27.5
55
SDA
0
0
0.4
0.4
VOL
Low-level output logic
Resolution
V
ALERT
Bits
37.5
75
10 bits
Conversion time
ms
11 bits
110
150
300
74
12 bits
220
Timeout time
25
54
ms
V
POWER SUPPLY
Operating range
2.7
5.5
85
Serial bus inactive
50
100
410
0.1
IQ
Quiescent current
Shutdown current
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 3.4 MHz
Serial bus inactive
µA
3
ISD
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 3.4 MHz
60
µA
380
TEMPERATURE RANGE
Specified range
–40
–55
125
127
°C
°C
Operating range
(1) Specified for 12-bit resolution.
Copyright © 2015, Texas Instruments Incorporated
5
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
6.6 Timing Requirements
see the Timing Diagrams and Two-Wire Timing Diagrams sections for additional information(1)
HIGH-SPEED
MODE
FAST MODE
UNIT
MIN
MAX
MIN
MAX
ƒ(SCL)
t(BUF)
SCL operating frequency
V+
0.001
0.4
0.001
160
2.38
MHz
ns
Bus-free time between STOP and START
condition
1300
600
Hold time after repeated START condition.
After this period, the first clock is generated.
t(HDSTA)
160
ns
See the Timing Diagrams section
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
Repeated START condition setup time
STOP condition setup time
Data hold time
600
600
4
160
160
4
ns
ns
ns
ns
ns
ns
ns
ns
900
120
Data setup time
100
1300
600
10
SCL clock low period
SCL clock high period
Data fall time
V+ , see the Timing Diagrams section
See the Timing Diagrams section
280
60
t(HIGH)
tFD
See the Timing Diagrams section
300
300
150
40
See the Two-Wire Timing Diagrams section
tRC
tFC
Clock rise time
Clock fall time
SCLK ≤ 100 kHz, see the Timing Diagrams
section
1000
300
ns
ns
See the Two-Wire Timing Diagrams section
40
(1) Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not
production tested.
6
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
6.7 Typical Characteristics
at TA = 25°C and V+ = 5 V (unless otherwise noted)
85
75
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
65
V+ = 5 V
55
45
V+ = 2..7V
35
−0.1
25
−
55
−
−
15
35
5
25
45
65
85 105 125 130
−
55
−
35
−
15
5
25
45
65
85 105 125 130
Temperature (°C)
Temperature (°C)
Serial bus inactive
Figure 1. Quiescent Current vs Temperature
Figure 2. Shutdown Current vs Temperature
2
1.5
1
300
V+ = 5 V
250
200
150
100
0.5
0
V+ = 2.7 V
−0.5
−1
−1.5
−2
−
−
35
−
15
55
5
25
45
65
85 105 125 130
−
55
−
35
−
15
5
25
45
65
85
105 125 130
Temperature (°C)
Temperature (°C)
3 typical units, 12-bit resolution
12-bit resolution
Figure 4. Temperature Error vs Temperature
Figure 3. Conversion Time vs Temperature
500
Hs Mode
Fast Mode
450
400
350
300
250
200
150
100
50
125°C
25°C
−
55°C
0
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 5. Quiescent Current With Bus Activity vs Temperature
Copyright © 2015, Texas Instruments Incorporated
7
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TMP175-Q1 and TMP75-Q1 devices are digital temperature sensors that are optimal for thermal
management and thermal protection applications. The TMP175-Q1 and TMP75-Q1 are two-wire, SMBus, and
I2C interface compatible. The devices are specified over a temperature range of –40°C to +125°C. The
Functional Block Diagram section shows the internal block diagram of the TMP175-Q1 and TMP75-Q1 devices.
The temperature sensor in the TMP175-Q1 and TMP75-Q1 devices is the chip itself. Thermal paths run through
the package leads as well as the plastic package. The package leads provide the primary thermal path because
of the lower thermal resistance of the metal.
7.2 Functional Block Diagram
Temperature
Diode
Temp.
1
2
Control
Logic
8
7
V+
A0
SDA
SCL
Sensor
ΔΣ
Serial
ADC
Interface
3
4
6
5
ALERT
GND
A1
A2
Config.
and Temp.
Register
OSC
8
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
7.3 Feature Description
7.3.1 Digital Temperature Output
The digital output from each temperature measurement conversion is stored in the read-only Temperature
register. The Temperature register of the TMP175-Q1 or TMP75-Q1 is a 12-bit, read-only register that stores the
output of the most recent conversion. Two bytes must be read to obtain data and are listed in Table 6 and
Table 7. The first 12 bits are used to indicate temperature with all remaining bits equal to zero. The data format
for temperature is listed in Table 1. Negative numbers are represented in binary twos complement format.
Following power-up or reset, the Temperature register reads 0°C until the first conversion is complete.
The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration register and setting the
resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits (MSBs) in the Temperature
register are used with the unused least significant bits (LSBs) set to zero.
Table 1. Temperature Data Format
DIGITAL OUTPUT
BINARY
TEMPERATURE
(°C)
HEX
7FF
7FF
640
500
4B0
320
190
004
000
FFC
E70
C90
128
127.9375
100
80
0111 1111 1111
0111 1111 1111
0110 0100 0000
0101 0000 0000
0100 1011 0000
0011 0010 0000
0001 1001 0000
0000 0000 0100
0000 0000 0000
1111 1111 1100
1110 0111 0000
1100 1001 0000
75
50
25
0.25
0
–0.25
–25
–55
7.3.2 Serial Interface
The TMP175-Q1 and TMP75-Q1 operate only as slave devices on the SMBus, two-wire, and I2C interface-
compatible bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and
SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes
and bus noise. The TMP175-Q1 and TMP75-Q1 support the transmission protocol for fast (up to 400 kHz) and
high-speed (up to 2.38-MHz) modes. All data bytes are transmitted MSB first.
7.3.2.1 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device a START condition is initiated, indicated by pulling the data line (SDA) from a high
to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data
transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted
as a control signal.
When all data are transferred, the master generates a STOP condition indicated by pulling SDA from low to high
when SCL is high.
Copyright © 2015, Texas Instruments Incorporated
9
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
7.3.2.2 Serial Bus Address
To communicate with the TMP175-Q1 and TMP75-Q1, the master must first address slave devices through a
slave address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent
of executing a read or write operation.
The TMP175-Q1 features three address pins to allow up to 27 devices to be addressed on a single bus interface.
Table 2 describes the pin logic levels used to properly connect up to 27 devices. A 1 indicates that the pin is
connected to the supply (VCC) and a 0 indicates that the pin is connected to GND; float indicates that the pin is
left unconnected. The state of the A0, A1, and A2 pins is sampled on every bus communication and must be set
prior to any activity on the interface.
Table 2. Address Pins and Slave Addresses for the TMP175-Q1
A2
A1
A0
SLAVE ADDRESS
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110101
0110110
0110111
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
0
1
1
1
Float
Float
Float
Float
Float
Float
Float
Float
0
0
0
0
Float
1
0
1
0
1
Float
1
1
Float
Float
Float
Float
Float
Float
0
0
1
0
0
1
1
0
1
1
0
Float
Float
Float
Float
Float
Float
Float
0
1
1
0
1
1
0
Float
Float
Float
1
Float
10
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
The TMP75-Q1 features three address pins, allowing up to eight devices to be connected per bus. Pin logic
levels are described in Table 3. The address pins of the TMP175-Q1 and TMP75-Q1 are read after reset, at start
of communication, or in response to a two-wire address acquire request. After the state of the pins are read, the
address is latched to minimize power dissipation associated with detection.
Table 3. Address Pins and Slave Addresses for the TMP75-Q1
A2
0
A1
0
A0
0
SLAVE ADDRESS
1001000
0
0
1
1001001
0
1
0
1001010
0
1
1
1001011
1
0
0
1001100
1
0
1
1001101
1
1
0
1001110
1
1
1
1001111
7.3.2.3 Writing and Reading to the TMP175-Q1 and TMP75-Q1
Accessing a particular register on the TMP175-Q1 and TMP75-Q1 devices is accomplished by writing the
appropriate value to the Pointer register. The value for the Pointer register is the first byte transferred after the
slave address byte with the R/W bit low. Every write operation to the TMP175-Q1 and TMP75-Q1 requires a
value for the Pointer register (see Figure 7).
When reading from the TMP175-Q1 and TMP75-Q1 devices, the last value stored in the Pointer register by a
write operation is used to determine which register is read by a read operation. To change the register pointer for
a read operation, a new value must be written to the Pointer register. This action is accomplished by issuing a
slave address byte with the R/W bit low, followed by the Pointer register byte. No additional data are required.
The master can then generate a START condition and send the slave address byte with the R/W bit high to
initiate the read command; see Figure 9 for details of this sequence. If repeated reads from the same register are
desired, the Pointer register bytes do not have to be continually sent because the TMP175-Q1 and TMP75-Q1
remember the Pointer register value until it is changed by the next write operation.
Register bytes are sent MSB first, followed by the LSB.
7.3.2.4 Slave Mode Operations
The TMP175-Q1 and TMP75-Q1 can operate as a slave receiver or slave transmitter.
7.3.2.4.1 Slave Receiver Mode
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP175-Q1 or TMP75-
Q1 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer
register. The TMP175-Q1 or TMP75-Q1 then acknowledges reception of the Pointer register byte. The next byte
or bytes are written to the register addressed by the Pointer register. The TMP175-Q1 and TMP75-Q1
acknowledge reception of each data byte. The master can terminate data transfer by generating a START or
STOP condition.
7.3.2.4.2 Slave Transmitter Mode
The first byte is transmitted by the master and is the slave address, with the R/W bit high. The slave
acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most
significant byte of the register indicated by the Pointer register. The master acknowledges reception of the data
byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of
the data byte. The master can terminate data transfer by generating a Not-Acknowledge bit on reception of any
data byte, or by generating a START or STOP condition.
Copyright © 2015, Texas Instruments Incorporated
11
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
7.3.2.5 SMBus Alert Function
The TMP175-Q1 and TMP75-Q1 support the SMBus alert function. When the TMP75-Q1 and TMP175-Q1 are
operating in interrupt mode (TM = 1), the ALERT pin of the TMP75-Q1 or TMP175-Q1 can be connected as an
SMBus alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master
sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP75-Q1 or TMP175-Q1 is
active, the devices acknowledge the SMBus Alert command and respond by returning its slave address on the
SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling
below TLOW caused the ALERT condition. This bit is high if the temperature is greater than or equal to THIGH. This
bit is low if the temperature is less than TLOW; see Figure 10 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus Alert command determines which device clears its ALERT status. If the TMP75-Q1 or TMP175-Q1
wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the
TMP75-Q1 or TMP175-Q1 loses the arbitration, its ALERT pin remains active.
7.3.2.6 General Call
The TMP175-Q1 and TMP75-Q1 respond to a two-wire, general-call address (0000000) if the eighth bit is 0. The
device acknowledges the general call address and responds to commands in the second byte. If the second byte
is 00000100, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins, but do not reset. If the
second byte is 00000110, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins and resets
their internal registers to their power-up values.
7.3.2.7 High-Speed Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation.
The TMP175-Q1 and TMP75-Q1 devices do not acknowledge this byte, but do switch their input filters on SDA
and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 2.38 MHz. After the
Hs-mode master code is issued, the master transmits a two-wire slave address to initiate a data transfer
operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving
the STOP condition, the TMP175-Q1 and TMP75-Q1 switch the input and output filter back to fast-mode
operation.
7.3.2.8 Time-out Function
The TMP175-Q1 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START
and STOP condition. The TMP175-Q1 releases the bus if it is pulled low and waits for a START condition. To
avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL
operating frequency.
7.3.3 Timing Diagrams
The TMP175-Q1 and TMP75-Q1 devices are two-wire, SMBus, and I2C interface compatible. Figure 6 to
Figure 10 describe the various operations on the TMP175-Q1. The following list provides bus definitions.
Parameters for Figure 6 are defined in the Timing Requirements table.
Bus Idle: Both the SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a
START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data transfer can be signaled by the master generating a
Not-Acknowledge bit on the last byte that is transmitted by the slave.
12
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
7.3.3.1 Two-Wire Timing Diagrams
t(LOW)
tF
tR
t(HDSTA)
SCL
t(SUSTO)
t(HDSTA)
t(HIGH) t(SUSTA)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 6. Two-Wire Timing Diagram
1
9
1
9
SCL
SDA
…
…
1
0
0
1
-
A2
A1
A0
R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
Device
ACK By
Device
Frame 2Pointer Register Byte
Wire Slave Address Byte
Frame 1Two
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D7 D6
D5
D4 D3
D2
D1
D0
D7
D6
D5
D4
D3 D2
D1 D0
ACK By
Device
ACK By
Device
Stop By
Master
Frame 3Data Byte 1
Frame 4Data Byte 2
Figure 7. Two-Wire Timing Diagram for the TMP75-Q1 Write Word Format
1
9
1
9
SCL
…
…
SDA
A6
A5
A4 A3 A2
A1
A0
R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D7 D6
D5
D4
D3 D2 D1
D0
D7
D6
D5
D4
D3 D2
D1 D0
ACK By
Device
ACK By
Device
Stop By
Master
Frame 3 Data Byte 1
Frame 4 Data Byte 2
Figure 8. Two-Wire Timing Diagram for the TMP175-Q1 Write Word Format
Copyright © 2015, Texas Instruments Incorporated
13
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
1
9
1
9
…
SCL
…
SDA
1
0
0
1
R/W
0
0
0
0
0
0
P1
P0
0
0
0
Start By
Master
ACK By
ACK By
Device
Device
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
…
(Continued)
SDA
…
0
0
0
1
0
0
1
R/W
D7
D6
D5
D4
D3
D2
D1 D0
(Continued)
Start By
Master
ACK By
From
Device
ACK By
Master
Device
y
Frame 3 Two-Wire Slave Address B te
Frame 4 Data Byte 1Read Register
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4
D3 D2
D1
D0
(Continued)
From
Device
ACK By
Master
Stop By
Master
Frame 5 Data Byte 2 Read Register
NOTE: Address pins A0, A1, and A2 = 0.
Figure 9. Two-Wire Timing Diagram for Read Word Format
ALERT
SCL
1
9
1
9
SDA
Sta tus
0
0
0
1
1
0
0
R/W
1
0
0
1
0
0
0
Start By
Master
ACK By
From
NACK By Stop By
Master Master
Device
Device
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address Byte
NOTE: Address pins A0, A1, and A2 = 0.
Figure 10. Timing Diagram for SMBus ALERT
14
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
7.4 Device Functional Modes
7.4.1 Shutdown Mode (SD)
The shutdown mode of the TMP175-Q1 and TMP75-Q1 devices lets the user save maximum power by shutting
down all device circuitry other than the serial interface, thus reducing current consumption to typically less than
0.1 μA. Shutdown mode is enabled when the SD bit is 1; the device shuts down when the current conversion is
completed. When SD is equal to 0, the device maintains a continuous conversion state.
7.4.2 One-Shot (OS)
The TMP175-Q1 and TMP75-Q1 feature a one-shot temperature measurement mode. When the device is in
shutdown mode, writing 1 to the OS bit starts a single temperature conversion. The device returns to the
shutdown state at the completion of the single conversion. This feature is useful to reduce power consumption in
the TMP175-Q1 and TMP75-Q1 when continuous temperature monitoring is not required. When the configuration
register is read, OS always reads zero.
7.4.3 Thermostat Mode (TM)
The thermostat mode bit of the TMP175-Q1 and TMP75-Q1 indicates to the device whether to operate in
comparator mode (TM = 0) or interrupt mode (TM = 1). For more information on comparator and interrupt modes,
see the High- and Low-Limit Registers section.
7.4.3.1 Comparator Mode (TM = 0)
In comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in
the T(HIGH) register and remains active until the temperature falls below the value in the T(LOW) register. For more
information on the comparator mode, see the High- and Low-Limit Registers section.
7.4.3.2 Interrupt Mode (TM = 1)
In interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds T(HIGH) or goes below the
T(LOW) registers. The ALERT pin is cleared when the host controller reads the Temperature register. For more
information on the interrupt mode, see the High- and Low-Limit Registers section.
Copyright © 2015, Texas Instruments Incorporated
15
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
7.5 Programming
7.5.1 Pointer Register
Figure 11 shows the internal register structure of the TMP175-Q1 and TMP75-Q1. The 8-bit Pointer register of
the devices is used to address a given data register. The Pointer register uses the two LSBs to identify which of
the data registers must respond to a read or write command. Table 4 identifies the bits of the Pointer register
byte. Table 5 describes the pointer address of the registers available in the TMP175-Q1 and TMP75-Q1. The
power-up reset value of P1/P0 is 00.
Pointer
Register
Temperature
Register
SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
Figure 11. Internal Register Structure of the TMP175-Q1 and TMP75-Q1
Table 4. Pointer Register Byte (pointer = N/A) [reset = 00h]
P7
P6
P5
P4
P3
P2
P1
P0
0
0
0
0
0
0
Register Bits
Table 5. Pointer Addresses of the TMP175-Q1 and TMP75-Q1
P1
0
P0
0
TYPE
R only, default
R/W
REGISTER
Temperature register
Configuration register
TLOW register
0
1
1
0
R/W
1
1
R/W
THIGH register
16
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
7.5.2 Temperature Register
The Temperature register of the TMP175-Q1 or TMP75-Q1 is a 12-bit, read-only register that stores the output of
the most recent conversion. Two bytes must be read to obtain data and are described in Table 6 and Table 7.
Byte 1 is the most significant byte and is followed by byte 2, the least significant byte. The first 12 bits are used
to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read
if that information is not needed. Following the power-up or reset value, the Temperature register reads 0°C until
the first conversion is complete.
Table 6. Byte 1 of the Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T11
T10
T9
T8
T7
T6
T5
T4
Table 7. Byte 2 of the Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T3
T2
T1
T0
0
0
0
0
7.5.3 Configuration Register
The Configuration register is an 8-bit read/write register used to store bits that control the operational modes of
the temperature sensor. Read and write operations are performed MSB first. The format of the Configuration
register for the TMP175-Q1 and TMP75-Q1 is shown in Table 8, followed by a breakdown of the register bits.
The power-up or reset value of the Configuration register are all bits equal to 0.
Table 8. Configuration Register Format
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
OS
R1
R0
F1
F0
POL
TM
SD
Copyright © 2015, Texas Instruments Incorporated
17
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
7.5.3.1 Polarity (POL)
The Polarity bit of the TMP175-Q1 lets the user adjust the polarity of the ALERT pin output. If the POL bit is set
to 0 (default), the ALERT pin becomes active low. When the POL bit is set to 1, the ALERT pin becomes active
high and the state of the ALERT pin is inverted. The operation of the ALERT pin in various modes is shown in
Figure 12.
THIGH
Measured
Temperature
TLOW
Device ALERT Pin
(Comparator Mode)
POL =0
Device ALERT Pin
(Interrupt Mode)
POL =0
Device ALERT Pin
(Comparator Mode)
POL =1
Device ALERT Pin
(Interrupt Mode)
POL =1
Read
Read
Time
Read
Figure 12. Output Transfer Function Diagrams
7.5.3.2 Fault Queue (F1/F0)
A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH
and TLOW registers. Additionally, the number of fault conditions required to generate an alert can be programmed
using the fault queue. The fault queue is provided to prevent a false alert resulting from environmental noise. The
fault queue requires consecutive fault measurements in order to trigger the Alert function. Table 9 defines the
number of measured faults that can be programmed to trigger an Alert condition in the device. For the THIGH and
TLOW register format and byte order, see the High- and Low-Limit Registers section.
Table 9. Fault Settings of the TMP175-Q1 and TMP75-Q1
F1
0
F0
0
CONSECUTIVE FAULTS
1
2
4
6
0
1
1
0
1
1
18
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
7.5.3.3 Converter Resolution (R1/R0)
The Converter Resolution bits control the resolution of the internal analog-to-digital (ADC) converter. This control
allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 10
identifies the resolution bits and the relationship between resolution and conversion time.
Table 10. Resolution of the TMP175-Q1 and TMP75-Q1
CONVERSION TIME
R1
R0
RESOLUTION
(Typical)
27.5 ms
55 ms
0
0
1
1
0
1
0
1
9 bits (0.5°C)
10 bits (0.25°C)
11 bits (0.125°C)
12 bits (0.0625°C)
110 ms
220 ms
7.5.4 High- and Low-Limit Registers
In comparator mode (TM = 0), the ALERT pin of the TMP175-Q1 and TMP75-Q1 becomes active when the
temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to
fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated TLOW value for
the same number of faults.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register
occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin is also
cleared if the device is placed in shutdown mode. When cleared, the ALERT pin only becomes active again by
the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active and
remains active until cleared by a read operation of any register or a successful response to the SMBus alert
response address. When the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming
active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the
device with the General-Call Reset command. This action also clears the state of the internal registers in the
device, returning the device to comparator mode (TM = 0).
Copyright © 2015, Texas Instruments Incorporated
19
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
Both operational modes are represented in Figure 12. Table 11, Table 12, Table 13, and Table 14 describe the
format for the THIGH and TLOW registers. The most significant byte is sent first, followed by the least significant
byte. Power-up reset values for THIGH and TLOW are:
THIGH = 80°C and TLOW = 75°C
The format of the data for THIGH and TLOW is the same as for the Temperature register.
Table 11. Byte 1 of the THIGH Register
D7
D6
D5
D4
D3
D2
D1
D0
H11
H10
H9
H8
H7
H6
H5
H4
Table 12. Byte 2 of the THIGH Register
D7
D6
D5
D4
D3
D2
D1
D0
H3
H2
H1
H0
0
0
0
0
Table 13. Byte 1 of the TLOW Register
BYTE
D7
L11
D6
D5
D4
D3
D2
D1
D0
L4
1
L10
L9
L8
L7
L6
L5
Table 14. Byte 2 of the TLOW Register
D7
D6
L2
D5
D4
D3
D2
D1
D0
L3
L1
L0
0
0
0
0
All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the Alert function for
all converter resolutions. The three LSBs in THIGH and TLOW can affect the Alert output even if the converter is
configured for 9-bit resolution.
20
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP175-Q1 and TMP75-Q1 devices are used to measure the printed circuit board (PCB) temperature of
where the device is mounted. The TMP175-Q1 and TMP75-Q1 feature SMBus, two-wire, and I2C interface
compatibility, with the TMP175-Q1 allowing up to 27 devices on one bus and the TMP75-Q1 allowing up to eight
devices on one bus. The TMP175-Q1 and TMP75-Q1 both feature a SMBus Alert function. The TMP175-Q1 and
TMP75-Q1 require no external components for operation except for pullup resistors on SCL, SDA, and ALERT,
although a 0.1-μF bypass capacitor is recommended.
The sensing device of the TMP175-Q1 and TMP75-Q1 devices is the device itself. Thermal paths run through
the package leads as well as the plastic package. The lower thermal resistance of metal causes the leads to
provide the primary thermal path.
8.2 Typical Application
2.7-V to 5.5-V
Supply Voltage
0.01-µF
Supply Bypass Capacitor
5-kꢀ
Pullup Resistors
TMP175-Q1,
TMP75-Q1
1
2
3
4
8
V+
A0
A1
A2
SDA
SCL
Two-Wire
Host Controller
7
6
5
ALERT
GND
Figure 13. Typical Connections of the TMP175-Q1 and TMP75-Q1
8.2.1 Design Requirements
The TMP175-Q1 and TMP75-Q1 devices requires pullup resistors on the SCL, SDA, and ALERT pins. The
recommended value for the pullup resistor is 5 kΩ. In some applications the pullup resistor can be lower or
higher than 5 kΩ, but must not exceed 3 mA of current on the SCL and SDA pins and must not exceed 4 mA on
the ALERT pin. A 0.1-μF bypass capacitor is recommended, as shown in Figure 13. The SCL, SDA, and ALERT
lines can be pulled up to a supply that is equal to or higher than VS through the pullup resistors. For the TMP175-
Q1, to configure one of 27 different addresses on the bus, connect A0, A1, and A2 to either the GND or the V+
pin or float these pins. Float indicates that the pin is left unconnected. For the TMP75-Q1, to configure one of
eight different addresses on the bus, connect A0, A1, and A2 to either the GND or V+ pin.
Copyright © 2015, Texas Instruments Incorporated
21
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
Typical Application (continued)
8.2.2 Detailed Design Procedure
Place the TMP175-Q1 and TMP75-Q1 devices in close proximity to the heat source that must be monitored, with
a proper layout for good thermal coupling. This placement ensures that temperature changes are captured within
the shortest possible time interval. To maintain accuracy in applications that require air or surface temperature
measurement, take care to isolate the package and leads from ambient air temperature. A thermally-conductive
adhesive is helpful in achieving accurate surface temperature measurement.
8.2.3 Application Curve
Figure 14 shows the step response of the TMP175-Q1 and TMP75-Q1 devices to a submersion in an oil bath of
100ºC from room temperature (27ºC). The time-constant, or the time for the output to reach 63% of the input
step, is 1.5 s. The time-constant result depends on the PCB where the TMPx175 devices are mounted. For this
test, the TMP175-Q1 and TMP75-Q1 devices were soldered to a two-layer PCB that measured 0.375 inches ×
0.437 inches.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
-1
1
3
5
7
9
11 13 15 17 19
Time (s)
Figure 14. Temperature Step Response
22
Copyright © 2015, Texas Instruments Incorporated
TMP175-Q1, TMP75-Q1
www.ti.com.cn
ZHCSEE7 –NOVEMBER 2015
9 Power Supply Recommendations
The TMP175-Q1 and TMP75-Q1 devices operate with power supplies in the range of 2.7 V to 5.5 V. A power-
supply bypass capacitor is required for stability; place this capacitor as close as possible to the supply and
ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or
high-impedance power supplies can require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommended
value of this bypass capacitor is 0.01 μF. Additional decoupling capacitance can be added to compensate for
noisy or high-impedance power supplies. Pull up the open-drain output pins SDA, SCL, and ALERT through 5-kΩ
pullup resistors.
10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
VS
A0
A1
A2
SCL
ALERT
GND
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 15. Layout Example
版权 © 2015, Texas Instruments Incorporated
23
TMP175-Q1, TMP75-Q1
ZHCSEE7 –NOVEMBER 2015
www.ti.com.cn
11 器件和文档支持
11.1 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访
问。
表 15. 相关链接
部件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TMP175-Q1
TMP75-Q1
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
SMBus is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
24
版权 © 2015, Texas Instruments Incorporated
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
www.ti.com.cn/telecom
数字音频
www.ti.com.cn/audio
www.ti.com.cn/amplifiers
www.ti.com.cn/dataconverters
www.dlp.com
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
www.ti.com.cn/computer
www.ti.com/consumer-apps
www.ti.com/energy
www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
视频和影像
www.ti.com.cn/industrial
www.ti.com.cn/medical
www.ti.com.cn/security
www.ti.com.cn/automotive
www.ti.com.cn/video
www.ti.com.cn/clockandtimers
www.ti.com.cn/interface
www.ti.com.cn/logic
逻辑
电源管理
www.ti.com.cn/power
www.ti.com.cn/microcontrollers
www.ti.com.cn/rfidsys
www.ti.com/omap
微控制器 (MCU)
RFID 系统
OMAP应用处理器
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP175AQDGKRQ1
TMP175AQDRQ1
TMP75AQDGKRQ1
TMP75AQDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
8
8
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
175Q
NIPDAU
NIPDAUAG
NIPDAU
T175Q1
75Q1
VSSOP
SOIC
DGK
D
T75Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
TMP175AQDRQ1
具有27 个 I2C/SMBus 地址、采用业界通用 LM75 外形尺寸和引脚排列的汽车类温度传感器 | D | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMP175_12
Digital Temperature Sensor with Two-Wire InterfaceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMP17FS
Low Cost, Current Output Temperature TransducerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ADI
TMP17FSZ
Low Cost, Current Output Temperature TransducerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ADI
TMP17FSZ-RL
Low Cost, Current Output Temperature TransducerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ADI
TMP17GS
Low Cost, Current Output Temperature TransducerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ADI
TMP17GSZ
Low Cost, Current Output Temperature TransducerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ADI
TMP17GSZ-REEL
Analog Temperature Sensor, ANALOG TEMP SENSOR-VOLTAGE, 3.50Cel, RECTANGULAR, THROUGH HOLE MOUNT, MS-012AA, SOIC-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ADI
TMP17GSZ-RL
Low Cost, Current Output Temperature TransducerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ADI
TMP1826
具有 2kbit EEPROM 的 1-Wire®、±0.2°C 精度数字温度传感器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMP1826DGKR
具有 2kbit EEPROM 的 1-Wire®、±0.2°C 精度数字温度传感器 | DGK | 8 | -55 to 150Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMP1827
1-Wire®, ±0.2°C accurate digital temperature sensor with authentication, 2-Kbit EEPROMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明