TMUX6221 [TI]
具有 1.8V 逻辑电平和闩锁效应抑制的 36V、1:1 (SPST) 2 通道精密开关(高电平有效);型号: | TMUX6221 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 1.8V 逻辑电平和闩锁效应抑制的 36V、1:1 (SPST) 2 通道精密开关(高电平有效) 开关 |
文件: | 总39页 (文件大小:1885K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMUX6221, TMUX6222
ZHCSOX0 –MARCH 2023
TMUX622x 具有1.8V 逻辑器件的36V、低RON、1:1 (SPST)、2 沟道开关
1 特性
3 说明
• 双电源电压范围:±4.5V 至±18 V
• 单电源电压范围:4.5V 至36 V
• 低导通电阻:2.1 Ω
• –40°C 至+125°C 工作温度
• 兼容1.8V 逻辑电平
• 逻辑引脚具有集成的下拉电阻器
• 失效防护逻辑
• 轨到轨运行
TMUX622x 是互补金属氧化物半导体 (CMOS) 开关,
采用双通道 1:1 (SPST) 配置。该器件支持单电源
(4.5V 至 36 V)、双电源(±4.5V 至 ±18 V)或非对
称电源( 例如, VDD = 12V , VSS = –5V ) 。
TMUX622x 可在源极 (Sx) 和漏极 (D) 引脚上支持从
VSS 到VDD 范围的双向模拟和数字信号。
TMUX622x 可以通过控制 SEL 引脚打开信号路径 1
(S1 至 D1)或信号路径 2(S2 至 D2)来启用或禁
用。所有逻辑控制输入均支持 1.8V 到 VDD 的逻辑电
平,因此,当器件在有效电源电压范围内运行时,可确
保TTL 和CMOS 逻辑兼容性。失效防护逻辑电路允许
先在控制引脚上施加电压,然后在电源引脚上施加电
压,从而保护器件免受潜在的损害。
• 双向运行
2 应用
• 有线网络
• 远程无线电单元
• 患者监护和诊断
• 超声波扫描仪
• 光学测试设备
• 光纤网络
• 工厂自动化和工业控制
• 可编程逻辑控制器(PLC)
• 模拟输入模块
• 交流充电(桩)站
• 半导体测试
TMUX622x 是精密开关和多路复用器系列器件。这些
器件具有非常低的导通和关断漏电流 (50pA),因此可
用于高精度测量应用。
封装信息(1)
封装尺寸(标称值)
器件型号
TMUX6221
TMUX6222
封装
DGS(VSSOP,
10)
3.00mm × 3.00mm
• 数据采集系统
• 燃气表
• 流量变送器
(1) 如需了解所有可用封装,请参阅数据表末尾的封装选项附录。
VDD
VSS
VDD
VSS
SW
SW
S1
D1
D2
S1
S2
D1
D2
SW
SW
S2
SEL1
SEL2
SEL1
SEL2
TMUX6221
(SELx = Logic 1)
TMUX6222
(SELx = Logic 1)
方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SCDS452
TMUX6221, TMUX6222
ZHCSOX0 –MARCH 2023
www.ti.com.cn
Table of Contents
7.9 Crosstalk...................................................................19
7.10 Bandwidth............................................................... 19
7.11 THD + Noise............................................................20
7.12 Power Supply Rejection Ratio (PSRR)...................20
8 Detailed Description......................................................21
8.1 Overview...................................................................21
8.2 Functional Block Diagram.........................................21
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................23
8.5 Truth Tables.............................................................. 23
9 Application and Implementation..................................24
9.1 Application Information............................................. 24
9.2 Typical Applications.................................................. 24
9.3 Power Supply Recommendations.............................26
9.4 Layout....................................................................... 26
10 Device and Documentation Support..........................28
10.1 Documentation Support.......................................... 28
10.2 Receiving Notification of Documentation Updates..28
10.3 支持资源..................................................................28
10.4 Trademarks.............................................................28
10.5 静电放电警告.......................................................... 28
10.6 术语表..................................................................... 28
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Thermal Information....................................................5
6.4 Recommended Operating Conditions.........................5
±15 V Dual Supply: Electrical Characteristics ..................6
±15 V Dual Supply: Switching Characteristics .................7
36 V Single Supply: Electrical Characteristics ................. 8
36 V Single Supply: Switching Characteristics ................ 9
12 V Single Supply: Electrical Characteristics ............... 10
12 V Single Supply: Switching Characteristics ...............11
±5 V Dual Supply: Electrical Characteristics ..................12
±5 V Dual Supply: Switching Characteristics .................13
7 Parameter Measurement Information..........................14
7.1 On-Resistance.......................................................... 14
7.2 Off-Leakage Current................................................. 14
7.3 On-Leakage Current................................................. 15
7.4 tON(EN) and tOFF(EN) .................................................. 16
7.5 tON (VDD) Time............................................................17
7.6 Propagation Delay.................................................... 17
7.7 Charge Injection........................................................18
7.8 Off Isolation...............................................................18
Information.................................................................... 28
11.1 Tape and Reel Information......................................29
11.2 Mechanical Data..................................................... 31
4 Revision History
DATE
REVISION
NOTES
March 2023
*
Initial Release
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English Data Sheet: SCDS452
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ZHCSOX0 –MARCH 2023
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5 Pin Configuration and Functions
S1
S2
1
2
3
4
5
10
9
D1
D2
N.C.
GND
VDD
8
VSS
SEL2
SEL1
7
6
Not to scale
图5-1. DGS Package,
10-Pin VSSOP
(Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
NAME
S1
NO.
1
I/O
I/O
Drain pin. Can be an input or output.
S2
2
Source pin 1. Can be an input or output.
N.C.
GND
3
No internal connection. Can be shorted to GND or left floating.
Ground (0 V) reference
—
4
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
5
6
7
P
I
Logic control input, has internal pull-down resistor. Controls the switch connection. For more
information, see 节8.5.
SEL1
SEL2
Logic control input, has internal pull-down resistor. Controls the switch connection. For more
information, see 节8.5.
I
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
8
P
D2
D1
9
I/O
I/O
Drain pin. Can be an input or output.
Drain pin. Can be an input or output.
10
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to 节8.4.
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English Data Sheet: SCDS452
TMUX6221, TMUX6222
ZHCSOX0 –MARCH 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
V
38
VDD –VSS
VDD
Supply voltage
38
V
–0.5
–38
VSS
0.5
V
VSEL or VEN
ISEL or IEN
VS or VD
IIK
Logic control input pin voltage (SELx)
Logic control input pin current (SELx)
Source or drain voltage (Sx, Dx)
Diode clamp current(3)
38
V
–0.5
30
VDD+0.5
30
mA
V
–30
VSS–0.5
–30
mA
mA
°C
°C
°C
IS or ID (CONT)
TA
Source or drain continuous current (Sx, Dx)
Ambient temperature
IDC + 10 %(4)
150
–55
–65
Tstg
Storage temperature
150
TJ
Junction temperature
150
(1) Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute Maximum Rating do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If
used outside the Recommended Operating Condition but within the Absolute Maximum Rating, the device may not be fully functional,
and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(4) Refer to Source or Drain Continuous Current table for IDC specifications.
6.2 ESD Ratings
VALUE
UNIT
TMUX622x
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SCDS452
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6.3 Thermal Information
TMUX622x
DGS (VSSOP)
10 PINS
TBD
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
TBD
TBD
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TBD
ΨJT
TBD
ΨJB
RθJC(bot)
TBD
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4.5
VSS
0
NOM
MAX
36
UNIT
V
(1)
Power supply voltage differential
VDD –VSS
VDD
Positive power supply voltage
36
V
VS or VD
VSEL or VEN
Signal path input/output voltage (source or drain pin) (Sx, D)
Address or enable pin voltage
VDD
36
V
V
(2)
IS or ID (CONT) Source or drain continuous current (Sx, D)
TA Ambient temperature
IDC
mA
°C
125
–40
(1) VDD and VSS can be any value as long as 4.5 V ≤(VDD –VSS) ≤36 V, and the minimum VDD is met.
(2) Refer to Source or Drain Continuous Current table for IDC specifications.
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English Data Sheet: SCDS452
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MAX UNIT
±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
2.1
2.9
3.8
Ω
Ω
VS = –10 V to +10 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
4.5
Ω
0.05
0.5
0.25
0.3
Ω
On-resistance mismatch between VS = –10 V to +10 V
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
channels
ID = –10 mA
0.35
0.6
Ω
Ω
VS = –10 V to +10 V
IS = –10 mA
0.7
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
0.85
Ω
0.01
0.05
VS = 0 V, IS = –10 mA
Ω/°C
nA
nA
nA
nA
nA
nA
nA
nA
nA
0.15
1.6
15
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
–0.15
–1.6
–15
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
0.05
0.05
0.15
1.6
15
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
–0.15
–1.6
–15
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
0.15
1.6
15
–0.15
–1.6
–15
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
2.5
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
1.5
µA
µA
pF
IIL
–0.1 –0.005
CIN
3.5
POWER SUPPLY
25°C
39
7
60
70
85
25
30
45
µA
µA
µA
µA
µA
µA
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SCDS452
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±15 V Dual Supply: Switching Characteristics
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
100
170
185
200
180
195
210
ns
ns
VS = 10 V
RL = 300 Ω, CL = 35 pF
tON
Turn-on time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
100
ns
VS = 10 V
RL = 300 Ω, CL = 35 pF
ns
tOFF
Turn-off time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
0.19
0.2
ms
ms
ms
ps
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
25°C
0.2
tPD
Propagation delay
Charge injection
500
-15
RL = 50 Ω, CL = 5 pF
QINJ
VS = 0 V, CL = 100 pF
25°C
pC
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
OISO
OISO
XTALK
XTALK
BW
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
25°C
25°C
dB
dB
–70
–50
–114
–93
60
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
dB
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Crosstalk
dB
RL = 50 Ω, CL = 5 pF
VS = 0 V
MHz
dB
–3dB Bandwidth
Insertion loss
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
IL
–0.18
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–40
VPP = 15 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0005
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
33
33
pF
pF
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
120
pF
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English Data Sheet: SCDS452
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MAX UNIT
36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
25°C
2.5
3.2
4.2
4.9
0.2
0.25
0.3
1
Ω
Ω
VS = 0 V to 30 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.1
0.3
Ω
VS = 0 V to 30 V
ID = –10 mA
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
Ω
Ω
VS = 0 V to 30 V
IS = –10 mA
1.5
2
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
Ω
0.009
0.05
VS = 18 V, IS = –10 mA
Ω/°C
nA
nA
nA
nA
nA
nA
nA
nA
nA
0.25
3.5
26
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
–0.25
–3.5
–26
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 30 V
0.05
0.05
0.25
3.5
26
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
–0.25
–3.5
–26
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 30 V
0.25
3.5
26
–0.25
–3.5
–26
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
2.5
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
1.5
µA
µA
pF
IIL
–0.1 –0.005
CIN
3.5
POWER SUPPLY
25°C
30
60
70
85
µA
µA
µA
VDD = 39.6 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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English Data Sheet: SCDS452
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36 V Single Supply: Switching Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
110
180
190
200
180
195
200
ns
ns
VS = 18 V
RL = 300 Ω, CL = 35 pF
tON
Turn-on time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
90
ns
VS = 18 V
RL = 300 Ω, CL = 35 pF
ns
tOFF
Turn-off time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
0.17
0.19
0.19
500
ms
ms
ms
ps
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
25°C
tPD
Propagation delay
Charge injection
RL = 50 Ω, CL = 5 pF
QINJ
VS = 18 V, CL = 100 pF
25°C
pC
–13
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
OISO
OISO
XTALK
XTALK
BW
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
25°C
25°C
dB
dB
–70
–50
–112
–93
65
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
dB
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Crosstalk
dB
RL = 50 Ω, CL = 5 pF
VS = 6 V
MHz
dB
–3dB Bandwidth
Insertion loss
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
IL
–0.19
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–60
VPP =18 V, VBIAS = 18 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0004
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
25°C
25°C
35
35
pF
pF
CS(ON),
CD(ON)
On capacitance
VS = 18 V, f = 1 MHz
25°C
120
pF
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MAX UNIT
12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
25°C
4.6
6
7.5
8.4
0.2
0.32
0.35
2
Ω
Ω
VS = 0 V to 10 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.08
1.2
Ω
VS = 0 V to 10 V
ID = –10 mA
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
Ω
Ω
VS = 0 V to 10 V
IS = –10 mA
2.2
2.4
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
Ω
0.017
0.05
VS = 6 V, IS = –10 mA
Ω/°C
nA
nA
nA
nA
nA
nA
nA
nA
nA
0.5
2
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
–0.5
–2
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 10 V
12
0.5
2
–12
–0.5
–2
0.05
0.05
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 10 V
12
0.5
2
–12
–0.5
–2
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
12
–12
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
2.5
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
1.5
µA
µA
pF
IIL
–0.1 –0.005
CIN
3.5
POWER SUPPLY
25°C
15
45
55
65
µA
µA
µA
VDD = 13.2 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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12 V Single Supply: Switching Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
120
180
210
230
210
235
250
ns
ns
VS = 8 V
RL = 300 Ω, CL = 35 pF
tON
Turn-on time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
130
ns
VS = 8 V
RL = 300 Ω, CL = 35 pF
ns
tOFF
Turn-off time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
0.19
0.2
ms
ms
ms
ps
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
25°C
0.2
tPD
Propagation delay
Charge injection
500
–6
RL = 50 Ω, CL = 5 pF
QINJ
VS = 6 V, CL = 100 pF
25°C
pC
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
OISO
OISO
XTALK
XTALK
BW
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
25°C
25°C
dB
dB
–70
–50
–112
–93
75
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
dB
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Crosstalk
dB
RL = 50 Ω, CL = 5 pF
VS = 6 V
MHz
dB
–3dB Bandwidth
Insertion loss
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
IL
–0.3
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–65
VPP = 6 V, VBIAS = 6 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0009
CS(OFF)
CD(OFF)
CS(ON)
CD(ON)
Source off capacitance
Drain off capacitance
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
38
38
pF
pF
,
On capacitance
VS = 6 V, f = 1 MHz
25°C
110
pF
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MAX UNIT
±5 V Dual Supply: Electrical Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
4
7.2
8.6
10
Ω
Ω
VDD = +4.5 V, VSS = –4.5 V
VS = –4.5 V to +4.5 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.1
1.3
0.3
0.35
0.4
2.2
2.5
2.8
Ω
On-resistance mismatch between VS = –4.5 V to +4.5 V
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
channels
ID = –10 mA
Ω
Ω
VS = –4.5 V to +4.5 V
ID = –10 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
Ω
0.019
0.05
VS = 0 V, IS = –10 mA
Ω/°C
nA
nA
nA
nA
nA
nA
nA
nA
nA
0.25
1
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
–0.25
–1
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
12
0.25
1
–12
–0.25
–1
0.05
0.05
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
12
0.25
1
–12
–0.25
–1
VDD = +5.5 V, VSS = –5.5 V
Switch state is on
VS = VD = ±4.5 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
12
–12
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
2.5
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
1.5
µA
µA
pF
IIL
–0.1 –0.005
CIN
3.5
POWER SUPPLY
25°C
26
5
45
55
65
11
14
22
µA
µA
µA
µA
µA
µA
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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±5 V Dual Supply: Switching Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
220
300
350
380
280
330
350
ns
ns
VS = 3 V
RL = 300 Ω, CL = 35 pF
tON
Turn-on time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
210
ns
VS = 3 V
RL = 300 Ω, CL = 35 pF
ns
tOFF
Turn-off time from control input
–40°C to +85°C
–40°C to +125°C
25°C
ns
0.19
0.19
0.19
500
–5
ms
ms
ms
ps
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
25°C
tPD
Propagation delay
Charge injection
RL = 50 Ω, CL = 5 pF
QINJ
VS = 0 V, CL = 100 pF
25°C
pC
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
OISO
OISO
XTALK
XTALK
BW
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
25°C
25°C
dB
dB
–70
–50
–117
–94
78
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
dB
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Crosstalk
dB
RL = 50 Ω, CL = 5 pF
VS = 0 V
MHz
dB
–3dB Bandwidth
Insertion loss
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
IL
–0.35
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–68
VPP = 5 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.001
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
40
40
pF
pF
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
110
pF
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. 图 7-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using the following setup, where RON is computed as RON = V / ISD
:
V
ISD
Sx
Dx
VS
图7-1. On-Resistance
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current.
2. Drain off-leakage current.
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
图7-2 shows the setup used to measure both off-leakage currents.
.
.
VDD
VSS
VDD
VSS
Is (OFF)
ID (OFF)
D1
D2
D1
D2
S1
S2
S1
S2
A
A
Is (OFF)
ID (OFF)
VD
VD
VS
VS
A
A
GND
GND
VS
VS
VD
VD
IS(OFF)
ID(OFF)
图7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VSS
VDD
VSS
Is (ON)
ID (ON)
S1
S2
D1
D2
D1
D2
S1
S2
N.C.
N.C.
A
N.C.
A
Is (ON)
ID (ON)
VD
A
A
N.C.
VS
GND
GND
VD
VS
IS(ON)
ID(ON)
图7-3. On-Leakage Measurement Setup
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7.4 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-4
shows the setup used to measure turn-on time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-4
shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VSEL
0 V
VDD
VSS
tr < 20 ns
tf < 20 ns
50%
50%
VS
Sx
Dx
Output
tON
tOFF
90%
RL
CL
Output
0 V
10%
GND
VSELx
图7-4. Turn-On and Turn-Off Time Measurement Setup
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7.5 tON (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图7-5 shows the setup used to measure turn on time, denoted by the symbol tON (VDD)
.
VSS
0.1 µF
0.1 µF
VDD
Supply
VDD
VDD
VSS
tr = 10 µs
4.5 V
Ramp
VS
D1
D2
Output
CL
S1
0 V
tON
RL
Output
VS
S2
90%
Output
0 V
CL
3 V
SELx
GND
图7-5. tON (VDD) Time Measurement Setup
7.6 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 7-6 and 方程式 1 shows the setup used to measure propagation
delay, denoted by the symbol tPD
.
VDD
VSS
0.1 µF
0.1 µF
250 mV
Input
VDD
S1
VSS
50%
50%
tr < 40 ps
tf < 40 ps
(VS)
50 Ω
50 Ω
Output
CL
D1
D2
VS
0 V
tPD
1
tPD 2
RL
S2
Output
VS
Output
0 V
50%
50%
RL
CL
GND
图7-6. Propagation Delay Measurement Setup
t
= max t 1, t 2
PD
(1)
Prop Delay
PD
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7.7 Charge Injection
The TMUX622x has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QC. 图 7-7 shows the setup used to measure charge injection from source (Sx) to drain
(D).
VDD
VSS
0.1 µF
0.1 µF
VS
3 V
VSEL
VDD
VSS
tr < 20 ns
tf < 20 ns
S1
S2
Output
CL
D1
D2
0 V
VS
Output
CL
Output
VS
VOUT
SELx
QINJ = CL ×
VOUT
VSEL
GND
图7-7. Charge-Injection Measurement Setup
7.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图7-8 and 方
程式2 shows the setup used to measure off isolation. Use off isolation equation to compute off isolation.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
D1
50
VOUT
VSIG
50
Sx/Dx
50
GND
图7-8. Off Isolation Measurement Setup
V
OUT
Off Isolation = 20 × LOG
(2)
V
S
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7.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 7-9 shows the setup used to measure, and 方程式 3 shows the
equation used to calculate crosstalk.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VOUT
S1
S2
D1
50
50
Vs
D2
50
50
GND
VSIG
图7-9. Crosstalk Measurement Setup
V
OUT
Crosstalk = 20 × LOG
(3)
V
S
7.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 7-10 and 方程式 4 shows the setup used to
measure bandwidth.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
Sx
Dx
50
VOUT
VSIG
50
GND
图7-10. Bandwidth Measurement Setup
V
OUT
Bandwidtℎ = 20 × Log
(4)
V
S
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7.11 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD + N.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Audio Precision
SX
40 Ω
Dx
VOUT
VS
RL
GND
图7-11. THD + N Measurement Setup
7.12 Power Supply Rejection Ratio (PSRR)
PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage
pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave
of 100 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the
AC PSRR.
VDD
Network Analyzer
VSS
DC Bias
Injector
With and Without
Capacitor
50 Ω
0.1 µF
0.1 µF
VDD
S1
VSS
620 mVPP
VIN
VBIAS
Other Sx/
Dx pins
50 Ω
50 Ω
VOUT
D1
GND
RL
CL
图7-12. AC PSRR Measurement Setup
V
OUT
PSRR = 20 × Log
(5)
V
IN
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8 Detailed Description
8.1 Overview
The TMUX622x is a 1:1, 2-channel switch. Each input is turned on or turned off based on the state of the select
line and enable pin.
8.2 Functional Block Diagram
The following figure shows the functional block diagram of the TMUX622x.
VDD
VSS
VDD
VSS
SW
SW
S1
S2
D1
D2
S1
S2
D1
D2
SW
SW
SEL1
SEL2
SEL1
SEL2
TMUX6221
(SELx = Logic 1)
TMUX6222
(SELx = Logic 1)
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX622x conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail-to-Rail Operation
The valid signal path input and output voltage for TMUX622x ranges from VSS to VDD
.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX622x has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs allows the
device to interface with processors that have lower logic I/O rails and eliminates the need for an external
translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations, refer to
Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Integrated Pull-Down Resistor on Logic Pins
The TMUX622x have internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The
value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher voltages. This
feature integrates up to four external components and reduces system size and cost.
8.3.5 Fail-Safe Logic
The TMUX622x supports Fail-Safe Logic on the control input pins (EN and SEL) allowing for operation up to 36
V above ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to be
applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-
Safe Logic feature allows the logic input pins of the TMUX622x to be ramped to +36 V while VDD and VSS = 0 V.
The logic control inputs are protected against positive faults of up to +36 V in powered-off condition, but do not
offer protection against negative overvoltage conditions.
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8.3.6 Latch-Up Immune
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX622x family of devices are constructed on silicon-on-insulator (SOI) based process where an oxide
layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures
from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events
due to overvoltage or current injections. The latch-up immunity feature allows the TMUX622x family of switches
and multiplexers to be used in harsh environments.
8.3.7 Ultra-Low Charge Injection
The TMUX622x has a transmission gate topology, as shown in 图 8-1. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图8-1. Transmission Gate Topology
The TMUX622x contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce
charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This
will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the
Source (Sx) instead of the Drain (Dx). As a general rule, Cp should be 20x larger than the equivalent load
capacitance on the Drain (Dx). 图8-2 shows charge injection variation with different compensation capacitors on
the Source side. This plot was captured on the TMUX6219 as part of the TMUX62xx family with a 100 pF load
capacitance.
图8-2. Charge Injection Compensation
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8.4 Device Functional Modes
The TMUX622x devices have two independently selectable single-pole, single-throw switches that are turned-on
or turned-off based on the state of the corresponding select pin. The control pins can be as high as 36 V.
The TMUX622x devices can be operated without any external components except for the supply decoupling
capacitors. The SEL pins has internal pull-down resistor of 4 MΩ. If unused, tie the SEL pins to GND so that the
device does not consume additional current. For more information, see Implications of Slow or Floating CMOS
Inputs. Unused signal path inputs (S1, S2, D1, or D2) should be connected to GND.
8.5 Truth Tables
表8-1 provides the truth tables for the TMUX622x.
表8-1. TMUX6221 Truth Table
SEL x
CHANNEL x
Channel x OFF
Channel x ON
0
1
表8-2. TMUX6222 Truth Table
CHANNEL x
SEL x
0
1
Channel x ON
Channel x OFF
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
TMUX622x is part of the precision switches and multiplexers family of devices. TMUX622x offers low RON, low
on and off leakage currents and ultra-low charge injection performance. These properties make TMUX622x ideal
for implementing high precision industrial systems requiring selection of one of two inputs or outputs.
9.2 Typical Applications
9.2.1 Switched Gain Amplifier –Discrete PGA
Switches and multiplexers are commonly used in the feedback path of the amplifier circuits to provide
configurable gain control. By using various resistor values on each switch path, the TMUX622x allows the
system to have multiple gain settings. An external resistor, ensures the amplifier is not operating in an open loop
configuration, and gives up to 4 gain settings. The leakage current, on-resistance, and charge injection
performance of the TMUX622x are key specifications to evaluate when selecting a device for gain control.
图9-1 shows the TMUX622x configured to select the gain of an op-amp, creating a discrete PGA.
For more information on how to use TI's analog switches in Discrete Programmable Gain Amplifier (PGA) such
as the impact of On-Capacitance, see Choosing the Right Multiplexer for a Discrete Programmable Gain
Amplifier (PGA)
V
DD VSS
0.1µF
0.1µF
VI/O
Processor
SEL1
SEL2
720
110
1.8V Logic I/O
Digital Processing
900
VI/O
VDD
-
OP
AMP
Gain / Filter
Network
ADC
VIN
+
VSS
图9-1. Gain Switching
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9.2.1.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETERS
Supply (VDD
Supply (VSS
VALUES
15 V
)
)
-15 V
Input or output signal range
Control logic thresholds
-15 V to 15 V (Rail-to-Rail)
1.8 V compatible
9.2.1.2 Detailed Design Procedure
The TMUX622x device can operate without any external components except for the supply decoupling
capacitors. All inputs signals passing through the switch must fall within the recommend operating conditions of
the TMUX622x including signal range and continuous current. For this design example, with a supply of +15 V
and -15 V, the signals can range from +15 V to -15 V when the device is powered.
The application shown in Switching Gain Settings demonstrates how to use the TMUX622x to control the
feedback gain of a precision op-amp. This feedback design can very sensitive to induced voltage and current
offsets. The TMUX622x has a typical on-leakage current of 100 pA which would lead to an accuracy well within
1% of a full scale 1 µA signal, thus minimizing errors from current offsets. The low on-resitance of the
TMUX622x leads to a low error in the feedback resistance and resulting gain. This additionally minimizes any
voltage offsets.
表9-2. Programable Gain and Error
SEL1
SEL2
Gain
10x
5x
Gain Error
0%
0
1
0
0
0
1
0.13%
0.16%
2x
9.2.1.3 Application Curves
The TMUX622x is capable of switching signals with minimal distortion because of the ultra-low leakage currents
and excellent on-resistance flatness. 图9-2 shows how the on-resistance for the TMUX622x varies with different
supply voltages.
TA = 25°C
图9-2. On-Resistance vs Source or Drain Voltage
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9.3 Power Supply Recommendations
The TMUX622x operates across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply
mode). The device also performs well with asymmetrical supplies such as VDD = 12 V and VSS = –5 V.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the
VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as
possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)
that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply
decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use
of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple
vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes.
Always ensure the ground (GND) connection is established before supplies are ramped.
9.4 Layout
9.4.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 9-3 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图9-3. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Some key considerations are:
• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and
GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as
possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground
planes.
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9.4.2 Layout Example
S1
S2
D1
D2
TMUX622x
NC
VSS
SEL1
SEL2
GND
VDD
Wide (low inductance)
trace for power
C
C
Wide (low inductance)
trace for power
Via to ground plane
图9-4. TMUX622x Layout Example
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment.
• Texas Instruments, Multiplexers and Signal Switches Glossary.
• Texas Instruments, QFN/SON PCB Attachment.
• Texas Instruments, Quad Flatpack No-Lead Logic Packages.
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
• Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PTMUX6221DGSR
PTMUX6222DGSR
VSSOP
VSSOP
DGS
DGS
10
10
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
2500
2500
Length (mm) Width (mm)
Height (mm)
50.0
PTMUX6221DGSR
PTMUX6222DGSR
VSSOP
VSSOP
DGS
DGS
10
10
366.0
366.0
364.0
364.0
50.0
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11.2 Mechanical Data
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
10
SYMM
6
5
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
1
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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5-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTMUX6221DGSR
PTMUX6222DGSR
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
2500
2500
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2023
Addendum-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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