TMUX8213 [TI]

TMUX821x 100-V, Flat Ron, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8-V Logic;


型号：	TMUX8213
厂家：	TEXAS INSTRUMENTS
描述：	TMUX821x 100-V, Flat Ron, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8-V Logic
文件：	总32页 (文件大小：1266K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMUX8212

SCDS434A – OCTOBER 2021 – REVISED DECEMBER 2021

TMUX821x 100-V, Flat Ron, 1:1 (SPST), 4-Channel Switches

with Latch-Up Immunity and 1.8-V Logic

1 Features

3 Description

•

High supply voltage capable:

The TMUX8211, TMUX8212, and TMUX8213 are

modern high voltage capable analog switches

with latch-up immunity. Each device has four

independently controllable 1:1, single-pole single-

throw (SPST) switch channels. The devices work well

with dual supplies, a single supply, or asymmetric

supplies up to a maximum supply voltage of 100 V.

The TMUX821x devices provide consistent analog

parametric performance across the entire supply

voltage range. The TMUX821x family supports

bidirectional analog and digital signals on the source

(Sx) and drain (Dx) pins.

– Dual supply: ±10 V to ±50 V

– Single supply: 10 V to 100 V

– Asymmetric dual supply operation

Consistent parametrics across supply voltages

Latch-up immune

High continuous current: 200 mA

Low crosstalk: –110 dB

Low input leakage: 10 pA

Low on-resistance flatness: 0.05 Ω

Low on-resistance: 5 Ω

Low capacitance: 12 pF

Removes need for additional logic rail (V_L)

1.8-V Logic capable

Fail-safe logic: up to 48 V independent of supply

Integrated pull-down resistor on logic pins

Bidirectional signal path

•

All logic inputs support logic levels of 1.8 V, 3.3 V, and

5 V and can be connected as high as 48 V, allowing

for system flexibility with control signal voltage. Fail-

safe logic circuitry allows voltages on the logic pins to

be applied before the supply pin, protecting the device

from potential damage.

Wide operating temperature T_A: –40°C to 125°C

Industry-standard TSSOP and

smaller WQFN packages

The device family provides latch-up immunity,

preventing undesirable high current events between

parasitic structures within the device. A latch-up

condition typically continues until the power supply

rails are turned off and can lead to device failure.

The latch-up immunity feature allows this family of

multiplexers to be used in harsh environments.

2 Applications

•

High voltage bidirectional switching

Analog and digital signal switching

Semiconductor test equipment

LCD test equipment

Battery test equipment

Data acquisition systems (DAQ)

Digital multi-meter (DMM)

Factory automation and control

Programmable logic controllers (PLC)

Analog input modules

Device Information⁽¹⁾

PART NUMBER

PACKAGE

TSSOP (16)

WQFN (16)⁽²⁾

BODY SIZE (NOM)

TMUX8211

TMUX8212

TMUX8213

5.00 mm × 4.40 mm

4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) Preview package.

SEL1

SEL2

SEL3

SEL4

SEL1

SEL2

SEL3

SEL1

SEL2

SEL3

SEL4

TMUX8211

TMUX8212

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT

TMUX8213

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMUX8212

www.ti.com

SCDS434A – OCTOBER 2021 – REVISED DECEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings: TMUX821x Devices...... 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions:

8.5 Charge Injection........................................................19

8.6 Off Isolation...............................................................19

8.7 Crosstalk...................................................................20

8.8 Bandwidth................................................................. 20

8.9 THD + Noise............................................................. 21

9 Detailed Description......................................................22

9.1 Overview...................................................................22

9.2 Functional Block Diagram.........................................22

9.3 Feature Description...................................................22

9.4 Device Functional Modes..........................................24

10 Application and Implementation................................25

10.1 Application Information........................................... 25

10.2 Typical Application.................................................. 25

11 Power Supply Recommendations..............................27

12 Layout...........................................................................28

12.1 Layout Guidelines................................................... 28

12.2 Layout Example...................................................... 28

13 Device and Documentation Support..........................29

13.1 Documentation Support.......................................... 29

13.2 Receiving Notification of Documentation Updates..29

13.3 Support Resources................................................. 29

13.4 Trademarks.............................................................29

13.5 Electrostatic Discharge Caution..............................29

13.6 Glossary..................................................................29

14 Mechanical, Packaging, and Orderable

TMUX821x Devices.......................................................5

7.4 Thermal Information....................................................5

7.5 Electrical Characteristics (Global): TMUX821x

Devices..........................................................................6

7.6 Electrical Characteristics (±15-V Dual Supply)........... 6

7.7 Electrical Characteristics (±36-V Dual Supply)........... 7

7.8 Electrical Characteristics (±50-V Dual Supply)........... 8

7.9 Electrical Characteristics (72-V Single Supply)...........9

7.10 Electrical Characteristics (100-V Single Supply).....10

7.11 Switching Characteristics: TMUX821x Devices.......11

7.12 Typical Characteristics............................................12

8 Parameter Measurement Information..........................17

8.1 On-Resistance.......................................................... 17

8.2 Off-Leakage Current................................................. 17

8.3 On-Leakage Current................................................. 18

8.4 Device Turn-On and Turn-Off Time...........................18

Information.................................................................... 29

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (October 2021) to Revision A (December 2021)

Page

•

Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1

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5 Device Comparison Table

PRODUCT

TMUX8211

TMUX8212

TMUX8213

DESCRIPTION

High Voltage, 4-channel, 1:1 (SPST) switches, (Logic Low)

High Voltage, 4-channel, 1:1 (SPST) switches, (Logic High)

High Voltage, 4-channel, 1:1 (SPST) switches, (Logic Low + Logic High)

6 Pin Configuration and Functions

SEL1

SEL2

SEL3

N.C.

SEL1

GND

SEL4

Thermal

Pad

GND

SEL4

N.C.

SEL3

Not to scale

Figure 6-1. PW Package

16-Pin TSSOP

Figure 6-2. RUM Package (Preview)

16-Pin WQFN

Top View

Table 6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

TSSOP

WQFN⁽²⁾

I/O

Source pin 1. Can be an input or output.

Drain pin 1. Can be an input or output.

Logic control input 1.

SEL1

Negative power supply. This pin is the most negative power-supply potential. In single-supply

applications, this pin can be connected to ground. For reliable operation, connect a decoupling

capacitor ranging from 1 µF to 10 µF between V_SSand GND.

V_SS

GND

SEL4

Ground (0 V) reference

Logic control input 4.

I/O

Drain pin 4. Can be an input or output.

Source pin 4. Can be an input or output.

Source pin 3. Can be an input or output.

Drain pin 3. Can be an input or output.

Logic control input 3.

SEL3

N.C.

—

No internal connection.

Positive power supply. This pin is the most positive power-supply potential. For reliable operation,

connect a decoupling capacitor ranging from 1 µF to 10 µF between V_DDand GND.

V_DD

SEL2

Logic control input 2.

I/O

Drain pin 2. Can be an input or output.

Source pin 2. Can be an input or output.

The thermal pad is not connected internally. It is recommended that the pad be tied to GND or V_SS

for best performance.

Thermal Pad

—

(1) I = input, O = output, I/O = input and output, P = power

(2) Preview package.

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7 Specifications

7.1 Absolute Maximum Ratings: TMUX821x Devices

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

110

0.5

UNIT

V_DD–V_SS

V_DD

Supply voltage

–0.5

–110

–0.5

–30

V_SS

V_SELx

I_SELx

V_Sor V_D

I_DC

Logic control input pin voltage (SELx)

Logic control input pin current (SELx)

Source or drain voltage (Sx, Dx)

Source or drain continuous current (Sx, Dx)

Diode clamp current at 85°C

Diode clamp current at 125°C

Storage temperature

V_SS–2

–200

–100

–15

V_DD+2

200

100

°C

(2)

I_IK

T_stg

T_A

–65

150

1680

720

Ambient temperature

–55

°C

T_J

Junction temperature

°C

(3)

P_tot

Total power dissipation (QFN)

Total power dissipation (TSSOP)

(4)

P_tot

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not

sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,

performance, and shorten the device lifetime.

(2) Signal path pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum

ratings.

(3) For QFN package: P_totderates linearly above T_A= 70°C by 24.0 mW/°C

(4) For TSSOP package: P_totderates linearly above T_A= 70°C by 10.5 mW/°C

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins⁽²⁾

V_(ESD)Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions: TMUX821x Devices

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

100

V_DD

UNIT

(1)

V_DD– V_SS

V_DD

Power supply voltage differential

Positive power supply voltage

(2)

V_Sor V_D

V_SEL

Signal path input/output voltage (source or drain pin)

Logic input pin voltage

V_SS

T_A

Ambient temperature

–40

125

200

190

100

185

125

°C

I_DC1ch.⁽³⁾

Continuous current through switch for TSSOP or QFN on 1 channel

T_A= 25°C

Continuous current through switch on all channels at the

same time, QFN package

I_DCAll ch.⁽⁴⁾

T_A= 85°C

T_A= 125°C

T_A= 25°C

T_A= 85°C

T_A= 125°C

Continuous current through switch on all channels at the

same time, TSSOP package

I_DCAll ch.⁽⁴⁾

(1) V_DDand V_SScan be any value as long as 10 V ≤ (V_DD– V_SS) ≤ 100 V, and the minimum V_DDis met.

(2) V_Sor V_Dis the voltage on any Source or Drain pins.

(3) Max continuous current shown for a single channel at a time.

(4) Max continuous current shown for all channels at a time. Refer to max power dissipation (P_tot) to ensure package limitations are not

violated.

7.4 Thermal Information

TMUX821x

PW (TSSOP)

16 PINS

96.0

TMUX821x

RUM (WQFN)

16 PINS

41.6

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

26.8

25.3

42.7

16.0

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.2

0.3

Ψ_JB

42.0

16.0

R_θJC(bot)

N/A

3.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics (Global): TMUX821x Devices

over operating free-air temperature range (unless otherwise noted)

typical at V_DD= +36 V, V_SS= –36 V, GND = 0 V and T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

LOGIC INPUTS

V_IH

V_IL

I_IH

Logic voltage high

–40°C to +125°C

1.3

0.8

3.8

Logic voltage low

Input leakage current

Logic input capacitance

Logic inputs = 0 V, 5 V, or 48 V

0.4

µA

I_IL

–0.2 –0.005

C_IN

POWER SUPPLY

25°C

350

800

900

800

900

µA

I_DD

V_DDsupply current

Logic inputs = 0 V, 5 V, or 48 V

–40°C to +85°C

–40°C to +125°C

25°C

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

7.6 Electrical Characteristics (±15-V Dual Supply)

V_DD= +15 V ± 10%, V_SS= –15 V ± 10%, GND = 0 V (unless otherwise noted)

Typical at T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

V_S= –10 V to +10 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.2

0.3

0.4

0.5

On-resistance mismatch between V_S= –10 V to +10 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

channels

I_D= –10 mA

V_S= –10 V to +10 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

25°C

0.07

V_S= 0 V, I_S= –10 mA

–40°C to +125°C

25°C

0.03

0.01

Ω/°C

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

–4

I_S(OFF)

–40

V_D= –10 V / +10 V

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

0.01

–40°C to +85°C

–40°C to +125°C

25°C

–4

I_D(OFF)

–40

V_D= –10 V / +10 V

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

25°C

–1

–2

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

ΔI_S(ON)

ΔI_D(ON)

Leakage current mismatch

between channels⁽²⁾

85°C

125°C

120

(1) When V_Sis positive,V_Dis negative. And when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating. And when V_Dis at a voltage potential, V_Sis floating.

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7.7 Electrical Characteristics (±36-V Dual Supply)

V_DD= +36 V ± 10%, V_SS= –36 V ± 10%, GND = 0 V (unless otherwise noted)

Typical at T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

V_S= –25 V to +25 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.1

0.3

0.4

0.5

On-resistance mismatch between V_S= –25 V to +25 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

channels

I_D= –10 mA

V_S= –25 V to +25 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

25°C

0.12

V_S= 0 V, I_S= –10 mA

–40°C to +125°C

25°C

0.03

0.01

Ω/°C

V_DD= 39.6 V, V_SS= –39.6 V

Switch state is off

V_S= +25 V / –25 V

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

–4

I_S(OFF)

–40

V_D= –25 V / +25 V

V_DD= 39.6 V, V_SS= –39.6 V

Switch state is off

V_S= +25 V / –25 V

0.01

–40°C to +85°C

–40°C to +125°C

25°C

–4

I_D(OFF)

–40

V_D= –25 V / +25 V

V_DD= 39.6 V, V_SS= –39.6 V

Switch state is on

V_S= V_D= ±25 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

25°C

–1

–2

V_DD= 39.6 V, V_SS= –39.6 V

Switch state is on

V_S= V_D= ±25 V

ΔI_S(ON)

ΔI_D(ON)

Leakage current mismatch

between channels⁽²⁾

85°C

125°C

120

(1) When V_Sis positive,V_Dis negative. And when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating. And when V_Dis at a voltage potential, V_Sis floating.

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7.8 Electrical Characteristics (±50-V Dual Supply)

V_DD= +50 V, V_SS= –50 V, GND = 0 V (unless otherwise noted)

Typical at T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

V_S= –45 V to 45 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.2

0.3

0.4

0.5

On-resistance mismatch between V_S= –45 V to 45 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

channels

I_D= –10 mA

V_S= –45 V to 45 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

25°C

0.13

V_S= 0 V, I_S= –10 mA

–40°C to +125°C

25°C

0.03

0.01

Ω/°C

V_DD= 50 V, V_SS= –50 V

Switch state is off

V_S= +45 V / –45 V

V_D= –45 V / +45 V

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

–4

I_S(OFF)

–40

V_DD= 50 V, V_SS= –50 V

Switch state is off

V_S= +45 V / –45 V

V_D= –45 V / +45 V

0.01

–40°C to +85°C

–40°C to +125°C

25°C

–4

I_D(OFF)

–40

V_DD= 50 V, V_SS= –50 V

Switch state is on

V_S= V_D= ±45 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

25°C

–2

–5

V_DD= 50 V, V_SS= –50 V

Switch state is on

V_S= V_D= ±45 V

ΔI_S(ON)

ΔI_D(ON)

Leakage current mismatch

between channels⁽²⁾

85°C

125°C

220

(1) When V_Sis positive,V_Dis negative. And when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating. And when V_Dis at a voltage potential, V_Sis floating.

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7.9 Electrical Characteristics (72-V Single Supply)

V_DD= +72 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

V_S= 0 V to 60 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.2

0.3

0.4

0.5

On-resistance mismatch between V_S= 0 V to 60 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

channels

I_D= –10 mA

V_S= 0 V to 60 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

25°C

0.05

V_S= 0 V, I_S= –10 mA

–40°C to +125°C

25°C

0.03

0.01

Ω/°C

Switch state is off

V_S= +60 V / 1 V

V_D= 1 V / +60 V

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

–4

–40

0.01

Switch state is off

V_S= +60 V / 1 V

V_D= 1 V / +60 V

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

–4

–40

I_S(ON)

I_D(ON)

Switch state is on

V_S= V_D= 1 V / +60 V

–40°C to +85°C

–40°C to +125°C

25°C

–2

–5

ΔI_S(ON)

ΔI_D(ON)

Leakage current mismatch

between channels⁽²⁾

Switch state is on

V_S= V_D= 1 V / +60 V

85°C

125°C

300

(1) When V_Sis 60 V, V_Dis 1 V. Or when V_Sis 1 V, V_Dis 60 V.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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7.10 Electrical Characteristics (100-V Single Supply)

V_DD= +100 V, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

V_S= 0 V to +95 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.2

0.3

0.4

0.5

On-resistance mismatch between V_S= 0 V to +95 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

channels

I_D= –10 mA

V_S= 0 V to +95 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

25°C

0.07

V_S= 50 V, I_S= –10 mA

–40°C to +125°C

25°C

0.03

0.01

Ω/°C

Switch state is off

V_S= +95 V / 1 V

V_D= 1 V / +95 V

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

–4

–40

0.01

Switch state is off

V_S= +95 V / 1 V

V_D= 1 V / +95 V

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

–4

–40

I_S(ON)

I_D(ON)

Switch state is on

V_S= V_D= 1 V / +95 V

–40°C to +85°C

–40°C to +125°C

25°C

–4

–10

100

450

ΔI_S(ON)

ΔI_D(ON)

Leakage current mismatch

between channels⁽²⁾

Switch state is on

V_S= V_D= 1 V / +95 V

85°C

125°C

(1) When V_Sis 95 V, V_Dis 1 V. Or when V_Sis 1 V, V_Dis 95 V.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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7.11 Switching Characteristics: TMUX821x Devices

over operating free-air temperature range (unless otherwise noted)

typical at V_DD= +36 V, V_SS= –36 V, GND = 0 V and T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

V_S= 10 V

R_L= 10 kΩ, C_L= 15 pF

t_ON

Turn-on time from enable

–40°C to +85°C

–40°C to +125°C

25°C

µs

(EN)

100

V_S= 10 V

R_L= 10 kΩ, C_L= 15 pF

t_OFF

Turn-off time from enable

–40°C to +85°C

–40°C to +125°C

600

700

µs

V_DDramp rate = 1 V/µs,

V_S= 10 V

R_L= 10 kΩ, C_L= 15pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

25°C

t_PD

Propagation delay

Charge injection

R_L= 50 Ω , C_L= 5 pF

25°C

190

Q_INJ

V_S= (V_DD+ V_SS) / 2, C_L= 1 nF

–1.3

R_L= 50 Ω , C_L= 5 pF

V_S= (V_DD+ V_SS) / 2, f = 100 kHz

O_ISO

X_TALK

I_L

Off isolation

25°C

–110

420

R_L= 50 Ω , C_L= 5 pF

V_S= (V_DD+ V_SS) / 2, f = 100 kHz

Inter-channel crosstalk

–3dB bandwidth

Insertion loss

R_L= 50 Ω , C_L= 5 pF

V_S= (V_DD+ V_SS) / 2

MHz

R_L= 50 Ω , C_L= 5 pF

V_S= (V_DD+ V_SS) / 2, f = 1 MHz

–0.4

Dual supply voltage

V_PP= 5 V, V_BIAS= (V_DD+ V_SS) / 2

R_L= 1 kΩ , C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total harmonic distortion + Noise

25°C

0.0008

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= (V_DD+ V_SS) / 2 V, f = 1 MHz 25°C

C_S(ON),

C_D(ON)

On capacitance

V_S= (V_DD+ V_SS) / 2 V, f = 1 MHz 25°C

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7.12 Typical Characteristics

at T_A= 25°C, V_DD= +36 V, and V_SS= –36 V (unless otherwise noted)

T_A= 125C

T_A= 85C

T_A= 25C

T_A= -40C

-40

-30

-20

-10

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 36 V, V_SS= –36 V

Flatest Ron Region

V_DD= 36 V, V_SS= –36 V

Figure 7-1. On-Resistance vs Source or Drain Voltage

Figure 7-2. On-Resistance vs Source or Drain Voltage

160

150

T_A= 125C

V_DD/V_SS= ±39.6 V

V_DD/V_SS= ±36 V

V_DD/V_SS= ±32.4 V

V_DD/V_SS= ±16.5 V

V_DD/V_SS= ±15 V

V_DD/V_SS= ±13.5 V

140

130

120

110

100

T_A= 85C

T_A= 25C

T_A= -40C

140

120

100

-36

-28

-20

-12

-4

-40

-30

-20

-10

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 36 V, V_SS= –36 V

Dual Supply Voltages

Figure 7-3. On-Resistance vs Source or Drain Voltage

Figure 7-4. On-Resistance vs Source or Drain Voltage

160

T_A= 125C

T_A= 85C

T_A= 25C

T_A= -40C

T_A= 125C

T_A= 85C

T_A= 25C

T_A= -40C

140

120

100

-16

-12

-8

-4

-12

-8

-4

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 15 V, V_SS= –15 V

Figure 7-5. On-Resistance vs Source or Drain Voltage

Figure 7-6. On-Resistance vs Source or Drain Voltage

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7.12 Typical Characteristics (continued)

at T_A= 25°C, V_DD= +36 V, and V_SS= –36 V (unless otherwise noted)

160

140

120

100

T_A= 125C

T_A= 85C

T_A= 25C

T_A= −40C

T_A= 125C

T_A= 85C

T_A= 25C

T_A= −40C

10 15 20 25 30 35 40 45 50 55 60 65 70 75

V_Sor V_D- Source or Drain Voltage (V)

10 15 20 25 30 35 40 45 50 55 60 65 70 75

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 72 V, V_SS= 0 V

Figure 7-7. On-Resistance vs Source or Drain Voltage

Figure 7-8. On-Resistance vs Source or Drain Voltage

160

T_A= 125C

T_A= 85C

T_A= 25C

T_A= -40C

T_A= 85C

140

120

100

T_A= 25C

T_A= -40C

90 100

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 100 V, V_SS= 0 V

Figure 7-9. On-Resistance vs Source or Drain Voltage

Figure 7-10. On-Resistance vs Source or Drain Voltage

100

I_D(OFF)V_S/V_D: -25V/25V

I_D(OFF)V_S/V_D: 25V-25V

I_S(OFF)V_S/V_D: -25V/25V

I_S(OFF)V_S/V_D: 25V/-25V

I_(ON)V_S= V_D= -25V

I_(ON)V_S= V_D= 25V

I_D(OFF)V_S/V_D: -25V/25V

I_D(OFF)V_S/V_D: 25V-25V

I_S(OFF)V_S/V_D: -25V/25V

I_S(OFF)V_S/V_D: 25V/-25V

I_(ON)V_S= V_D= -25V

I_(ON)V_S= V_D= 25V

0.1

0.01

-2

0.001

100

120

100

120

Temperature (C)

V_DD= 36 V, V_SS= –36 V

Figure 7-11. Leakage Current vs Temperature

V_DD= 36 V, V_SS= –36 V

Figure 7-12. Leakage Current vs Temperature

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7.12 Typical Characteristics (continued)

at T_A= 25°C, V_DD= +36 V, and V_SS= –36 V (unless otherwise noted)

100

I_D(OFF)V_S/V_D: 1V/60V

I_D(OFF)V_S/V_D: 60V/1V

I_S(OFF)V_S/V_D: 1V/60V

I_S(OFF)V_S/V_D: 60V/1V

I_(ON)V_S= V_D= 1V

I_D(OFF)V_S/V_D: 1V/95V

I_D(OFF)V_S/V_D: 95V/1V

I_S(OFF)V_S/V_D: 1V/95V

I_S(OFF)V_S/V_D: 95V/1V

I_(ON)V_S= V_D= 1V

I_(ON)V_S= V_D= 60V

I_(ON)V_S= V_D= 95V

0.1

0.01

0.001

100

120

140

100

120

Temperature (C)

V_DD= 72 V, V_SS= 0 V

V_DD= 100 V, V_SS= 0 V

Figure 7-13. Leakage Current vs Temperature

Figure 7-14. Leakage Current vs Temperature

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

T_A= 125C

T_A= 85C

T_A= 25C

T_A= 125C

T_A= 85C

T_A= 25C

-5

-36

-28

-20

-12

-4

-36

-28

-20

-12

-4

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 36 V, V_SS= –36 V

I_S(OFF)and I_D(OFF)

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 36 V, V_SS= –36 V

I_ON

Figure 7-15. Off-Leakage Current vs Source or Drain Voltage

Figure 7-16. On-Leakage Current vs Source or Drain Voltage

0.7

T_A= 125C

T_A= 85C

T_A= 25C

T_A= 125C

0.6

0.5

0.4

0.3

0.2

0.1

T_A= 85C

T_A= 25C

-0.1

-0.2

-0.3

-0.4

-5

-36

10 15 20 25 30 35 40 45 50 55 60 65 70 75

V_Sor V_D- Source or Drain Voltage (V)

-28

-20

-12

-4

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 72 V, V_SS= 0 V

Figure 7-18. On-Leakage Current vs Source or Drain Voltage

Figure 7-17. Off-Leakage Current vs Source or Drain Voltage

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7.12 Typical Characteristics (continued)

at T_A= 25°C, V_DD= +36 V, and V_SS= –36 V (unless otherwise noted)

T_A= 125C

T_A= 85C

T_A= 25C

-5

90 100

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 100 V, V_SS= 0 V

I_S(OFF)and I_D(OFF)

V_DD= 100 V, V_SS= 0 V

I_ON

Figure 7-19. Off-Leakage Current vs Source or Drain Voltage

Figure 7-20. On-Leakage Current vs Source or Drain Voltage

400

375

350

325

T_A= 125C

-0.2

-0.4

-0.6

-0.8

-1

T_A= 85C

T_A= 25C

T_A= −40C

300

V_DD/V_SS: 72V/0V - All Channels Enabled

V_DD/V_SS: ±36V - All Channels Enabled

V_DD/V_SS: 72V/0V - All Channels Disabled

275

250

V_DD/V_SS: ±36V - All Channels Disabled

225

-1.2

-1.4

-1.6

-1.8

200

175

150

125

20 30 40 50 60 70 80 90 100 110 120 130

-36

-28

-20

-12

-4

Temperature (C)

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 36 V, V_SS= –36 V

Figure 7-22. Supply Current vs Temperature

Figure 7-21. Charge Injection vs Source Voltage

T_(ON)

T_(OFF)

V_DD/V_SS: ±36V

-10

V_DD/V_SS: 72V/0V

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

100

10k

100k

Frequency (Hz)

10M 100M 1G

-36

-28

-20

-12

-4

V_Sor V_D- Source or Drain Voltage (V)

T_A= 25°C

V_DD= 36 V, V_SS= –36 V

Figure 7-24. Off Isolation vs Frequency

Figure 7-23. Turn-On and Turn-Off Times vs Source Voltage

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7.12 Typical Characteristics (continued)

at T_A= 25°C, V_DD= +36 V, and V_SS= –36 V (unless otherwise noted)

V_DD/V_SS: ±36V - Adjacent

V_DD/V_SS: ±36V - Non-Adjacent

V_DD/V_SS: 72V/0V - Adjacent

-10

-20

-30

-40

V_DD/V_SS: 72V/0V - Non-Adjacent

-50

-60

-70

-80

-90

-100

-110

-120

-130

100

10k

100k

10M 100M 1G

Frequency (Hz)

T_A= 25°C

Bandwidth

Figure 7-25. Crosstalk vs Frequency

Figure 7-26. Insertion Loss vs Frequency

0.005

V_DD/V_SS: ±15V

V_PP: 5V

R_L= 1k

V_DD/V_SS: ±36V

V_PP: 5V

R_L: 1k

V_PP: 2V

R_L: 50

0.004

0.003

0.002

0.001

100

10k

Frequency (Hz)

T_A= 25°C

Figure 7-27. THD+N vs Frequency

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8 Parameter Measurement Information

8.1 On-Resistance

The on-resistance of the TMUX821x is the ohmic resistance across the source (Sx) and drain (Dx) pins of

the device. The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote

on-resistance. Figure 8-1 shows the measurement setup used to measure R_ON. ΔR_ONrepresents the difference

between the R_ONof any two channels, while R_{ON_FLAT}denotes the flatness that is defined as the difference

between the maximum and minimum value of on-resistance measured over the specified analog signal range.

V_DD

V_SS

4₁₀

V_DD

V_SS

I_S

V_S

GND

Figure 8-1. On-Resistance Measurement Setup

8.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:

1. Source off-leakage current I_S(OFF): the leakage current flowing into or out of the source pin when the switch

is off.

2. Drain off-leakage current I_D(OFF): the leakage current flowing into or out of the drain pin when the switch is

off.

Figure 8-2 shows the setup used to measure both off-leakage currents.

V_DD

V_SS

V_DD

V_SS

I_{s (OFF)}

I_{D (OFF)}

V_D

V_S

GND

I_{D (OFF)}

I_{s (OFF)}

V_D

V_S

GND

I_S(OFF)

I_D(OFF)

Figure 8-2. Off-Leakage Measurement Setup

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8.3 On-Leakage Current

Source on-leakage current (I_S(ON)) and drain on-leakage current (I_D(ON)) denote the channel leakage currents

when the switch is in the on state. I_S(ON)is measured with the drain floating, while I_D(ON)is measured with the

source floating. Figure 8-3 shows the circuit used for measuring the on-leakage currents.

V_DD

V_SS

V_DD

V_SS

I_{s (OFF)}

I_{D (OFF)}

N.C. N.C.

V_S

GND

I_{s (OFF)}

I_{D (OFF)}

N.C. N.C.

V_S

GND

I_S(ON)

I_D(ON)

Figure 8-3. On-Leakage Measurement Setup

8.4 Device Turn-On and Turn-Off Time

Turn-on time (t_ON) is defined as the time taken by the output of the TMUX8211, TMUX8212, and TMUX8213

to rise to a 90% final value after the SELx signal has risen (for NC switches) or fallen (for NO switches) to a

50% final value. Turn off time (t_OFF) is defined as the time taken by the output of the TMUX8211, TMUX8212,

and TMUX8213 to fall to a 10% initial value after the SELx signal has fallen (for NC switches) or risen (for NO

switches) to a 50% initial value. Figure 8-4 shows the setup used to measure t_ONand t_OFF

V_DD

V_SS

0.1 µF

Output

0.1 µF

3 V

V_DD

V_SS

GND

t_r< 20 ns

t_f< 20 ns

50%

V_SEL

0 V

V_S

R_L

C_L

SELx

0.9

t_OFF

0.1

GND

t_ON

Output

GND

V_SEL

GND

Figure 8-4. Enable Delay Measurement Setup

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8.5 Charge Injection

Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during

switching, and is denoted by the symbol Q_INJ. Figure 8-5 shows the setup used to measure charge injection from

the source to drain.

V_DD

V_SS

0.1 µF

GND

0.1 µF

GND

V_DD

V_SS

Output

3 V

V_SELx

0 V

t_r< 20 ns

t_f< 20 ns

C_L

V_S

GND

Output

C_L

Output

V_S

V_OUT

Q_INJ= C_L×

V_OUT

V_S

SELx

GND

V_SELx

GND

Figure 8-5. Charge-Injection Measurement Setup

8.6 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to

the source pin (Sx) of an off-channel. The characteristic impedance, Z_O, for the measurement is 50 Ω. Figure 8-6

shows the setup used to measure off isolation.

V_DD

V_SS

0.1 µF

GND

0.1 µF

V_DD

V_SS

Network Analyzer

GND

S_X

V_OUT

R_S

V_S

50Ω

SELx

Other

Sx/ Dx

pins

V_SELx

GND

50Ω

8₁₇₆

1BB +OKH=PEKJ = 20 × .KC

Figure 8-6. Off Isolation Measurement Setup

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8.7 Crosstalk

Crosstalk (X_TALK) is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is

applied at the source pin (Sx) of an on-channel. The characteristic impedance, Z_O, for the measurement is 50 Ω,

as shown in Figure 8-7.

V_DD

V_SS

0.1 µF

GND

0.1 µF

V_DD

V_SS

Network Analyzer

GND

S_X

S_Y

D_X

D_Y

50Ω

R_S

V_OUT

Other

Sx/ Dx

pins

50Ω

V_S

50Ω

INx

V_INx

GND

8₁₇₆

+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC

Figure 8-7. Inter-channel Crosstalk Measurement Setup

8.8 Bandwidth

Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx). Figure 8-8 shows the

setup used to measure bandwidth of the switch.

V_DD

V_SS

0.1 µF

GND

0.1 µF

V_DD

V_SS

Network Analyzer

GND

S_X

V_OUT

R_S

Other

Sx/ Dx

pins

V_S

50Ω

SELx

V_SELx

50Ω

GND

8₁₇₆

$=J@SE@PD = 20 × .KC

Figure 8-8. Bandwidth Measurement Setup

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8.9 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as

the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at

the multiplexer output. The on-resistance of the device varies with the amplitude of the input signal and results

in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is

denoted as THD+N. Figure 8-9 shows the setup used to measure THD+N of the devices.

V_DD

V_SS

0.1 µF

GND

0.1 µF

V_DD

V_SS

Audio Precision

GND

S_X

R_S

V_OUT

V_S

R_L

Other

Sx/ Dx

pins

SELx

V_SELX

GND

50Ω

Figure 8-9. THD+N Measurement Setup

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9 Detailed Description

9.1 Overview

The TMUX8211, TMUX8212 and TMUX8213 are a modern complementary metal-oxide semiconductor (CMOS)

analog switches in quad single-pole single-throw configuration. The devices work well with dual supplies, a

single supply, or asymmetric supplies.

9.2 Functional Block Diagram

SEL1

SEL2

SEL3

SEL4

SEL1

SEL2

SEL3

SEL4

SEL1

SEL2

SEL3

SEL4

TMUX8211

TMUX8212

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT

TMUX8213

9.3 Feature Description

9.3.1 Bidirectional Operation

The devices conduct equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each signal

path has similar characteristics in both directions.

9.3.2 Flat On-Resistance

The TMUX821x devices are designed with a special switch architecture to produce ultra-flat on-resistance

(R_ON) across most of the switch input operating region. The flat R_ONresponse allows the device to be used in

precision sensor applications since the R_ONis controlled regardless of the signals sampled. The architecture

is implemented without a charge pump so no unwanted noise is produced from the device to affect sampling

accuracy.

The flatest on-resistance region extends from V_SSto roughly 5 V below V_DD. Once the signal is within 5 V of V_DD

the on-resistance will expoentially increase and may impact desired signal transmission.

9.3.3 Protection Features

These devices offer a number of protection features to enable robust system implementations.

9.3.3.1 Fail-Safe Logic

Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting

the device from potential damage. Additionaly the fail safe logic feature allows the logic inputs of the mux to be

interfaced with high voltages, allowing for simplified interfacing if only high voltage control signals are present.

The logic inputs are protected against positive faults of up to +48 V in powered-off condition, but do not offer

protection against negative overvoltage condition.

Fail-safe logic also allows the devices to interface with a voltage greater than V_DDon the control pins during

normal operation to add maximum flexibility in system design. For example, with a V_DD= 15 V, the logic control

pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog

feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic

inputs can be interfaced as high as 48 V.

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9.3.3.2 ESD Protection

All pins support HBM ESD protection level up to ±2 kV, which helps protect the devices from ESD events during

the manufacturing process.

9.3.3.3 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the

low impedance path.

In the TMUX821x devices, an insulating oxide layer is placed on top of the silicon substrate to prevent any

parasitic junctions from forming. As a result, the devices are latch-up immune under all circumstances by device

construction.

The TMUX821x devices are constructed on silicon on insulator (SOI) based process where an oxide layer is

added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from

forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due

to overvoltage or current injections. The latch-up immunity feature allows the TMUX821x to be used in harsh

environments. For more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help

Improve System Reliability.

9.3.4 1.8 V Logic Compatible Inputs

The TMUX821x devices have 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs

allows the TMUX821x to interface with processors that have lower logic I/O rails and eliminates the need for an

external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations

refer to Simplifying Design with 1.8 V logic Muxes and Switches.

9.3.5 Integrated Pull-Down Resistor on Logic Pins

The TMUX821x have internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The

value of this pull-down resistor is approximately 4 MΩ, but is clamped to 1 µA at higher voltages. This feature

integrates up to four external components and reduces system size and cost.

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9.4 Device Functional Modes

9.4.1 Normal Mode

In Normal Mode operation, signals of up to V_DDand V_SScan be passed through the switch from source (Sx)

to drain (Dx) or from drain (Dx) to source (Sx). The select (SELx) pins determine which switch path to turn on,

according to the Truth Table. The following conditions must be satisfied for the switch to stay in the ON condition:

•

The difference between the primary supplies (V_DD– V_SS) must be greater than or equal to 10 V. With a

minimum V_DDof 10 V.

•

The input signals on the source (Sx) or the drain (Dx) must be be between V_DDand V_SS.

The logic control (SELx) must have selected the switch.

9.4.2 Truth Tables

Table 9-1, Table 9-2, and Table 9-3 show the truth tables for the TMUX8211, TMUX8212, and TMUX8213,

respectively.

Table 9-1. TMUX8211 Truth Table

SEL #⁽¹⁾

CHANNEL #

Channel # ON

Channel # OFF

(1) "#"designates the channel number controlled by SEL pin: "1, 2,

3, or 4"

Table 9-2. TMUX8212 Truth Table

SEL #⁽¹⁾

CHANNEL #

Channel # OFF

Channel # ON

(1) "#"designates the channel number controlled by SEL pin: "1, 2,

3, or 4"

Table 9-3. TMUX8213 Truth Table

SEL1 SEL2 SEL3 SEL4

ON / OFF CHANNELS

CHANNEL 1 ON

CHANNEL 1 OFF

CHANNEL 2 OFF

CHANNEL 2 ON

CHANNEL 3 OFF

CHANNEL 3 ON

CHANNEL 4 ON

CHANNEL 4 OFF

X⁽¹⁾

(1) "X" means "do not care."

If unused, SELx pins must be tied to GND or Logic High in order to ensure the device does not consume

additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx

or Dx) should be connected to GND for best performance.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The TMUX821x are high voltage switches capable of supporting analog and digital signals. The high voltage

capability of these multiplexers allow them to be used in systems with high voltage signal swings, or in systems

with high common mode voltages.

Additionally, the TMUX821x devices provide consistent analog parametric performance across the entire supply

voltage range allowing the devices to be powered by the most convient supply rails in the system while still

providing excellent performance.

10.2 Typical Application

A common feature of many PMUs (precision measurement units) is the ability to change current ranges. This

allows for a system defined current clamp when testing devices and reduces possible damage to the PMU and

DUT (device under test). In high voltage PMUs, large relays are often used to enable this switching, but this

comes with the trade-off of size. To reduce system size, a multi-channel high voltage switch can be added to

facilitate this switching with minimal impact to system size and performance. The TMUX821x allows for switching

between multiple current ranges, and has the added flexibility to use multiple channels in parallel for high current

applications.

^DDV_SS

Gain / Filter

Network

TMUX8212

10k

V_DD

DUT

DAC

High Voltage

Offset

V_SS

–

^DDV_SS

Gain / Filter

Network

TMUX8212

10k

V_DD

DUT

DAC

High Voltage

Offset

V_SS

–

Figure 10-1. TMUX8212 Application Schematic

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10.2.1 Design Requirements

Table 10-1. Design Parameters

PARAMETERS

Positive supply (V_DD) mux and Op Amps

Positive supply (V_SS) mux and Op Amps

Maximum input or output signals with common mode shift

Control logic thresholds

VALUES

36 V

-36 V

-36 V to 36 V

1.8 V compatible, up to 48 V

-40°C to +125°C

Temperature range

10.2.2 Detailed Design Procedure

Multiplexing PMU systems enables a small, flexible solution that can be used over a wide range of current

ranges. TI’s high voltage multiplexers offer a size advantage over typical relay solutions while still achieving an

extremely low level of distortion, noise, and leakage. This high voltage multiplexer can be use in tandem with

high voltage operational amplifiers and DACs to create an accurate PMU with excellent signal-to-noise ratio.

In this example application, the TMUX8212 is paired with a high voltage amplifier and a DAC. The DAC

generates an arbitrary voltage signal that feeds into the amplifier. An additional high voltage offset is also fed

into the amplifier to add any needed common mode shift. This arbitrary signal is then passed through a current

limiting resistor before reaching the DUT. To change the current range of the system, different current limiting

resistors are added in series with each channel of the multiplexer. In this example, the first channel of the

multiplexer uses a 10 kΩ resistor for the low current clamp. This ensures the maximum output current of the

PMU in this range is 5 mA. During the system operation, the PMU is set to this lower current range in the

beginning of the test routine. After the DUT is initially checked in this range and is operating normally with no

unexpected shorts, the current range can be switched to high current. This ensures that the PMU and DUT will

not be unnecessarily damaged from excess current due to a short. In this example, the remaining three channels

of the TMUX8212 are connected in parallel, increasing the maximum current through the device and reducing

the low on-resistance. Because of the flexibility of the TMUX8212, this could easily be modified to fit any system

need. For example, if less maximum current is needed, then two channels could be connected in parallel instead

of three, and the additional single channel could be used to add a third current range option. The additional input

channels make this multiplexed application increasingly valuable by greatly reducing solution size.

The TMUX821x switches have exceptionally flat on-resistance and low leakage currents across the signal

voltage range. The ultra-flat on-resistance ensures that the current clamp stays constant across the signal

voltage range, and the low leakage current reduces the potential noise/offset when measuring on the lowest

current range. Additionally, excellent crosstalk and off-isolation performance allows the TMUX821x devices

to perform well in multi-channel switching applications without having an unselected channel impact the

measurement on selected channels.

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10.2.3 Application Curves

The example application utilizes the excellent leakage and on-resistance flatness performance of the TMUX821x

devices. Figure 10-2 shows the leakage current for a channel that is ON across a varying source voltage. Figure

10-3 shows the extremely flat on-resistance across source voltage while operating within the flatest R_ONrange of

the TMUX821x devices. These features make the devices an ideal solution for applications that require excellent

linearity and low distortion.

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

T_A= 125C

T_A= 85C

T_A= 25C

T_A= 125C

T_A= 85C

T_A= 25C

T_A= -40C

-20 -10

-40

-36

-28

-20

-12

-4

-30

V_Sor V_D- Source or Drain Voltage (V)

Figure 10-2. On-Leakage

Figure 10-3. R_ONFlatness

11 Power Supply Recommendations

The TMUX821x devices operate across a wide supply range of ±10 V to ±50 V (10 V to 100 V in single-supply

mode). They also perform well with asymmetrical supplies such as V_DD= 50 V and V_SS= –10 V. For improved

supply noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at both the V_DDand V_SS

pins to ground. An additional 0.1 µF capacitor placed closest to the supply pins will provide the best supply

decoupling solution. Always ensure the ground (GND) connection is established before supplies are ramped.

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12 Layout

12.1 Layout Guidelines

The image below illustrates an example of a PCB layout with the TMUX821x device. Some key considerations

are:

•

For reliable operation, connect at least one decoupling capacitor ranging from 0.1 µF to 10 µF between V_DD

and V_SSto GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to

the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

Keep the input lines as short as possible.

Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

•

12.2 Layout Example

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

SEL2

VDD

SEL1

VSS

GND

SEL4

TMUX821x

N.C.

SEL3

Via to ground plane

Figure 12-1. TMUX821x TSSOP Layout Example

Via to ground plane

VSS

SEL1

GND

SEL4

SEL2

SEL3

N.C.

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

VDD

Figure 12-2. TMUX821x QFN Layout Example

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation, see the following:

•

Texas Instruments, Implications of Slow or Floating CMOS Inputs application note

Texas Instruments, Multiplexers and Signal Switches Glossary application report

Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application

report

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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28-Dec-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTMUX8212PWR

TMUX8212PWR

ACTIVE

TSSOP

2000

TBD

Call TI

-40 to 125

2000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

TM8212

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Dec-2021

Addendum-Page 2

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TMUX8213 [TI]

相关型号：

TMUX8213PWR

TMUX821X

TMUXHS221

TMUXHS221NKGR

TMUXHS221NKGT

TMUXHS4212

TMUXHS4212IRKSR

TMUXHS4212IRKST

TMUXHS4212RKSR

TMUXHS4212RKST

TMUXHS4412

TMUXHS4412I