TPA3221_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

TPA3221 100W 立体声 200W 单声道高清模拟输入 D 类放大器

1 特性

3 说明

1

•

7V 到 30V 宽电源电压操作

TPA3221 是一款可在全功率、空闲和待机状态下实现

高效操作的高功率 D 类放大器。该器件采用具有高达

100kHz 带宽的闭环反馈，从而在音频频带内提供低失

真并提供出色的质量。该器件以 AD 或低空闲电流

HEAD（高效 AD 模式）调制运行，并可为 4Ω 负载提

供 2 x 105W 的功率，或为 2Ω 负载提供 1 x 208W 功

率。

立体声 (2 x BTL) 和单声道 (1 x PBTL) 操作

THD+N 为 10% 时的输出功率

–

105W/4Ω，BTL 立体声配置

112W/3Ω，BTL 立体声配置

208W/2Ω，PBTL 单声道配置

•

THD+N 为 1% 时的输出功率

–

88W/4Ω，BTL 立体声配置

100W/3Ω，BTL 立体声配置

170W/2Ω，PBTL 单声道配置

TPA3221 具有单端或差分模拟输入接口，该接口最高

支持 2V_RMS并具有四种可选增益：18dB、24dB、

30dB 和 34dB。TPA3221 还实现了大于 90% 的效

率、低空闲功率 (<0.25 W) 和超低待机功耗 (<0.1

W)。这是通过使用 70mΩ MOSFET、经优化的栅极驱

动方案和低功耗操作模式实现的。TPA3221 包含用于

轻松集成在单电源系统中的内置 LDO。为了进一步简

化设计，该级器件集成了重要的保护功能，其中包括

欠压、过压、逐周期电流限制、短路、削波检测、过热

警告和关断以及直流扬声器保护。

•

用于可选单电源操作的 5V 栅极驱动器或内置 LDO

闭环反馈设计

–

高达 100kHz 的信号带宽，用于高清源的高频成

分

–

1W/4Ω 时的 THD+N 为 0.02%

PSRR 为 60dB（BTL，无输入信号）

输出噪声（A 加权）< 75µV

SNR（A 加权）> 108dB

器件信息⁽¹⁾

AD 或 HEAD 调制方案

器件型号

TPA3221

封装

封装尺寸（NOM）

•

低功耗操作模式

HTSSOP (44)

6.10mm x 14.00mm

–

待机模式：静音，< 1mA 关断

低空闲电流 HEAD 调制方案

单通道 BTL 操作

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

•

多输入操作，可简化前置放大器设计

–

差动或单端模拟输入

TPA322x

RIGHT

LEFT

LC Filter

可选增益：18dB、24dB、30dB、34dB

集成式保护：欠压、过压、逐周期电流限制、短

路、削波检测、过热警告和关断以及直流扬声器保

护

TAS5630

PBTL

Detect

Audio Source

And Control

OTW_CLIP

RESET

FAULT

CMUTE

VDD

AVDD

GVDD

•

90% 高效 D 类操作 (4Ω)

5V

散热垫位于封装的底部

Modulation Mode Select

Switching Frequency Select

Master/Slave Synchronization

HEAD

Power Supply

30V

FREQ_ADJ

OSCM/P

PVDD

具有电压和功率级别选项的引脚兼容系列器件

2 应用

110VAC->240VAC

•

蓝牙和 Wi-Fi™扬声器

条形音箱

低音炮

书架立体声系统

专业和公共广播 (PA) 扬声器和

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASEE9

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

9.1 Overview ................................................................. 15

9.2 Functional Block Diagrams ..................................... 16

9.3 Feature Description................................................. 18

9.4 Device Functional Modes........................................ 24

10 Application and Implementation........................ 30

10.1 Application Information.......................................... 30

10.2 Typical Applications .............................................. 30

11 Power Supply Recommendations ..................... 34

11.1 Power Supplies ..................................................... 34

12 Layout................................................................... 36

12.1 Layout Guidelines ................................................. 36

12.2 Layout Examples................................................... 37

13 器件和文档支持 ..................................................... 40

13.1 文档支持................................................................ 40

13.2 接收文档更新通知 ................................................. 40

13.3 社区资源................................................................ 40

13.4 商标....................................................................... 40

13.5 静电放电警告......................................................... 40

13.6 Glossary................................................................ 40

14 机械、封装和可订购信息....................................... 40

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Audio Characteristics (BTL) ...................................... 9

7.7 Audio Characteristics (PBTL) ................................... 9

7.8 Typical Characteristics, BTL Configuration, AD-

mode ........................................................................ 10

7.9 Typical Characteristics, PBTL Configuration, AD-

mode ........................................................................ 13

8

9

Parameter Measurement Information ................ 15

Detailed Description ............................................ 15

4 修订历史记录

Changes from Revision A (November 2017) to Revision B

Page

•

Changed OUT_P To: OUT1_P for 1 x BTL in Table 1 .......................................................................................................... 4

Added pins OSCM, OSCP to the Interface pins in the Absolute Maximun Ratings table...................................................... 5

Changed the T_JMIN value From: 0°C To –40°C in the Absolute Maximun Ratings table .................................................... 5

Deleted T_JJunction Temperature from the Recommended Operating Conditions table ....................................................... 5

Changed the capacitor on IN1_P, IN2_P and IN1_M, IN2_M From: 10µF To: 1µF in 图 50............................................... 30

Changed the capacitor on IN1_P and IN1_M From: 10µF To: 1µF in 图 51 ....................................................................... 32

Changed the capacitor on IN1_P and IN1_M From: 10µF To: 1µF in 图 52 ....................................................................... 33

Changes from Original (September 2017) to Revision A

Page

•

将“预告信息”更改成了“生产数据” ............................................................................................................................................ 1

2

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

5 Device Comparison Table

THERMAL PAD

LOCATION

TPA3221

PIN-COMPATIBLE

DEVICE NAME

DESCRIPTION

TPA3220

TPA3244

TPA3245

TPA3250

35 W Stereo, 100 W Peak HD, Analog-Input, Pad-Down Class-D Amplifier

Bottom

Top

Y

40 W Stereo, 100 W Peak Ultra-HD, Analog-Input, Pad-Down Class-D

Amplifier

100 W Stereo, 200 W Mono Ultra-HD, Analog-Input Class-D Amplifier

70 W Stereo, 130 W Peak Ultra-HD, Analog-Input, Pad-Down Class-D

Amplifier

Bottom

TPA3251

TPA3255

175 W Stereo, 350 W Mono Ultra-HD, Analog-Input Class-D Amplifier

315 W Stereo, 600 W Mono Ultra-HD, Analog-Input Class-D Amplifier

Top

6 Pin Configuration and Functions

The TPA3221 is available in a thermally enhanced TSSOP package.

The package type contains a heat slug that is located on the top side of the device for convenient thermal

coupling to the heat sink.

DDV Package

HTSSOP 44-Pin

(Top View)

VDD

GAIN/SLV

OTW_CLIP

FAULT

GND

BST1_P

BST1_M

GND

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

2

3

GND

4

5

OUT1_P

PVDD

GND

6

GND

7

IN1_P

PVDD

8

PVDD

IN1_M

RESET

HEAD

9

OUT1_M

GND

10

11

12

13

14

15

16

17

18

19

OSCM

OSCP

GND

OUT2_P

PVDD

FREQ_ADJ

IN2_P

PVDD

IN2_M

CMUTE

GND

PVDD

OUT2_M

GND

20

21

22

BST2_P

AVDD

GVDD

BST2_M

3

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

Pin Functions

NAME

NO.

11

I/O

I

DESCRIPTION

HEAD

AVDD

0 = AD, 1 = HEAD. Refer to: AD-Mode and HEAD-Mode PWM Modulation

AVDD voltage supply. Refer to: Internal LDO, AVDD and GVDD Supplies

21

P

BST1_M

BST1_P

BST2_M

BST2_P

43

P

OUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required.

Refer to: BST capacitors

44

23

24

P

OUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required.

Refer to: BST capacitors

OUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required.

Refer to: BST capacitors

OUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required.

Refer to: BST capacitors

CMUTE

17

4

P

O

Mute and Startup Timing Capacitor. Connect a 33 nF capacitor to GND. Refer to: Device Reset

Shutdown signal, open drain; active low. Refer to: Error Reporting

FAULT

FREQ_ADJ

14

Oscillator frequency programming pin. Refer to: Oscillator

Closed loop gain and master/slave programming pin.

Refer to: Input Configuration, Gain Setting And Master / Slave Operation

GAIN/SLV

GND

2

I

5, 6, 7, 18, 19, 20, 25, 26, 33,

34, 41, 42

P

Ground

GVDD

IN1_M

IN1_P

IN2_M

IN2_P

OSCM

22

9

P

Gate drive supply. Refer to: Internal LDO, AVDD and GVDD Supplies

Negative audio input for channel 1

I

8

I

Positive audio input for channel 1

16

15

12

Negative audio input for channel 2

I

Positive audio input for channel 2

I/O

Oscillator synchronization interface.

Refer to: Input Configuration, Gain Setting And Master / Slave Operation

OSCP

13

3

I/O

O

Oscillator synchronization interface.

Refer to: Input Configuration, Gain Setting And Master / Slave Operation

OTW_CLIP

Clipping warning and Over-temperature warning; open drain; active low.

Refer to: Error Reporting

OUT1_M

OUT1_P

OUT2_M

OUT2_P

PVDD

35

O

P

I

Negative output for channel 1

39, 40

Positive output for channel 1

27, 28

Negative output for channel 2

32

Positive output for channel 2

29, 30, 31, 36, 37, 38

PVDD supply. Refer to: PVDD Capacitor Recommendation, PVDD Supply

Device reset Input; active low. Refer to: Fault Handling, Powering Up, Powering Down

Input power supply. Refer to: Internal LDO, VDD Supply

Ground, connect to grounded heatsink. Placed on top side of device.

RESET

10

1

VDD

P

PowerPad™

Table 1. Mode Selection Pins

MODE PINS⁽¹⁾

OUTPUT

CONFIGURATION

INPUT MODE⁽²⁾

DESCRIPTION

IN2_M IN2_P HEAD

X

0

1

1N/2N + 1

2 × BTL

Stereo, BTL output configuration, AD mode modulation

Stereo, BTL output configuration, HEAD mode modulation

Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P

and OUT1_M to OUT2_M, AD mode modulation

0

1

0

1

0

1

0

1

1N/2N + 1

1 x PBTL

1 x BTL

Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P

and OUT1_M to OUT2_M, HEAD mode modulation

Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode

modulation

Mono, BTL configuration. OUT1_M and OUT1_P active, HEAD mode

modulation

(1) X refers to inputs connected through AC coupling capacitor, 0 refers to logic low (GND), 1 refers to logic high (AVDD).

(2) 2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control (RESET) input pins.

4

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

37

UNIT

V

PVDD to GND⁽²⁾

BST_X to GVDD⁽²⁾

37

V

BST1_M, BST1_P, BST2_M, BST2_P to GND⁽²⁾

47.8

43

V

Supply voltage

VDD to GND

V

GVDD to GND⁽²⁾

5.5

43

V

AVDD to GND

OUT1_M, OUT1_P, OUT2_M, OUT2_P to GND⁽²⁾

V

IN1_M, IN1_P, IN2_M, IN2_P to GND

5.5

9

V

Interface pins

HEAD, FREQ_ADJ, GAIN/SLV, CMUTE, RESET, OSCP, OSCM to GND

FAULT, OTW_CLIP to GND

V

Continuous sink current, FAULT, OTW_CLIP to GND

Operating junction temperature range

mA

°C

T_J

–40

150

T_stg

Storage temperature range

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins

±1000

V

(1)

V_ESD

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

±250

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

PVDD

Power-stage supply

DC supply voltage

7

30

32

V

Supply voltage for internal LDO regulator

to supply GVDD and AVDD

7

32

V

VDD⁽¹⁾

External supply for VDD, GVDD and

AVDD. Internal LDO bypassed

DC supply voltage

4.5

5

5.5

AVDD

Supply voltage for analog circuits

Supply voltage for gate-drive circuitry

Output filter inductance

DC supply voltage

4.5

5

5.5

V

GVDD

DC supply voltage

L_OUT(BTL)

Minimum output inductance at I_OC

10

Output filter inductance, PBTL before the

LC filter

Minimum output inductance at I_OC

5

10

μH

L_OUT(PBTL)

Output filter inductance, PBTL after the

LC filter

Minimum output inductance at half I_OC

each inductor

,

Nominal

575

510

460

49.5

29.7

9.9

600

533

480

50

625

555

PWM frame rate selectable for AM

interference avoidance; 1% Resistor

tolerance

F_PWM

AM1

kHz

AM2

500

Nominal; Master mode

AM1; Master mode

AM2; Master mode

50.5

30.3

10.1

R_{(FREQ_ADJ)}

PWM frame rate programming resistor

PVDD close decoupling capacitors

30

kΩ

10

C_PVDD

1.0

μF

Voltage on FREQ_ADJ pin for slave

mode operation

V_{(FREQ_ADJ)}

Slave Mode (Connect to AVDD)

5

V

(1) VDD must be connected to a supply of 5V in LDO bypass mode; OR 7V to 30V with LDO active. VDD can be connected directly to

PVDD in LDO bypass mode, but must not exceed PVDD voltage.

7.4 Thermal Information

TPA3221

DDV 44-PINS HTSSOP

THERMAL METRIC⁽¹⁾

UNIT

FIXED 85°C

HEATSINK

JEDEC STANDARD 4 LAYER

PCB

TEMPERATURE⁽²⁾

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

44.8

1.1

5.5

2.0

n/a

°C/W

R_θJC(top)

R_θJB

14.9

0.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

14.7

n/a

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil

thickness. In this model heat sink temperature is considered to be the ambient temperature and only path for dissipation is to the

heatsink.

6

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

7.5 Electrical Characteristics

PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, T_C(Case temperature) = 75 °C, f_S= 600 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator. Only used as reference

AVDD

node when supplied by internal LDO. Voltage VDD = 30 V

regulator bypassed for VDD = 5 V.

5

V

Operating, no audio signal

Reset mode

25

118

150

50

10

1

mA

VDD supply current. LDO mode (VDD > 7 V)

I_VDD

Operating, no audio signal

Reset mode

µA

VDD supply current. LDO bypass mode

(VDD = 5 V)

Operating, no audio signal

Reset mode

Gate-supply current. LDO bypass mode

(VDD = 5 V)

I_AVDD

mA

50% duty cycle

16

50

16

50

15

Gate-supply current. LDO bypass mode

(VDD = 5 V), AD-mode modulation

Reset mode

µA

mA

µA

I_GVDD

HEAD-mode modulation

Reset mode

Gate-supply current. LDO bypass mode

(VDD = 5 V), HEAD-mode modulation

50% duty cycle with recommended output filter

Total PVDD idle current, AD-mode

modulation, BTL

50% duty cycle with recommended output filter, T_C

= 25 ºC

13

1

Reset mode, No switching

I_PVDD

mA

HEAD-mode modulation with recommended output

filter

10

Total PVDD idle current, HEAD-mode

modulation, BTL

HEAD-mode with recommended output filter, T_C

25 ºC

=

9

1

Reset mode, No switching

ANALOG INPUTS

V_IN

I_IN

Maximum input voltage swing

Maximum input current

±2.8

1

V

-1

mA

R₁= 5.6 kΩ, R₂= OPEN

R₁= 20 kΩ, R₂= 100 kΩ

R₁= 39 kΩ, R₂= 100 kΩ

R₁= 47 kΩ, R₂= 75 kΩ

R₁= 51 kΩ, R₂= 51 kΩ

R₁= 75 kΩ, R₂= 47 kΩ

R₁= 100 kΩ, R₂= 39 kΩ

R₁= 100 kΩ, R₂= 16 kΩ

G = 18 dB

18

24

30

34

18

24

30

34

48

24

12

7.7

Inverting voltage Gain, V_OUT/V_IN(Master

Mode)

G

dB

Inverting voltage Gain, V_OUT/V_IN(Slave Mode)

G = 24 dB

R_IN

Input resistance

kΩ

G = 30 dB

G = 34 dB

OSCILLATOR

Nominal, Master Mode

AM1, Master Mode

3.45

3.6

3.75

3.33

3

(1)

f_OSC(IO)

F_PWM× 6

3.06 3.198

MHz

AM2, Master Mode

2.76

1.88

2.88

V_IH

V_IL

High level input voltage

Low level input voltage

V

1.65

3.78

EXTERNAL OSCILLATOR (Slave Mode)

f_OSC(IO)

CLK input on OSCM/OSCP (Slave Mode)

2.3

MHz

OUTPUT-STAGE MOSFETs

Drain-to-source resistance, low side (LS)

Drain-to-source resistance, high side (HS)

70

mΩ

T_J= 25 °C, Excludes metallization resistance,

GVDD = 5 V

R_DS(on)

(1) Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 4 : 4.5 : 5

7

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

Electrical Characteristics (continued)

PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, T_C(Case temperature) = 75 °C, f_S= 600 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I/O PROTECTION

V_uvp,AVDD

Undervoltage protection limit, AVDD

4

V

(2)

V_{uvp,AVDD,hyst}

Undervoltage protection hysteresis, AVDD

Undervoltage protection limit, PVDD_x

Undervoltage protection hysteresis, PVDD_x

Overvoltage protection limit, PVDD_x

Overvoltage protection hysteresis, PVDD_x

0.1

V_uvp,PVDD

6.4

V

(2)

V_{uvp,PVDD,hyst}

0.45

34

V

V_ovp,PVDD

V

(2)

V_{ovp,PVDD,hyst}

0.45

125

V

(2)

OTW

Overtemperature warning, OTW_CLIP

115

145

135

165

°C

Temperature drop needed below OTW

temperature for OTW_CLIP to be inactive

after OTW event.

(2)

OTW_hyst

20

°C

OTE⁽²⁾

Overtemperature error

155

20

°C

A reset needs to occur for FAULT to be

released following an OTE event

(2)

OTE_hyst

OTE-OTW_{(differential)}

OTE-OTW differential

25

°C

(2)

OLPC

Overload protection counter

f_PWM= 600 kHz (1024 PWM cycles)

1.7

10

ms

A

I_{OC, BTL}

Overcurrent limit protection, speaker output

current

Nominal peak current in 1Ω load

I_{OC, PBTL}

I_{DCspkr, BTL}

I_{DCspkr, PBTL}

20

A

BTL current imbalance threshold

PBTL current imbalance threshold

1.8

3.6

A

DC Speaker Protection Current Threshold

A

Time from switching transition to flip-state induced

by overcurrent.

I_OCT

I_PD

Overcurrent response time

150

3

ns

Connected when RESET is active to provide

bootstrap charge. Not used in SE mode.

Output pulldown current of each half

mA

STATIC DIGITAL SPECIFICATIONS

V_IH

V_IL

I_lkg

High level input voltage

1.9

V

Low level input voltage

Input leakage current

HEAD, OSCM, OSCP,CMUTE, RESET

0.8

100

μA

OTW/SHUTDOWN (FAULT)

Internal pullup resistance, OTW_CLIP to

R_{INT_PU}

20

3

26

32

kΩ

AVDD, FAULT to AVDD

High level output voltage

Low level output voltage

OTW_CLIP, FAULT

V_OH

Internal pullup resistor

I_O= 4 mA

3.3

200

30

3.6

V

V_OL

500

mV

Device fanout

No external pullup

devices

(2) Specified by design.

8

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

7.6 Audio Characteristics (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,

VDD = 5 V, GVDD = 5 V, R_L= 4 Ω, f_S= 600 kHz, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, AD-Modulation,

AES17 + AUX-0025 measurement filters, unless otherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 3 Ω, 10% THD+N

MIN

TYP MAX UNIT

112

R_L= 4 Ω, 10% THD+N

R_L= 3 Ω, 1% THD+N

R_L= 4 Ω, 1% THD+N

1 W

105

P_O

Power output per channel

W

100

88

THD+N Total harmonic distortion + noise

0.02

%

A-weighted, AES17 filter, Input Capacitor

Grounded, Gain = 18 dB

V_n

Output integrated noise

75

μV

|V_OS

|

Output offset voltage

Signal-to-noise ratio⁽¹⁾

Dynamic range

Inputs AC coupled to GND

A-weighted, Gain = 18 dB

20

108

109

60

mV

dB

SNR

DNR

P_O= 0, all outputs switching, AD-modulation,

T_C= 25°C⁽²⁾

0.37

0.25

W

P_idle

Power dissipation due to idle losses (I_{PVDD_X})

P_O= 0, all outputs switching, HEAD-

modulation, T_C= 25°C⁽²⁾

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

7.7 Audio Characteristics (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,

VDD = 5 V, GVDD = 5 V, R_L= 2 Ω, f_S= 600 kHz, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, Pre-Filter PBTL, AD-

Modulation, AES17 + AUX-0025 measurement filters, unless otherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 2 Ω, 10% THD+N

MIN

TYP MAX UNIT

208

155

R_L= 3 Ω, 10% THD+N

R_L= 4 Ω, 10% THD+N

R_L= 2 Ω, 1% THD+N

R_L= 3 Ω, 1% THD+N

R_L= 4 Ω, 1% THD+N

1 W

120

W

P_O

Power output per channel

170

125

98

THD+N Total harmonic distortion + noise

0.02

%

A-weighted, AES17 filter, Input Capacitor

Grounded, Gain = 18 dB

V_n

Output integrated noise

75

μV

|V_OS

|

Output offset voltage

Signal to noise ratio⁽¹⁾

Dynamic range

Inputs AC coupled to GND

A-weighted, Gain = 18 dB

20

108

110

60 mV

dB

SNR

DNR

dB

P_O= 0, all outputs switching, AD-

modulation, T_C= 25°C⁽²⁾

0.20

0.17

W

P_idle

Power dissipation due to idle losses (IPVDD_X)

P_O= 0, all outputs switching, HEAD-

modulation, T_C= 25°C⁽²⁾

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

9

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

7.8 Typical Characteristics, BTL Configuration, AD-mode

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, R_L= 4 Ω, f_S=

600 kHz, 18 dB, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, AD-Modulation, AES17 + AUX-0025

measurement filters, unless otherwise noted.

10

1

10

1

3W

4W

8W

R_L= 4W

T_C= 75èC

1W

10W

50W

0.1

0.01

0.1

0.01

T_C= 75èC

100 200

0.001

0.0005

0.001

10m

100m

1

10

20

100

1k

10k 20k

Po - Output Power - W

D001

f - Frequency - Hz

D002

Figure 1. Total Harmonic Distortion + Noise vs Output

Power, AD-mode

Figure 2. Total Harmonic Distortion+Noise vs Frequency,

AD-mode

120

10

3W

AUX-0025 Filter

1W

3W - CB3C Limited

80 kHz analyzer BW

R_L= 4W, T_C= 75èC

10W

50W

100

4W

8W

1

0.1

80

60

40

0.01

20

THD+N = 10%

T_C= 75èC

0

0.001

5

10

15

20

25

30

35

20

100

1k

10k

40k

PVDD - Supply Voltage - V

f - Frequency - Hz

D004

D003

Figure 4. Output Power vs Supply Voltage, AD-mode

Figure 3. Total Harmonic Distortion+Noise vs Frequency,

AD-mode

120

100

3W

4W

8W

3W

3W - CB3C Limited

100

4W

8W

80

60

40

10

20

THD+N = 1%

T_C= 75èC

PVDD = 30V

0

1

10m

5

10

15

20

25

30

35

100m

1

10

100 300

PVDD - Supply Voltage - V

2 Channel Output Power - W

D005

D006

Figure 5. Output Power vs Supply Voltage, AD-mode

Figure 6. System Efficiency vs Output Power, AD-mode

10

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

Typical Characteristics, BTL Configuration, AD-mode (continued)

100

10

1

100

10

1

3W

4W

8W

3W

4W

8W

T_C= 75èC

PVDD = 24V

T_C= 75èC

PVDD = 12V

10m

100m

1

10

100 200

10m

100m

1

10

50

2 Channel Output Power - W

D007

D008

Figure 7. System Efficiency vs Output Power, AD-mode

Figure 8. System Efficiency vs Output Power, AD-mode

75

150

3W

4W

8W

125

100

75

50

25

50

3W

4W

8W

25

0

T_C= 75èC

PVDD = 30V

THD+N = 10%

75 100

0

25

50

75 100 125 150 175 200 225 250

2 Channel Output Power - W

0

25

50

T_C- Case Temperature - èC

D009

D010

Figure 9. System Power Loss vs Output Power, AD-mode

Figure 10. Output Power vs Case Temperature, AD-mode

0

T_C= 75èC

4W

T_C= 75èC

4W

V_ref= 21.21 V

P_out= 1W/channel

FFT size = 16384

-20

-40

-20

-40

FFT size = 16384

AUX-0025 filter

80kHz Analyzer BW

-60

-80

-100

-120

-140

-160

-100

-120

-140

AUX-0025 filter

80kHz Analyzer BW

0

5k 10k 15k 20k 25k 30k 35k 40k 45k48k

f - Frequency - Hz

0

5k

10k

15k

20k

25k

30k

35k

40k

f - Frequency - Hz

D011

D012

18 kHz + 19 kHz

Ratio 1 : 1

Figure 11. Noise Amplitude vs Frequency, AD-mode

Figure 12. CCIF Intermodulation, AD-mode

11

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

Typical Characteristics, BTL Configuration, AD-mode (continued)

0

T_C= 75èC

P_out= 25W/channel

FFT size = 16384

T_C= 75èC

PSU Ripple - 250mV_p-p

4W

CH1

CH2

-20

-40

-60

-80

-100

-120

-140

-100

-120

AUX-0025 filter

80kHz Analyzer BW

0

5k

10k

15k

20k

25k

30k

35k

40k

20

100

1k

f - Frequency - Hz

10k 20k

f - Frequency - Hz

D013

D014

18 kHz + 19 kHz

Ratio 1 : 1

Figure 13. CCIF Intermodulation, AD-mode

Figure 14. Power Supply Rejection Ratio vs Frequency, AD-

mode

0

-20

15

R_L= 4W, T_C= 75èC

Aggressor Amplitude = 2V_RMS(1W)

CH2 to CH1

CH1 to CH2

AD Mode

HEAD Mode

-40

10

5

-60

-80

-100

-120

R_L= 4W

T_C= 25èC

20

100

1k

10k 20k

0

f - Frequency - Hz

D015

5

10

15

20

25

30

35

PVDD - Supply Voltage - V

D026

Figure 15. Channel to Channel Crosstalk vs Frequency, AD-

mode

Figure 16. Idle Current vs Supply Voltage

12

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

7.9 Typical Characteristics, PBTL Configuration, AD-mode

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, R_L= 2 Ω, f_S=

600 kHz, 18 dB, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, Pre-Filter PBTL, AD Modulation, AES17 +

AUX-0025 measurement filters, unless otherwise noted.

10

1

10

1

2W

3W

4W

1W

25W

100W

R_L= 2W

T_C= 75èC

0.1

0.01

0.1

0.01

0.001

0.0005

T_C= 75èC

100 300

0.001

10m

100m

1

10

20

100

1k

10k 20k

Po - Output Power - W

f - Frequency - Hz

D016

D017

Figure 17. Total Harmonic Distortion+Noise vs Output

Power, AD-mode

Figure 18. Total Harmonic Distortion + Noise vs Frequency,

AD-mode

225

10

2W

AUX-0025 Filter

80 kHz analyzer BW

R_L= 2W, T_C= 75èC

1W

25W

100W

200

175

150

125

100

75

2W - CB3C Limited

3W

4W

1

0.1

0.01

50

THD+N = 10%

25

T_C= 75èC

0

0.001

5

10

15

20

25

30

35

20

100

1k

10k

40k

PVDD - Supply Voltage - V

f - Frequency - Hz

D019

D018

Figure 20. Output Power vs Supply Voltage, AD-mode

Figure 19. Total Harmonic Distortion+Noise vs Frequency,

AD-mode

200

100

2W

3W

4W

2W

3W

4W

175

150

125

100

75

10

50

25

THD+N = 1%

T_C= 75èC

PVDD = 30V

0

1

10m

5

10

15

20

25

30

35

100m

1

10

100 300

PVDD - Supply Voltage - V

2 Channel Output Power - W

D020

D021

Figure 21. Output Power vs Supply Voltage, AD-mode

Figure 22. System Efficiency vs Output Power, AD-mode

13

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

Typical Characteristics, PBTL Configuration, AD-mode (continued)

40

30

20

10

0

250

200

150

100

50

2W

3W

4W

2W

3W

4W

T_C= 75èC

PVDD = 30V

THD+N = 10%

75 100

0

25

50

75

100 125 150 175 200 225

0

25

50

2 Channel Output Power - W

T_C- Case Temperature - èC

D022

D023

Figure 23. System Power Loss vs Output Power, AD-mode

Figure 24. Output Power vs Case Temperature, AD-mode

0

T_C= 75èC

P_out= 1W/channel

FFT size = 16384

T_C= 75èC

P_out= 50W/channel

FFT size = 16384

2W

-20

-40

-20

-40

-60

-80

-100

-120

-140

-100

-120

-140

AUX-0025 filter

80kHz Analyzer BW

AUX-0025 filter

80kHz Analyzer BW

0

5k

10k

15k

20k

25k

30k

35k

40k

0

5k

10k

15k

20k

25k

30k

35k

40k

f - Frequency - Hz

D024

D025

18 kHz + 19 kHz

Ratio 1 : 1

18 kHz + 19 kHz

Ratio 1 : 1

Figure 25. CCIF Intermodulation vs Frequency, AD-mode

Figure 26. CCIF Intermodulation vs Frequency, AD-mode

14

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Recommended Operating Conditions.

Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to

out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to

use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can

be used to reduce the out of band noise remaining on the amplifier outputs.

9 Detailed Description

9.1 Overview

TPA3221 is designed as a feature-enhanced cost efficient high power Class-D audio amplifier. It has built-in

advanced protection circuitry to ensure maximum product robustness as well as a flexible feature set including

built in LDO for easy supply of low voltage circuitry, selectable gain, switching frequency, master/slave

synchronization of multiple devices, selectable PWM modulation scheme, mute function, temperature and

clipping status signals. TPA3221 has a bandwidth up to 100 kHz and low output noise designed for high

resolution audio applications and accepts both differential and single ended analog audio inputs at levels from 1

V_RMSto 2 V_RMS. With its closed loop operation TPA3221 is designed for high audio performance with a system

power supply between 7 V and 30 V.

To facilitate system design, the TPA3221 needs only a (typical) 30 V power stage supply. The TPA3221 has an

internal voltage regulator supplied from the VDD pin for the analog and digital system blocks and the output

stage gate drive respectively. The VDD pin can be connected directly to PVDD in case of only this power supply

rail being available.

To reduce device power losses an external 5 V supply can be used for the AVDD and VDD supply pins. The

internal voltage regulator connected to the VDD pin is automatically turned off if an external 5 V supply is used

for this pin. Although supplied from the same 5 V source, separating AVDD and VDD on the printed-circuit board

(PCB) by RC filters (see application diagram for details) is recommended. These RC filters provide the

recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as

close to their associated pins as possible. In general, the physical loop with the power supply pins, decoupling

capacitors and GND return path to the device pins must be kept as short as possible and with as little area as

possible to minimize induction (see Layout Examples for additional information).

The floating supplies for the output stage high side gate drives are supplied by built-in bootstrap circuitry

requiring only an external capacitor for each half-bridge.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap

pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential

and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33 nF ceramic

capacitors, size 0603 or 0805, for the bootstrap supply. These 33 nF capacitors ensure sufficient energy storage,

even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during

the remaining part of the PWM cycle.

Special attention should be paid to the power stage power supply; this includes component selection, PCB

placement, and routing.

For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X

node is decoupled with 1 μF ceramic capacitors placed as close as possible to the PVDD supply pins. It is

recommended to follow the PCB layout of the TPA3221 reference design. For additional information on

recommended power supply and required components, see the application diagrams in this data sheet.

If using external power supply for the AVDD and VDD internal regulators, this supply should be from a low-noise,

low-output-impedance voltage regulator. Likewise, the 30 V power stage supply is assumed to have low output

impedance throughout the entire audio band, and low noise. The power supply sequence is not critical as

facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power supply

is settled for minimum turn on audible artefacts. Moreover, the TPA3221 is fully protected against erroneous

power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within

the specified range (see the Recommended Operating Conditions table of this data sheet).

15

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

9.2 Functional Block Diagrams

VDD

AVDD

REGULATOR

(Auto Bypass)

VDD

RESET

AVDD

GVDD

ERROR

HANDLING

OTW_CLIP

FAULT

DIFFOC

CB3C

IOUT1_M

IOUT1_P

IOUT2_M

IOUT2_P

OVER-LOAD

PROTECTION

CURRENT

SENSE

GAIN/SLV

PWM ACTIVITY

DETECTOR

PVDD

PPSC

OUT_X

HEAD

POWER-UP

RESET

TEMP

SENSE

I/O LOGIC

CMUTE

STARTUP

CONTROL

PVDD

AVDD

UVP

STARTUP & CONTROL

FREQ_ADJ

OVP

PVDD

OSCILLATOR

OSCM

OSCP

OUTPUT DC

CONTROL

PROTECTION

GVDD

BST1_M

PVDD

-

GATE-DRIVE

OUT1_M

GND

+

IN1_P

IN1_M

ANALOG

LOOP

FILTER

PWM

RECEIVER

TIMING

CONTROL

+

-

OUT_1_P

PVDD

GVDD

BST1_P

CHANNEL 1

GVDD

BST2_M

PVDD

-

GATE-DRIVE

OUT2_M

GND

+

IN2_P

IN2_M

ANALOG

LOOP

FILTER

PWM

RECEIVER

TIMING

CONTROL

+

-

OUT2_P

PVDD

GVDD

BST2_P

CHANNEL 2

16

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

Functional Block Diagrams (接下页)

System

microcontroller or

Analog circuitry

BST1_P

OSCM

OSCP

Oscillator

Synchronization

Bootstrap

Capacitors

BST1_M

2^ndOrder

OUT1_P

L-C Output

Filter for

each

Output

H-Bridge 1

IN1_M

Input DC

Blocking

Caps

ANALOG_IN1_M

ANALOG_IN1_P

OUT1_M

Input

H-Bridge 1

IN1_P

H-Bridge

2-CHANNEL

H-BRIDGE

BTL MODE

Hardwire PWM

Frame Adjust

& Master/Slave

Mode

FREQ_ADJ

2^ndOrder

L-C Output

Filter for

each

OUT2_P

OUT2_M

IN2_M

IN2_P

Input DC

Blocking

Caps

ANALOG_IN2_M

ANALOG_IN2_P

Output

H-Bridge 2

Input

H-Bridge 2

H-Bridge

PBTL

Detect

BST2_P

BST2_M

Hardwire

Mode

HEAD

Bootstrap

Capacitors

Control

PVDD

GND

PVDD

VDD, AVDD

& GVDD

Power Supply

Decoupling

30 V

Power Supply

Decoupling

SYSTEM

Power

Supplies

GND

5 V or 7-30 V

VDD (5 V or 7-30 V)

VAC

*NOTE1: Logic AND in or outside microcontroller

图 27. System Block Diagram

17

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

9.3 Feature Description

9.3.1 Internal LDO

TPA3221 has a built in optional LDO (Low dropout voltage regulator) to supply the analog and digital circuits as

well as the gate drive for the output stages. The LDO can be used in systems where only the high voltage power

rail is available, hence no additional power supply rails need to be generated for the TPA3221 to operate. As

being a linear regulator, the LDO will add to the power losses of the device due to the (PVDD-5V) voltage drop

and the supply current for AVDD and GVDD given in the Electrical Characteristics table.

VDD

+7V≤PVDD

470uF

100nF

GND

AVDD

GVDD

5V LDO

3R3

1µF

TPA322x

1µF

图 28. Internal LDO for Single Supply Systems

When using the internal LDO in TPA3221 the VDD terminal should be connected to a voltage source between

7V and PVDD. In a single supply system the VDD terminal should be connected directly to the PVDD terminal.

The LDO output is connected to the AVDD terminal, and can be used to supply the gate drive by supplying the

GVDD from AVDD through a RC filter for best noise performance as shown in 图 28.

+5V

VDD

470uF

100nF

GND

AVDD

GVDD

5V LDO

3R3

1µF

TPA322x

1µF

图 29. Internal LDO Bypass for Highest Power Efficiency

For highest system power efficiency the LDO can be bypassed by connecting VDD to an external 5 V supply. In

this configuration AVDD and GVDD should be supplied by 5 V from the external power supply. GVDD should be

supplied through a RC filter for best noise performance as shown in 图 29.

9.3.1.1 Input Configuration, Gain Setting And Master / Slave Operation

TPA3221 is designed to accept either a differential or a single-ended audio input signal. To accept a wide range

of system front ends TPA3221 has selectable input gain that allows full scale output with a wide range of input

signal levels.

Best system noise performance is obtained with balanced audio interface. However, to be used in systems with

only a single ended audio input signal available, one input terminal can be connected to AC ground, to accept

single ended audio input signals.

IN1_P

IN1_M

+

-

IN1_M

IN2_P

IN2_M

+

-

IN2_M

TPA322x

图 30. Balanced Audio Input Configuration

18

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

Feature Description (接下页)

In systems with single ended audio inputs the device gain will typically need to be set higher than for systems

with balanced audio input signals.

IN1_P

IN1

+

-

IN1_M

IN2_P

IN2

+

-

IN2_M

TPA322x

图 31. Single Ended Audio Input Configuration

9.3.2 Gain Setting And Master / Slave Operation

The gain of TPA3221 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode

is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets

the GAIN in Master mode in gains of 18, 24, 30, 34 dB respectively, while the next four stages sets the GAIN in

Slave mode in gains of 18, 24, 30, 34 dB respectively. The gain setting is latched when RESET goes high and

cannot be changed while RESET is high. 表 2 shows the recommended resistor values, the state and gain:

表 2. Gain and Master / Slave

Master / Slave

Mode

Differential Input Signal Level

(each input pin)

Single Ended Input Signal

Level

Gain

R1 (to GND)

R2 (to AVDD)

Master

Slave

18 dB

24 dB

30 dB

34 dB

18 dB

24 dB

30 dB

34 dB

5.6 kΩ

20 kΩ

39 kΩ

47 kΩ

51 kΩ

75 kΩ

100 kΩ

OPEN

100 kΩ

75 kΩ

51 kΩ

47 kΩ

39 kΩ

16 kΩ

2 VRMS

1 VRMS

2 VRMS

0.5 VRMS

0.32 VRMS

2 VRMS

1 VRMS

0.63 VRMS

2 VRMS

Slave

1 VRMS

2 VRMS

Slave

0.5 VRMS

0.32 VRMS

1 VRMS

Slave

0.63 VRMS

AVDD

R2

AVDD

GAIN/SLV

TPA322x

R1

GND

图 32. Gain and Master / Slave Setup

For easy multi-channel system design TPA3221 has a Master / Slave feature that allows automatic

synchronization of multiple slave devices operated at the PWM switching frequency of a master device. This

benefits system noise performance by eliminating spurious crosstalk sum and difference tones due to

unsynchronized channel-to-channel switching frequencies. Furthermore the Master / Slave scheme is designed

to interleave switching of the individual channels in a multi-channel system such that the power supply current

ripple frequency is moved to a higher frequency which reduces the RMS ripple current in the power supply bulk

capacitors.

19

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

The Master / Slave scheme and the interleaving of the output stage switching is automatically configured by

connecting the OSCx pins between a master and multiple slave devices. Connect the OSCx pins in either

positive or negative polarity to configure either a Slave1 or Slave2 device. Connect the OSCM of the Master

device to the OSCM of a slave device to configure for Slave1 or OSCP to configure for Slave2. Then connect the

remaining OSCx pins between the master and slave devices. The Master, Slave1 and Slave2 PWM switching will

be 30 degrees out of phase with each other. All switching channels are automatically synchronized by releasing

RESET on all devices at the same time.

AVDD

47k

OSCM

OSCP

OSCM

OSCP

OSCM

OSCP

OSCM

OSCP

OSCM

OSCP

OSCM

OSCP

OSCM

OSCP

TPA322x

SLAVE1

RESET

TPA322x

SLAVE2

RESET

TPA322x

SLAVE1

RESET

TPA322x

MASTER

RESET

TPA322x

SLAVE2

RESET

TPA322x

SLAVE1

RESET

TPA322x

SLAVE2

RESET

图 33. Gain and Master PCB Implementation

Placement on the PCB and connection of multiple TPA3221 devices in a multi channel system is illustrated in 图

33. Slave devices should be placed on either side of the master device, with a Slave1 device on one side of the

Master device, and a Slave2 device on the other. In systems with more than 3 TPA3221 devices, the master

should be in the middle, and every second slave devices should be a Slave1 or Slave 2 as illustrated in 图 33. A

47kΩ pull up resistor to AVDD should be connected to the master device OSCM output and a 47kΩ pull down

resistor to GND should be connected to the master OSCP CLK outputs.

9.3.3 AD-Mode and HEAD-Mode PWM Modulation

TPA3221 has the option of using either AD-Mode or HEAD-Mode PWM modulation scheme. AD mode has

continuous switching of the two half bridge outputs in each BTL output channel. Both half bridge outputs are

switching in HEAD mode, but with reduced duty cycle for idle operation and while playing small signals. With

higher output levels one half bridge stops switching on HEAD mode operation. HEAD benefits both device power

loss and EMI performance, where AD mode is considered to have the highest audio performance.

SPACE

HEAD

AVDD

HEAD

AVDD

TPA322x

图 34. AD-Mode Configuration

图 35. HEAD-Mode Configuration

OUTP

OUTN

0V

0A

OUTP Current

OUTN Current

0A

图 36. AD Mode Output Waveforms, Idle

20

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

OUTP

OUTN

0V

>0A

OUTP Current

OUTN Current

<0A

图 37. AD Mode Output Waveforms, High Level Output

PVDD

OUTX_P (PWM)

OUTX_M (PWM)

PVDD/2

SpeakerX_P

SpeakerX_M

0V

SpeakerX_Diff

图 38. AD Mode Speaker Output Signals, Low or and High Level Output

OUTP

OUTN

0V

0A

OUTP Current

OUTN Current

0A

图 39. HEAD Mode Output Waveforms, Idle

OUTP

OUTN

0V

>0A

OUTP Current

OUTN Current

<0A

图 40. HEAD Mode Output Waveforms, High Level Output

21

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

PVDD

OUTX_P (PWM)

OUTX_M (PWM)

SpeakerX_P

SpeakerX_M

0V

SpeakerX_Diff

图 41. HEAD Mode Speaker Output Signals, Low Level Output

PVDD

OUTX_P (PWM)

OUTX_M (PWM)

SpeakerX_P

SpeakerX_M

0V

SpeakerX_Diff

0V

图 42. HEAD Mode Speaker Output Signals, High Level Output

22

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

9.3.4 Oscillator

The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.

To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency

can be changed from nominal to higher values. These values should be chosen such that the nominal and the

higher value switching frequencies together results in the fewest cases of interference throughout the AM band.

The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in master

mode according to the description in the Recommended Operating Conditions table.

For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to AVDD. This configures the

OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter channel

delay is automatically setup between the switching of the audio channels, which can be illustrated by no idle

channels switching at the same time. This will not influence the audio output, but only the switch timing to

minimize noise coupling between audio channels through the power supply to optimize audio performance and to

get better operating conditions for the power supply. The inter channel delay will be setup for a slave device

depending on the polarity of the OSC_I/O connection such that a slave mode 1 is selected by connecting the

master device OSC_I/O to the slave 1 device OSC_I/O with same polarity (+ to + and - to -), and slave mode 2 is

selected with the inverse polarity (+ to - and - to +).

9.3.5 Input Impedance

The TPA3221 input stage is a fully differential input stage and the input impedance changes with the gain setting

from 7.7 kΩ at 34 dB gain to 47 kΩ at 18 dB gain. Table 1 lists the values from min to max gain. The tolerance of

the input resistor value is ±20 % so the minimum value will be higher than 6.2 kΩ. The inputs need to be AC-

coupled to minimize the output DC-offset and ensure correct ramping of the output voltages during power-ON

and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with

the following cut-off frequency:

If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. 表 3

lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10 times lower

capacitors can used – for example, a 1 μF can be used.

表 3. Recommended Input AC-Coupling Capacitors

Input AC-Coupling

Capacitance

Gain

Input Impedance

Input High Pass Filter

18 dB

24 dB

30 dB

34 dB

48 kΩ

24 kΩ

12 kΩ

7.7 kΩ

4.7 µF

0.7 Hz

1.3 Hz

2.1 Hz

10 µF

The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum, film or ceramic. If

a polarized type is used the positive connection should face such that the capacitor has a positive DC bias.

9.3.6 Error Reporting

The FAULT, and OTW_CLIP, pins are active-low, open-drain outputs. The FAULT function is for protection-mode

signaling to a system-control device. Any fault resulting in device shutdown is signaled by the FAULT pin going

low. Also, OTW_CLIP goes low when the device junction temperature exceeds 125°C (see 表 4).

表 4. Error Reporting

FAULT

OTW_CLIP

DESCRIPTION

Overtemperature (OTE), overload (OLP), undervoltage (UVP), or overvoltage (OVP).

Junction temperature higher than 125°C (overtemperature warning)

0

Overload (OLP), undervoltage (UVP), or overvoltage (OVP). Junction temperature

lower than 125°C

0

1

0

1

Junction temperature higher than 125°C (overtemperature warning)

Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)

23

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI

recommends monitoring the OTW_CLIP signal using the system microcontroller and responding to an

overtemperature warning signal by turning down the volume to prevent further heating of the device resulting in

device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and

OTW_CLIP outputs.

9.4 Device Functional Modes

TPA3221 can be configured in either a stereo BTL (Bridge Tied Load) mode, mono BTL mode (only one output

BTL channel active), or in a mono PBTL (Parallel Bridge Tied Load) mode. In PBTL mode the two output BTL

channels are parallelled with double output current available. The parallelling of the two BTL outputs can be

made either before the output LC filter, or after the output LC filter. For PBTL mode the audio performance will in

general be higher when parallelling before the output LC filter, but parallelling after the LC output filter may be

preferred in some systems.

See Table 1 for mode configuration setup.

OUT1_P

IN1_P

IN1_M

IN1_P

IN1_M

IN1_P

IN1_M

OUT1_M

OUT2_P

OUT1_M

OUT2_P

IN1_M

IN2_P

TPA322x

IN2_P

IN2_M

IN2_P

IN2_M

AVDD

OUT2_M

图 43. Stereo BTL

图 44. Mono BTL

OUT1_P

IN1_P

IN1_M

IN1_P

IN1_M

IN1_P

IN1_M

IN1_P

IN1_M

OUT1_M

TPA322x

IN2_P

IN2_M

IN2_P

IN2_M

OUT2_P

OUT2_M

图 45. Mono PBTL, Pre LC Filter

9.4.1 Powering Up

图 46. Mono PBTL, Post LC Filter

The TPA3221 does not require a power-up sequence because of the integrated undervoltage protection (UVP),

but it is recommended to hold RESET low until PVDD supply voltage is stable to avoid audio artifacts. The

outputs of the H-bridges remain in a high-impedance state until the gate-drive supply (GVDD) and AVDD

voltages are above their UVP voltage thresholds (see the Electrical Characteristics table of this data sheet). This

allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pull-down of the half-

bridge output as well as initiating a controlled ramp up sequence of the output voltage.

24

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

PVDD

VDD

GVDD

RESET

AVDD

FAULT

VIN_X

OUT_X

VOUT_X

t

Precharge

C 20 ms

t

Startup ramp

V_CMUTE

图 47. Startup Timing

When RESET is released to turn on TPA3221, FAULT signal will turn low and AVDD voltage regulator will be

enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the

Electrical Characteristics table of this data sheet). After a pre-charge time to stabilize the DC voltage across the

input AC coupling capacitors, the ramp up sequence starts and completes once the CMUTE node is charged to

its final value.

9.4.1.1 Startup Ramp Time

During the startup ramp the CMUTE capacitor is charged by an internal current generator. With use of the

recommended 33 nF CMUTE capacitor value, the startup ramp time is approximately 20 ms. Higher CMUTE

capacitor value will increase the ramp time, and a lower value will decrease the ramp time. The recommended

CMUTE capacitor value is selected for minimum audible artifacts during startup and shutdown ramp.

9.4.2 Powering Down

The TPA3221 does not require a power-down sequence. The device remains fully operational as long as the

VDD, AVDD and PVDD voltages are above their undervoltage protection (UVP) voltage thresholds (see the

Electrical Characteristics table of this data sheet). Although not specifically required, it is a good practice to hold

RESET low during power down, thus preventing audible artifacts including pops or clicks by initiating a controlled

ramp down sequence of the output voltage. The ramp down sequence will complete once the CMUTE node is

discharged.

25

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

9.4.2.1 Power Down Ramp Time

During the power down ramp the CMUTE capacitor is discharged by internal circuitry. With use of the

recommended 33 nF CMUTE capacitor value, the power-down ramp time is approximately 20 ms.

9.4.3 Device Reset

Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down

is complete. Output pull downs are active in both BTL mode and PBTL mode with RESET low.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the RESET input low

enables weak pull-down of the half-bridge outputs.

Asserting RESET low removes any fault information to be signaled on the FAULT output, that is, FAULT is

forced high. A rising-edge transition on RESET allows the device to resume operation after a fault. To ensure

thermal reliability, the rising edge of RESET must occur no sooner than 4 ms after the falling edge of FAULT.

The TPA3221 will enter a low power state once the ramp down sequence is complete.

9.4.4 Device Soft Mute

Asserting CMUTE low initiates the device soft mute function. The soft mute function initiates a ramp down

sequence of the outputs, and the output FETs go into a Hi-Z state after the ramp down is complete. All internal

circuits are powered while in soft mute state. External control of the soft mute function must provide high

impedance output when not engaged (open drain output) to allow the CMUTE node to charge/discharge during

device ramp up and ramp down when de-asserting and asserting RESET.

9.4.5 Device Protection System

The TPA3221 contains advanced protection circuitry carefully designed to facilitate system integration and ease

of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as

short circuits, overload, overtemperature, overvoltage and undervoltage. The TPA3221 responds to a fault by

immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In

situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault

condition has been removed, that is, the supply voltage has increased. The device will handle errors, as shown

in 表 5.

表 5. Device Protection

BTL MODE

LOCAL ERROR IN

PBTL MODE

LOCAL ERROR IN

TURNS OFF

A

B

C

D

A

B

C

D

A+B

A+B+C+D

C+D

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,

does not assert FAULT).

9.4.5.1 Overload and Short Circuit Current Protection

TPA3221 has fast reacting current sensors on all high-side and low-side FETs. To prevent output current from

increasing beyond the overcurrent threshold, TPA3221 uses current limiting of the output current for each

switching cycle (Cycle By Cycle Current Control, CB3C) in case of excess output current. CB3C prevents

premature shutdown due to high output current transients caused by high level music transients and a drop of

real speaker’s load impedance, and allows the output current to be limited to a maximum programmed level. If

the maximum output current persists, i.e. the power stage being overloaded with too low load impedance, the

device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z) state

until a RESET cycle is initiated. CB3C works individually for each full-bridge output. If an over current event is

triggered, CB3C performs a state flip of the full-bridged output that is cleared upon beginning of next PWM

frame.

26

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

PWM_X

HS PWM

RISING EDGE PWM

SETS CB3C LATCH

LS PWM

OC EVENT RESETS

CB3C LATCH

OC THRESHOLD

OUTPUT CURRENT

OCH

HS GATE-DRIVE

LS GATE-DRIVE

图 48. CB3C Timing Example

9.4.5.2 Signal Clipping and Pulse Injector

A built in activity detector monitors the PWM activity of the OUT_X pins. TPA3221 is designed to drive

unclipped output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying

excessive input signal voltage, or in case of CB3C current protection being active, the amplifier feedback

loop of the audio channel will respond to this condition with a saturated state, and the output PWM signals

will stop unless special circuitry is implemented to handle this situation. To prevent the output PWM signals

from stopping in a clipping or CB3C situation, narrow pulses are injected to the gate drive to maintain output

activity. The injected narrow pulses are injected at every 4^thPWM frame, and thus the effective switching

frequency during this state is reduced to 1/4 of the normal switching frequency.

Signal clipping is signalled on the OTW_CLIP pin and is self clearing when signal level reduces and the

device reverts to normal operation. The OTW_CLIP pulses starts at the onset to output clipping, typically at a

THD level around 0.01%, resulting in narrow OTW_CLIP pulses starting with a pulse width of ~500ns.

图 49. Signal Clipping PWM and Speaker Output Signals

27

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

9.4.5.3 DC Speaker Protection

The output DC protection scheme protects a speaker from excess DC current in case one terminal of the

speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short

circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current

levels. The output DC protection detects any unbalance of the output and input current of a BTL or PBTL output

configuration (current into/out of one half-bridge equals current out of/into the other half-bridge), and in the event

of the unbalance exceeding a programmed threshold, the overload counter increments until its maximum value

and the affected output channel is shut down. DC Speaker Protection is enabled in both BTL and PBTL mode

operation.

9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage in the case that a power output pin

(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent

after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is

performed at startup after RESET is pulled high. When PPSC detection is activated by a short on the output, all

half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence

and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that

there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to

PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The

typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low. If no shorts are

present the PPSC detection passes, and FAULT is released. A device reset will start a new PPSC detection.

PPSC detection is enabled in both BTL and PBTL output configurations. To make sure not to trip the PPSC

detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.

9.4.5.5 Overtemperature Protection OTW and OTE

TPA3221 has a two-level temperature-protection system that asserts an active-low warning signal (OTW_CLIP)

when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds

155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-

impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,

RESET must be asserted. Thereafter, the device resumes normal operation.

9.4.5.6 Undervoltage Protection (UVP), Overvoltage Protection (OVP) and Power-on Reset (POR)

The UVP, OVP and POR circuits of the TPA3221 fully protect the device in any power-up/down, and brownout

situation, and also in overvoltage situation with PVDD not exceeding the values stated in Absolute Maximum

Ratings. While powering up, the POR circuit ensures that all circuits are fully operational when the AVDD supply

voltage reaches the value stated in the Electrical Characteristics table. Although AVDD is independently

monitored, a supply voltage drop below the UVP threshold on AVDD pin results in all half-bridge outputs

immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device

automatically resumes operation when all supply voltages have increased above their UVP threshold. In case of

an OVP event, all half-bridge outputs are immediately set in the high-impedance (Hi-Z) state and FAULT is

asserted low until PVDD is below the OVP threshold.

28

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

9.4.5.7 Fault Handling

If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel

fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and

will assert FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires

resetting the device by toggling RESET. De-asserting RESET should never be allowed with excessive system

temperature, so it is advised to monitor RESET with a system microcontroller and only release RESET (RESET

high) if the OTW_CLIP signal is cleared (high). A channel fault results in shutdown of the PWM activity of the

affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being

present.

表 6. Error Reporting

Fault/Event

Description

Latched/Self

Clearing

Action needed to

Clear

Fault/Event

Global or Channel

Reporting Method

Output FETs

PVDD_X UVP

PVDD_X OVP

AVDD UVP

Increase affected

supply voltage

Voltage Fault

Global

FAULT pin

Self Clearing

HI-Z

POR (AVDD UVP)

Power On Reset

Thermal Warning

Global

FAULT pin

OTW pin

Self Clearing

Allow AVDD to rise

HI-Z

Cool below OTW

threshold

OTW

Normal operation

OTE

Thermal Shutdown

OC Shutdown

Global

FAULT pin

Latched

Toggle RESET

HI-Z

OLP (CB3C>1.7 ms)

Channel

Reduce signal level

or remove short

Flip state, cycle by

cycle at fs/3

CB3C

OC Limiting

Channel

Global

None

Self Clearing

No OSC_IO activity

in Slave Mode

Resume OSC_IO

activity

Stuck at Fault⁽¹⁾

HI-Z

(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics

table of this data sheet.

29

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

TPA3221 can be configured either in stereo BTL, mono BTL or mono PBTL mode depending on output power

conditions and system design.

10.2 Typical Applications

10.2.1 Stereo BTL Application

+5V

470uF

100nF

5.6k

33nF

1

2

3

4

5

6

7

8

9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

VDD

BST1_P

BST1_M

GND

10µH

GAIN/SLV

OTW_CLIP

FAULT

GND

10nF

33nF

/OTW_CLIP

/FAULT

1nF

1µF

GND

3R3

OUT1_P

PVDD

3R3

GND

10nF

GND

1µF

10µH

1µF

470uF

IN1_P

IN1_M

IN1_P

IN1_M

RESET

HEAD

OSCM

OSCP

FREQ_ADJ

IN2_P

IN2_M

CMUTE

GND

PVDD

1µF

PVDD

GND

10

11

12

13

14

15

16

17

18

19

/RESET

OUT1_M

GND

1µF

TPA322x

GND

OUT2_P

PVDD

50k

1µF

10µH

IN2_P

IN2_M

PVDD

1µF 470uF

10nF

1µF

PVDD

1nF

1µF

OUT2_M

GND

3R3

CMUTE

1k

26

25

24

23

3R3

GND

CMUTE

+5V

33nF

20

21

22

10nF

GND

33nF

10µH

AVDD

GVDD

BST2_P

BST2_M

3R3

1µF

33nF

图 50. Typical Differential (2N) AD-Mode BTL Application

30

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

Typical Applications (接下页)

10.2.1.1 Design Requirements

For this design example, use the parameters in 表 7.

表 7. Design Requirements, BTL Application

DESIGN PARAMETER

Low Power Supply

High Power Supply

EXAMPLE

5 V

7 - 30 V

IN1_M = ±2.8V (peak, max)

IN1_P = ±2.8V (peak, max)

IN2_M = ±2.8V (peak, max)

IN2_P = ±2.8V (peak, max)

Inductor-Capacitor Low Pass Filter (10 µH + 1 µF)

3 - 8 Ω

Analog Inputs

Output Filters

Speaker Impedance

10.2.1.2 Detailed Design Procedures

A rising-edge transition on RESET input allows the device to execute the startup sequence and starts switching.

A toggling OTW_CLIP signal is indicating that the output is approaching clipping. The signal can be used either

to decrease audio volume or to control an intelligent power supply nominally operating at a low rail adjusting to a

higher supply rail.

The device inverts the audio signal from input to output.

The AVDD pin is not recommended to be used as a voltage source for external circuitry when internal LDO is

enabled (VDD ≥ 7 V).

10.2.1.2.1 Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good

audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this

application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices.

Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the

selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage

overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple

current created by high power output. A minimum voltage rating of 50 V is required for use with a 30 V power

supply.

10.2.1.2.2 PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These

capacitors should be selected for proper voltage margin and adequate capacitance to support the power

requirements. In practice, with a well designed system power supply, 470 μF, 50 V supports most applications.

The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed

switching.

10.2.1.2.3 BST capacitors

To ensure large enough bootstrap energy storage for the high side gate drive to work correctly with all audio

source signals, 33 nF / 50V X7R BST capacitors are recommended.

10.2.1.2.4 PCB Material Recommendation

FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3221. The use of this

material can provide for higher power output, improved thermal performance, and better EMI margin due to lower

PCB trace inductance.

31

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

10.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)

TPA3221 can be configured in mono PBTL mode by paralleling the outputs before the LC filter or after the LC

filter (see Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)). Paralleled

outputs before the LC filter is recommended for better performance and limiting the number of output LC filter

inductors.

+5V

470uF

100nF

33nF

1

2

3

4

5

6

7

8

9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

VDD

BST1_P

BST1_M

GND

5.6k

GAIN/SLV

OTW_CLIP

FAULT

GND

33nF

/OTW_CLIP

/FAULT

GND

OUT1_P

PVDD

GND

PVDD

GND

1µF

10µH

470uF

IN1_P

IN1_M

IN1_P

IN1_M

RESET

HEAD

OSCM

OSCP

FREQ_ADJ

IN2_P

IN2_M

CMUTE

GND

PVDD

1µF

10nF

PVDD

1nF

10

11

12

13

14

15

16

17

18

19

/RESET

OUT1_M

GND

470nF

1µF

3R3

TPA322x

GND

3R3

OUT2_P

PVDD

10nF

50k

10µH

PVDD

1µF 470uF

PVDD

GND

OUT2_M

GND

CMUTE

1k

26

25

24

23

GND

CMUTE

+5V

33nF

20

21

22

GND

33nF

AVDD

GVDD

BST2_P

BST2_M

3R3

1µF

33nF

图 51. Typical Differential (2N) AD-Mode PBTL Application

10.2.2.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

表 8. Design Requirements, PBTL Application

DESIGN PARAMETER

Low Power Supply

High Power Supply

EXAMPLE

5 V

7 - 30 V

IN1_M = ±2.8 V (peak, max)

IN1_P = ±2.8 V (peak, max)

IN2_M = Grounded

Analog Inputs

IN2_P = Grounded

Output Filters

Inductor-Capacitor Low Pass Filter (10 µH + 1 µF)

2 - 4 Ω

Speaker Impedance

32

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)

TPA3221 can be configured in mono PBTL mode by paralleling the outputs before the LC filter (see Typical

Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)) or after the LC filter.

Paralleled outputs after the LC filter may be preferred if: a single board design must support both PBTL and BTL,

or in the case multiple, smaller paralleled inductors are preferred due to size or cost. Paralleling after the LC filter

requires four inductors, one for each OUT_x. This section shows an example of paralleled outputs after the LC

filter.

+5V

470uF

100nF

33nF

1

2

3

4

5

6

7

8

9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

VDD

BST1_P

BST1_M

GND

10µH

5.6k

GAIN/SLV

OTW_CLIP

FAULT

GND

33nF

/OTW_CLIP

/FAULT

GND

OUT1_P

PVDD

GND

PVDD

GND

1µF

10µH

1µF

IN1_P

IN1_M

IN1_P

IN1_M

RESET

HEAD

OSCM

OSCP

FREQ_ADJ

IN2_P

IN2_M

CMUTE

GND

470uF

PVDD

1µF

10nF

PVDD

1nF

10

11

12

13

14

15

16

17

18

19

/RESET

OUT1_M

GND

1µF

3R3

TPA322x

GND

3R3

OUT2_P

PVDD

10nF

50k

10µH

PVDD

1µF 470uF

PVDD

GND

OUT2_M

GND

CMUTE

1k

26

25

24

23

GND

CMUTE

+5V

33nF

20

21

22

GND

33nF

10µH

AVDD

GVDD

BST2_P

BST2_M

3R3

1µF

33nF

图 52. Typical Differential (2N) AD-Mode PBTL Application

10.2.3.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

表 9. Design Requirements, PBTL Application

DESIGN PARAMETER

Low Power Supply

High Power Supply

EXAMPLE

5 V

7 - 30 V

IN1_M = ±2.8 V (peak, max)

IN1_P = ±2.8 V (peak, max)

IN2_M = Grounded

Analog Inputs

IN2_P = Grounded

Output Filters

Inductor-Capacitor Low Pass Filter (10 µH + 1 µF)

2 - 4 Ω

Speaker Impedance

33

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

11 Power Supply Recommendations

11.1 Power Supplies

The TPA3221 device requires a single external power supply for proper operation. A high-voltage supply, PVDD,

is required to power the output stage of the speaker amplifier and its associated circuitry. PVDD can be used to

supply an internal LDO to supply 5 V to AVDD and GVDD (connect VDD to PVDD).

Additionally, in LDO bypass mode an external power supply should be connected to VDD, AVDD and GVDD to

power the gate-drive and other internal digital and analog circuit blocks in the device.

The allowable voltage range for both the PVDD and VDD/AVDD/GVDD supplies are listed in the Recommended

Operating Conditions table. Ensure both the PVDD and the VDD/AVDD/GVDD supplies can deliver more current

than listed in the Electrical Characteristics table.

11.1.1 VDD Supply

VDD can be connected to PVDD in systems using only a single power supply. VDD is connected to an internal

LDO that is then used to supply AVDD and GVDD for digital and analog circuits as well as to supply the gate

drive.

To reduce device power consumption, the internal LDO can be bypassed by connecting VDD, AVDD and GVDD

to an external 5 V power supply.

Proper connection, routing, and decoupling techniques are highlighted in the TPA3221 device EVM User's Guide

(as well as the Application Information section and Layout Examples section) and must be followed as closely as

possible for proper operation and performance. Deviation from the guidance offered in the TPA3221 device EVM

User's Guide, which followed the same techniques as those shown in the Application Information section, may

result in reduced performance, errant functionality, or even damage to the TPA3221 device. To simplify the

power supply requirements for the system, the TPA3221 device includes a integrated low-dropout (LDO) linear

regulator to create a 5V rail for AVDD and GVDD supplies. The linear regulator is internally connected to the

VDD supply and its output is present on the AVDD pin, providing a connection point for an external bypass

capacitors. It is important to note that the linear regulator integrated in the device has only been designed to

support the current requirements of the internal circuitry, and should not be used to power any additional external

circuitry. Additional loading on these pins could cause the voltage to sag and increase noise injection, which

negatively affects the performance and operation of the device.

11.1.2 AVDD and GVDD Supplies

AVDD and GVDD can be supplied either through the internal LDO or from external 5 V power supply to power

internal analog and digital circuits and the gate-drives for the output H-bridges. Proper connection, routing, and

decoupling techniques are highlighted in the TPA3221 device EVM User's Guide (as well as the Application

Information section and Layout Examples section) and must be followed as closely as possible for proper

operation and performance. Deviation from the guidance offered in the TPA3221 device EVM User's Guide,

which followed the same techniques as those shown in the Application Information section, may result in reduced

performance, errant functionality, or even damage to the TPA3221 device.

11.1.3 PVDD Supply

The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which

provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are

highlighted in the TPA3221 device EVM User's Guide (as well as the Application Information section and Layout

Examples section) and must be followed as closely as possible for proper operation and performance. Due the

high-voltage switching of the output stage, it is particularly important to properly decouple the output power

stages in the manner described in the TPA3221 device EVM User's Guide. The lack of proper decoupling, like

that shown in the EVM User's Guide, can results in voltage spikes which can damage the device, or cause poor

audio performance and device shutdown faults.

34

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

Power Supplies (接下页)

11.1.4 BST Supply

TPA3221 has built-in bootstrap supply for each half bridge gate drive to supply the high side MOSFETs, only

requiring a single capacitor per half bridge. The capacitors are connected to each half bridge output, and are

charged by the GVDD supply via an internal diode while the PWM outputs are in low state. The high side gate

drive is supplied by the voltage across the BST capacitor while the output PWM is high. It is recommended to

place the BST capacitors close to the TPA3221 device, and to keep PCB routing traces at minimum length.

35

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

12 Layout

12.1 Layout Guidelines

•

Use an unbroken ground plane to have good low impedance and inductance return path to the power supply

for power and audio signals.

•

Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as

many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.

•

PCB layout, audio performance and EMI are linked closely together.

Routing the audio input should be kept short and together with the accompanied audio source ground.

The small bypass capacitors on the PVDD lines should be placed as close the PVDD pins as possible.

A local ground area underneath the device is important to keep solid to minimize ground bounce.

Orient the passive component so that the narrow end of the passive component is facing the TPA3221

device, unless the area between two pads of a passive component is large enough to allow copper to flow in

between the two pads.

•

Avoid placing other heat producing components or structures near the TPA3221 device.

Avoid cutting off the flow of heat from the TPA3221 device to the surrounding ground areas with traces or via

strings, especially on output side of device.

36

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

12.2 Layout Examples

12.2.1 BTL Application Printed Circuit Board Layout Example

T3

T1

1

2

44

43

42

41

40

39

38

37

T2

3

4

5

6

7

8

T2

9

36

35

34

33

32

31

30

29

28

27

26

25

24

23

10

11

12

13

14

15

16

17

18

19

20

21

22

T2

T1

T3

System Processor

Bottom to top layer connection via

Bottom Layer Signal Traces

Pad to top layer ground pour

Top Layer Signal Traces

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer

copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)

B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat

sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without

going through vias. No vias or traces should be blocking the current path.

C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

D. Note T3: Heat sink needs to have a good connection to PCB ground.

图 53. BTL Application Printed Circuit Board - Composite

37

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

Layout Examples (接下页)

12.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example

T3

T1

1

2

44

43

42

41

40

39

38

37

T2

3

4

5

6

7

8

T2

9

36

35

34

33

32

31

30

29

28

27

26

25

24

23

10

11

12

T2

13

14

15

16

17

18

19

20

21

22

T2

T1

T3

System Processor

Bottom to top layer connection via

Bottom Layer Signal Traces

Pad to top layer ground pour

Top Layer Signal Traces

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer

copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)

B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat

sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without

going through vias. No vias or traces should be blocking the current path.

C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

D. Note T3: Heat sink needs to have a good connection to PCB ground.

图 54. PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board - Composite

38

TPA3221

www.ti.com.cn

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

Layout Examples (接下页)

12.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example

T3

T1

1

2

44

43

42

41

40

39

38

37

T2

3

4

5

6

7

8

T2

9

36

35

34

33

32

31

30

29

28

27

26

25

24

23

10

11

12

T2

13

14

15

16

17

18

19

20

21

22

T2

T1

T3

System Processor

Bottom to top layer connection via

Bottom Layer Signal Traces

Pad to top layer ground pour

Top Layer Signal Traces

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer

copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)

B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat

sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without

going through vias. No vias or traces should be blocking the current path.

C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

D. ote T3: Heat sink needs to have a good connection to PCB ground.

图 55. PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board - Composite

39

TPA3221

ZHCSH28B –SEPTEMBER 2017–REVISED DECEMBER 2017

www.ti.com.cn

13 器件和文档支持

13.1 文档支持

•

TPA3220 评估模块用户指南

TPA3221 和 TPA3220 安装指南和配置工具

TPA32xx 放大器的多器件配置

13.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录

13.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

13.4 商标

E2E is a trademark of Texas Instruments.

Wi-Fi is a trademark of Wi-Fi Alliance.

All other trademarks are the property of their respective owners.

13.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

40

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPA3221DDVR

HTSSOP DDV

44

2000

330.0

24.4

8.6

15.6

1.8

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DDV 44

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TPA3221DDVR

2000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DDV HTSSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TPA3221DDV

44

35

530

11.89

3600

4.9

Pack Materials-Page 3

PACKAGE OUTLINE

DDV0044D

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

1

.

2

5

0

PLASTIC SMALL OUTLINE

C

8.3

7.9

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

42X 0.635

44

1

2X (0.3)

NOTE 6

14.1

13.9

NOTE 3

2X

13.335

7.30

6.72

EXPOSED

THERMAL

PAD

(0.15) TYP

NOTE 6

2X (0.6)

NOTE 6

23

22

0.27

0.17

44X

4.43

3.85

0.08

C A B

6.2

6.0

B

(0.15) TYP

0.25

1.2

1.0

GAGE PLANE

SEE DETAIL A

0.75

0.50

0.15

0.05

0 - 8

DETAIL A

TYPICAL

4218830/A 08/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. The exposed thermal pad is designed to be attached to an external heatsink.

6. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DDV0044D

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

SEE DETAILS

SYMM

44X (1.45)

44X (0.4)

1

44

42X (0.635)

SYMM

(R0.05) TYP

23

22

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

0.05 MIN

AROUND

0.05 MAX

AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4218830/A 08/2016

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDV0044D

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

44X (1.45)

44X (0.4)

SYMM

1

44

42X (0.635)

SYMM

23

22

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE :6X

4218830/A 08/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

10. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPA3221
厂家：	TEXAS INSTRUMENTS
描述：	具有低空闲电流的 100W 立体声、200W 单声道、7V 至 32V 电源电压、模拟输入 D 类音频放大器放大器音频放大器
文件：	总50页 (文件大小：2251K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPA3221 [TI]

相关型号：

TPA3221DDV

TPA3221DDVR

TPA3223

TPA3223DDVR

TPA3244

TPA3244DDW

TPA3244DDWR

TPA3245

TPA3245DDV

TPA3245DDVR

TPA3250

TPA3250D2DDW