TPD3S014TDBVRQ1 [TI]
适用于汽车 USB 主机端口的限流开关和 D+/D- ESD 保护器件 | DBV | 6 | -40 to 105;
| 型号： | TPD3S014TDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于汽车 USB 主机端口的限流开关和 D+/D- ESD 保护器件 | DBV | 6 | -40 to 105 开关 |
| 文件： | 总28页 (文件大小：2385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD3S014-Q1
ZHCSEX2C –MARCH 2016 –REVISED AUGUST 2020
TPD3S014-Q1 适用于汽车USB 主机端口的限流开关和D+/D– ESD 保护
1 特性
3 说明
• 符合AEC-Q100 标准（2 级）
– 环境温度范围：-40°C 至+105°C
• 提供功能安全
TPD3S014-Q1 是一款集成器件，具有一个限流负载开
关和一个基于双通道瞬态电压抑制器 (TVS)、用于
USB 接口的静电放电(ESD) 保护二极管阵列。
– 可帮助进行功能安全系统设计的文档
• 持续电流额定值为0.5A
• 固定的恒流限值为0.85A（典型值）
• 快速过流响应–2μs
• 集成输出放电
• 反向电流阻断
• 短路保护
• 带有自动重启的过热保护
• 内置软启动
TPD3S014-Q1 器件适用于很可能出现大容性负载和短
路情况的 USB 等应用，可提供短路保护和过流保护。
当输出负载超过电流限制阈值时，TPD3S014-Q1 通过
在恒定电流模式下运行即可将输出电流限制到安全水
平。快速过载响应特性有助于减轻 5V 主电源的负担，
当输出短路时可以快速调节电源。电流限制开关的上升
和下降此时受到控制，力求尽量减小器件开关过程中的
浪涌电流。
• IEC 61000-4-2 4 级静电放电(ESD) 保护（外部引
脚）
TPD3S014-Q1 支持 0.5A 的持续电流。TVS 二极管阵
列的额定 ESD 冲击消散值高于 IEC 61000-4-2 国际标
准中规定的最高水平。
– ±12kV 接触放电(IEC 61000-4-2)
– ±15kV 空气间隙放电(IEC 61000-4-2)
• ISO 10605 330pF，330Ω ESD 保护（外部引脚）
此器件高度集成，并且采用易于布线的 DBV 封装，可
对音响主机、USB 集线器和媒体接口等应用中的 USB
接口提供强力的电路保护。
– ±8kV 接触放电
– ±15kV 气隙放电
• 6 引脚小外形尺寸晶体管(SOT)-23 封装(2.90mm
× 1.60mm)
器件信息(1)
封装尺寸（标称值）
器件型号
封装
SOT-23 (6)
TPD3S014-Q1
2.90mm × 1.60mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 终端设备：
– 音响主机
– 后座娱乐系统
– 远程信息处理
– USB 集线器
– 导航模块
• 接口：
– USB 2.0
– USB 3.0
From Processor
5 V Source
TPD3S014œQ1
OUT
EN
IN
150 ꢀF
0.1 ꢀF
USB Port
VBUS
D-
D1
D2 GND
USB Transceiver
D+
GND
Copyright © 2016, Texas Instruments Incorporated
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDG5
TPD3S014-Q1
ZHCSEX2C –MARCH 2016 –REVISED AUGUST 2020
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................18
11 Layout...........................................................................18
11.1 Layout Guidelines................................................... 18
11.2 Layout Example...................................................... 18
11.3 Power Dissipation and Junction Temperature.........18
12 Device and Documentation Support..........................21
12.1 Documentation Support.......................................... 21
12.2 支持资源..................................................................21
12.3 Trademarks.............................................................21
12.4 静电放电警告.......................................................... 21
12.5 术语表..................................................................... 21
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—AEC Specification...............................4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 ESD Ratings—ISO Specification................................ 4
6.5 Recommended Operating Conditions.........................4
6.6 Thermal Information....................................................5
6.7 Electrical Characteristics: TJ = TA = 25°C...................5
6.8 Electrical Characteristics: –40°C ≤TA ≤105°C......6
6.9 Typical Characteristics................................................7
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
Information.................................................................... 21
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (April 2016) to Revision C (August 2020)
Page
• 向特性部分添加了功能安全链接........................................................................................................................ 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
Changes from Revision A (April 2016) to Revision B (April 2016)
Page
• 更改了电气特性：–40°C ≤TA ≤105°C 表将TA 从125°C 更改为105°C.......................................................1
• 将功率耗散和结温部分中的温度从125°C 更改为105°C...................................................................................1
Changes from Revision * (March 2016) to Revision A (April 2016)
Page
• 将器件状态从产品预发布更改为量产数据.........................................................................................................1
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5 Pin Configuration and Functions
EN
1
2
6
5
D2
D1
GND
IN
3
4
OUT
图5-1. DBV Package 6-Pin SOT-23 Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
D1
NO.
5
I/O
USB data+ or USB data–
D2
6
EN
1
I
Enable input, logic high turns on power switch
Ground
GND
2
—
Input voltage and power-switch drain; Connect a 0.1-µF or greater ceramic capacitor
from IN to GND close to the IC
IN
3
4
I
OUT
O
Power-switch output, connect to load
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VIN
VOUT
EN
D1
6
6
6
6
6
6
–0.3
–0.3
–0.3
–0.3
–0.3
–6
Input voltage(3)
V
D2
Voltage from VIN to VOUT
Junction temperature
Storage temperature
V
TJ
Internally limited
Tstg
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Voltages are with respect to GND unless otherwise noted.
(3) See the Input and Output Capacitance section.
6.2 ESD Ratings—AEC Specification
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
Contact discharge(1)
Air-gap discharge(1)
±12000
±15000
V(ESD)
Electrostatic discharge
IEC 61000-4-2, VOUT, Dx pins
V
(1) VOUT was tested on a PCB with input and output bypassing capacitors of 0.1 µF and 120 µF, respectively.
6.4 ESD Ratings—ISO Specification
VALUE
±8000
UNIT
Contact discharge(1)
ISO 10605 330 pF, 330 Ω,
VOUT, Dx pins
V(ESD)
Electrostatic discharge
V
Air-gap discharge(1)
±15000
(1) VOUT was tested on a PCB with input and output bypassing capacitors of 0.1 µF and 120 µF, respectively.
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
0
MAX
5.5
UNIT
V
VIN
VEN
VIH
VIL
Input voltage
Input voltage, EN
5.5
V
High-level Input voltage, EN
Low-level Input voltage, EN
Input decoupling capacitance, IN to GND
Continuous output current (TPD3S014-Q1)
Operating junction temperature
2
V
0.7
V
CIN
IOUT
TJ
0.1
µF
A
(1)
0.5
125
°C
–40
(1) Package and current ratings may require an ambient temperature derating of 85°C
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6.6 Thermal Information
TPD3S014-Q1
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
185.8
124.7
32.0
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
See the Power Dissipation and Junction Temperature section
23.7
ψJT
31.5
ψJB
RθJC(bot)
N/A
RθJA (Custom)
120.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics: TJ = TA = 25°C
VIN = 5 V, VEN = VIN, IOUT = 0 A (unless otherwise noted). Parameters over a wider operational range are shown in Electrical
Characteristics: –40°C ≤TA ≤105°C table.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
mΩ
A
POWER SWITCH
97
97
120
140
RDS(on)
Input –Output resistance
–40°C ≤(TJ, TA) ≤+85°C
CURRENT LIMIT
(2)
IOS
0.67
0.85
0.02
1.01
Current limit, see 图8-3
SUPPLY CURRENT
IOUT = 0 A
1
2
ISD
Supply current, switch disabled
µA
µA
µA
–40°C ≤(TJ, TA) ≤+85°C, VIN = 5.5 V, IOUT
=
=
0 A
IOUT = 0 A
66
74
85
1
ISE
Supply current, switch enabled
Reverse leakage current
–40°C ≤(TJ, TA) ≤+85°C, VIN = 5.5 V, IOUT
0 A
VOUT = 5 V, VIN = 0 V, Measure IVOUT
0.2
IREV
–40°C ≤(TJ, TA) ≤+85°C, VOUT = 5 V, VIN = 0
V, Measure IVOUT
5
OUTPUT DISCHARGE
RPD
Output pull-down resistance(3)
VIN = VOUT = 5 V, disabled
400
456
600
Ω
ESD PROTECTION
Differential capacitance between
the D1, D2 lines
0.02
pF
pF
ΔCIO
ƒ= 1 MHz, VIO = 2.5 V
CIO
(D1, D2 to GND)
1.4
0.2
0.2
ƒ= 1 MHz, VIO = 2.5 V
Dx to GND
Ω
Ω
Dynamic on-resistance D1, D2
IEC clamps(4)
RDYN
GND to Dx
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) See the Current Limit for explanation of this parameter.
(3) These Parameters are provided for reference only, and do not constitute a part of TI’s published device specifications for purposes of
TI’s product warranty.
(4) RDYN was extracted using the least squares first of the TLP characteristics between I = 20 A and I = 30 A.
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6.8 Electrical Characteristics: –40°C ≤TA ≤105°C
4.5 V ≤VIN ≤5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C (unless otherwise noted)
PARAMETER
POWER SWITCH
RDS(on)
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
97
164
2
Input –output resistance
mΩ
ENABLE INPUT (EN)
Threshold
Input rising
VEN = 0 V
1
1.45
0.13
0
V
V
Hysteresis
Leakage current
1
µA
–1
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑
See 图8-2
tON
Turnon time
1
1.6
2.1
2.2
ms
ms
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓
See 图8-2
tOFF
Turnoff time
1.7
2.7
tR
tF
Rise time, output
Fall time, output
0.4
0.64
0.4
0.9
0.8
ms
ms
CL = 1 µF, RL = 100 Ω, VIN = 5 V, See 图8-1
CL = 1 µF, RL = 100 Ω, VIN = 5 V, See 图8-1
0.25
CURRENT LIMIT
(2)
IOS
0.65
0.85
2
1.05
A
Current limit, see 图8-3
VIN = 5 V (see 图8-3)
One Half full load →RSHORT = 50 mΩMeasure
from application to when current falls below
120% of final value
tIOS
Short-circuit response time(2)
µs
SUPPLY CURRENT
ISD
Supply current, switch disabled
IOUT = 0 A
0.02
66
10
94
20
µA
µA
µA
ISE
Supply current, switch enabled
Reverse leakage current
IOUT = 0 A
IREV
VOUT = 5.5 V, VIN = 0 V, Measure IVOUT
0.2
UNDERVOLTAGE LOCKOUT
VUVLO
Rising threshold
Hysteresis
3.5
3.77
0.14
4
V
V
VIN↑
VIN↓
OUTPUT DISCHARGE
VIN = 4 V, VOUT = 5 V, Disabled
VIN = 5 V, VOUT = 5 V, Disabled
350
300
545
456
1200
800
RPD
Output pull-down resistance
Ω
THERMAL SHUTDOWN
In current limit
135
155
TSHDN
Rising threshold (TJ)
°C
°C
Not in current limit
Hysteresis(3)
ESD PROTECTION
20
II
Input leakage current (D1, D2)
VI = 3.3 V
IO = 8 mA
IBR = 1 mA
0.02
1
µA
V
Diode forward voltage (D1, D2);
Lower clamp diode
VD
VBR
0.95
Breakdown voltage (D1, D2)
6
V
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) See the Current Limit section for explanation of this parameter.
(3) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of
TI’s product warranty.
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6.9 Typical Characteristics
7.5
7
1.5
1.4
1.3
1.2
1.1
1
7.5
7
1.5
IN
IN
1.4
1.3
1.2
1.1
1
OUT
EN
IOUT
OUT
EN
IOUT
6.5
6
6.5
6
5.5
5
5.5
5
4.5
4
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4.5
4
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-6
-4
-2
0
2
4 6
Time (ms)
8
10 12 14 16
-6
-4
-2
0
2
4 6
Time (ms)
8
10 12 14 16
D001
D001
图6-1. Turn ON into 10 Ω
图6-2. Enable into Short
7.5
7
1.2
7.5
7
56
52
48
IN
IN
OUT
IOUT
1.12
1.04
0.96
0.88
0.8
CIN = 300 mF, COUT = 150 mF
OUT
EN
IOUT
6.5
6
6.5
6
44
40
36
32
28
24
20
16
12
8
5.5
5
5.5
5
4.5
4
0.72
0.64
0.56
0.48
0.4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
0.32
0.24
0.16
0.08
0
1.5
1
1.5
1
4
0.5
0
-10
0.5
0
-4
0
-4
-5
0
5
10 15
Time (ms)
20
25
30
35
-2
0
2
4
6
Time (µs)
8
10 12 14 16 18
D001
D001
图6-3. Pulsed Output Short
图6-4. Short Applied
7
6
14
-40°C
25°C
85°C
VIN = 5 V
12
10
8
5
125°C
4
3
6
2
4
1
2
0
0
-1
-40
-20
0
20
40
60
80
100 120 140
-2
Junction Temperature (èC)
D007
0
0.5
1
1.5
2
2.5
3
Output Voltage (V)
3.5
4
4.5
5
D001
图6-5. Reverse Leakage Current (IREV) vs
图6-6. Output Discharge Current vs Output
Temperature
Voltage
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0.5
0.475
0.45
0.425
0.4
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.375
0.35
0.325
0.3
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temprature (èC)
D027
Junction Temprature (èC)
D026
图6-8. Output Fall Time (tF) vs Temperature
图6-7. Short Circuit Current (IOS) vs Temperature
0.8
2.8
All Unit Types
2.4
0.75
0.7
2
1.6
1.2
0.8
0.4
0
0.65
0.6
0.55
-0.4
0.5
-0.8
-40
-20
0
20
40
60
Junction Temprature (°C)
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temprature (èC)
D028
D001
图6-9. Output Rise Time (tR) vs Temperature
图6-10. Disabled Supply Current (ISD) vs
Temperature
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
4
-40 (°C)
25 (°C)
85 (°C)
125 (°C)
-40 (èC)
All Unit Types
All Unit Types, VIN = 0 V
3.5
25 (èC)
85 (èC)
125 (èC)
3
2.5
2
1.5
1
0.5
0
-0.2
-0.5
4
4.2
4.4
4.6
4.8
Input Voltage (V)
5
5.2
5.4
5.6
4
4.2
4.4
4.6
Output Voltage (V)
4.8
5
5.2
5.4
5.6
D001
D001
图6-11. Disabled Supply Current (ISD) vs Input
图6-12. Reverse Leakage Current (IREV) vs Output
Voltage
Voltage
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72
85
80
75
70
65
60
55
50
45
-40 (°C)
All Unit Types, VIN = 5.5 V
All Unit Types
25 (°C)
85 (°C)
125 (°C)
70
68
66
64
62
60
58
56
-40
-20
0
20
40
60
80
100 120 140
4
4.2
4.4
4.6
4.8
Input Voltage (V)
5
5.2
5.4
5.6
Junction Temprature (èC)
D001
D001
图6-13. Enabled Supply Current (ISE) vs
图6-14. Enabled Supply Current (ISE) vs Input
Temperature
Voltage
35
35
32.5
30
32.5
30
27.5
25
27.5
25
22.5
20
22.5
20
17.5
15
17.5
15
12.5
10
12.5
10
7.5
5
7.5
5
2.5
0
2.5
0
0
2
4
6
8
10
Voltage (V)
12
14
16
18
20
0
0.8 1.6 2.4 3.2 4 4.8 5.6 6.4 7.2
Voltage (V)
8
D001
D001
图6-15. D1/D2 Positive TLP Curve
图6-16. D1/D2 Negative TLP Curve
1
0.8
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
20
10
0
D1/D2 Pins
-0.2
-0.4
-0.6
-0.8
-1
-10
-2 -1
0
1
2
3
4
5
6
Voltage (V)
7
8
9 10 11 12 13 14
-25
0
25
50
75 100 125 150 175 200 225
Time (ns)
D001
D001
图6-17. D1/D2 I-V Curve
图6-18. D1/D2 IEC 61000-4-2 8-kV Contact
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20
10
D1/D2 Pins
0
-10
-20
-30
-40
-50
-60
-70
-80
-25
0
25
50
75
Time (ns)
100
125
150
175
D001
图6-19. D1/D2 IEC 61000-4-2 –8-kV Contact
7 Parameter Measurement Information
IOUT
VOUT
RLOAD
VIN
IN
OUT
150 µF
0.1 µF1
Enable
Signal
EN
D1
D2
GND
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A. During the short applied tests, 300 µF is used because of the use of an external supply.
图7-1. Test Circuit for System Operation
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8 Detailed Description
8.1 Overview
The TPD3S014-Q1 is a highly integrated device that features a current limited load switch and a two-channel
TVS based ESD protection diode array for USB interfaces. The TPD3S014-Q1 provides 0.5 A of continuous load
current in 5 V circuits. This part uses N-channel MOSFETs for low resistance, maintaining voltage regulation to
the load. It is designed for applications where short circuits or heavy capacitive loads will be encountered.
Device features include enable, reverse blocking when disabled, output discharge pull-down, over-current
protection, and over-temperature protection. Finally, with two channels of TVS ESD protection diodes integrated,
the TPD3S014-Q1 provides system level ESD protection to all the pins of the USB port.
8.2 Functional Block Diagram
Back
Gate
Control
IN
Current
Limit
OUT
UVLO
Thermal
Sense
Control Logic
+
Charge
Pump
EN
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8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The UVLO circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in
hysteresis prevents unwanted on and off cycling becuase of input voltage drop from large current surges.
8.3.2 Enable
The logic enable input (EN) controls the power switch, bias for the charge pump, driver, and other circuits. The
supply current is reduced to less than 1 µA when the TPD3S014-Q1 is disabled. The enable input is compatible
with both TTL and CMOS logic levels.
The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times
are internally controlled. The rise time is controlled by both the TPD3S014-Q1 and the external loading
(especially capacitance). The TPD3S014-Q1 fall time is controlled by the loading (R and C), and the output
discharge (RPD). An output load consisting of only a resistor experiences a fall time set by the TPD3S014-Q1. An
output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant if it is
longer than the TPD3S014-Q1 tF. See 图 8-1 and 图 8-2 showing tR, tF, tON, and tOFF. The enable must not be
left open; it may be tied to VIN.
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90%
10%
VEN
50%
tON
50%
tR
tF
VOUT
tOFF
图8-1. Power-On and Power-Off Timing
90%
VOUT
10%
图8-2. Enable Timing, Active-High Enable
8.3.3 Internal Charge Pump
The TPD3S014-Q1 incorporates an internal charge pump and gate drive circuitry necessary to drive the N-
channel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage
to pull the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall
times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-
start functionality. The MOSFET power switch blocks current from OUT to IN when turned off by the UVLO or
disabled.
8.3.4 Current Limit
The TPD3S014-Q1 responds to overloads by limiting output current to the static current-limit (IOS) levels shown
in the Electrical Characteristics: TJ = TA = 25°C table. When an overload condition is present, the device
maintains a constant output current, with the output voltage determined by (IOS × RLOAD). Two possible overload
conditions can occur.
The first overload condition occurs when either:
1. The input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS
)
or
2. The input voltage is present and the TPD3S014-Q1 is enabled into a short circuit.
The output voltage is held near zero potential with respect to ground and the TPD3S014-Q1 ramps the output
current to IOS. The TPD3S014-Q1 limits the current to IOS until the overload condition is removed or the device
begins to thermal cycle. The device subsequently cycles current off and on as the thermal protection engages.
The second condition is when an overload occurs while the device is enabled and fully turned on. The device
responds to the overload condition within tIOS when the specified overload (per Electrical Characteristics: TJ = TA
= 25°C, Electrical Characteristics: –40°C ≤ TA ≤ 105°C tables) is applied (See 图 8-3 and 图 8-4). The
response speed and shape varies with the overload level, input circuit, and rate of application. The current-limit
response varies between simply settling to IOS, or turnoff and controlled return to IOS. Similar to the previous
case, the TPD3S014-Q1 limits the current to IOS until the overload condition is removed or the device begins to
thermal cycle.
IOUT
VIN
Decreasing
Load
120% x IOS
Slope = -RDS(ON)
Resistance
IOS
0 A
tIOS
0 V
图8-3. Output Short Circuit Parameters
0 A
IOUT
IOS
图8-4. Output Characteristic Showing Current
Limit
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The TPD3S014-Q1 thermal cycles if an overload condition is present long enough to activate thermal limiting in
any of the cases shown in 图 8-3 and 图 8-4. This is because of the relatively large power dissipation [(VIN –
VOUT) × IOS] driving the junction temperature up. The devices turn off when the junction temperature exceeds
135°C (minimum) while in current limit. The devices remains off until the junction temperature cools down to
20°C and then restarts.
There are two kinds of current limit profiles typically available in TI switch products similar to the TPD3S014-Q1.
Many older designs have an output I vs V characteristic similar to the plot labeled "Current Limit with Peaking" in
图 8-5. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the short
circuit current (IOS). IOC is often specified as a maximum value. The TPD3S014-Q1 part does not present
noticeable peaking in the current limit, corresponding to the characteristic labeled "Flat Current Limit" in 图 8-5.
This is why the IOC parameter is not present in the Electrical Characteristics: TJ = TA = 25°C, Electrical
Characteristics: –40°C ≤TA ≤105°C tables.
Current Limit
with Peaking
Flat Current
Limit
VIN
VIN
Decreasing
Load
Decreasing
Load
Slope = -RDS(ON)
Slope = -RDS(ON)
Resistance
Resistance
0 V
0 V
0 A
0 A
IOUT
IOUT
IOS IOC
IOS
图8-5. Current Limit Profiles
8.3.5 Output Discharge
A 470 Ω (typical) output discharge resistance dissipates stored charge and leakage current on OUT when the
TPD3S014-Q1 is in UVLO or disabled. The pull-down circuit loses bias gradually as VIN decreases, causing a
rise in the discharge resistance as VIN falls towards 0 V.
8.3.6 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized
for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor between IN and
GND is recommended as close to the device as possible for local noise decoupling.
All protection circuits such as the TPD3S014-Q1 has the potential for input voltage overshoots and output
voltage undershoots.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high
impedance (before turnon). Theoretically, the peak voltage is 2 times the applied. The second cause is because
of the abrupt reduction of output short circuit current when the TPD3S014-Q1 turns off and energy stored in the
input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as
the TPD3S014-Q1 output is shorted. Applications with large input inductance (for example, connecting the
evaluation board to the bench power-supply through long cables) may require large input capacitance reduce
the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current-limit speed
of the TPD3S014-Q1 to hard output short circuits isolates the input bus from faults. However, ceramic input
capacitance in the range of 1 µF to 22 µF adjacent to the TPD3S014-Q1 input aids in both speeding the
response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are
permitted.
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Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred
and the TPD3S014-Q1 has abruptly reduced OUT current. Energy stored in the inductance drives the OUT
voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a
cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing
USB standard applications, a 120-µF minimum output capacitance is required. Typically a 150- µF electrolytic
capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require
120 µF of capacitance, and there is potential to drive the output negative, a minimum of 10-µF ceramic
capacitance on the output is recommended. The voltage undershoot must be controlled to less than 1.5 V for 10
µs.
8.4 Device Functional Modes
8.4.1 Operation With VIN < 4 V (Minimum VIN)
These devices operate with input voltages above 4 V. The maximum UVLO voltage on IN is 4 V and the devices
will operate at input voltages above 4 V. Any voltage below 4 V may not work with these devices. The minimum
UVLO is 3.5 V, so some devices may work between 3.5 V and 4 V. At input voltages below the actual UVLO
voltage, these devices will not operate.
8.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.45 V typical and 2 V maximum. With EN held below that voltage
the device is disabled and the load switch will be open. The IC quiescent current is reduced in this state. When
the EN pin is above its rising edge threshold and the input voltage on the IN pin is above its UVLO threshold, the
device becomes active. The load switch is closed, and the current limit feature is enabled. The output voltage on
OUT ramps up with the soft start value TON in order to prevent large inrush current surges on VBUS because of a
heavy capacitive load. When EN voltage is lowered below is falling edge threshold, the device output voltage
also ramps down with soft turnoff value TOFF to prevent large inductive voltages being presented to the system in
the case a large load current is following through the device.
8.4.3 Operation of Level 4 IEC 61000-4-2 ESD Protection
Regardless of which functional mode the devices are in, the TPD3S014-Q1 provides Level 4 IEC 61000-4-2
ESD Protection on the pins of the USB connector.
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9 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPD3S014-Q1 is a device that features a current limited load switch and a two-channel TVS based ESD
protection diode array. It is typically used to provide a complete protection solution for USB host ports. USB host
ports are required by the USB specification to provide a current limit on the VBUS path in order to protect the
system from overcurrent conditions on the port that could lead to system damage and user injury. Additionally,
USB ports typically require system level IEC ESD protection because of direct end-user interaction. The
following design procedure can be used to determine how to properly implement the TPD3S014-Q1 in your
systems to provide a complete, one-chip solution for your USB ports.
9.2 Typical Application
From Processor
5 V Source
TPD3S014œQ1
OUT
EN
IN
150 ꢀF
0.1 ꢀF
USB Port
VBUS
D-
D1
D2 GND
USB Transceiver
D+
GND
Copyright © 2016, Texas Instruments Incorporated
图9-1. USB2.0 Application Schematic
9.2.1 Design Requirements
For this design example, design parameters shown in 表9-1 are used.
表9-1. Design Parameters
DESIGN PARAMETER
VALUE
Standard downstream port
0 V to 5.25 V
USB port type
Signal voltage range on VBUS
Current range on VBUS
0 mA to 500 mA
0 V to 0.7 V(1)
2 V to 5.5 V(1)
330 mV
Drive EN low (disabled)
Drive EN high (enabled)
Maximum voltage droop allowed on adjacent USB port
Maximum data rate
480 Mbps
(1) If active low logic is desired, see the Implementing Active Low Logic section.
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9.2.2 Detailed Design Procedure
To properly implement your USB port with the TPD3S014-Q1, the first step is to determine what type of USB port
is implemented in the system, whether it be a Standard Downstream Port (SDP), Charging Downstream Port
(CDP), or Dedicated Charging Port (DCP); this informs us what maximum continuous operating current will be
on VBUS. In our example, we are implementing an SDP port, so the maximum continuous current allowed to be
pulled by a device is 500 mA. Therefore, we must choose a current limit switch that is 5.25 V tolerant, can
handle 500 mA continuous DC current, and has a current limit point is above 500 mA so it will not current limit
during normal operation. The TPD3S014-Q1 is therefore the best choice for this application, as it has these
features, and in fact was specifically designed for this application.
The next decision point is choosing the input and output capacitors for the current limit switch. A minimum of 0.1
µF is always recommended on the IN pin. For the OUT pin on VBUS, USB standard requires a minimum of 120
µF; typically a 150 µF capacitor is used. The purpose of the capacitance requirement on the VBUS line in the
USB specification is to prevent the adjacent USB port's VBUS voltage from dropping more than 330 mV during a
hot-plug or fault occurrence on the VBUS pin of one USB port. Hot-plugs and fault conditions on one USB port
must not disturb the normal operation of an adjacent USB port; therefore, it is possible to use an output
capacitance lower than 120 µF if the system is able to keep voltage droops on adjacent USB ports less than or
equal to 330 mV. For example, if the DC/DC powering VBUS has a fast transient response, 120 µF may not be
required.
If the USB port is powered from a shared system 5 V rail, a system designer may desire to use an input
capacitor larger than 0.1 µF on the IN pin. This is largely dependent on the PCB layout and parasitics, as well as
your maximum tolerated voltage droop on the shared rail during transients. For more information on choosing
input and output capacitors, see the Input and Output Capacitance section.
The EN pin controls the on and off state of the device, and typically is connected to the system processor for
power sequencing. However, the EN pin can also be shorted to the IN pin to always have the TPD3S014-Q1 on
when 5 V power supply on; this also saves a GPIO pin on your processor.
For a USB port with High-Speed 480 Mbps operation, low capacitance TVS ESD protection diodes are required
to protect the D+ and D– lines in the event of system level ESD event. The TPD3S014-Q1 has 2-channels of
low capacitance TVS ESD protection diodes integrated. When placed near the USB connector, the TPD3S014-
Q1 offers little or no signal distortion during normal operation. The TPD3S014-Q1 also ensures that the core
system circuitry is protected in the event of an ESD strike. PCB layout is critical when implementing TVS ESD
protection diodes in your system. See the Layout section for proper guidelines on routing your USB lines with the
TPD3S014-Q1.
9.2.3 Implementing Active Low Logic
For active low logic, a transistor can be used with the TPD3S014-Q1 EN Pin. 图 9-2 shows how to implement
Active low logic for EN pin.
Using an nFET transistor, when the Processor sends a low signal, the transistor is switched off, and VLOGIC pulls
up EN through R1. When the Processor sends a “high”signal, the nFET is switched on and sinks current from
the EN Pin and R1. For 5 V VLOGIC, with the appropriate on-resistance (RON) value in the nFET and resistance
for R1, the VIL for EN can be met. For example, with a transistor with RON of 3 Ω, a pull-up resistor as low as 11
Ω provides a logic level of 0.7 V. For power-budgeting concerns, a better choice is R1 of 40 kΩ which provides
0.25 V for EN when the Processor asserts high, and 4.96 V when the Processor asserts low.
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VLOGIC
R1
40 kΩ
TPD3S014-Q1
EN
Processor
EN_Out
Copyright © 2016, Texas Instruments Incorporated
图9-2. Implementing Active Low Logic for EN Pin
9.2.4 Application Curves
图9-3. Eye-Diagram Without EVM
图9-4. Eye-Diagram With EVM, Without TPD3S014-
Q1
图9-5. Eye-Diagram of TPD3S014-Q1 on EVM
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10 Power Supply Recommendations
The TPD3S014-Q1 is designed to operate from a 5-V input voltage supply. This input must be well regulated. If
the input supply is located more than a few inches away from the TPD3S014-Q1, additional bulk capacitance
may be required in addition to the recommended minimum 0.1-µF bypass capacitor on the IN pin to keep the
input rail stable during fault events.
11 Layout
11.1 Layout Guidelines
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
GND
D+
D-
EN
GND
IN
D2
D1
OUT
Top Layer GND Plane
VBUS
Via
图11-1. USB2.0 Type A TPD3S014-Q1 Board Layout
11.3 Power Dissipation and Junction Temperature
anged Temperature from 125°C to 105°C in Power Dissipation and Junction Temperature section
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It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPD3S014-Q1. The system designer can control choices of the devices proximity to other power dissipating
devices and printed circuit board (PCB) design based on these calculations. These have a direct influence on
maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often
determined by system considerations. It is important to remember that these calculations do not include the
effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around
these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low
as practical. In particular, connect the GND pin to a large ground plane for the best thermal dissipation. The
following PCB layout example in 图 11-2 was used to determine the RθJA Custom thermal impedances noted in
the Thermal Information table. It is based on the use of the JEDEC high-k circuit board construction with 4, 1 oz.
copper weight layers (2 signal and 2 plane).
GND
D+
D-
EN
GND
IN
D2
D1
OUT
V
BUS
OUT: W: 10.424 mm, H:4.536 mm, A: 47.28 mm2
GND: W: 6.57 mm, H: 7.53 mm, A: 49.47 mm2
& 6 x 0.879 mm diameter vias
IN: W: 4.26 mm
H: 5.82 mm
A: 24.79 mm2
& 4 x 0.879 mm
diameter vias
GND: W: 4.44 mm, H: 4.00 mm, A: 17.76 mm2
& 2 x 0.533 mm diameter vias
图11-2. PCB Layout Example
The following procedure requires iteration a power loss is because of the internal MOSFET I2 × RDS(ON), and
RDS(ON) is a function of the junction temperature. See 方程式 1. As an initial estimate, use the RDS(ON) at 105°C
from the Typical Characteristics, and the preferred package thermal resistance for the preferred board
construction from the Thermal Information table.
TJ = TA + [(IOUT 2 × RDS(ON)) × RθJA
]
(1)
where
• IOUT = Rated OUT pin current (A)
• RDS(ON) = Power switch on-resistance at an assumed TJ (Ω)
• TA = Maximum ambient temperature (°C)
• TJ = Maximum junction temperature (°C)
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• RθJA = Thermal resistance (°C/W)
If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using
the typical characteristic plot and recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction with a lower RθJA. The junction temperature
derating curve based on the TI standard reliability duration is shown in 图11-3.
130
TI Standard
125
120
115
110
105
100
95
90
85
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
IOUT (ADC
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
)
D001
图11-3. Junction Temperature Derating Curve
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD3S014-Q1EVM User's Guide, SLVUAQ0.
12.2 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD3S014TDBVRQ1
ACTIVE
SOT-23
DBV
6
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 105
13WW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD3S014TDBVRQ1
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
TPD3S014TDBVRQ1
6
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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