TPD4S012_14 [TI]
4-CHANNEL ESD SOLUTION FOR USB-HS/USB OTG/USB CHARGER INTERFACE;
| 型号： | TPD4S012_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-CHANNEL ESD SOLUTION FOR USB-HS/USB OTG/USB CHARGER INTERFACE |
| 文件： | 总9页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD4S012
www.ti.com
SLVS928A –MARCH 2009–REVISED NOVEMBER 2009
4-CHANNEL ESD SOLUTION FOR USB-HS/USB OTG/USB CHARGER INTERFACE
Check for Samples: TPD4S012
1
FEATURES
DRY PACKAGE
(TOP VIEW)
•
Integrated ESD Clamps for D+, D–, VBUS, and
ID Pins to Provide Single-Chip ESD Protection
for USB High Speed, USB-OTG, and USB
Charger Interface
V
1
2
3
6
5
4
D+
D–
ID
BUS
N.C.
•
Special Snap Back Technology Allows
High-voltage Tolerance During Normal
Operation while Reducing the Clamp Voltage
during System Level ESD Stress
GND
YFP PACKAGE
(TOP VIEW)
•
•
•
USB Signal Pins (D+, D–, ID)
–
–
0.8-pF Line Capacitance
Tolerates 6 V Signal
A1
A2
D+
D–
GND
ID
VBUS Line (VBUS
)
B1
C1
B2
C2
–
–
11-pF Line Capacitance
Tolerates 20 V Signal
V
V
BUS
BUS
Flow-Through Pin Mapping for the High-Speed
Lines Ensures Zero Additional Skew Due to
Board Layout While Placing the ESD
N.C. – Not internally connected
D+, D–, and ID pins are exact equivalent
ESD clamp circuits. Any of these pins can
be connected to any other D+, D–, or ID
pin if it becomes easier to route the traces
from the USB connector.
Protection Chip Near the Connector
•
•
Supports Data Rates in Excess of 480 Mbps
IEC 61000-4-2 (Level 4) System Level ESD
Compliance Measured at the D+, D–, and ID
Pins
DESCRIPTION
The TPD4S012 is
a
four-channel electrostatic
–
–
±10-kV IEC 61000-4-2 Contact Discharge
±10-kV IEC 61000-4-2 Air-Gap Discharge
discharge (ESD) solution for USB charger or USB
on-the-go (OTG) interface. In many cell phone
applications, the USB connector is the de facto
communication port for external communications like
high-speed data transfer, audio signal, charging,
car-kit, etc. In order to support different interfaces, the
USB port needs to handle different voltage levels. For
example, some chargers require the VBUS port of the
USB connector to handle in excess of the normal
VBUS voltage per USB specifications. The TPD4S012
offers combinations of two different clamp voltages to
match the voltage tolerances of the different signal
interfaces using the common USB connector. Refer
to Figure 5-6 & Figure 9-12, special snap back
technology allows high-voltage tolerance during
normal operation while reducing the clamp voltage
during system level ESD stress.
•
•
3 Amps Peak Pulse Current (8/20 μs Pulse) for
VBUS and D+, D–, and ID Lines
Industrial Temperature Range: –40°C to 85°C
APPLICATIONS
•
•
•
•
•
Cellular Phones
Digital Cameras
Global Positioning Systems (GPS)
Portable Digital Assistants (PDA)
Portable Computers
The TPD4S012 conforms to IEC61000-4-2 (Level 4)
ESD. The device is offered in space-saving packages
with flow-through pin mapping.
The TPD4S012 is characterized for operation over
ambient air temperature of –40°C to 85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPD4S012
SLVS928A –MARCH 2009–REVISED NOVEMBER 2009
www.ti.com
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
(1) (2)
TA
PACKAGE
NOMINAL DIMENSIONS (mm)
SON – DRY
WCSP – XXX
Reel of 3000
Reel of 3000
W = 1.0, L = 1.45, H = 0.55, Pitch = 0.5
W = 0.8, L = 1.2, H = 0.5, Pitch = 0.4
TPD4S012DRYR
TPD4S012XXXR
3B
TBD
–40°C to 85°C
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
APPLICATION SCHEMATIC
V
BUS
V
BUS
D+
D+
D–
-
D–
PMU/USB
Controller
ID
ID
GND
GND
If the ID pin is not used, it can be left floating.
Board Layout Recommendations
GND
ID
Core PMU Chip/
USB Controller
D–
D+
V
BUS
Figure 1. Using DRY Package
V
V
BUS
ID
BUS
C2
B2
C1
Core PMU Chip/
USB Controller
B1
A1
D–
D+
A2
GND
Figure 2. Using YFP Package
The TPD4S012 can provide system-level ESD protection to the high-speed differential ports. The flow-through
package offers flexibility for board routing. Figure 1 and Figure 2 show the board layout scheme for the D+ and
D– lines of a single differential pair. It allows the differential signal pairs couple together right after they touch the
ESD ports of the TPD4S012.
2
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPD4S012
TPD4S012
www.ti.com
SLVS928A –MARCH 2009–REVISED NOVEMBER 2009
CIRCUIT DIAGRAM
V
BUS
D+
D–
-
ID
GND
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
DRY
PIN NO.
XXX
BALL NO.
NAME
1
2
3
4
5
6
A1
B1
D+
D–
ESD clamp Provides ESD protection to the high-speed differential data lines
ESD clamp Provides ESD protection to the high-speed differential data lines
ESD clamp Provides ESD protection to the high-speed differential data lines
B2
ID
A2
GND
N.C.
VBUS
Pwr
–
Ground
–
Not internally connected
C1, C2
ESD clamp ESD clamp for high-voltage tolerant VBUS line(s)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–65
MAX
20
UNIT
V
VBUS voltage tolerance
VBUS pin
IO voltage tolerance
D+, D–, ID pins
6
V
Tstg
TA
Storage temperature range
125
85
°C
°C
kV
kV
kV
kV
W
Operating free-air temperature range
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air-Gap Discharge
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air-Gap Discharge
Peak pulse power (tp = 8/20 μs)
Peak pulse current (tp = 8/20 μs)
–40
D+, D–, ID
±10
±10
±10
±9
D+, D–, ID
VBUS pin
VBUS pin
D+, D–, ID, VBUS pins
D+, D–, ID, VBUS pins
60
3
A
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): TPD4S012
TPD4S012
SLVS928A –MARCH 2009–REVISED NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBUS = 5 V
IVBUS
VBUS operating current
D+, D–, ID pins open
D+, D–, ID pins
μA
VBUS = 19 V
0.1
0.5
0.5
VIO = 2.5 V, VBUS
5 V
=
IIO
IO port current
0.1
μA
VD
D+, D–, ID pins (lower clamp
diode)
Diode forward voltage
VBUS pin capacitance
IO capacitance
IIO = 8 mA
VBUS = 5 V
VIO = 2.5 V
0.6
0.8
11
0.95
15
1
V
CVBUS
CIO
pF
pF
D+, D–, ID pins (DRY
package)
0.8
D+, D–, ID, and VBUS pins,
including central clamp dioded
during positive ESD pulse
IIO = 1.5 A
1.2
1
RDYN
Dynamic resistance
Breakdown voltage
Ω
D+, D–, ID, and VBUS pins,
including central clamp diode
during negative ESD pulse
IIO = 1 A
D+, D–, ID pins
VBUS pin(s)
6
9
VBR
IIO = 1 mA
V
20
24
TYPICAL CHARACTERISTICS
3.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Power
3.0
Current
2.5
2.0
1.5
1.0
0.5
0
Power
Current
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Time (ms)
Time (ms)
Figure 3. Peak Pulse Power Waveform at the D+, D–, or ID Pin
Figure 4. Peak Pulse Power Waveform at the VBUS Pin
4
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Product Folder Link(s): TPD4S012
TPD4S012
www.ti.com
SLVS928A –MARCH 2009–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS (continued)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0
5
10
15
20
25
30
2
4
6
8
10
10
12
14
0
Voltage (V)
Voltage (V)
Figure 5. D+, D–, or ID Clamp Voltage Under ESD Event
Figure 6. VBUS Clamp Voltage Under ESD Event
1.80E-11
1.70E-11
1.60E-11
1.50E-11
1.40E-11
1.30E-11
1.20E-11
1.10E-11
1.00E-11
9.00E-12
1.70E-12
1.60E-12
1.50E-12
1.40E-12
1.30E-12
1.20E-12
1.10E-12
V
to GND
BUS
1.00E-12
9.00E-13
8.00E-13
7.00E-13
D+ to GND
0.0
1.0
2.0
3.0
4.0
5.0
0.0
1.0
2.0
3.0
4.0
5.0
Volts
Volts
Figure 7. D+, D–, or ID Capacitance, TA = 27°C
Figure 8. VBUS Capacitance, TA = 27°C
140
120
100
80
40
20
0
–20
–40
–60
–80
–100
–120
60
40
20
0
–20
–40
25 50 75 100 125 150 175 200 225 250
Time (ns)
25 50 75 100 125 150 175 200 225 250
Time (ns)
0
0
Figure 9. IEC Clamping Waveform, 8 kV Contact, D+, 25 ns/div
Figure 10. IEC Clamping Waveform, –8 kV Contact, D+, 25
ns/div
Copyright © 2009, Texas Instruments Incorporated
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TPD4S012
SLVS928A –MARCH 2009–REVISED NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
140
120
100
80
40
20
0
–20
–40
–60
–80
–100
–120
60
40
20
0
–20
–40
25 50 75 100 125 150 175 200 225 250
Time (ns)
25 50 75 100 125 150 175 200 225 250
Time (ns)
0
0
Figure 11. VBUS IEC Clamping Waveform, 8 kV Contact, D+, 25
ns/div
Figure 12. VBUS IEC Clamping Waveform, –8 kV Contact, D+, 25
ns/div
6
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPD4S012
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPD4S012DRYR
ACTIVE
SON
DRY
6
5000
TBD
Call TI
Call TI
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
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