TPS2115A [TI]
AUTOSWITCHING POWER MUX; 自动开关MUX型号: | TPS2115A |
厂家: | TEXAS INSTRUMENTS |
描述: | AUTOSWITCHING POWER MUX |
文件: | 总20页 (文件大小:208K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SBVS044A − MARCH 2004 − REVISED MAY 2004
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FEATURES
APPLICATIONS
D
Two-Input, One-Output Power Multiplexer
With Low r Switches:
D
D
D
D
D
D
D
PCs
DS(on)
PDAs
− 84 mΩ Typ (TPS2115A)
− 120 mΩ Typ (TPS2114A)
Reverse and Cross-Conduction Blocking
Digital Cameras
Modems
D
D
D
D
D
D
Cell Phones
Digital Radios
MP3 Players
Wide Operating Voltage Range . . . .2.8 V to
5.5 V
Low Standby Current . . . . 0.5-µA Typ
Low Operating Current . . . . 55-µA Typ
Adjustable Current Limit
PW PACKAGE
(TOP VIEW)
Controlled Output Voltage Transition Times,
Limits Inrush Current and Minimizes Output
Voltage Hold-Up Capacitance
1
2
3
4
8
7
6
5
STAT
D0
D1
ILIM
IN1
OUT
IN2
D
D
D
D
CMOS- and TTL-Compatible Control Inputs
GND
Manual and Auto-Switching Operating Modes
Thermal Shutdown
Available in a TSSOP-8 Package
DESCRIPTION
The TPS211xA family of power multiplexers enables seamless transition between two power supplies, such as a battery
and a wall adapter, each operating at 2.8−5.5 V and delivering up to 1 A. The TPS211xA family includes extensive protection
circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply
transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power
multiplexer applications.
TYPICAL APPLICATION
Switch Status
IN1: 2.8 − 5.5 V
TPS2115APW
R1
0.1 µF
1
2
3
4
8
IN1
OUT
IN2
STAT
D0
7
6
5
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2: 2.8 − 5.5 V
0.1 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2004, Texas Instruments Incorporated
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SBVS044A − MARCH 2004 − REVISED MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
FEATURE
TPS2110A
TPS2111A
TPS2112A
TPS2113A
TPS2114A
TPS2115A
Current Limit Adjustment Range
0.31−0.75A 0.63−1.25A 0.31−0.75A 0.63−1.25A 0.31−0.75A 0.63−1.25A
Manual
Yes
Yes
Yes
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Switching Modes
Automatic
Switch Status Output
Package
No
No
Yes
Yes
Yes
Yes
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
ORDERING INFORMATION
(1)
T
A
PACKAGE
ORDERING NUMBER
MARKINGS
2114A
TPS2114APW
−40°C to 85°C
TSSOP-8 (PW)
TPS2115APW
2115A
(1)
The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2114APWR) to indicate tape and reel.
PACKAGE DISSIPATION RATINGS
DERATING FACTOR ABOVE
T
≤ 25°C
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
T
= 25°C
POWER RATING
POWER RATING
A
TSSOP-8 (PW)
3.9 mW/°C
387 mW
213 mW
155 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TPS2114A, TPS2115A
−0.3 V to 6 V
−0.3 V to 6 V
5 mA
(2)
Input voltage range at pins IN1, IN2, D0, D1, ILIM
(2)
Output voltage range, V
Output sink current, I
, V
O(OUT) O(STAT)
O(STAT)
TPS2114A
TPS2115A
0.9 A
Continuous output current, I
O
1.5 A
Continuous total power dissipation
Operating virtual junction temperature range, T
See Dissipation Rating Table
−40°C to 125°C
−65°C to 150°C
260°C
J
Storage temperature range, T
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
(2)
RECOMMENDED OPERATING CONDITIONS
MIN
1.5
2.8
1.5
2.8
0
MAX UNIT
V
V
V
V
≥ 2.8 V
< 2.8 V
≥ 2.8 V
< 2.8 V
5.5
I(IN2)
I(IN2)
I(IN1)
I(IN1)
Input voltage at IN1, V
Input voltage at IN2, V
V
I(IN1)
5.5
5.5
V
I(IN2)
5.5
Input voltage, V
, V
5.5
0.75
1.25
125
V
I(DO) I(D1)
TPS2114A
TPS2115A
0.31
0.63
−40
Current limit adjustment range, I
O(OUT)
A
Operating virtual junction temperature, T
°C
J
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX UNIT
Human body model
CDM
2
kV
V
500
2
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SBVS044A − MARCH 2004 − REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, V
= V
I(IN2)
= 5.5 V, R = 400 Ω (unless otherwise noted)
ILIM
I(IN1)
TPS2114A
TPS2115A
PARAMETER
POWER SWITCH
TEST CONDITIONS
UNIT
MIN TYP MAX
MIN TYP MAX
V
I(IN1)
V
I(IN1)
V
I(IN1)
V
I(IN1)
V
I(IN1)
V
I(IN1)
= V
= V
= V
= V
= V
= V
= 5.0 V
= 3.3 V
= 2.8 V
= 5.0 V
= 3.3 V
= 2.8 V
120
120
120
140
140
140
220
220
220
84
84
84
110
110
110
150
150
150
I(IN2)
I(IN2)
I(IN2)
I(IN2)
I(IN2)
I(IN2)
T = 25°C,
J
mΩ
mΩ
I
L
= 500 mA
Drain-source
on-state resistance
(INx−OUT)
(1)
r
DS(on)
T = 125°C,
J
L
I
= 500 mA
(1)
The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case,
the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
PARAMETER
LOGIC INPUTS (D0 AND D1)
TEST CONDITIONS
MIN TYP MAX
UNIT
V
V
High-level input voltage
Low-level input voltage
2
V
V
IH
0.7
1
IL
D0 or D1 = High, sink current
D0 or D1 = Low, source current
SUPPLY AND LEAKAGE CURRENTS
D1 = High, D0 = Low (IN1 active), V
Input current at D0 or D1
µA
0.5
1.4
5
= 5.5 V, V
= 3.3 V, V
= 3.3 V,
= 5.5 V,
I(IN1)
I(IN2)
55
1
90
12
75
1
I
= 0 A
O(OUT)
D1 = High, D0 = Low (IN1 active), V
= 0 A
I(IN1)
I(IN2)
I
O(OUT)
D0 = D1 = Low (IN2 active), V
Supply current from IN1
(operating)
µA
= 5.5 V, V
= 3.3 V,
= 5.5 V,
I(IN1)
I(IN2)
I
= 0 A
O(OUT)
D0 = D1 = Low (IN2 active), V
= 0 A
= 3.3 V, V
I(IN1)
I(IN2)
I
O(OUT)
D1 = High, D0 = Low (IN1 active), V
= 5.5 V, V
= 3.3 V, V
= 3.3 V,
= 5.5 V,
I(IN1)
I(IN2)
1
I
= 0 A
O(OUT)
D1 = High, D0 = Low (IN1 active), V
= 0 A
I(IN1)
I(IN2)
75
12
90
2
I
O(OUT)
D0 = D1 = Low (IN2 active), V
Supply current from IN2
(operating)
µA
= 5.5 V, V
= 3.3 V,
= 5.5 V,
I(IN1)
I(IN2)
1
55
I
= 0 A
O(OUT)
D0 = D1 = Low (IN2 active), V
= 0 A
= 3.3 V, V
I(IN1)
I(IN2)
I
O(OUT)
D0 = D1 = High (inactive), V
= 5.5 V, V
= 3.3 V, V
= 5.5 V, V
= 3.3 V, V
= 3.3 V,
= 5.5 V,
= 3.3 V,
= 5.5 V,
I(IN1)
I(IN1)
I(IN1)
I(IN1)
I(IN1)
I(IN2)
I(IN2)
I(IN2)
I(IN2)
0.5
I
= 0 A
O(OUT)
D0 = D1 = High (inactive), V
= 0 A
Quiescent current from IN1
(STANDBY)
µA
µA
1
I
O(OUT)
D0 = D1 = High (inactive), V
= 0 A
1
I
O(OUT)
D0 = D1 = High (inactive), V
= 0 A
Quiescent current from IN2
(STANDBY)
0.5
0.1
0.1
0.3
2
I
O(OUT)
Forward leakage current from IN1 D0 = D1 = High (inactive), V
(measured from OUT to GND)
Forward leakage current from IN2 D0 =D1= High (inactive), V
= 5.5 V, IN2 open,
5
µA
µA
µA
V
= 0 V (shorted), T = 25°C
J
O(OUT)
= 5.5 V, IN1 open,
I(IN2)
= 0 V (shorted), T = 25°C
5
(measured from OUT to GND)
V
O(OUT)
J
Reverse leakage current to INx
(measured from INx to GND)
D0 = D1 = High (inactive), V
= 0 V, V
O(OUT)
= 5.5 V, T = 25°C
5
I(INx)
J
3
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SBVS044A − MARCH 2004 − REVISED MAY 2004
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating junction temperature range, V
= V
I(IN2)
= 5.5 V, R = 400 Ω (unless otherwise noted)
ILIM
I(IN1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT CIRCUIT
R
= 400 Ω
0.51
0.30
0.95
0.47
0.63
0.36
1.25
0.71
0.80
0.50
1.56
0.99
ILIM
ILIM
ILIM
ILIM
TPS2114A
TPS2115A
R
R
R
= 700 Ω
= 400 Ω
= 700 Ω
Current limit accuracy
A
Time for short-circuit output current to
settle within 10% of its steady state value.
(1)
t
d
Current limit settling time
1
ms
Input current at ILIM
V
= 0 V, I
O(OUT)
= 0 A
−15
0
µA
I(ILIM)
(1)
Not tested in production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO
Falling edge
1.15
1.25
1.30
57
IN1 and IN2 UVLO
V
Rising edge
1.35
65
(1)
IN1 and IN2 UVLO hysteresis
30
mV
Falling edge
Rising edge
2.4
2.53
2.58
50
Internal V
Internal V
UVLO (the higher of IN1 and IN2)
V
DD
2.8
75
(1)
UVLO hysteresis
(1)
30
mV
DD
UVLO deglitch for IN1, IN2
Falling edge
110
µs
(1)
Not tested in production.
PARAMETER
REVERSE CONDUCTION BLOCKING
TEST CONDITIONS
MIN
TYP
MAX
UNIT
D0 = D1 = high, V
I(INx)
= 3.3 V. Connect OUT to a 5 V
Minimum output-to-input voltage
difference to block switching
supply through a series 1-kΩ resistor. Let D0 = low.
Slowly decrease the supply voltage until OUT connects
to IN1.
∆V
O(I_block)
80
100
120
mV
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
(1)
Thermal shutdown threshold
TPS211xA is in current limit.
TPS211xA is in current limit.
135
125
(1)
Recovery from thermal shutdown
°C
(1)
Hysteresis
10
20
IN2−IN1 COMPARATORS
Hysteresis of IN2−IN1 comparator
0.1
10
0.2
50
V
(1)
Deglitch of IN2−IN1 comparator (both ↑↓)
µs
(1)
Not tested in production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STAT OUTPUT
Leakage current
Saturation voltage
V
= 5.5 V
0.01
0.13
150
1
µA
V
O(STAT)
= 2 mA, IN1 switch is on
I
0.4
I(STAT)
Deglitch time (falling edge only)
µs
4
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SBVS044A − MARCH 2004 − REVISED MAY 2004
SWITCHING CHARACTERISTICS
over recommended operating junction temperature range, V
= V
I(IN2)
= 5.5 V, R = 400 Ω (unless otherwise noted)
ILIM
I(IN1)
TPS2114A
TPS2115A
PARAMETER
POWER SWITCH
TEST CONDITIONS
UNIT
MIN TYP MAX
MIN TYP MAX
T = 25°C, C = 1 µF,
J
L
Output rise time from
(1)
t
V
V
= V
= V
= 5 V
= 5 V
I = 500 mA,
0.5
1.0
0.5
1.5
0.7
1
1.8
1
3
2
ms
ms
r
f
I(IN1)
I(IN2)
L
an enable
See Figure 1(a)
T = 25°C, C = 1 µF,
J
L
L
Output fall time from
(1)
t
I
= 500 mA,
0.35
0.5
I(IN1)
I(IN2)
a disable
See Figure 1(a)
T = 125°C, C = 10 µF,
IN1 to IN2 transition,
J
L
I
L
= 500 mA
V
I(IN1)
V
I(IN2)
= 3.3 V,
= 5 V
40
40
60
60
40
40
60
60
[Measure transition time
as 10−90% rise time or
from 3.4 V to 4.8 V on
(1)
Transition time
t
t
µs
IN2 to IN1 transition,
V
I(IN1)
V
I(IN2)
= 5 V,
= 3.3 V
V
],
O(OUT)
See Figure 1(b)
V
= V = 5 V
I(IN2)
T = 25°C, C = 10 µF,
I(IN1)
J
L
Turn-on propagation
(1)
t
t
Measured from enable to
10% of V
I
L
= 500 mA,
0.5
3
1
5
ms
ms
PLH1
delay from enable
See Figure 1(a)
O(OUT)
Turn-off propagation
delay from a
(1)
disable
V
= V = 5 V,
I(IN2)
T = 25°C, C = 10 µF,
I(IN1)
J
L
Measured from disable
to 90% of V
I = 500 mA,
PHL1
L
See Figure 1(a)
O(OUT)
Logic 1 to Logic 0
transition on D1,
V
I(IN1)
V
I(IN2)
V
I(D0)
= 1.5 V,
= 5 V,
= 0 V,
T = 25°C, C = 10 µF,
J
L
Switch-over rising
propagation delay
t
I
L
= 500 mA,
40
100
40
100
µs
PLH2
(1)
See Figure 1(c)
Measured from D1 to
10% of V
O(OUT)
Logic 0 to Logic 1
transition on D1,
V
I(IN1)
V
I(IN2)
V
I(D0)
= 1.5V,
= 5V,
= 0 V,
T = 25°C, C = 10 µF,
J
L
Switch-over falling
propagation delay
t
I
L
= 500 mA,
2
3
10
2
5
10
ms
PHL2
(1)
See Figure 1(c)
Measured from D1 to
90% of V
O(OUT)
(1)
Not tested in production.
5
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SBVS044A − MARCH 2004 − REVISED MAY 2004
TRUTH TABLE
> V
(1)
OUT
D1
0
D0
V
I(IN2)
I(IN1)
STAT
0
1
1
0
1
X
Hi-Z
IN2
IN1
IN2
IN1
Hi-Z
0
No
Yes
X
0
Hi-Z
0
0
1
1
X
0
X = Don’t care.
(1)
The under-voltage lockout circuit causes the output OUT to go Hi-Z if the
selected power supply does not exceed the IN1/IN2 UVLO, or if neither
of the supplies exceeds the internal V
UVLO
DD
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
D0
2
3
5
8
I
I
I
I
TTL- and CMOS-compatible input pins. Each pin has a 1-µA pull-up. The truth table shown above illustrates the
functionalityof D0 and D1.
D1
GND
IN1
Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at
least one supply exceeds the internal V
DD
UVLO.
IN2
6
4
I
I
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and
at least one supply exceeds the internal V UVLO.
DD
from ILIM to GND sets the current limit I to 250/R
ILIM
A resistor R
ILIM
and 500/R for the TPS2114A and TPS2115A,
ILIM
L
ILIM
respectively.
OUT
7
1
O
O
Power switch output
STAT
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z
(i.e., EN is equal to logic 0).
6
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SBVS044A − MARCH 2004 − REVISED MAY 2004
FUNCTIONAL BLOCK DIAGRAM
Internal V
DD
1 µA
1 µA
V = 0 V
f
V = 0 V
f
I
O(OUT)
Q1
8
6
7
4
IN1
IN2
OUT
ILIM
Q2
Charge
Pump
k* I
O(OUT)
TPS2114A: k = 0.2%
TPS2115A: k = 0.1%
V
DD
ULVO
_
+
0.5 V
IN2
ULVO
Cross-Conduction
Detector
+
IN1
ULVO
+
0.6 V
+
_
_
EN2
EN1
Q1 is ON
Q2 is ON
UVLO (V
100 mV
+
)
DD
V
> V
I(INx)
O(OUT)
+
_
UVLO (IN2)
UVLO (IN1)
D0
EN1
2
3
D0
D1
Thermal
Sense
Control
Logic
D1
IN2
+
_
5
GND
IN1
1
STAT
Q2 is ON
7
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PARAMETER MEASUREMENT INFORMATION
90%
10%
90%
10%
V
O(OUT)
0 V
t
r
t
f
t
t
PHL1
PLH1
DO−D1
Switch Off
Switch Off
Switch Enabled
(a)
5 V
4.8 V
V
O(OUT)
3.4 V
3.3 V
t
t
DO−D1
Switch #2 Enabled
(b)
Switch #1 Enabled
5 V
1.85 V
4.65 V
V
O(OUT)
1.5 V
t
t
PHL2
PLH2
DO−D1
Switch #1 Enabled
Switch #2 Enabled
(c)
Switch #1 Enabled
Figure 1. Propagation Delays and Transition Timing Waveforms
8
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SBVS044A − MARCH 2004 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER RESPONSE
V
I(DO)
5 V
2V/Div
TPS2115APW
0.1 µF
1
2
8
7
NC
IN1
STAT
D0
f = 28 Hz
78% Duty Cycle
OUT
IN2
V
I(D1)
3
4
6
5
D1
50 Ω
1
µF
2V/Div
ILIM
GND
400 Ω
3.3 V
V
O(OUT)
2V/Div
0.1 µF
Output Switchover Response Test Circuit
t − Time − 1 ms/div
Figure 2
OUTPUT TURN-ON RESPONSE
V
I(DO)
5 V
2V/Div
TPS2115APW
0.1 µF
1
2
8
7
IN1
STAT
D0
NC
f = 28 Hz
78% Duty Cycle
V
OUT
IN2
I(D1)
3
4
6
5
2V/Div
D1
50 Ω
1
ILIM
GND
µF
400 Ω
3.3 V
V
O(OUT)
2V/Div
0.1 µF
Output Turn-On Response Test Circuit
t − Time − 2 ms/div
Figure 3
9
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SBVS044A − MARCH 2004 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER VOLTAGE DROOP
V
I(DO)
5 V
2V/Div
TPS2115APW
0.1 µF
1
2
8
7
IN1
STAT
D0
NC
V
f = 580 Hz
90% Duty Cycle
OUT
IN2
I(D1)
C
L
= 1 µF
3
4
6
5
2V/Div
D1
50 Ω
C
L
ILIM
GND
400 Ω
V
O(OUT)
2V/Div
0.1 µF
C
L
= 0 µF
Output Switchover Voltage Droop Test Circuit
Figure 4
t − Time − 40 µs/div
10
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SBVS044A − MARCH 2004 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
5
V
I
= 5 V
4.5
4
3.5
3
R = 10 Ω
L
2.5
2
1.5
1
0.5
0
R
L
= 50 Ω
0.1
1
10
100
C
L
− Load Capacitance − µF
V
I
TPS2115APW
0.1 µF
8
7
6
5
1
2
3
4
IN1
NC
STAT
f = 28 Hz
50% Duty Cycle
OUT
IN2
D0
D1
ILIM
GND
400 Ω
50 Ω
10 Ω
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
100 µF
Output Switchover Voltage Droop Test Circuit
Figure 5
11
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SBVS044A − MARCH 2004 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
AUTO SWITCHOVER VOLTAGE DROOP
V
I(IN1)
2V/Div
5 V
TPS2115A
Ω
1k
µ
0.1 F
1
2
8
7
IN1
STAT
VOUT
D0
OUT
IN2
f = 220 Hz
20% Duty Cycle
3
4
6
5
3.3V
D1
Ω
50
µ
10
F
ILIM
GND
µ
F
0.1
Ω
400
V
O(OUT)
2V/Div
75% less output voltage
droop compared to TPS2115
Auto Switchover Voltage Droop Test Circuit
t − Time − 250 µs/div
Figure 6
12
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SBVS044A − MARCH 2004 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
INRUSH CURRENT
vs
LOAD CAPACITANCE
300
250
200
150
100
V = 5 V
I
V = 3.3 V
I
50
0
0
20
40
60
80
100
C
L
− Load Capacitance − µF
V
I
TPS2115APW
0.1 µF
8
7
6
5
To Oscilloscope
1
2
3
4
NC
NC
IN1
OUT
IN2
STAT
D0
f = 28 Hz
90% Duty Cycle
D1
50 Ω
ILIM
GND
400 Ω
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
100 µF
Output Capacitor Inrush Current Test Circuit
Figure 7
13
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TYPICAL CHARACTERISTICS
SWITCH ON-RESISTANCE
vs
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
JUNCTION TEMPERATURE
120
115
110
105
100
95
180
160
140
TPS2114A
TPS2114A
TPS2115A
120
100
90
80
60
TPS2115A
85
80
2
3
4
5
6
−50
0
50
100
150
V
I(INx)
− Supply Voltage − V
T
J
− Junction Temperature − °C
Figure 8
Figure 9
IN1 SUPPLY CURRENT
vs
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0.96
0.94
0.92
60
58
56
54
52
50
48
46
44
IN1 Switch is ON
= 0 V
Device Disabled
= 0 V
V
I(IN2)
V
I(IN2)
I
= 0 A
O(OUT)
I
= 0 A
O(OUT)
0.90
0.88
0.86
0.84
0.82
42
40
2
3
4
5
6
2
3
4
5
6
V
I(IN1)
− Supply Voltage − V
V − IN1 Supply Voltage − V
I(IN1)
Figure 10
Figure 11
14
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SBVS044A − MARCH 2004 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.2
80
70
IN1 Switch is ON
Device Disabled
V
V
I
= 5.5 V
= 3.3 V
= 0 A
V
I(IN1)
V
I(IN2)
I
= 5.5 V
= 3.3 V
= 0 A
I(IN1)
I(IN2)
O(OUT)
1
O(OUT)
60
50
I
= 5.5 V
I
I(IN1)
I(IN1)
0.8
0.6
0.4
0.2
0
40
30
20
10
0
I
I
3.3 V
I(IN2)
I(IN2) =
−50
0
50
100
150
−50
0
50
100
150
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 12
Figure 13
15
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SBVS044A − MARCH 2004 − REVISED MAY 2004
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 14
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once
the voltage on IN1 falls below this value, the TPS2114A/5A will select the higher of the two supplies. This usually
means that the TPS2114A/5A will swap to IN2.
Switch Status
IN1: 2.8 − 5.5 V
TPS2115APW
R1
0.1 µF
1
2
3
4
8
7
6
5
IN1
OUT
IN2
STAT
D0
NC
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2: 2.8 − 5.5 V
C2
0.1 µF
Figure 14. Auto-Selecting for a Dual Power Supply Application
In Figure 15, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects
to IN1 if D1 is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are compatible
with both TTL and CMOS logic.
Switch Status
IN1: 2.8 − 5.5 V
TPS2115APW
R1
0.1 µF
1
2
3
4
8
7
6
5
IN1
OUT
IN2
STAT
D0
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2: 2.8 − 5.5 V
0.1 µF
Figure 15. Manually Switching Power Sources
16
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SBVS044A − MARCH 2004 − REVISED MAY 2004
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to
the higher of IN1 and IN2.
MANUAL SWITCHING MODE
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
1, otherwise OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET
switch if the output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply
voltage. Once a supply has been connected to the output, it will remain connected regardless of output voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor R
from ILIM to GND sets the current limit to 250/R
and 500/R
for the TPS2114A and
ILIM
ILIM
ILIM
TPS2115A, respectively. Setting resistor R
limiting.
equal to zero is not recommended as that disables current
ILIM
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2114A/5A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot-plugging a load such as a PCI card. The TPS2114A/5A slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
17
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
TPS2114APW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
8
8
8
8
8
8
8
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2114APWR
TPS2114APWRG4
TPS2115APW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2115APWG4
TPS2115APWR
TPS2115APWRG4
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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