TPS2151IPWPR [TI]
ADJUSTABLE LDO AND SWITCH WITH DUAL CURRENT LIMIT FOR USB;
| 型号： | TPS2151IPWPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ADJUSTABLE LDO AND SWITCH WITH DUAL CURRENT LIMIT FOR USB 光电二极管 输出元件 调节器 |
| 文件： | 总25页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
ADJUSTABLE LDO AND SWITCH WITH DUAL CURRENT LIMIT FOR
USB HIGH-POWER PERIPHERAL POWER MANAGEMENT
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
D
D
D
Complete Power Management Solution for
USB High-Power Peripherals
The TPS2140/41/50/51 is a USB 1.0 and 2.0
Specification-compatible IC containing a dual-current-
limiting power switch and an adjustable low dropout
regulator (LDO). Both the switch and LDO limit inrush
current by controlling the turnon slew rate. The unique
dual-current-limiting feature of the switch allows USB
peripherals to utilize high-value capacitance at the
output of the switch, while keeping the inrush current
low. During turnon, the switch limits the current
delivered to the capacitive load to less than 100 mA.
When the output voltage from the switch reaches about
93% of the input voltage, the switch power good output
goes high, and the switch current limit increases to
800mA (minimum), at which point higher current loads
can be turned on. The higher current limit provides short
circuit protection while allowing the peripheral to draw
maximum current from the USB bus.
250 mA Low-Dropout Regulator (LDO) With
Enable and 325 mA (Typ) Current Limit
LDO Supports 2.7 V to 5.5 V V and 0.9 V to
IN
3.3 V Adjustable V
OUT
40 mΩ (Typ) High-Side MOSFET With Dual
Current Limit
Undervoltage Lockout and Power Good for
LDO and Switch
CMOS- and TTL-Compatible Enable Inputs
85 µA (Typ) Supply Current
5 µA (Typ) Standby Supply Current
Available in 14-Pin HTSSOP (PowerPAD )
–40°C to 85°C Ambient Temperature Range
Alternative to TPS2148/58 3.3-V LDO With
3.3-V Switch and 5-V Switch
The switch and LDO function independently, providing
flexibility in DSP applications requiring separate core
and I/O voltages. For example, in a DSP application
operating from a 3.3-V rail, the LDO can supply the DSP
core voltage down to 0.9 V, while the switch powers the
3.3-V (typical) DSP I/O supply. If supply sequencing is
required, the LDO power good output can be used to
enable the switch.
APPLICATIONS
D
High-Power USB Peripherals
– ADSL Modems
– Digital Still and PC Cameras
– Zip Drives
– Speakers
D
DSP Sequencing
AVAILABLE OPTIONS
PACKAGED DEVICES
PACKAGE
AND PIN
COUNT
TARGET
APPLICATION
T
A
DESCRIPTION
ACTIVE LOW
ACTIVE HIGH
(SWITCH)
(SWITCH)
AdjustableLDOand3.3Vswitchwithdualcurrent
limit
DSP
USB
HTSSOP-14
HTSSOP-14
TPS2140IPWP
TPS2150IPWP
TPS2151IPWP
–40°C to 85°C
Adjustable LDO and 5 V switch with dual current
limit
TPS2141IPWP
NOTE: All options available taped and reeled. Add an R suffix (e.g., TPS2140IPWPR)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
USB is a trademark of Universal Serial Bus Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
TPS2140/41/50/51
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
SW_PG
SW_IN
SW_IN
LDO_IN
SW_EN
LDO_EN
GND
SW_PLDN
SW_OUT
SW_OUT
LDO_OUT
LDO_PLDN
ADJ
†
8
LDO_PG
†
Pin 5 is active high for TPS2150 and TPS2151.
USB peripheral application
D+
D–
USB
Function
Controller
TPS2151
LDO
GND
5 V
1.5 kΩ
LDO_PLDN
LDO_OUT
LDO_IN
ADJ
LDO_EN
SW_IN
LDO_PG
5 V
Circuitry
SW_OUT
Switch
SW_PLDN
SW_PG
SW_EN
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
functional block diagram
CS
SW_OUT
SW_IN
SW_OUT
SW_PG
2-Level
Current
Limit
Driver
VREF
SW_PLDN
†
SW_EN
V
Charge
Pump
Thermal
Sense
CC
Select
LDO_PG
VREF
0.9 V to 3.3 V
250 mA
ADJ
LDO_IN
LDO
LDO_OUT
LDO_PLDN
LDO_EN
GND
†
The pin is active low for TPS2140 and TPS2141, with an internal pullup.
The pin is active high for TPS2150 and TPS2151, with an internal pulldown.
Terminal Functions
TERMINAL
NAME
ADJ
GND
I/O
DESCRIPTION
NO.
9
I
Feedback adjustment of LDO regulator to set output voltage
Ground
7
LDO_EN
LDO_IN
6
I
I
Enable signal for LDO regulator, active high, no internal pullup or pulldown
Input of LDO regulator
4
LDO_OUT
LDO_PG
LDO_PLDN
11
8
O
O
I
Output of LDO regulator
Power good signal for LDO output, open-drain, active high
Output pulldown pin used for LDO when connected to LDO_OUT
10
5
SW_EN or
SW_EN
I
Active-high enable for switch on TPS2150 and TPS2151 devices with internal pulldown
Active-low enable for switch on TPS2140 and TPS2141 devices with internal pullup
SW_IN
2, 3
12, 13
1
I
Input of the switch
SW_OUT
SW_PG
SW_PLDN
O
O
I
Output of switch
Power good signal for switch output, active high logic-level signal, no external pullup required.
Output pulldown pin used for switch when connected to SW_OUT.
14
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
detailed description
GND
Ground
SW_IN
SW_IN is the input to an integrated N-channel MOSFET, which has a maximum on-state resistance of 65 mΩ.
Configured as a high-side switch, the power switch prevents current, flow from OUT to IN and IN to OUT when
disabled. The power switch is rated at 500 mA, continuous current and has a dual current limit feature.
dual current limit
The current limiter for the switch limits the initial current drawn from SW_IN to 100 mA maximum. The user can
estimate the amount of time it takes to charge a capacitor (CL) connected to SW_OUT by using the following
relationship:
CL × V
/ 0.1 < t
< CL × V
/ 0.05
I(SW_IN)
I(SW_IN)
CHG
Capacitance in farads. If V
= 5 V, then
I(SW_IN)
50 × CL< t
<100 × CL
CHG
When the voltage at output SW_OUT rises above 93% of the voltage at SW_IN, the current limit is increased
to 1800 mA maximum. The SW_PG can be used to turn on loads which may draw more than 50 mA.
In the event of an overload on SW_OUT, the protection circuit limits the current delivered to 1800 mA maximum.
As the output voltage drops and it crosses 80% of the SW_IN voltage, the current limiter reverts back to the
low-current limit mode of 100 mA maximum.
SW_IN also serves as one of the two inputs to an internal voltage selector that provides operating voltage to
the whole device. The other input to the selector is LDO_IN.
SW_OUT
SW_OUT is the output of the internal power-distribution switch.
SW_EN or SW_EN
The logic input disables or enables the power switch. This signal is active low (SW_EN) for TPS2140/41 and
active high (SW_EN) for TPS2150/51. SW_EN has an internal pullup and SW_EN has an internal pulldown.
SW_PG
SW_PG signals the presence of an undervoltage condition on SW_OUT. The pin is driven by a CMOS output
buffer and is pulled low during an undervoltage condition. To minimize erroneous SW_PG responses from
transients on the voltage rail, the voltage sense circuit incorporates a rising and falling edge deglitch filter. When
SW_OUT voltage is lower than 88% of 3.3 V for TPS2140/50, or 5 V for TPS2141/51, SW_PG goes low to
indicate an undervoltage condition on SW_OUT.
SW_PLDN
SW_PLDN is an open drain output incorporated to provide a discharge path. When the power switch is on, this
pin is open; otherwise it is pulled down to ground. When this pin is connected to SW_OUT, the output voltage
fall time is reduced but the rise time remains unaffected.
LDO_IN
The LDO_IN serves as the input to the internal LDO. The adjustable LDO has a dropout voltage of 0.5 V
maximum and is rated for 250 mA of continuous current. LDO_IN is also used as one of the two inputs for V
selection.
CC
4
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
detailed description (continued)
LDO_OUT
LDO_OUT is the output of the internal LDO. It has an output voltage range of 0.9 V to 3.3 V.
LDO_EN
LDO_EN is used to enable or disable the internal LDO and is compatible with CMOS and TTL logic. LDO_EN
is an active high input.
ADJ
ADJ is used to adjust the LDO output voltage (LDO_OUT) anywhere between 0.9 V and 3.3 V by connecting
a resistor divider from LDO_OUT to ground (ADJ connects to the center point of the resistor divider).
LDO_PG
LDO_PG signals the presence of an undervoltage condition on LDO_OUT. LDO_PG is an open-drain output
and is pulled low during an undervoltage condition. To minimize erroneous LDO_PG responses from transients
on the voltage rail, the voltage sense circuit incorporates a 150-µs falling deglitch filter. When the LDO_OUT
voltage is lower than 94% of a threshold voltage (set by an external resistor divider), LDO_PG goes low to
indicate an undervoltage condition. A pullup resistor from LDO_PG to a power rail is required for proper
operation.
LDO_PLDN
LDO_PLDN is an open drain output incorporated to provide a discharge path. When the LDO is on, this pin is
open; otherwise, it is pulled down to ground. When this pin is connected to LDO_OUT, the output voltage fall
time is reduced but the rise time remains unaffected.
current sense
Both the power switch and the LDO have integrated current sense circuits. When an overload or short circuit
is encountered, the current-sense circuitry sends a control signal to the driver. The driver reduces the gate
voltage until the current drops back to the limiting value.
thermal sense
A dual-threshold thermal trip is implemented to protect the device. The lower thermal trip point is used to protect
the device during an overcurrent condition. The higher thermal trip point is used to protect the device when the
junction temperature rises but not due to an overcurrent condition.
undervoltage lockout
A voltage sense circuit monitors both input voltages on SW_IN and LDO_IN. When the input voltage is below
its respective threshold, a control signal turns off the related channel (the power switch or the LDO).
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range for bus switch and LDO: V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
I(SW_IN)
V
I(LDO_IN)
Output voltage range for bus switch and LDO:V
V
O(SW_OUT)
O(LDO_OUT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
V . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage range for pulldown transistors:
Logic input/output voltage range:
V
or V
I(SW_PLDN) , I(LDO_PLDN)
V
V
V V , V
I(SW_EN)
I(LDO_PG)
I(/SW_EN), I(LDO_EN), I(ADJ) I(SW_PG),
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Output current for bus switch and LDO: I
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 mA to 10 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 10 mA
O(SW_OUT)
O(LDO_OUT)
I(SW_PLDN)
I(LDO_PLDN)
Sink current for pulldown switches:
I
I
I
I
Output current for logic outputs:
O(SW_PG)
O(LDO_PG)
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
J
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T ≤ 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
PWP-14
2266.7 mW
26.7 mW/°C
1066.7 mW 666.7 mW
NOTE: This device is mounted on an JEDEC low-k board (2 oz traces on surface), 1 W power applied
with no air flow.
recommended operating conditions
MIN
2.7
4.1
2.7
0
MAX
5.5
5.5
5.5
5.5
5.5
0.6
UNIT
V
V
V
V
V
TPS2140 and TPS2150
TPS2141 and TPS2151
I(SW_IN),
I(SW_IN),
I(LDO_IN)
I(SW_EN)
Input voltage, V
V
I
or V
V
I(/SW_EN), I(LDO_EN)
V
0
I(SW_PLDN), I(LDO_PLDN)
I
I
at T = 110°C
J
O(SW_OUT)
O(LDO_OUT)
Output current, I
A
O
‡
at T =110°C
0.25
110
J
Operating virtual junction temperature, T
–40
°C
J
‡
Assuming the power dissipation does not exceed the device’s thermal limit. Refer to the power dissipation and junction temperature section for
the power dissipation calculation.
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
electrical characteristics over recommended operating junction temperature range,
V
=3.3VforTPS2140/50,V
=5VforTPS2141/51,V
=5V,alloutputsunloaded
I(SW_IN)
I(SW_IN)
I(LDO_IN)
(unless otherwise noted)
general
PARAMETER
TEST CONDITIONS
TYP
85
MAX
UNIT
MIN
2.7 V < V
< 5.5 V, V
= 0,
I(SW_IN)
I(LDO_IN)
TPS2140, TPS2150
V
= 5.5 V or V
= 0 V,
110
I(SW_EN)
I(/SW_EN)
Power switch operat-
ing supply current
V
= 0 V, No load
I(LDO_EN)
4.1 V< V
< 5.5 V, V
= 0,
I(SW_IN)
I(LDO_IN)
I
OP_SW
TPS2141, TPS2151
TPS2140, TPS2150
TPS2141, TPS2151
V
= 5.5 V or V
= 0 V,
I(/SW_EN)
85
5
110
10
I(SW_EN)
V
= 0 V, No load
ILDO_EN)
µA
2.7 V< V
<5.5 V, V
= 0,
I(LDO_IN)
I(SW_IN)
V
= 0 V or V
= 5.5 V,
I(/SW_EN)
I(SW_EN)
Power switch standby
supply current
V
= 0 V, No load
I(LDO_EN)
4.1 V< V
< 5.5 V, V
= 0,
= 5.5 V,
I(SW_IN)
I(LDO_IN)
I(SW_IN)
I(SW_IN)
I(SW_EN)
I
STBY_SW
V
= 0 V or V
5
10
I(SW_EN)
I(/SW_EN)
V
= 0 V, No load
I(LDO_EN)
2.7 V< V
<5.5 V, V
= 0 V,
= 5.5 V,
I(LDO_IN)
LDO operating supply current I
LDO standby supply current I
V
= 0 V or V
90
5
120
10
OP_LDO
I(SW_EN)
I(/SW_EN)
V
= 5 V, No load
I(LDO_EN)
µA
2.7 V< V
<5.5 V, V
= 0 V,
= 5.5 V,
I(LDO_IN)
V
= 0 V or V
STBY_LDO
I(SW_EN)
I(/SW_EN)
V
= 0 V, No load
I(LDO_EN)
2.7 V< V
V
<5.5 V, V
= 5.5 V or
= 5 V, No load
I(SW_IN)
TPS2140, TPS2150
= 0 V, V
150
150
10
I(/SW_EN)
I(LDO_EN)
<5.5 V
Power switch and LDO
total operating supply
2.7 V< V
I(LDO_IN)
4.1 V< V
<5.5 V, V
= 5.5 V or
I(SW_IN)
I(SW_EN)
current I
OP_TOTAL
TPS2141, TPS2151
TPS2140, TPS2150
TPS2141, TPS2151
V
= 0 V, V
= 5 V, No load
I(LDO_EN)
I(/SW_EN)
2.7 V< V
<5.5 V
I(LDO_IN)
µA
2.7 V< V
V
<5.5 V, V
= 0 V or
I(SW_EN)
I(SW_IN)
= 5.5 V, V
= 0 V, No load
I(LDO_EN)
I(/SW_EN)
Power switch and LDO
total standby supply
2.7 V<V
<5.5 V
I(LDO_IN)
4.1 V< V
V
<5.5 V, V
= 0 V or
I(SW_EN)
I(SW_IN)
current I
STBY_TOTAL
= 5.5 V, V
= 0 V, No load
I(LDO_EN)
10
I(/SW_EN)
2.7 V<V
<5.5 V
I(LDO_IN)
7
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
electrical characteristics over recommended operating junction temperature range,
V
=3.3VforTPS2140/50,V
=5VforTPS2141/51,V
=5V,alloutputsunloaded
I(SW_IN)
I(SW_IN)
I(LDO_IN)
(unless otherwise noted) (continued)
power switch
†
PARAMETER
TEST CONDITIONS
TYP
40
MAX
50
UNIT
MIN
T = 25°C, I = 500 mA,
J
V
= 3.3 V or V
= 0 V
I(/SW_EN)
I(SW_EN)
TPS2140, TPS2150
T = 110°C, I = 500 mA,
J
65
50
V
= 3.3 V or V
= 0 V
I(/SW_EN)
I(SW_EN)
Switch on resistance
(SW_IN to SW_OUT)
mΩ
T = 25°C, I = 500 mA,
J
40
V
= 5 V or V
= 0 V
I(/SW_EN)
I(SW_EN)
TPS2141, TPS2151
T = 110°C, I = 500 mA,
J
65
V
= 5 V or V
= 0 V
I(/SW_EN)
I(SW_EN)
Switch low-current-limit cutoff
Low current limit is disabled when V
O(SW_OUT)
91%
76%
50
93%
79%
75
96%
82%
99
threshold, V
is above this %V
level
I(SW_IN)
COFF(SW_OUT)
Switch low-current-limit
cutin threshold, V
Low current limit is enabled V
is be-
O(SW_OUT)
low this %V
level
CIN(SW_OUT)
I(SW_IN)
Low-current-limit mode:
Ramp-up current limit, IRCL
Switch current limit
Switch forward leak-
T = 25°C
50
47
75
75
99
99
J
Low-current-limit mode: Short-
circuit dc current limit, I
OS
SW_OUT is enabled into a
short to ground
mA
T = 110°C
J
T = 25°C
J
900
800
1300
1300
1800
1800
High-current-limit mode:
Overload dc current limit, I
OL
T = 110°C
J
V
V
= 0 V, V
= 5.5 V,
I(SW_IN)
O(SW_OUT)
Current into pin SW_OUT
Current into pin SW_OUT
10
10
age current I
= 0 V or V
= 5 V
LK_SW
I(SW_EN)
I(/SW_EN)
µA
Switch reverse leak-
age current I
V
V
= 5.5 V, V
= 0 V,
= 5 V
O(SW_OUT)
I(SW_IN)
= 0 V or V
RLK_SW
I(SW_EN)
I(/SW_EN)
V
V
= 3.3 V
= 1 V
9
15
5
I(SW_PLDN)
I(PLDN_SW)
Switch pulldown transistor current
mA
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
timing parameters, power switch
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
MIN
t
t
t
t
Turnon time
Turnoff time
Rise time
C = 10 µF, No load
L
1
on
C = 10 µF, SW_OUT is connected to SW_PLDN, No load
L
8
0.5
5
off
ms
C = 10 µF, No load
L
r
f
Fall time
C = 10 µF, SW_OUT is connected to SW_PLDN, No load
L
undervoltage lockout, SW_IN
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.7
UNIT
V
TPS2140, TPS2150
TPS2141, TPS2151
TPS2140, TPS2150
TPS2141, TPS2151
Switch UVLO rising threshold
Switch UVLO falling threshold
4.1
2.3
3.5
2.45
3.9
‡
UVLO hysteresis
250
mV
‡
Not tested in production.
8
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
electrical characteristics over recommended operating junction temperature range,
=3.3VforTPS2140/50,V =5VforTPS2141/51,V =5V,alloutputsunloaded
V
I(SW_IN)
I(SW_IN)
I(LDO_IN)
(unless otherwise noted) (continued)
adjustable voltage regulator (V
= 0.9 V to 3.3 V)
set
PARAMETER
TEST CONDITIONS
= V + 0.6 V to 5.5 V and
TYP
MAX
UNIT
MIN
V
V
I(LDO_IN)
set
V
V
V
Output voltage total tolerance
Line regulation
> 2.7 V, I
= 5 mA to
–4%
3%
O(LDO_OUT)
O(LDO_OUT)
O(LDO_OUT)
I(LDO_IN)
O(LDO_OUT)
250 mA
V
V
= V
+ 0.6 V to 5.5 V and
O(LDO_OUT)
I(LDO_IN)
I(LDO_IN)
0.03
0.1
%/V
> 2.7 V, I
= 5 mA
O(LDO_OUT)
V
V
=V
+ 0.6 V to 5.5 V and
= 5 mA to
I(LDO_IN)
O(LDO_OUT)
Load regulation
> 2.7 V, I
I(LDO_IN) O(LDO_OUT)
0.6% 1.3%
250 mA ( a percentage of V
)
set
V
V
≥ V
≥ 2.7 V, I
+ 0.6 V
O(LDO_OUT)
I(LDO_IN)
Regulated output voltage set
range
V
SET
= 0 mA to
O(LDO_OUT)
0.9
3.3
V
I(LDO_IN)
250 mA
V
V
ADJ reference voltage
Drop-out voltage
0.8
V
V
ref
V
– V
= 250 mA
= –0.1 V,
SET
I(LDO_IN)
0.18
0.5
DROP
I
O(LDO_OUT)
Vac = 1 kHz sine wave, 100 mV
superimposed on LDO_IN, C = 4.7 µF,
L
pp
Power supply rejection ratio,
20 log(Vac/Vo)
PSRR
50
dB
‡
ESR = 0.25 Ω, I = 5 mA
O
LDO_OUT is enabled into a
short to ground
T = –40°C
to 110°C
J
‡
Short circuit peak current
0.7
2
500
10
10
1
A
LDO current limit
Overload or short circuit dc
current limit
LDO_OUT is over-loaded or en- T = –40°C
J
abled into a short to ground
250
325
mA
to 110°C
LDO forward leakage
V = 0 V, V
O(LDO_OUT) I(LDO_IN)
= 5.5 V,
Current into pin LDO_OUT
Current into pin LDO_OUT
Turnon time
current I
V
= 0 V
LK_LDO
I(EN_LDO)
µA
LDO reverse leakage
V
V
= 5.5 V, V
= 0 V
I(EN_LDO)
= 0 V,
I(LDO_IN)
O(LDO_OUT)
current I
RLK_LDO
From 50% V
to 90% V
,
,
I(EN_LDO)
O(LDO_OUT)
t
0.1
0.1
0.35
0.4
ON_LDO
R = V
L
/0.2, C = 10 µF (20%)
O(LDO_OUT) L
From 50% V
to 10% V
O(LDO_OUT)
I(EN_LDO)
t
Turnoff time
1
OFF_LDO
R
= V
/0.2, C = 10 µF (20%)
O(LDO_OUT) L
ms
mA
L
V
= 5V, V
ramping up from
I(EN_LDO)
I(LDO_IN)
V
ramp-up time (0%
O(LDO_OUT)
10% to 90% in 0.1 ms, R = V
/0.2,
O(LDO_OUT)
0.1
9
0.65
1
L
to 90%)
C
= 10 µF (20%)
L
V
= 3.3 V
15
5
I(PLDN_LDO)
I(LDO_PLDN)
LDO pulldown transistor current
V
= 1 V
‡
Not tested in production.
undervoltage lockout, LDO_IN
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.7
UNIT
V
LDO UVLO rising threshold
LDO UVLO falling threshold
2.25
250
2.45
V
‡
UVLO hysteresis
mV
‡
Not tested in production.
9
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
electrical characteristics over recommended operating junction temperature range,
V
=3.3VforTPS2140/50,V
=5VforTPS2141/51,V
=5V,alloutputsunloaded
I(SW_IN)
I(SW_IN)
I(LDO_IN)
(unless otherwise noted) (continued)
logic section (SW_EN, SW_EN, LDO_EN, ADJ, SW_PG, LDO_PG)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
, source
V
V
V
= 0 V
= 5 V
1
1
5
I(/SW_EN)
I(/SW_EN)
I(SW_EN)
I(EN_LDO)
Logic input current
, sink
5
1
µA
I(SW_EN)
I(LDO_EN)
= 0 V – 5.5 V
–1
2
V
V
V
V
V
V
V
V
IH_MIN(/SW_EN)
IH_MIN(SW_EN)
IH_MIN(LDO_EN)
IL_MAX(/SW_EN)
IL_MAX(SW_EN)
IL_MAX(LDO_EN)
IF(/SW_EN)
Logic input high level
2
V
V
2
0.8
0.8
0.8
Logic input low level
Floating input voltage
SW_EN pin is open
SW_EN pin is open
2.5
V
0.4
1
IF(SW_EN)
LDO feedback input current
SW_PG sense threshold, V
I
V
I(ADJ)
= 0 V – 5.5 V
–1
µA
I(ADJ)
TPS2140, TPS2150
TPS2141, TPS2151
Percentage of V
85%
88%
90%
TH_SW
I(SW_IN)
A percentage of output voltage set point
, derived from a resistor divider
LDO_PG sense threshold, V
92%
94%
96%
TH_LDO
V
SET
‡
PG hysteresis (all)
V
2%
1
2.5%
2.5
3.5%
TH_HYS
‡
SW_PG rising edge deglitch
t
t
ms
d_SWPG_rise
d_PG_fail
‡
PG falling edge deglitches times (all)
50
150
µs
V
SW_PG minimum output high state
voltage
Source current I
= 1 mA,
I(SW_IN)
O(SW_PG)
> V
TH_SW
V
V
V
OH_MIN(SW_PG)
V
–0.5
I(SW_OUT)
SW_PG maximum output low state
voltage
Sink current I
= 1 mA,
O(SW_PG)
V
0.5
0.5
OL_MAX(SW_PG)
V
< V
TH_SW
I(SW_OUT)
LDO_PG maximum output low state
voltage
Sink current I
= 1 mA,
O(SW_PG)
OH_MIN(LDO_PG)
V
< V
TH_LDO
I(LDO_OUT)
LDO_PG leakage current
I
V
= 5.5 V
1
µA
LK(LDO_PG)
O(LDO_PG)
‡
Not tested in production.
thermal shutdown characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
‡
‡
Over temperature trip point
Low thermal shutdown
125
137
Switch and/or LDO in current limit
°C
‡
(whole device)
Hysteresis
10
10
Over temperature trip point
155
170
High thermal shutdown
(whole device)
Switch and LDO are not in current limit
°C
‡
Hysteresis
‡
Not tested in production.
10
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
V
V
O(LDO_OUT)
O(SW_OUT)
I
O
I
O
C
C
L
L
LOAD CIRCUIT
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
V
DD
DD
SW_EN
LDO_EN
50%
50%
50%
50%
GND
GND
t
t
pd(off)
pd(off)
t
t
pd(on)
O(SW_OUT)
pd(on)
O(LDO_OUT)
V
V
I(SW_IN)
(SET)
90%
10%
90%
10%
V
V
GND
GND
Propagation Delay (SW_OUT)
Propagation Delay (LDO_OUT)
t
t
t
t
r
f
r
f
V
V
I(SW_IN)
(SET)
V
V
O(SW_OUT)
90%
10%
O(LDO_OUT)
90%
10%
GND
GND
Rise/Fall Time (SW_OUT)
Rise/Fall Time (LDO_OUT)
V
V
DD
DD
SW_EN
LDO_EN
50%
50%
50%
50%
GND
GND
t
t
off
off
t
t
on
on
V
V
I(SW_IN)
(SET)
90%
10%
90%
10%
V
V
O(SW_OUT)
O(LDO_OUT)
GND
GND
Turn On/Off Time (SW_OUT)
Turn On/Off Time (LDO_OUT)
Figure 1. Test Circuits and Voltage Waveforms
Current
Meter
DUT
IN
OUT
A
+
Figure 2. Current Limit Test Circuit
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TPS2150, TPS2151
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PARAMETER MEASUREMENT INFORMATION
V
I (SW_EN)
5 V/div
V
I (SW_EN)
5 V/div
LDO_EN = 5 V
LDO_EN = 0 V
V
V
O (SW_OUT)
5 V/div
V
V
O (SW_OUT)
5 V/div
O (SW_OUT)
5 V/div
O (SW_OUT)
5 V/div
t – Time – 1 ms/div
t – Time – 200 µs/div
Figure 3. Switch Turnon Delay and Rise Time With Figure 4. Switch Turnoff Delay and Fall Time With
10-µF Load (SW_OUT Shorted With SW_PLDN) 10-µF Load (SW_OUT Shorted With SW_PLDN)
V
I (SW_EN)
5 V/div
V
I (SW_EN)
5 V/div
LDO_EN = 5 V
LDO_EN = 0 V
V
V
O (SW_OUT)
5 V/div
V
V
O (SW_OUT)
5 V/div
O (SW_OUT)
5 V/div
O (SW_OUT)
5 V/div
t – Time – 10 ms/div
t – Time – 2 ms/div
Figure 5. Switch Turnon Delay and Rise Time With Figure 6. Switch Turnoff Delay and Fall Time With
120-µF Load (SW_OUT Shorted With SW_PLDN)
120-µF Load (SW_OUT Shorted With SW_PLDN)
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SLVS399 – JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
V
V
I (SW_EN)
5 V/div
I (SW_EN)
5 V/div
C
= 600 µF
L(SW_OUT)
C
= 10 µF
L(SW_OUT)
I
I
I (SW_IN)
50 m A/div
I (SW_IN)
0.1 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 7. Switch Turnon Inrush Current With
Different Load Capacitance
Figure 8. Switch Short-Circuit Current, With
Switch Enabled Into a Short Circuit
V
V
I (LDO_EN)
5 V/div
I (LDO_EN)
5 V/div
SW_EN = 5 V
SW_EN = 0 V
V
V
O (LDO_OUT)
1 V/div
SW_EN = 5 V
SW_EN = 0 V
V
V
O (LDO_OUT)
1 V/div
O (LDO_OUT)
1 V/div
O (LDO_OUT)
1 V/div
t – Time – 1 ms/div
t – Time – 200 µs/div
Figure 9. LDO Turnon Delay and Rise Time With 4.7
Figure 10. LDO Turnoff Delay and Fall Time With
4.7 µF Load (LDO_OUT Shorted With LDO_PLDN)
µF Load (LDO_OUT Shorted With LDO_PLDN)
13
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
V
V
I (LDO_EN)
O(LDO_OUT)
5 V/div
1 V/div
I
I (LDO_IN)
0.2 A/div
I
I (LDO_IN)
0.2 A/div
t – Time – 1 ms/div
t – Time – 1 ms/div
Figure 11. LDO Short-Circuit Current, With LDO
Enabled Into a Short Circuit
Figure 12. LDO Short-Circuit Current, With
Short Circuit Connected Into Enabled LDO
C
= 4.7 µF
L
5.5 V
ESR = 1 Ω
3.3 V
V
V
O(LDO_OUT)
0.2 V/div
I (LDO_IN)
1 V/div
3.8 V
3.3 V
250 mA
V
O (LDO_OUT)
0.1 V/div
I
O(LDO_OUT)
0.1 A/div
0 mA
C
= 4.7 µF
L
ESR = 1 Ω
t – Time – 100 µs/div
t – Time – 25 µs/div
Figure 13. LDO Line Transient Response
Figure 14. LDO Load Transient Response
14
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
LDO TYPICAL REGIONS OF STABILITY
LDO TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
EQUIVALENT SERIES RESISTANCE
vs
vs
LOAD CURRENT
LOAD CURRENT
100
10
100
10
V = 2.7 5 V,
V = 2.7 5 V,
I
I
V
C
= 0.9 V,
= 4.7 µF
V
= 0.9 V,
O
O
O
C
= 10 µF
O
Max ESR
Max ESR
1
1
Min ESR
100
Min ESR
100
0.1
0.1
0
50
150
200
250
0
50
I
150
200
250
I
L
– Load Current – mA
– Load Current – mA
L
Figure 15
Figure 16
LDO TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
SUPPLY CURRENT
vs
LOAD CURRENT
JUNCTION TEMPERATURE
140
120
100
80
100
V = 2.7 5 V,
I
Switch on,
LDO on
V
= 0.9 V,
O
C
= 100 µF
O
10
1
Max ESR
Switch off
LDO on
60
Switch on,
LDO off
40
0.1
Switch off,
LDO off
20
0
Min ESR
0.01
0
50
100
150
200
250
–50
0
50
100
150
I
L
– Load Current – mA
T
J
– Junction Temperature – °C
Figure 17
Figure 18
15
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
SWITCH STATIC DRAIN-SOURCE
SUPPLY CURRENT
vs
ON-STATE RESISTANCE
vs
SUPPLY VOLTAGE
JUNCTION TEMPERATURE
140
60
SW = On,
LDO = On
V
= 5 V
I (SW_IN)
120
50
40
SW = Off,
LDO = On
100
80
60
40
20
0
30
20
10
0
SW = On,
LDO = Off
SW = Off,
LDO = Off
2.5
3
3.5
4
4.5
5
5.5
–50
0
50
100
150
V
CC
– Supply Voltage – V
T
J
– Junction Temperature – °C
Figure 19
Figure 20
TPS2140
SWITCH SHORT-CIRCUIT CURRENT
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
vs
JUNCTION TEMPERATURE
SUPPLY VOLTAGE
78
77
76
75
74
50
45
40
35
30
25
20
15
10
73
72
5
0
–50
0
50
100
150
2.5
3
3.5
4
4.5
5
5.5
T
J
– Junction Temperature – °C
V
CC
– Supply Voltage – V
Figure 21
Figure 22
16
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
SWITCH SHORT-CIRCUIT CURRENT
LDO SHORT-CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
vs
SUPPLY VOLTAGE
90
80
322
321
70
60
50
40
30
320
319
318
317
316
315
314
313
20
10
0
2.5
3
3.5
4
4.5
5
5.5
–50
0
50
100
150
V
CC
– Supply Voltage – V
T
J
– Junction Temperature – °C
Figure 23
Figure 24
LDO SHORT-CIRCUIT CURRENT
vs
SUPPLY VOLTAGE
312
310
308
306
304
302
300
298
296
2.5
3
3.5
4
4.5
5
5.5
V
CC
– Supply Voltage – V
Figure 25
17
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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
APPLICATION INFORMATION
external capacitor requirements on power lines
Ceramic bypass capacitors (0.01 µF to 0.1 µF) between SW_IN and GND and LDO_IN and GND, close to the
device, are recommended to improve load transient response and noise rejection. Bulk capacitors (4.7 µF or
higher) between SW_IN and GND and LDO_IN and GND are also recommended, especially if load transients
in the hundreds of milliamps with fast rise times are anticipated. A 66-µF bulk capacitor is recommended from
SW_OUT to ground, especially when the output load is heavy. This precaution helps reduce transients seen
on the power rails. Additionally, bypassing the outputs with a 0.1-µF ceramic capacitor improves the immunity
of the device to short-circuit transients.
LDO output capacitor requirements
Stabilizing the internal control loop of the LDO requires an output capacitor connected between LDO_OUT and
GND. The minimum recommended capacitance is 4.7 µF with an ESR value between 200 mΩ and 8.5 Ω. Solid
tantalum electrolytic, aluminum electrolytic and multilayer ceramic capacitors are all suitable, provided they
meet the ESR requirements (see Figures 15, 16, and 17). The adjustable LDO (for output voltages lower than
3 V) requires a bypass capacitor across the feedback resistor as shown in Figure 26. The nominal value of this
capacitor is determined by using the following equation:
1
C +
Ǔ * 4 pF
f
3
ǒ
63.7 10 2 3.14 R1
(1)
where R1 is derived by programming the adjustable LDO (see programming the adjustable LDO regulator
section shown below).
TPS2140/41/50/51
LDO_IN
LDO_OUT
R1
R2
C
0.1 µF
f
0.1 µF
10 µF
4.7 µF
LDO_EN
GND
ADJ
Figure 26. LDO External Resistor Divider
programming the adjustable LDO regulator
The output voltage of the TPS2140/41/50/51 adjustable regulator is programmed using an external resistor
divider as shown in Figure 26. The output voltage is calculated using equation 2:
R1
ref ǒ1 )
Ǔ
LDO_OUT + V
R2
where V = 0.8 V typical (internal reference voltage).
(2)
ref
Resistors R1 and R2 should be chosen for approximately 4-µA (minimum) divider current. Lower value resistors
can be used but offer no inherent advantage and waste more power. Higher values should be avoided as a
minimum load is required to sink the LDO forward leakage and maintain regulation. The recommended design
procedure is to choose R2 = 200 kΩ to set the divider current at 4-µA and then solve the LDO_OUT equation
for R1.
18
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TPS2140, TPS2141
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APPLICATION INFORMATION
programming the adjustable LDO regulator (continued)
Table 1. Output Voltage Programming Guide
OUTPUT VOLTAGE
R1
R2
Cf
†
3.3
625 kΩ
550 kΩ
425 kΩ
250 kΩ
175 kΩ
50 kΩ
200 kΩ
200 kΩ
200 kΩ
200 kΩ
200 kΩ
200 kΩ
NR
NR
†
3.0
2.5
2 pF
6 pF
1.8
1.5
1.0
10.3 pF
46 pF
†
NR – Not required
overcurrent
When an overcurrent condition is detected, the device maintains a constant output current. Complete shutdown
occurs only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output is shorted before the device is
enabled. Once enabled the TPS2140/41/50/51 sense the short and immediately switch to a constant-current
output.
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a very short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded. The TPS2140/41/50/51 are capable of delivering current up to the current-limit threshold without
damagingthedevice. Oncethethresholdhasbeenreached, thedeviceswitchesintoitsconstant-currentmode.
dual current limit
The TPS2140/41/50/51 has a dual-current-limited power switch. When the output voltage of the power switch
is below a defined power-good threshold voltage, the typical current the switch can conduct is approximately
75 mA. Therefore, the inrush current can be limited to about 75 mA even if there is a very large capacitor on
the load. When the switch output voltage reaches the power-good threshold voltage, the internal controller
enables the higher current limit, which is at least 0.8 A and at most 1.8 A. This dual-current-limit feature
completely solves the large inrush current problems that most power management applications experience.
Figure 7 shows the inrush currents with different load capacitance. The current spike at C = 600 µF is due to
L
voltage difference between input and output once the higher current limit is enabled.
Because the lower current limit is only about 75 mA, the initial resistive load or equivalent load current on the
switch output must be less than 50 mA, excluding the load capacitors.
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APPLICATION INFORMATION
power dissipation and junction temperature
The major source of power dissipation for the TPS2140/41/50/51 comes from the internal voltage regulator and
the N-channel MOSFET. Checking the power dissipation and junction temperature is always a good design
practice and it starts with determining the r
of the N-channel MOSFET according to the input voltage and
DS(on)
operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and
read r from the graphs shown in the Typical Characteristics section of this data sheet. Using this value,
DS(on)
the power dissipation per switch can be calculated using:
2
P = r
× I
D
DS(on)
(3)
The power dissipation for the internal voltage regulator is calculated using:
+ ǒVI–V
Ǔ
P
I
D
O(min)
O
(4)
(5)
(6)
The total power dissipation for the device becomes:
= P + P
P
D(total)
D(LDO)
D(switch)
Finally, calculate the junction temperature:
T = P × R
+ T
A
J
D
θJA
Where:
T = Ambient temperature °C
A
R
= Thermal resistance °C/W, equal to inverting the derating factor found on the power dissipation
θJA
table in this data sheet.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The overcurrent faults force the TPS2140/41/50/51 into constant-current mode at
first, whichcausesthevoltageacrossthehigh-sideswitchtoincrease;undershort-circuitconditions, thevoltage
across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to
rise to high levels.
IfeitherthepowerdistributionswitchortheLDOisinovercurrent, athermalsensortripsatapproximately135°C,
turning off both circuits. Normal operation resumes when the die temperature drops approximately 10°C. If
neither the power distribution switch nor the LDO is in overcurrent, a second thermal sensor trips at
approximately 160°C. Normal operation resumes when the die temperature drops approximately 10°C.
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APPLICATION INFORMATION
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the device (LDO and switch) is in the off state at power up. The UVLO
also keeps the device from being turned on until the power supply has reached the start threshold (see
undervoltage lockout table), even if the switches are enabled. The UVLO is also activated whenever the input
voltage falls below the stop threshold as defined in the undervoltage lockout table. This function facilitates the
design of hot-insertion systems where it is not possible to turn off the power switches before input power is
removed. Upon reinsertion, the power switches are turned on with a controlled rise time to reduce EMI and
voltage overshoots.
universal serial bus (USB) applications
The universal serial bus (USB) interface is a multiplexed serial bus operating at either 12 Mbps, or 1.5 Mbps
for USB 1.1, or 480 Mbps for USB 2.0. The USB interface is designed to accommodate the bandwidth required
by PC peripherals such as keyboards, printers, scanners, and mice. The four-wire USB interface was conceived
for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two
lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D
D
D
D
D
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions
The TPS2140/41/50/51 are well suited for USB hub and peripheral applications. The internal LDO can be used
to provide the 3.3-V power needed by the controller while the switch distributes power to the downstream
functions.
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
D
Hosts/self-powered hubs must:
–
–
Current-limit downstream ports
Report overcurrent conditions on USB VBUS
D
Bus–powered hubs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 µF)
D
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
21
www.ti.com
TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
APPLICATION INFORMATION
USB power-distribution requirements (continued)
The feature set of the TPS2140/41/50/51 allows them to meet the requirements of functions. The integrated
current-limiting is required by hubs and peripheral functions. The logic-level enable and controlled rise times
meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered
functions.
USB applications
Figure 27 shows the TPS2151 being used in a USB bus-powered peripheral design. The internal 3.3-V LDO
is used to provide power for the USB function controller as well as to the 1.5-kΩ pullup resistor. One example
of USB bus-powered peripheral applications is the USB ADSL modem, which needs several power rails and
power sequencing.
D+
D–
USB
Function
Controller
TPS2151
GND
5 V
1.5 kΩ
LDO_PLDN
LDO_OUT
3.3 V
LDO_IN
LDO
4.7 µF
0.1 µF
0.1 µF
10 µF
ADJ
LDO_EN
LDO_PG
3.3 V
Circuitry
SW_EN
SW_IN
SW_OUT
SW_PLDN
Switch
†
C
5 V
0.1 µF
Circuitry
SW_PG
†
C can be very high-value capacitance
Figure 27. Bus-Powered USB Peripheral Application
22
www.ti.com
TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
APPLICATION INFORMATION
DSP applications
Figure 28 shows the TPS2150 in a DSP application. DSPs use 1.8-V core voltage and 3.3-V I/O voltage. In this
type of application the TPS2150 adjustable LDO is configured for a 1.8-V output specifically for the DSP core
voltage.
Theadditional3.3-VcircuitryispoweredthroughtheswitchoftheTPS2150onlyaftertheDSPisupandrunning.
3.3 V
TPS2150
Power
Supply
LDO_PLDN
TMS320Cxxxx
CVDD
4.7 µF
LDO_OUT
1.8 V
LDO_IN
LDO
LDO_EN
0.1 µF 10 µF
ADJ
LDO_PG
DVDD
RESET
SW_EN
SW_IN
3.3 V
SW_OUT
Switch
†
0.1 µF
C
SW_PLDN
Additional
3.3 V
0.1 µF
Circuitry
SW_PG
†
C can be very high-value capacitance
Figure 28. DSP Power Sequencing Application
system level design consideration of DSP power application
System level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as (or prior to and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus preventing bus contention with other chips on the board.
For some DSP systems, the core supply may be required to provide a considerable amount of current until the
I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s).
Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize
the effects of this current draw.
23
www.ti.com
TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/F 10/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
24
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Copyright 2002, Texas Instruments Incorporated
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