TPS22968NQDMGTQ1 [TI]

具有可调节上升时间和输出放电功能的 2 通道、5.5V、4A、27mΩ 汽车负载开关 | DMG | 10 | -40 to 125;


型号：	TPS22968NQDMGTQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有可调节上升时间和输出放电功能的 2 通道、5.5V、4A、27mΩ 汽车负载开关 \| DMG \| 10 \| -40 to 125 开关
文件：	总33页 (文件大小：1139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

TPS22968-Q1 5.5V、4A、27mΩ 导通电阻负载开关

1 特性

2 应用

•

集成双通道负载开关

符合汽车应用要求:

•

汽车电子产品

信息娱乐

仪表板

–

器件温度 1 级（工作环境温度范围：-40°C 至

125°C）

ADAS

•

输入电压范围：0.8V 至 5.5V

VBIAS 电压范围：2.5V 至 5.5V

导通电阻

3 说明

TPS22968-Q1 是一款具有可配置上升时间的小型双通

道负载开关。此器件包含两个可在 0.8 至 5.5V 输入电

压范围内运行的 N 通道 MOSFET，并且每通道可支持

最大 4A 的持续电流。每个开关可由一个打开/关闭输

入（ON1 和 ON2）独立控制，此输入可与低压控制信

号直接对接。 TPS22968-Q1 包含一个 270Ω 片上负

载电阻，用于在此开关被关闭时进行快速输出放电。

–

V_IN= 5V (V_BIAS= 5V) 时，R_ON= 29mΩ

V_IN= 3.3V (V_BIAS= 5V) 时，R_ON= 27mΩ

V_IN= 1.8V (V_BIAS= 5V) 时，R_ON= 26mΩ

•

每通道最大 4A 持续开关电流

低静态电流

–

V_BIAS= 5V 时为 58μA（双通道）

•

低控制输入阈值支持使用 1.2/1.8/2.5/3.3V 逻辑器

件

可通过 CT 引脚⁽¹⁾配置上升时间

快速输出放电 (QOD)⁽²⁾

TPS22968-Q1 采用节省空间的小型封装 (DMG)，并且

具有可湿性侧面和集成散热焊盘。可湿性侧面支持目

视焊接检查。器件在自然通风环境下的额定运行温度

范围为 40°C 至 125°C。

•

10 引脚晶圆级小外形无引线 (WSON) 封装，具有

可湿性侧面

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

•

静电放电 (ESD) 性能经测试符合 JEDEC STD 标准

TPS22968-Q1

WSON (10)

2.00mm x 3.00mm

–

±2kV 人体模型 (HBM) 和 ±1kV 器件充电模型

(CDM)

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

锁断性能达 100mA，符合 JESD 78 II 类规范的要

求

•

通用输入输出 (GPIO) 使能 - 高电平有效

(1)

有关 CT 值与上升时间的关系，请参见 Adjustable Rise Time

(2)

此特性通过一个 270Ω 电阻将开关的输出放电至接地 (GND)，

从而防止输出悬空。

典型应用电路原理图

VIN1

VOUT1

Dual

Power

Supply

C_IN

ON1

C_L

R_L

CT1

CT2

OFF

GND

VBIAS

Dual

DC/DC

converter

VIN2

ON2

VOUT2

C_IN

C_L

R_L

OFF

GND

TPS22968-Q1

GND

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLVSCP7

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 15

8.3 Feature Description................................................. 16

8.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

9.1 Application Information............................................ 17

9.2 Typical Application .................................................. 20

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics (V_BIAS= 5 V)..................... 5

6.6 Electrical Characteristics (V_BIAS= 3.3 V).................. 6

6.7 Electrical Characteristics (V_BIAS= 2.5 V).................. 7

6.8 Switching Characteristics.......................................... 8

6.9 Typical DC Characteristics........................................ 9

6.10 Typical AC Characteristics.................................... 11

Parameter Measurement Information ................ 14

Detailed Description ............................................ 15

10 Power Supply Recommendations ..................... 22

11 Layout................................................................... 22

11.1 Layout Guidelines ................................................. 22

11.2 Layout Example .................................................... 23

11.3 Thermal Considerations........................................ 24

12 器件和文档支持 ..................................................... 25

12.1 商标....................................................................... 25

12.2 静电放电警告......................................................... 25

12.3 术语表 ................................................................... 25

13 机械封装和可订购信息 .......................................... 25

4 修订历史记录

Changes from Original (November 2014) to Revision A

Page

•

已将器件状态更改为量产数据 ................................................................................................................................................. 1

TPS22968-Q1

www.ti.com.cn

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

5 Pin Configuration and Functions

DMG Package

(Top View)

DMG Package

(Bottom View)

VIN1

ON1

VOUT1

VIN1

ON1

CT1

GND

VBIAS

ON2

GND

CT2

VBIAS

ON2

CT2

VIN2

VOUT2

VIN2

Pin Functions

I/O

DESCRIPTION

NAME

VIN1

ON1

NO.

Switch 1 input. Bypass this input with a ceramic capacitor to GND.

Active-high switch 1 control input. Do not leave floating.

Bias voltage. Power supply to the device. Recommended voltage range for this pin is 2.5 to 5.5 V. See

V_INand V_BIASVoltage Range.

VBIAS

ON2

Active-high switch 2 control input. Do not leave floating.

VIN2

Switch 2 input. Bypass this input with a ceramic capacitor to GND.

VOUT2

CT2

—

Switch 2 output

Switch 2 slew rate control. Can be left floating.

GND

Ground

CT1

Switch 1 slew rate control. Can be left floating.

VOUT1

Thermal Pad

—

Switch 1 output

Thermal pad (exposed center pad) to alleviate thermal stress. Tie to GND. See Layout Guidelines.

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature (unless otherwise noted)⁽¹⁾

(2)

MIN

–0.3

MAX

UNIT

V_IN1,2

V_BIAS

Input voltage

Bias voltage

V_OUT1,2Output voltage

V_ON1,2

I_MAX

I_PLS

ON voltage

Maximum continuous switch current per channel, T_A= 50 °C

Maximum pulsed switch current, pulse <300 µs, 2% duty cycle

Maximum junction temperature

T_J

150

300

150

°C

T_LEAD

T_stg

Maximum lead temperature (10-s soldering time)

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged-Device Model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

MAX

V_BIAS

5.5

UNIT

V_IN1,2

Input voltage range

Bias voltage range

ON voltage range

Output voltage range

0.8

2.5

V_BIAS

V_ON1,2

V_OUT1,2

5.5

V_IN

V_{IH, ON1,2}High-level input voltage, ON1,2

V_{IL, ON1,2}Low-level input voltage, ON1,2

V_BIAS= 2.5 to 5.5 V

1.2

5.5

0.5

C_IN1,2

T_A

Input capacitor

1⁽¹⁾

µF

°C

(2)

Operating free-air temperature

–40

125

(1) Refer to Application Information.

(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature [T_A(max)] is dependent on the maximum operating junction temperature [T_J(max)], the

maximum power dissipation of the device in the application [P_D(max)], and the junction-to-ambient thermal resistance of the part/package

in the application (R_θJA), as given by the following equation: T_A(max)= T_J(max)– (R_θJA× P_D(max)).

TPS22968-Q1

www.ti.com.cn

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

6.4 Thermal Information

TPS22968-Q1

UNIT

THERMAL METRIC^{(1) (2)}

DMG (10 PINS)

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

55.6

71.0

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

21.7

°C/W

1.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

21.7

7.3

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

6.5 Electrical Characteristics (V_BIAS= 5 V)

V_BIAS= 5 V. Typical values are for T_A= 25°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP MAX

UNIT

POWER SUPPLIES AND CURRENTS

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

V_BIASquiescent current (both

channels)

I_OUT1= I_OUT2= 0 A,

V_IN1,2= V_ON1,2= V_BIAS= 5 V

µA

I_{Q, VBIAS}

V_BIASquiescent current (single I_OUT1= I_OUT2= 0 A,

channel)

V_ON2= 0 V, V_IN1,2= V_ON1= V_BIAS= 5.0 V

I_{SD, VBIAS}

V_BIASshutdown current

V_ON1,2= 0 V, V_OUT1,2= 0 V

0.5

0.1

0.07

0.05

0.04

V_IN1,2= 5 V

V_IN1,2= 3.3 V

V_IN1,2shutdown current (per

channel)

V_ON1,2= 0 V,

V_IN1,2= 1.8 V

V_OUT1,2= 0 V

I_{SD, VIN1,2}

µA

V_IN1,2= 1.2 V

V_IN1,2= 0.8 V

I_ON1,2

ON pin input leakage current

V_ON= 5.5 V

0.1

µA

mΩ

RESISTANCE CHARACTERISTICS

25°C

320

V_IN= 5 V

–40°C to 85°C

–40°C to 125°C

25°C

V_IN= 3.3 V

–40°C to 85°C

–40°C to 125°C

25°C

I_OUT= –200 mA,

V_IN= 1.8 V

R_ON

ON-state resistance

–40°C to 85°C

–40°C to 125°C

25°C

V_BIAS= 5 V

V_IN= 1.2 V

–40°C to 85°C

–40°C to 125°C

25°C

V_IN= 0.8 V

–40°C to 85°C

–40°C to 125°C

mΩ

R_PD

Output pulldown resistance

V_IN= 5 V, V_ON= 0 V, I_OUT= 5 mA

270

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

6.6 Electrical Characteristics (V_BIAS= 3.3 V)

V_BIAS= 3.3 V. Typical values are for T_A= 25°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP MAX

UNIT

POWER SUPPLIES AND CURRENTS

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

V_BIASquiescent current (both

channels)

I_OUT1= I_OUT2= 0 A,

V_IN1,2= V_ON1,2= V_BIAS= 3.3 V

µA

I_{Q, VBIAS}

V_BIASquiescent current (single I_OUT1= I_OUT2= 0 A, V_ON2= 0 V,

channel)

V_IN1,2= V_ON1= V_BIAS= 3.3 V

0.5

I_{SD, VBIAS}

V_BIASshutdown current

V_ON1,2= 0 V, V_OUT1,2= 0 V

0.1

V_IN1,2= 3.3 V

V_IN1,2= 1.8 V

V_IN1,2= 1.2 V

V_IN1,2= 0.8 V

0.07

0.05

0.04

V_IN1,2shutdown current (per

channel)

V_ON1,2= 0 V,

V_OUT1,2= 0 V

I_{SD, VIN1,2}

µA

I_ON1,2

ON pin input leakage current

V_ON= 5.5 V

0.1

µA

mΩ

RESISTANCE CHARACTERISTICS

25°C

320

V_IN= 3.3 V

V_IN= 1.8 V

V_IN= 1.2 V

V_IN= 0.8 V

–40°C to 85°C

–40°C to 125°C

25°C

–40°C to 85°C

–40°C to 125°C

25°C

I_OUT= –200 mA,

V_BIAS= 3.3 V

R_ON

ON-state resistance

–40°C to 85°C

–40°C to 125°C

25°C

–40°C to 85°C

–40°C to 125°C

mΩ

R_PD

Output pulldown resistance

V_IN= 3.3 V, V_ON= 0 V, I_OUT= 5 mA

270

TPS22968-Q1

www.ti.com.cn

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

6.7 Electrical Characteristics (V_BIAS= 2.5 V)

V_BIAS= 2.5 V. Typical values are for T_A= 25°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP MAX

UNIT

POWER SUPPLIES AND CURRENTS

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

V_BIASquiescent current (both

channels)

I_OUT1= I_OUT2= 0,

V_IN1,2= V_ON1,2= V_BIAS= 2.5 V

µA

I_{Q, VBIAS}

V_BIASquiescent current (single I_OUT1= I_OUT2= 0,

channel)

V_ON2= 0 V, V_IN1,2= V_ON1= V_BIAS= 2.5 V

0.4

I_{SD, VBIAS}

V_BIASshutdown current

V_ON1,2= 0 V, V_OUT1,2= 0 V

0.1

V_IN1,2= 2.5 V

0.07

0.05

0.04

V_IN1,2= 1.8 V

V_IN1,2= 1.2 V

V_IN1,2= 0.8 V

V_IN1,2shutdown current (per

channel)

V_ON1,2= 0 V,

V_OUT1,2= 0 V

I_{SD, VIN1,2}

µA

I_ON1,2

ON pin input leakage current

V_ON= 5.5 V

0.1

µA

mΩ

RESISTANCE CHARACTERISTICS

25°C

320

V_IN= 2.5 V

V_IN= 1.8 V

V_IN= 1.2 V

V_IN= 0.8 V

–40°C to 85°C

–40°C to 125°C

25°C

–40°C to 85°C

–40°C to 125°C

25°C

I_OUT= –200 mA,

V_BIAS= 2.5 V

R_ON

ON-state resistance

–40°C to 85°C

–40°C to 125°C

25°C

–40°C to 85°C

–40°C to 125°C

mΩ

R_PD

Output pulldown resistance

V_IN= 2.5 V, V_ON= 0 V, I_OUT= 5 mA

270

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

MAX UNIT

6.8 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

V_IN= V_ON= V_BIAS= 5 V, T_A= 25 °C (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

ON delay time

R_L= 10 Ω, C_L= 0.1 µF, CT = 1000 pF

1150

1400

µs

t_F

t_D

469

V_IN= 0.8 V, V_ON= V_BIAS= 5 V, T_A= 25 ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

ON delay time

R_L= 10 Ω, C_L= 0.1 µF, CT = 1000 pF

514

271

t_F

t_D

382

V_IN= 3.3 V, V_ON= 5 V, V_BIAS= 3.3 V, T_A= 25 ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

ON delay time

R_L= 10 Ω, C_L= 0.1 µF, CT = 1000 pF

1455

1592

t_F

t_D

681

V_IN= 0.8 V, V_ON= 5 V, V_BIAS= 3.3 V, T_A= 25 ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

ON delay time

R_L= 10 Ω, C_L= 0.1 µF, CT = 1000 pF

805

455

t_F

t_D

577

V_IN= 2.5 V, V_ON= 5 V, V_BIAS= 2.5 V, T_A= 25 ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

ON delay time

R_L= 10 Ω, C_L= 0.1 µF, CT = 1000 pF

1800

1830

t_F

t_D

909

V_IN= 0.8 V, V_ON= 5 V, V_BIAS= 2.5 V, T_A= 25 ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

ON delay time

R_L= 10 Ω, C_L= 0.1 µF, CT = 1000 pF

1140

664

t_F

t_D

798

TPS22968-Q1

www.ti.com.cn

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

6.9 Typical DC Characteristics

100

-40°C

25°C

125°C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

V_BIAS(V)

C001

V_ON= 5 V

V_OUT= Open

V_ON= 5 V

V_OUT= Open

Figure 1. I_{Q, VBIAS}vs V_BIAS(Single Channel)

Figure 2. I_{Q, VBIAS}vs V_BIAS(Dual Channel)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.0

1.5

1.0

0.5

0.0

-0.5

-40°C

25°C

-40°C

25°C

125°C

105°C

125°C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V_BIAS(V)

V_IN(V)

C001

V_ON= 0 V

V_OUT= 0 V

V_BIAS= 5 V

V_OUT= 0 V

V_ON= 0 V

Figure 3. I_{SD, VBIAS}vs V_BIAS

Figure 4. I_{SD, VIN}vs V_IN(One Channel)

VIN = 0.8V

VIN = 3.3V

VIN = 5.0V

VIN = 1.8V

VIN = 3.3V

-50

100

150

-50

100

150

Ambient Temperature (C)

C001

I_OUT= –200 mA

Figure 5. R_ONvs Ambient Temperature, V_BIAS= 3.3 V

Figure 6. R_ONvs Ambient Temperature , V_BIAS= 5 V

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

Typical DC Characteristics (continued)

-40°C

25°C

125°C

0.0

2.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V_IN(V)

C001

I_OUT= –200 mA

Figure 7. R_ONvs V_IN, V_BIAS= 3.3 V

Figure 8. R_ONvs V_IN, V_BIAS= 5 V

VIN = 0.8V

VIN = 3.3V

VIN = 5V

VIN = 3.3V

VIN = 2.5V

VIN = 1.8V

1.0

2.0

3.0

4.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

I_OUT(A)

V_BIAS(V)

C001

T_A= 25°C

V_BIAS= 5 V

T_A= 25°C

I_OUT= –200 mA

Figure 9. R_ONvs I_OUT

Figure 10. R_ONvs V_BIAS

320

310

300

290

280

270

260

250

2.5

2.0

1.5

1.0

0.5

0.0

-40°C

25°C

125°C

VBIAS = 2.5V

VBIAS = 3.3V

VBIAS = 5V

VBIAS = 5.5V

3.0

4.0

5.0

6.0

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

V_BIAS(V)

V_ON(V)

C001

V_IN= V_BIAS

V_ON= 0 V

I_OUT= 5 mA

T_A= 25°C

V_IN= 2 V

Figure 11. R_PDvs V_BIAS

Figure 12. V_OUTvs V_ON

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6.10 Typical AC Characteristics

C_IN= 1 µF, C_L= 0.1 µF, R_L= 10 Ω, CT = 1 nF (unless otherwise specified)

900

800

700

600

500

400

300

550

500

450

400

350

300

-40°C

25°C

-40°C

25°C

125°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V_IN(V)

C001

Figure 13. t_Dvs V_IN, V_BIAS= 3.3 V

Figure 14. t_Dvs V_IN, V_BIAS= 5 V

3.5

3.0

2.5

2.0

1.5

1.0

3.5

3.0

2.5

2.0

1.5

1.0

-40°C

25°C

-40°C

25°C

125°C

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0

2.0

3.0

4.0

6.0

V_IN(V)

C001

Figure 15. t_Fvs V_IN, V_BIAS= 3.3 V

Figure 16. t_Fvs V_IN, V_BIAS= 5 V

-40°C

25°C

125°C

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0

2.0

3.0

4.0

6.0

V_IN(V)

C001

Figure 17. t_OFFvs V_IN, V_BIAS= 3.3 V

Figure 18. t_OFFvs V_IN, V_BIAS= 5 V

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

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Typical AC Characteristics (continued)

C_IN= 1 µF, C_L= 0.1 µF, R_L= 10 Ω, CT = 1 nF (unless otherwise specified)

1700

1600

1500

1400

1300

1200

1100

1000

900

1200

1100

1000

900

-40°C

25°C

-40°C

25°C

125°C

800

700

600

500

800

700

400

0.0

2.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V_IN(V)

C001

Figure 19. t_ONvs V_IN, V_BIAS= 3.3 V

Figure 20. t_ONvs V_IN, V_BIAS= 5 V

1600

1400

1200

1000

800

-40°C

25°C

-40°C

25°C

1800

1600

1400

1200

1000

800

125°C

600

400

600

400

200

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0

2.0

3.0

4.0

5.0

6.0

V_IN(V)

C001

Figure 21. t_Rvs V_IN, V_BIAS= 3.3 V

Figure 22. t_Rvs V_IN, V_BIAS= 5 V

2000

1800

1600

1400

1200

1000

800

-40°C

VIN = 5V

14000

12000

10000

8000

6000

4000

2000

25°C

VIN = 3.3V

VIN = 1.8V

125°C

600

400

3.0

3.5

4.0

4.5

5.0

2000

4000

6000

8000

10000

V_BIAS(V)

C_T(pF)

C001

V_IN= 2.5 V

V_BIAS= 5 V

T_A= 25°C

Figure 23. t_Rvs V_BIAS

Figure 24. t_Rvs CT

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Typical AC Characteristics (continued)

C_IN= 1 µF, C_L= 0.1 µF, R_L= 10 Ω, CT = 1 nF (unless otherwise specified)

Figure 25. Turn-On Response Time

(V_IN= 0.8 V, V_BIAS= 2.5 V)

Figure 26. Turn-On Response Time

(V_IN= 0.8 V, V_BIAS= 5 V)

Figure 27. Turn-On Response Time

(V_IN= 2.5 V, V_BIAS= 2.5 V)

Figure 28. Turn-On Response Time

(V_IN= 5 V, V_BIAS= 5 V)

Figure 29. Turn-Off Response Time

(V_IN= 0.8 V, V_BIAS= 2.5 V)

Figure 30. Turn-Off Response Time

(V_IN= 0.8 V, V_BIAS= 5 V)

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

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Typical AC Characteristics (continued)

C_IN= 1 µF, C_L= 0.1 µF, R_L= 10 Ω, CT = 1 nF (unless otherwise specified)

Figure 31. Turn-Off Response Time

(V_IN= 2.5 V, V_BIAS= 2.5 V)

Figure 32. Turn-Off Response Time

(V_IN= 5 V, V_BIAS= 5 V)

7 Parameter Measurement Information

VIN

VOUT

CT1,2

C_IN= 1 μF

VBIAS

C_L

–

R_L

-–

(A)

GND

TPS22968-Q1

GND

OFF

Single channel shown for clarity.

Test Circuit

V_ON

50%

t_F

t_OFF

t_R

V_OUT

t_ON

90%

V_OUT

50%

10%

t_D

Timing Waveforms

A. Rise and fall times of the control signal is 100 ns.

Figure 33. Test Circuit and Timing Waveforms

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ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

8 Detailed Description

8.1 Overview

The device is a 5.5-V, 4-A, dual-channel ultra-low R_ONload switch with controlled turn on. The device contains

two N-channel MOSFETs. Each channel can support a maximum continuous current of 4 A. Each channel is

controlled by an on/off GPIO-compatible input. The ON pin must be connected and cannot be left floating. The

device is designed to control the turn-on rate and therefore the inrush current. By controlling the inrush current,

power supply sag can be reduced during turn-on. The slew rate for each channel is set by connecting a capacitor

to GND on the CT pins.

The slew rate is proportional to the capacitor on the CT pin. Refer to Adjustable Rise Time to determine the

correct CT value for a desired rise time.

The internal circuitry is powered by the VBIAS pin, which supports voltages from 2.5 to 5.5 V. This circuitry

includes the charge pump, QOD, and control logic. For these internal blocks to function correctly, a voltage

between 2.5 and 5.5 V must be supplied to VBIAS.

When a voltage is supplied to VBIAS and the ON1, 2 pin goes low, the QOD turns on. This connects VOUT1, 2

to GND through an on-chip resistor. The typical pulldown resistance (R_PD) is 270 Ω.

8.2 Functional Block Diagram

VIN1

Control

Logic

ON1

CT1

VOUT1

GND

VBIAS

Charge Pump

VOUT2

CT2

Control

Logic

ON2

VIN2

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8.3 Feature Description

8.3.1 ON/OFF Control

The ON pins control the state of the switch. Asserting ON high enables the switch. ON is active high and has a

low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard

GPIO logic threshold. It can be used with any microcontroller with 1.2-V or higher GPIO voltage. This pin cannot

be left floating and must be tied either high or low for proper functionality.

8.3.2 Quick Output Discharge (QOD)

The TPS22968-Q1 includes a QOD feature. When the switch is disabled, a discharge resistor is connected

between VOUT and GND. This resistor has a typical value of 270 Ω and prevents the output from floating while

the switch is disabled.

8.3.3 Adjustable Rise Time

A capacitor to GND on the CT pins sets the slew rate for each channel. The capacitor to GND on the CT pins

should be rated for 25 V and above. An approximate formula for the relationship between CT and slew rate with

V_BIAS= 5 V is:

SR = 0.35 × CT + 25

where

•

SR = slew rate (in µs/V)

CT = the capacitance value on the CT pin (in pF)

The units for the constant 25 is in µs/V.

(1)

Rise time can be calculated by multiplying the input voltage by the slew rate. Table 1 contains rise time values

measured on a typical device.

Table 1. Rise Time Table

Rise Time (µs)^{(1) (2)}

CTx (pF)

V_IN= 5 V

V_IN= 3.3 V

V_IN= 2.5 V

V_IN= 1.8 V

V_IN= 1.2 V

V_IN= 0.8 V

220

418

285

223

168

122

470

711

479

372

276

196

139

1000

2200

4700

10000

1405

3236

6415

13872

952

738

545

385

271

2174

4306

9261

1684

3317

7150

1246

2454

5253

876

615

1725

3694

1217

2591

(1) 10% - 90%, C_L= 0.1 µF, C_IN= 1 µF, R_L= 10 Ω, V_BIAS= 5 V

(2) Typical values at 25°C with a 25-V X7R 10% ceramic capacitor on CT

8.4 Device Functional Modes

Table 2. Functional Table

ONx

VINx to VOUTx

VOUTx to GND

Off

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

This section highlights some of the design considerations for implementing this device in various applications. A

PSPICE model for this device is also available on the product page for further aid.

9.1.1 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a

discharged load capacitor, a capacitor must be placed between VIN and GND. A 1-µF ceramic capacitor, C_IN,

placed close to the pins, is usually sufficient. Higher values of C_INcan be used to further reduce the voltage drop

during high-current applications. When switching heavy loads, TI recommends to have an input capacitor about

10× higher than the output capacitor to avoid excessive voltage drop.

9.1.2 Output Capacitor (Optional)

Due to the integrated body diode in the NMOS switch, TI highly recommends a C_INgreater than C_L. A C_Lgreater

than C_INcan cause the voltage on VOUT to exceed VIN when the system supply is removed. This could result in

current flow through the body diode from VOUT to VIN. TI recommends a C_INto C_Lratio of 10 to 1 for minimizing

V_INdip caused by inrush currents during startup.

9.1.3 V_INand V_BIASVoltage Range

For optimal R_ONperformance, make sure V_IN≤ V_BIAS. The device is still functional if V_IN> V_BIAS, but it will exhibit

R_ONgreater than what is listed in the Electrical Characteristics (V_BIAS= 5 V) and Electrical Characteristics (V_BIAS

= 2.5 V). See Figure 34 for an example of a typical device. Notice the increasing R_ONas V_INexceeds V_BIAS

voltage. Be sure to never exceed the maximum voltage rating for V_INand V_BIAS

VBIAS = 2.5V

VBIAS = 3.3V

VBIAS = 5V

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V_IN(V)

C001

T_A= 25°C

I_OUT= –200 mA

Figure 34. R_ONvs V_IN

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ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

Application Information (continued)

9.1.3.1 Parallel Configuration

To increase the current capabilities and lower the R_ONby approximately 50%, both channels can be placed in

parallel as shown in Figure 35 (parallel configuration). With this configuration, the CT1 and CT2 pins can be tied

together to use one capacitor, CT, as shown in Figure 35. With a single CT capacitor, the rise time will be half of

the typical rise-time value. Refer to the Table 1 for typical timing values.

VBIAS

VIN1

ON1

VOUT1

CT1

Power

System

Module

Source

TPS22968-Q1

VIN2

ON2

VOUT2

CT2

µC GPIO

GND

Figure 35. Parallel Configuration Schematic

9.1.3.2 Standby Power Reduction

TPS22968-Q1 can help to reduce the standby power consumption of a module. Some loads will consume a non-

trivial amount of power when turned off. If the power to the load is removed by the load switch, the standby

power consumption can be significantly reduced.

Always ON

Module

VBIAS

VIN1

ON1

VOUT1

CT1

Power

Source

TPS22968-Q1

GND

Standby

Module

µC GPIO

Single channel shown for clarity.

Figure 36. Standby Power Reduction Schematic

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ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

Application Information (continued)

9.1.3.3 Power Supply Sequencing Without a GPIO Input

In many end equipments, there is a need to power up various modules in a predetermined manner. TPS22968-

Q1 can solve the problem of power sequencing without adding any complexity to the overall system.

µC GPIO

VBIAS

VIN1

ON1

VOUT1

CT1

Power

Module 1

Source

TPS22968-Q1

VIN2

ON2

VOUT2

CT2

Power

Module 2

Source

GND

A. VIN1 must be greater V_IH

Figure 37. Power Sequencing Without a GPIO Input Schematic

9.1.3.4 Reverse Current Blocking

In certain applications, it may be desirable to have reverse current blocking. Reverse current blocking prevents

current from flowing from the output to the input of the load switch when the device is disabled. With the following

configuration, the TPS22968-Q1 can be converted into a single-channel switch with reverse current blocking. In

this configuration, VIN1 or VIN2 can be used as the input and VIN2 or VIN1 is the output.

VBIAS

VIN1

ON1

VOUT1

CT1

Power

Source

TPS22968-Q1

VIN2

ON2

VOUT2

CT2

System

Module

GND

µC GPIO

Figure 38. Reverse Current Blocking Schematic

TPS22968-Q1

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9.2 Typical Application

This application demonstrates how the TPS22968-Q1 can be used to power a downstream load with a large

capacitance. The example in Figure 39 is powering a 22-µF capacitive output load.

VIN1

ON1

VOUT1

Dual

Power

Supply

C_IN

C_L

R_L

CT1

CT2

OFF

GND

VBIAS

Dual

DC/DC

converter

VIN2

ON2

VOUT2

C_IN

C_L

R_L

OFF

GND

TPS22968-Q1

GND

Figure 39. Typical Application Schematic for Powering a Downstream Module

9.2.1 Design Requirements

For this design example, use the following as the input parameters.

Table 3. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_IN

3.3 V

5.0 V

V_BIAS

Output capacitance (C_L)

Allowable inrush current on VOUT

22 µF

0.400 A

9.2.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

•

V_INvoltage

V_BIASvoltage

Output capacitance (C_L)

Allowable inrush current on VOUT due to C_Lcapacitor

9.2.2.1 Inrush Current

To determine how much inrush current will be caused by the C_Lcapacitor, use Equation 2.

dV_OUT

= C_L´

INRUSH

where

•

I_INRUSH= amount of inrush current caused by C_L

C_L= capacitance on VOUT

dt = V_OUTrise time

dV_OUT= increase in V_OUTduring the rise time

(2)

Inrush current is proportional to rise time. The rise time is adjustable by use of the CT capacitor. The appropriate

rise time can be calculated using the design requirements and the inrush current equation (Equation 2).

400 mA = 22 µF × 3.3 V / dt

dt = 182 µs

(3)

(4)

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ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

To ensure an inrush current of less than 400 mA, choose a CT capacitor value that will yield a rise time of more

than 182 µs. See the oscilloscope captures in the Application Curves for an example of how the CT capacitor

can be used to reduce inrush current. See Table 1 for correlation between rise times and CT values.

An appropriate C_Lvalue should be placed on VOUT such that the I_MAXand I_PLSspecifications of the device are

not violated.

9.2.3 Application Curves

The two scope captures below show how the CT capacitor can be used to reduce inrush current.

VBIAS = 5 V

CT = Open

VIN = 3.3 V

C_L= 22 µF

T_A= 25°C

VBIAS = 5 V

CT = 220 pF

VIN = 3.3 V

C_L= 22 µF

T_A= 25°C

Figure 40. Inrush Current Without CT Capacitor

Figure 41. Inrush Current With CT = 220 pF

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ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

10 Power Supply Recommendations

The device is designed to operate from a V_BIASrange of 2.5 to 5.5 V and V_INrange of 0.8 to 5.5 V. This supply

must be well regulated and placed as close to the device pin as possible with the recommended 1-µF bypass

capacitor. If the supply is located more than a few inches from the device pins, additional bulk capacitance may

be required in addition to the ceramic bypass capacitors. If additional bulk capacitance is required, an electrolytic,

tantalum, or ceramic capacitor of 10 µF may be sufficient.

11 Layout

11.1 Layout Guidelines

•

VIN and VOUT traces should be as short and wide as possible to accommodate for high current.

Use vias under the exposed thermal pad for thermal relief for high current operation.

VINx pins should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical recommended

bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to

the device pins as possible.

•

VOUTx pins should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is one-tenth of the VINx bypass capacitor of X5R or X7R dielectric rating.

This capacitor should be placed as close to the device pins as possible.

•

The VBIAS pin should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.

The CTx capacitors should be placed as close to the device pins as possible. The typical recommended CTx

capacitance is a capacitor of X5R or X7R dielectric rating with a rating of 25 V or higher.

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ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

11.2 Layout Example

VIN1

ON1

VOUT1

CT1

VBIAS

ON2

GND

CT2

VIN2

VOUT2

Dual-channel layout

VIN1

ON1

VOUT1

CT1

VBIAS

ON2

GND

CT2

VIN2

VOUT2

Single-channel layout

Via to internal

or bottom layer

Via to GND

Figure 42. Layout Schematic

TPS22968-Q1

ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

11.3 Thermal Considerations

The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. To

calculate the maximum allowable dissipation, P_D(max)for a given ambient temperature, use Equation 5.

T_J(MAX)- T_A

D(MAX)

R_θJA

where

•

P_D(max)= maximum allowable power dissipation

T_J(max)= maximum allowable junction temperature (150°C for the TPS22968-Q1)

T_A= ambient temperature of the device

_θJA= junction to air thermal impedance. See Thermal Information. This parameter is highly dependent upon

board layout. (5)

Following are two examples demonstrating how to use the above information: For V_BIAS= 5 V, V_IN= 5 V, the

maximum allowable ambient temperature with a 3-A load through each channel can be determined by using the

following calculations.

NOTE

When calculating power dissipation in the switch, it is important to use the correct R_ON

value. R_ONis dependent on the junction temperature of the device.

P_D= I²× R × 2 (multiplied by 2 because there are two channels)

(6)

T_J(MAX)ꢀ T_A

2uI²uR

R_ꢀ-$

(7)

(8)

(9)

T_A= T_J(MAX)– R_θJA× 2 × I²× R

T_A= 150°C – 55.6°C/W × 2 × (3 A)²× 45 mΩ = 105°C

For V_BIAS= 5 V, V_IN= 5 V, the maximum continuous current for an ambient temperature of 85°C with the same

current flowing through each channel can be determined by using the following calculation:

T_J(MAX)- T_A

2´I²´R =

R_θJA

(10)

T_J(MAX)- T_A

I =

2´ R ´ R_θJA

(11)

ꢀꢁꢂq& ± ꢃꢁq&

2 u 45 m: u 55.6qC / W

3.6 A

(12)

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ZHCSDD9A –NOVEMBER 2014–REVISED FEBRUARY 2015

12 器件和文档支持

12.1 商标

All trademarks are the property of their respective owners.

12.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS22968NQDMGRQ1

TPS22968NQDMGTQ1

TPS22968QDMGRQ1

TPS22968QDMGTQ1

ACTIVE

WSON

DMG

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

Level-3-260C-168 HR

-40 to 125

11C

SIV

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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23-Jun-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS22968-Q1 :

Catalog : TPS22968

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS22968NQDMGRQ1 WSON

DMG

3000

250

179.0

8.4

2.3

3.2

1.0

4.0

8.0

TPS22968NQDMGTQ1

TPS22968QDMGRQ1

TPS22968QDMGTQ1

WSON

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS22968NQDMGRQ1

TPS22968NQDMGTQ1

TPS22968QDMGRQ1

TPS22968QDMGTQ1

WSON

DMG

3000

250

213.0

191.0

35.0

3000

250

Pack Materials-Page 2

PACKAGE OUTLINE

DMG0010A

WSON - 0.8 mm max height

SCALE 4.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

SEATING PLANE

(0.2) TYP

0.8

0.7

0.08 C

0.05

0.00

0.84 0.1

EXPOSED

THERMAL PAD

2.4 0.1

8X 0.5

0.3

0.2

10X

0.1

0.05

C A B

PIN 1 ID

(OPTIONAL)

0.35

10X

0.25

4222056/B 02/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DMG0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

10X (0.5)

10X (0.25)

(0.84)

(R0.05) TYP

(0.95)

(2.4)

SYMM

8X (0.5)

SYMM

(1.9)

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL EDGE

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222056/B 02/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

DMG0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.8)

SYMM

10X (0.5)

10X (0.25)

(1.08)

SYMM

(0.64)

METAL

TYP

(R0.05) TYP

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

86% PRINTED SOLDER COVERAGE BY AREA

SCALE:30X

4222056/B 02/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TPS22968NQDMGTQ1 [TI]

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