TPS22969 [TI]
具有输出放电功能的 5.5V、6A、4.4mΩ 负载开关;
| 型号： | TPS22969 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有输出放电功能的 5.5V、6A、4.4mΩ 负载开关 开关 |
| 文件： | 总30页 (文件大小：1955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS22969
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
TPS22969 5.5V，6A，4.4mΩ 导通电阻负载开关
1 特性
3 说明
1
•
•
•
•
集成单通道负载开关
TPS22969 是一款小型，超低 RON，单通道负载开
关，此开关具有受控开启功能。 此器件包含一个可在
0.8V 至 5.5V 的输入电压范围内运行的 N 通道金属氧
化物半导体场效应晶体管 (MOSFET)，并且支持 6A 的
最大持续
VBIAS 电压范围：2.5V 至 5.5V
VIN 电压范围：0.8V 至 5.5V
超低 RON 电阻
–
VIN = 1.05V (VBIAS = 5V) 时，RON = 4.4mΩ
电流。
•
•
•
•
6A 最大持续开关电流
低静态电流（VBIAS = 5V 时为 20µA（典型值））
低关断电流（VBIAS = 5V 时为 1µA（典型值））
器件的超低 RON 和高电流处理能力的组合使得此器件
非常适合于驱动具有非常严格压降耐受的处理器电源
轨。 器件的受控上升时间大大减少了由大容量负载电
容导致的涌入电流，从而减少或消除了电源损耗。 此
开关可由 ON 端子单独控制，此端子能够与微控制器
或低压离散逻辑电路生成的低压控制信号直接对接。
通过集成一个 224Ω 下拉电阻器，在开关关闭时实现
快速输出放电 (QOD)，此器件进一步减少总体解决方
案尺寸。
低控制输入阀值允许使用 1.2V 或更高通用输入输
出 (GPIO) 接口
•
V
BIAS 和 VIN 范围内的受控和固定转换率
VIN = 1.05V (VBIAS = 5V) 时，tR = 599µs
–
•
•
快速输出放电 (QOD)
带有散热焊盘的小外形尺寸无引线 (SON) 8 端子封
装
•
静电放电 (ESD) 性能经测试符合 JESD 22 规范
TPS22969 采用小型 3mm x 3mm SON-8 封装
–
–
2kV 人体模型 (HBM)
(DNY)。 DNY 封装集成有一个散热焊盘，此散热焊盘
可在高电流和高温应用中实现高功率耗散。 器件在自
然通风环境下的额定运行温度范围为 -40°C 至 85°C。
1kV 充电器件模型 (CDM)
2 应用范围
•
•
•
•
•
•
•
•
Ultrabook™/笔记本电脑
台式个人电脑
工业用个人电脑
Chromebook
服务器
器件信息
订货编号
封装
封装尺寸
3mm x 3mm
超薄小外形尺寸封装
(WSON) (8)
TPS22969DNY
机顶盒
电信系统
平板电脑
4 简化电路原理图
RON 与 VIN 之间的关系（此时，VBIAS = 5V，IOUT = -
200mA）
6
5.5
5
4.5
4
典型应用：驱动用于处理器的高电流内核电
源轨
3.5
-40C
3
25C
2.5
85C
2
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8
DG007
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCJ7
TPS22969
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
www.ti.com.cn
目录
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
Applications and Implementation ...................... 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 3
7.1 Absolute Maximum Ratings ...................................... 3
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Electrical Characteristics........................................... 6
7.7 Switching Characteristics.......................................... 7
7.8 Typical Characteristics.............................................. 9
Detailed Description ............................................ 14
9
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 20
12 器件和文档支持 ..................................................... 21
12.1 Trademarks........................................................... 21
12.2 Electrostatic Discharge Caution............................ 21
12.3 Glossary................................................................ 21
13 机械封装和可订购信息 .......................................... 21
8
5 修订历史记录
Changes from Original (February 2014) to Revision A
Page
•
完整版的最初发布版本。 ....................................................................................................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
TPS22969
www.ti.com.cn
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
6 Terminal Configuration and Functions
DNY PACKAGE
8 TERMINAL
VOUT
1
2
3
4
VIN
8
7
6
5
VOUT
VOUT
8
7
6
5
VIN
VIN
1
2
3
4
VOUT
VIN
VIN
(Exposed thermal
pad)
VIN
(Exposed thermal
pad)
VBIAS
ON
VOUT
GND
VBIAS
ON
VOUT
GND
Top View
Bottom View
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
Switch input. Place ceramic bypass capacitor(s) between this terminal and GND. See the Detailed
Description section for more information.
VIN
1, 2
I
I
Exposed thermal
Pad
Switch input. Place ceramic bypass capacitor(s) between this terminal and GND. See the Detailed
Description section for more information.
VIN
VBIAS
ON
3
4
5
I
I
Bias voltage. Power supply to the device.
Active high switch control input. Do not leave floating.
Ground.
GND
–
Switch output. Place ceramic bypass capacitor(s) between this terminal and GND. See the Detailed
Description section for more information.
VOUT
6, 7, 8
O
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
6
UNIT
V
VIN
Input voltage range
VBIAS
VOUT
VON
IMAX
IPLS
TA
Bias voltage range
6
V
Output voltage range
6
V
ON terminal voltage range
6
V
Maximum Continuous Switch Current
Maximum Pulsed Switch Current, pulse < 300-µs, 2% duty cycle
Operating free-air temperature range
Maximum junction temperature
6
A
8
A
–40
85
125
°C
°C
TJ
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2014, Texas Instruments Incorporated
3
TPS22969
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
www.ti.com.cn
7.2 Handling Ratings
MIN
MAX
UNIT
°C
TSTG
Storage temperature range
–65
150
300
2
TLEAD
Maximum lead temperature (10-s soldering time)
Human-Body Model (HBM)(2)
Charged-Device Model (CDM)(3)
°C
kV
(1)
VESD
1
kV
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
0.8
2.5
0
MAX
VBIAS
5.5
UNIT
V
VIN
Input voltage range
Bias voltage range
ON voltage range
Output voltage range
VBIAS
VON
VOUT
V
5.5
V
VIN
V
VIH, ON High-level voltage, ON
VIL, ON Low-level voltage, ON
VBIAS = 2.5V to 5.5V
VBIAS = 2.5V to 5.5V
1.2
0
5.5
V
0.5
V
CIN
Input Capacitor
1(1)
µF
(1) Refer to Detailed Description section.
7.4 Thermal Information
TPS22969
THERMAL METRIC(1)
UNIT
DNY
8 TERMINALS
RθJA
Junction-to-ambient thermal resistance
44.6
44.4
17.6
0.4
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
17.4
1.1
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
TPS22969
www.ti.com.cn
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
7.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature
–40°C ≤ TA ≤ 85°C (Full) and VBIAS = 5.0V. Typical values are for TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CURRENTS AND THRESHOLDS
IOUT = 0, VIN = VBIAS
VON = 5.0V
,
IQ, VBIAS
VBIAS quiescent current
VBIAS shutdown current
Full
Full
20.4
1.1
26.0
µA
µA
ISD, VBIAS
VON = 0V, VOUT = 0V
1.5
0.1
0.1
0.1
0.1
0.1
0.1
VIN = 5.0V
VIN = 3.3V
VIN = 1.8V
VIN = 1.05V
VIN = 0.8V
VON = 0V,
VOUT = 0V
ISD, VIN
VIN shutdown current
Full
µA
ION
ON terminal leakage current
ON terminal hysteresis
VON = 5.5V
VBIAS = VIN
Full
µA
VHYS, ON
25°C
113
4.4
4.4
4.4
4.4
4.4
4.4
mV
RESISTANCE CHARACTERISTICS
25°C
Full
5.0
5.6
5.0
5.6
5.0
5.6
5.0
5.6
5.0
5.6
5.0
5.6
VIN = 5.0V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 1.05V
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
25°C
Full
25°C
Full
IOUT = –200mA,
VBIAS = 5.0V
25°C
Full
RON
On-state resistance
25°C
Full
25°C
Full
VIN = 0.8V
IOUT = –6A,
VBIAS = 5.0V
VIN = 1.05V
Full
Full
4.6
5.8(1)
233
mΩ
RPD
Output pulldown resistance
VIN = 5.0V, VON = 0V, VOUT = 1V
224
Ω
(1) Parameter verified by design and characterization, but not tested in production.
Copyright © 2014, Texas Instruments Incorporated
5
TPS22969
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
www.ti.com.cn
7.6 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature
–40°C ≤ TA ≤ 85°C (Full) and VBIAS = 2.5V. Typical values are for TA = 25°C unless otherwise noted.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CURRENTS AND THRESHOLDS
IOUT = 0, VIN = VBIAS
VON = 5.0V
,
IQ, VBIAS
VBIAS quiescent current
VBIAS shutdown current
Full
Full
9.9
0.5
12.5
µA
µA
ISD, VBIAS
VON = 0V, VOUT = 0V
0.65
0.1
0.1
0.1
0.1
VIN = 2.5V
VIN = 1.8V
VIN = 1.05V
VIN = 0.8V
VON = 0V,
VOUT = 0V
ISD, VIN
VIN shutdown current
Full
µA
ON terminal input leakage
current
ION
VON = 5.5V
VBIAS = VIN
Full
0.1
µA
VHYS, ON
ON terminal hysteresis
25°C
83
4.7
4.6
4.5
4.5
224
mV
RESISTANCE CHARACTERISTICS
25°C
Full
5.3
6.0
5.2
5.8
5.1
5.7
5.1
5.7
233
VIN =2.5V
VIN =1.8V
VIN =1.05V
VIN = 0.8V
mΩ
mΩ
mΩ
25°C
Full
IOUT = –200mA,
VBIAS = 2.5V
RON
On-state resistance
25°C
Full
25°C
Full
mΩ
RPD
Output pulldown resistance
VIN = 2.5V, VON = 0V, VOUT = 1V
Full
Ω
6
Copyright © 2014, Texas Instruments Incorporated
TPS22969
www.ti.com.cn
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
7.7 Switching Characteristics
Refer to the timing test circuit in Figure 1 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN and VBIAS are already in steady state condition before the ON terminal is asserted high.
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VIN = 5V, VON = VBIAS = 5V, TA = 25ºC (unless otherwise noted)
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
2397
4
RL = 10Ω, CL = 0.1µF
2663
2
µs
tF
tD
1009
VIN = 1.05V, VON = VBIAS = 5V, TA = 25ºC (unless otherwise noted)
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
1064
4
RL = 10Ω, CL = 0.1µF
599
2
µs
µs
µs
µs
µs
tF
tD
727
VIN = 0.8V, VON = VBIAS = 5V, TA = 25ºC (unless otherwise noted)
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
981
4
RL = 10Ω, CL = 0.1µF
500
2
tF
tD
714
VIN = 2.5V, VON = 5V, VBIAS = 2.5V, TA = 25ºC (unless otherwise noted)
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
1576
8
RL = 10Ω, CL = 0.1µF
1372
2
tF
tD
865
VIN = 1.05V, VON = 5V, VBIAS = 2.5V, TA = 25ºC (unless otherwise noted)
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
1080
8
RL = 10Ω, CL = 0.1µF
604
2
tF
tD
738
VIN = 0.8V, VON = 5V, VBIAS = 2.5V, TA = 25ºC (unless otherwise noted)
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
994
8
RL = 10Ω, CL = 0.1µF
502
2
tF
tD
723
Copyright © 2014, Texas Instruments Incorporated
7
TPS22969
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
www.ti.com.cn
VIN
ON
VOUT
CIN = 1µF
ON
(A)
CL
+
-
RL
OFF
VBIAS
GND
TPS22969
GND
GND
Timing Test Circuit
VON
50%
50%
tF
tOFF
tR
VOUT
tON
90%
90%
VOUT
50%
50%
10%
10%
10%
tD
Timing Waveforms
(A) Rise and fall times of the control signal is 100ns.
Figure 1. Switching Characteristics Measurement Setup and Definitions
8
Copyright © 2014, Texas Instruments Incorporated
TPS22969
www.ti.com.cn
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
7.8 Typical Characteristics
25
20
15
10
5
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40C
25C
85C
-40C
25C
85C
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
VBIAS (V)
DG001
VBIAS (V)
DG002
VIN = VBIAS
VON = 5V
IOUT = 0A
VIN = VBIAS
VON = 0V
VOUT = 0V
Figure 2. IQ,VBIAS vs VBIAS
Figure 3. ISD,VBIAS vs VBIAS
6
0.03
5.5
5
0.025
0.02
0.015
0.01
0.005
0
4.5
4
3.5
3
-40C
25C
85C
VIN = 0.8V
VIN =1.2V
VIN =1.8V
VIN = 1.05V
VIN =1.5V
VIN =2.5V
2.5
2
-40
-15
10
35
60
85
DG004
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8
DG003_5V
Ambient Temperature (C)
VBIAS = 2.5V
VON = 5V
IOUT = –200mA
VBIAS = 5V
VON = 0V
VOUT = 0V
Figure 5. RON vs Ambient Temperature
Figure 4. ISD,VIN vs VIN
6
5.5
5
6
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
-40C
25C
85C
2.4
VIN = 0.8V
VIN = 1.2V
VIN = 2.5V
VIN = 4.2V
VIN = 1.05V
VIN = 1.8V
VIN = 3.3V
VIN =5V
2.5
2
2.5
2
0.8
1
1.2
1.4
1.6
1.8
2
2.2
-40
-15
10
35
60
85
DG006
DG005
VIN (V)
Ambient Temperature (C)
VBIAS = 5V
VON = 5V
IOUT = –200mA
VBIAS = 2.5V
VON = 5V
IOUT = –200mA
Figure 6. RON vs Ambient Temperature
Figure 7. RON vs VIN
Copyright © 2014, Texas Instruments Incorporated
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TPS22969
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
www.ti.com.cn
Typical Characteristics (continued)
6
6
5.5
5
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
-40C
25C
VBIAS = 2.5V
VBIAS = 5V
2.5
2
2.5
2
85C
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8
DG007
DG012
VBIAS = 5V
VON = 5V
IOUT = –200mA
TA = 25°C
VON = 5V
IOUT = –200mA
Figure 8. RON vs VIN
Figure 9. RON vs VIN
6
240
235
230
225
220
215
210
205
200
5.5
5
4.5
4
3.5
3
-40C
25C
85C
-40C
25C
85C
2.5
2
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.5 2.75
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
DG010
VIN (V)
DG016
VBIAS (V)
VBIAS = 2.5V
VON = 5V
IOUT = -6A
VON = 0V
VIN = 1.05V
VOUT = 1V
Figure 11. RON vs VIN at 6A load
Figure 10. RPD vs VBIAS
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
-40C
25C
85C
-40C
25C
85C
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8
2.5 2.75
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
DG017HYS
DG011
VBIAS (V)
VBIAS = 5V
VON = 5V
IOUT = -6A
VIN = VBIAS
Figure 12. RON vs VIN at 6A load
Figure 13. VHYS vs VBIAS
10
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TPS22969
www.ti.com.cn
ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
Typical Characteristics (continued)
1.2
1.2
1.1
1
1.1
1
0.9
0.8
0.7
0.6
0.5
0.9
0.8
0.7
0.6
0.5
-40C
25C
85C
-40C
25C
85C
2.5 2.75
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
2.5 2.75
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
DG098
DG017H
VBIAS (V)
VBIAS (V)
VIN = VBIAS
IOUT = 0A
VIN = VBIAS
IOUT = 0A
Figure 14. VIL,ON vs VBIAS
Figure 15. VIH,ON vs VBIAS
1000
1200
1100
1000
900
800
700
600
500
400
900
800
700
600
500
400
-40C
25C
85C
-40C
25C
85C
0.8
1.05
1.3
1.55
VIN (V)
1.8
2.05
2.3
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8
DG018
DG019
VBIAS = 2.5V
RL = 10Ω
CL = 0.1µF
VBIAS = 5V
RL = 10Ω
CL = 0.1µF
Figure 16. tD vs VIN
Figure 17. tD vs VIN
4
3
2
1
0
4
3
2
1
0
-40C
25C
85C
-40C
25C
85C
0.8
1.05
1.3
1.55
VIN (V)
1.8
2.05
2.3
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8
DG020
DG021
VBIAS = 2.5V
RL = 10Ω
CL = 0.1µF
VBIAS = 5V
RL = 10Ω
CL = 0.1µF
Figure 18. tF vs VIN
Figure 19. tF vs VIN
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Typical Characteristics (continued)
12
6
5
4
3
2
11
10
9
8
7
-40C
25C
85C
-40C
25C
85C
6
5
4
0.8
1.05
1.3
1.55
VIN (V)
1.8
2.05
2.05
2.05
2.3
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4
4
4.4 4.8
DG022
DG024
VBIAS = 2.5V
RL = 10Ω
CL = 0.1µF
VBIAS = 5V
RL = 10Ω
CL = 0.1µF
Figure 20. tOFF vs VIN
Figure 21. tOFF vs VIN
1800
3000
2500
2000
1500
1000
500
1600
1400
1200
1000
800
-40C
25C
85C
-40C
25C
85C
600
0.8
1.05
1.3
1.55
VIN (V)
1.8
2.3
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4.4 4.8
DG025
DG026
VBIAS = 2.5V
RL = 10Ω
CL = 0.1µF
VBIAS = 5V
RL = 10Ω
CL = 0.1µF
Figure 22. tON vs VIN
Figure 23. tON vs VIN
1600
3000
2500
2000
1500
1000
500
1400
1200
1000
800
-40C
25C
85C
-40C
25C
85C
600
400
0
0.8
1.05
1.3
1.55
VIN (V)
1.8
2.3
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4.4 4.8
DG027
DG028
VBIAS = 2.5V
RL = 10Ω
CL = 0.1µF
VBIAS = 5V
RL = 10Ω
CL = 0.1µF
Figure 24. tR vs VIN
Figure 25. tR vs VIN
12
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Typical Characteristics (continued)
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
VIN = 0.8V
VIN = 1.05V
VIN =1.5V
VIN =2.5V
VIN =3.6V
VIN =5.0V
3750
3250
2750
2250
1750
1250
750
VIN =1.2V
VIN =1.8V
VIN =3.3V
VIN =4.2V
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 3.6V
VBIAS = 4.2V
VBIAS = 5.0V
VBIAS = 5.5V
250
500
2.5 2.75
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
VIN (V)
4
4.4 4.8 5.2
VBIAS (V)
DG030
DG023
TA = 25°C
RL = 10Ω
CL = 0.1µF
TA = 25°C
RL = 10Ω
CL = 0.1µF
Figure 27. tR vs VBIAS for Various VIN
Figure 26. tR vs VIN for Various VBIAS
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8 Detailed Description
8.1 Overview
The device is a 5.5V, 6A load switch in a 8-terminal SON package. To reduce voltage drop for low voltage and
high current rails, the device implements an ultra-low resistance N-channel MOSFET which reduces the drop out
voltage through the device.
The device has a controlled and fixed slew rate which helps reduce or eliminate power supply droop due to large
inrush currents. During shutdown, the device has very low leakage currents, thereby reducing unneccessary
leakages for downstream modules during standby. Integrated control logic, driver, charge pump, and output
discharge FET eliminates the need for any external components, which reduces solution size and BOM count.
8.2 Functional Block Diagram
VIN
Charge
Pump
VBIAS
Control
Logic
Driver
ON
VOUT
GND
14
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8.3 Feature Description
8.3.1 On/off Control
The ON terminal controls the state of the load switch, and asserting the terminal high (active high) enables the
switch. The ON terminal is compatible with standard GPIO logic threshold and can be used with any
microcontroller or discrete logic with 1.2-V or higher GPIO voltage. This terminal cannot be left floating and must
be tied either high or low for proper functionality.
8.3.2 Input Capacitor (CIN)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic
capacitor, CIN, placed close to the terminals, is usually sufficient. Higher values of CIN can be used to further
reduce the voltage drop in high-current application. When switching heavy loads, it is recommended to have an
input capacitor 10 times higher than the output capacitor to avoid excessive voltage drop; however, a 10 to 1
ratio for capacitance is not required for proper functionality of the device, but a ratio smaller than 10 to 1 (such as
1 to 1) could cause a VIN dip upon turn-on due to inrush currents based on external factor such as board
parasitics and output bulk capacitance.
8.3.3 Output Capacitor (CL)
Due to the integrated body diode in the N-channel MOSFET, a CIN greater than CL is highly recommended. A CL
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current
flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN
dip caused by inrush currents during startup, however a 10 to 1 ratio for capacitance is not required for proper
functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause a VIN dip upon turn-on due to
inrush currents based on external factor such as board parasitics and output bulk capacitance.
8.3.4 VIN and VBIAS Voltage Range
For optimal RON performance, make sure VIN ≤ VBIAS. The device may still be functional if VIN > VBIAS but it will
exhibit RON greater than what is listed in the Electrical Characteristics table. See Figure 28 for an example of a
typical device. Notice the increasing RON as VIN increases. Be sure to never exceed the maximum voltage rating
for VIN and VBIAS. Performance of the device is not guaranteed for VIN > VBIAS
.
10
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 4.2V
VBIAS =5.5V
VBIAS = 3.0V
VBIAS = 3.6V
VBIAS =5.0V
9
8
7
6
5
4
3
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2
DG055
VIN (V)
Figure 28. RON vs VIN (VIN > VBIAS
)
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www.ti.com.cn
9 Applications and Implementation
9.1 Application Information
This section will highlight some of the design considerations when implementing this device in various
applications. A PSPICE model for this device is also available in the product page of this device on www.ti.com
for further aid.
9.2 Typical Application
This application demonstrates how the TPS22969 can be used to power downstream modules with large
capacitances. The example below is powering a 100-µF capacitive output load.
VIN
VOUT
VIN
VOUT
VIN
(exposed
pad)
CIN
CL = 100µF
VBIAS
VBIAS
GND
ON
ON
Figure 29. Typical Application Schematic for Powering a Downstream Module
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
VBIAS
1.05V
5.0V
6A
Load current
9.2.2 Detailed Design Procedure
To begin the design process, the designer needs to know the following:
•
•
•
VIN voltage
VBIAS voltage
Load current
9.2.2.1 VIN to VOUT Voltage Drop
The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN and VBIAS conditions of the device. Refer to the RON specification of the
device in the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based
upon the VIN and VBIAS conditions, use Equation 1 to calculate the VIN to VOUT voltage drop:
DV = ILOAD ´RON
(1)
where
•
•
•
ΔV = voltage drop from VIN to VOUT
ILOAD = load current
RON = On-resistance of the device for a specific VIN and VBIAS combination
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
16
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9.2.2.2 Inrush Current
To determine how much inrush current will be caused by the CL capacitor, use Equation 2:
dVOUT
I
= CL ´
INRUSH
dt
(2)
where
•
•
•
•
IINRUSH = amount of inrush caused by CL
CL = capacitance on VOUT
dt = time it takes for change in VOUT during the ramp up of VOUT when the device is enabled
dVOUT = change in VOUT during the ramp up of VOUT when the device is enabled
An appropriate CL value should be placed on VOUT such that the IMAX and IPLS specficiations of the device are
not violated.
Figure 30. Inrush current (VBIAS = 5V, VIN = 1.05V, CL = 100µF)
9.2.2.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To
calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use
Equation 3.
TJ(MAX) - TA
=
P
D(MAX)
θJA
(3)
where
•
•
•
•
PD(max) = maximum allowable power dissipation
TJ(max) = maximum allowable junction temperature (125°C for the TPS22969)
TA = ambient temperature of the device
ΘJA = junction to air thermal impedance. See Thermal Information section. This parameter is highly
dependent upon board layout.
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9.2.3 Application Curves
VBIAS = 5V
CL = 0.1µF
VIN = 5V
CIN = 1µF
CIN = 1µF
CIN = 1µF
VBIAS = 5V
CL = 0.1µF
VIN = 1.05V
CIN = 1µF
Figure 31. tR at VBIAS = 5V
Figure 32. tR at VBIAS = 5V
VBIAS = 2.5V
CL = 0.1µF
VIN = 2.5V
VBIAS = 2.5V
CL = 0.1µF
VIN = 1.05V
CIN = 1µF
Figure 33. tR at VBIAS = 2.5V
Figure 34. tR at VBIAS = 2.5V
VBIAS = 5V
CL = 0.1µF
VIN = 5V
VBIAS = 5V
CL = 0.1µF
VIN = 2.5V
CIN = 1µF
Figure 35. tF at VBIAS = 5V
Figure 36. tF at VBIAS = 5V
18
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ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
VBIAS = 2.5V
CL = 0.1µF
VIN = 2.5V
CIN = 1µF
VBIAS = 2.5V
CL = 0.1µF
VIN = 0.8V
CIN = 1µF
Figure 37. tF at VBIAS = 2.5V
Figure 38. tF at VBIAS = 2.5V
10 Power Supply Recommendations
The device is designed to operate from a VBIAS range of 2.5-V to 5.5-V and VIN range of 0.8-V to 5.5-V. This
supply must be well regulated and placed as close to the device terminal as possible with the recommended 1µF
bypass capacitor. If the supply is located more than a few inches from the device terminals, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. If additional bulk capacitance is
required, an electrolytic, tantalum, or ceramic capacitor of 10-µF may be sufficient.
11 Layout
11.1 Layout Guidelines
•
•
•
VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
Use vias under the exposed thermal pad for thermal relief for high current operation.
The VIN terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be
placed as close to the device terminals as possible.
•
•
The VOUT terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating.
This capacitor should be placed as close to the device terminals as possible.
The VBIAS terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.
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11.2 Layout Example
VIA to Power Ground Plane
VIA to VIN Plane
VIN Bypass
VIN
Capacitor
VIN
VOUT Bypass
Capacitor
VIN
To Bias Supply
VBIAS
ON
GND
To GPIO
control
Exposed Thermal
Figure 39. Recommended Board Layout
20
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ZHCSCB5A –MARCH 2014–REVISED MARCH 2014
12 器件和文档支持
12.1 Trademarks
Ultrabook is a trademark of Intel.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS22969DNYR
TPS22969DNYT
ACTIVE
ACTIVE
WSON
WSON
DNY
DNY
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
969A0
969A0
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS22969DNYR
TPS22969DNYT
WSON
WSON
DNY
DNY
8
8
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.0
1.0
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS22969DNYR
TPS22969DNYT
WSON
WSON
DNY
DNY
8
8
3000
250
367.0
213.0
367.0
191.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
WSON - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
DNY0008A
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
C
0.8
0.7
SEATING PLANE
0.08 C
0.05
0.00
1.6±0.1
SYMM
0.5
0.3
EXPOSED THERMAL
PAD
5X
(0.2) TYP
6X 0.65
4
5
SYMM
2X
1.95
2.4±0.1
0.35
0.25
8X
0.1
C A B
C
8
1
0.05
PIN1 ID
(OPTIONAL)
2X (0.2)
0.5
0.3
4221022/E 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WSON - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
DNY0008A
(1.6)
5X (0.6)
5X (0.3)
SYMM
(0.6)
1
8
3X (0.65)
SYMM
(1.6)
(0.325)
(2.4)
(0.95)
(0.975)
5
4
(R0.05) TYP
(0.55)
(2.8)
(Ø0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
0.07 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221022/E 06/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WSON - 0.8 mm max height
DNY0008A
PLASTIC QUAD FLATPACK- NO LEAD
2X (1.47)
SYMM
5X (0.6)
5X (0.3)
(0.6)
8
1
(0.325)
(1.6)
(0.63)
SYMM
2X
(1.06)
(0.975)
5
3X (0.65)
4
(R0.05) TYP
METAL
TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4221022/E 06/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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