TPS3806J20QDBVRQ1 [TI]
IC POWER SUPPLY SUPPORT CKT, Power Management Circuit;
| 型号： | TPS3806J20QDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC POWER SUPPLY SUPPORT CKT, Power Management Circuit 光电二极管 |
| 文件： | 总15页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3806I33-Q1
TPS3806J20-Q1
www.ti.com
SLVSBW8 –MARCH 2013
Dual Voltage Detector With Adjustable Hysteresis
Check for Samples: TPS3806I33-Q1, TPS3806J20-Q1
1
FEATURES
DESCRIPTION
•
•
Qualified for Automotive Applications
The TPS3806I33-Q1 integrates two independent
voltage detectors for battery voltage monitoring.
During power on, the device asserts RESET and
RSTSENSE when supply voltage VDD or the voltage
at the LSENSE input becomes higher than 0.8 V.
Thereafter, the supervisory circuit monitors VDD and
LSENSE, keeping RESET and RSTSENSE active as
long as VDD and LSENSE remain below the threshold
voltage, VIT. As soon as VDD or LSENSE rises above
the threshold voltage VIT, the device deasserts
AEC-Q100 Qualified With the Following
Results:
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C4B
•
Dual Voltage Detector With Adjustable
Hysteresis, 3.3-V Adjustable and 2-V
Adjustable
RESET
or
RSTSENSE,
respectively.
The
TPS3806I33-Q1 device has a fixed-sense threshold
voltage VIT set by an internal voltage divider at VDD
and an adjustable second-LSENSE input. In addition,
one can set an upper voltage threshold at HSENSE
•
•
•
•
Assured Reset at VDD = 0.8 V
Supply Current: 3 µA Typical at VDD = 3.3 V
Independent Open-Drain Reset Outputs
6-Pin SOT-23 Package
to
allow
a
wide
adjustable
hysteresis window.
The devices are available in
a
6-pin SOT-23
package. Characterization of the TPS3806I33-Q1
device is for operation over a temperature range of
–40°C to 125°C.
APPLICATIONS
•
•
•
Voltage Supervisor
Voltage Detector
Battery Monitor
TPS3806I33-Q1
DBV PACKAGE
(TOP VIEW)
1
6
5
4
HSENSE
RSTSENSE
GND
2
3
LSENSE
VDD
RESET
R4
R5
V
DD
RESET
TPS3806I33-Q1
R1
R2
LSENSE
RSTSENSE
3.6 V
Li-lon
Cell
HSENSE
GND
R3
Typical Operating Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2013, Texas Instruments Incorporated
TPS3806I33-Q1
TPS3806J20-Q1
SLVSBW8 –MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
TA
PACKAGE
QUANTITY
PART NUMBER
TOP-SIDE SYMBOL
PZHQ
STATUS
Active
TPS3806I33QDBVRQ1
TPS3806J20QDBVRQ1
–40°C to
125°C
DBV (SOT-23)
Reel of 3000
PZZQ
Preview
(1) For the most-current package and ordering information, see the Package Option Addendum located at the end of this data sheet or refer
to the TI Web site at www.ti.com.
TPS380
6
I
33 DBV R
Reel
Package
Nominal Supply Voltage
Nominal Threshold Voltage
Functionality
Family
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TPS3806J20-Q1, TPS3806I33-Q1
UNIT
V
(2)
Supply voltage, VDD
7
All other pins(2)
–0.3 to 7
V
Maximum low-output current, IOL
Maximum high-output current, IOH
5
–5
mA
mA
mA
mA
°C
Input clamp current, IIK (VI < 0 or VI > VDD
)
±10
Output clamp current, IOK (VO < 0 or VO > VDD
Operating free-air temperature range, TA
Storage temperature range, Tstg
)
±10
–40 to 125
–65 to 150
2
°C
Human-body model (HBM) AEC-Q100
Classification Level H2
kV
Electrostatic discharge rating, ESD
Charged-device model (CDM) AEC-Q100
Classification Level C4B
750
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation, the device must not be continuously operated at 7 V for more than
t = 1000 h.
2
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SLVSBW8 –MARCH 2013
THERMAL INFORMATION
TPS3806J20-Q1,
TPS3806I33-Q1
THERMAL METRIC(1)
UNIT
DBV
6 PINS
188.9
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
130.9
34.2
ψJT
25.4
ψJB
33.8
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN
1.3
0
MAX
6
UNIT
V
Supply voltage, VDD
Input voltage, VI
VDD + 0.3
125
V
Operating free-air temperature range, TA
–40
°C
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 1.5 V, IOL = 1 mA
VDD = 3.3 V, IOL = 2 mA
VDD = 6 V, IOL = 3 mA
MIN
TYP
MAX
UNIT
VOL
Low-level output voltage
0.3
V
V
V
Power-up reset voltage(1)
VDD ≥ 0.8 V, IOL = 50 µA
0.2
1.216
1.813
3.022
1.226
1.828
3.048
1.231
1.836
3.06
LSENSE
1.198 1.207
TPS3806J20-Q1
TPS3806I33-Q1
LSENSE
TA = 25°C
1.787
2.978
1.8
3
1.188 1.207
Negative-going
VIT
TPS3806J20-Q1
TPS3806I33-Q1
LSENSE
TA = 0°C to 70°C
TA = –40°C to 125°C
1.772
2.952
1.8
3
V
input threshold voltage(2)
1.183 1.207
TPS3806J20-Q1
TPS3806I33-Q1
1.764
2.94
1.8
3
V
1.2 V < VIT < 2.5 V
2.5 V < VIT < 3.5 V
60
90
Vhys Hysteresis
mV
II
Input current
LSENSE, HSENSE
–25
25
300
5
nA
nA
IOH
High-level output current
VDD = VIT + 0.2 V, VOH = VDD
VDD = 3.3 V, Output unconnected
VDD = 6 V, Output unconnected
VI = 0 V to VDD
3
4
1
IDD
Ci
Supply current
µA
pF
6
Input capacitance
(1) The lowest supply voltage at which RESET becomes active. tr,VDD ≥ 15 µs/V
(2) To ensure best stability of the threshold voltage, place a bypass capacitor (ceramic, 0.1 µF) near the supply terminals.
SWITCHING CHARACTERISTICS
at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD to RESET delay
Propagation (delay) time,
high-to-low-level output
tPHL
5
100
µs
LSENSE to RSTSENSE delay
VDD to RESET delay
VIH = 1.05 x VIT,
VIL = 0.95 x VIT
Propagation (delay) time,
low-to-high-level output
tPLH
5
100
µs
HSENSE to RSTSENSE delay
TIMING REQUIREMENTS
at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
5.5
TYP
MAX
UNIT
At VDD
tw
Pulse duration
VIH = 1.05 x VIT, VIL = 0.95 x VIT
µs
At SENSE
4
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TPS3806J20-Q1
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SLVSBW8 –MARCH 2013
V
DD
V
IT(HSENSE)
V
IT(LSENSE)
V ,V +V
IT DD hys
V (V
)
IT DD
0.8 V
RSTSENSE
RESET
= Undefined
Table 2. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
2
GND
I
I
Ground
HSENSE
LSENSE
RESET
RSTSENSE
VDD
6
Adjustable hysteresis input
Adjustable sense input
5
I
3
O
O
I
Active-low open-drain reset output (from VDD
Active-low open-drain reset output (from LSENSE)
Input supply voltage and fixed sense input
)
1
4
FUNCTION AND TRUTH TABLE
TPS3806I33-Q1
VDD > VIT
RESET
LSENSE > VIT
RSTSENSE
0
1
L
0
1
L
H
H
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FUNCTIONAL BLOCK DIAGRAM
TPS3806
LSENSE
HSENSE
RSTSENSE
RESET
_
+
R1
_
V
DD
+
R2
GND
Reference
Voltage of
1.207 V
Detailed Description
Operation
The TPS3806I33-Q1 monitors battery voltage and asserts RESET when a battery becomes discharged below a
certain threshold voltage. A comparator monitors the battery voltage via an external resistor divider. When the
voltage at the LSENSE input drops below the internal reference voltage, the RSTSENSE output pulls low. The
output remains low until the battery is replaced, or recharged above a second higher trip-point, set at HSENSE.
One can monitor a second voltage at VDD. The independent RESET output pulls low when the voltage at VDD
drops below the fixed threshold voltage. Because the TPS3806I33-Q1 outputs are open-drain MOSFETs, most
applications may require a pullup resistor.
Programming the Threshold Voltage Levels
Calculate the low-voltage threshold at LSENSE according to Equation 1:
R1 ) R2 ) R3
refǒ
Ǔ
V
+ V
(LSENSE)
R2 R3
(1)
(2)
where Vref = 1.207 V
Calculate the high-voltage threshold at HSENSE as shown in Equation 2:
R1 ) R2 ) R3
refǒ
Ǔ
V
+ V
(HSENSE)
where Vref = 1.207 V
R3
To minimize battery current draw, TI recommends using 1 MΩ as the total resistor value R(tot), with
R(tot) = R1 + R2 + R3.
6
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SLVSBW8 –MARCH 2013
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
versus
SUPPLY VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
versus
LOW-LEVEL OUTPUT CURRENT
6
1.60
V
< V
(LSENSE)
(HSENSE)
V
V
= 1.5 V
DD
1.40
1.20
RESET = Open
RSTSENSE = Open
= Low
(SENSE)
5
4
3
2
1
0
85°C
1.00
0.80
0.60
0.40
0.20
0
25°C
0°C
85°C
25°C
−40°C
0°C
−40°C
0
0.5
1
1.5
V
2
2.5
3
3.5
4
4.5
5
5.5
6
0
1
2
3
4
5
− Supply Voltage − V
I
− Low-Level Output Current − mA
DD
OL
Figure 1.
Figure 2.
LOW-LEVEL OUTPUT VOLTAGE
versus
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
versus
LOW-LEVEL OUTPUT CURRENT
0.50
0.45
3.5
3
V
= 1.5 V
= Low
V
V
= 6 V
DD
DD
V
= Low
(SENSE)
(SENSE)
0.40
0.35
85°C
85°C
2.5
2
25°C
0°C
25°C
0°C
0.30
0.25
0.20
0.15
−40°C
−40°C
1.5
1
0.5
0
0.10
0.05
0
Expanded View
0
0.5
1
1.5
2
2.5
3
0
5
10 15 20 25 30 35 40 45 50
I
− Low-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OL
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
LOW-LEVEL OUTPUT VOLTAGE
NORMALIZED INPUT THRESHOLD VOLTAGE
versus
versus
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE AT VDD
1
0.9
0.8
0.7
0.6
V
V
= 6 V
DD
1.005
1.004
= Low
(SENSE)
RESET = 100 kΩ to V
DD
85°C
25°C
0°C
1.003
1.002
1.001
1
−40°C
0.5
0.4
0.3
0.999
0.998
0.997
0.996
0.995
0.2
Expanded View
0.1
0
0
2
4
6
8
10 12 14 16 18 20
−40
−20
0
20
40
60
80
I
− Low-Level Output Current − mA
OL
T
A
− Free-Air Temperature at V − °C
DD
Figure 5.
Figure 6.
MINIMUM PULSE DURATION AT VDD
versus
VDD THRESHOLD OVERDRIVE VOLTAGE
MINIMUM PULSE DURATION AT LSENSE
versus
LSENSE THRESHOLD OVERDRIVE VOLTAGE
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
V
DD
− Threshold Overdrive Voltage − V
LSENSE − Threshold Overdrive Voltage − V
Figure 7.
Figure 8.
8
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS3806I33QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PZHQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3806I33-Q1 :
Catalog: TPS3806I33
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3806I33QDBVRQ1 SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
TPS3806I33QDBVRQ1
6
3000
Pack Materials-Page 2
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