TPS43337QDAPQ1 [TI]
IC DUAL SWITCHING CONTROLLER, Switching Regulator or Controller;
| 型号： | TPS43337QDAPQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC DUAL SWITCHING CONTROLLER, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总37页 (文件大小：1194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS43337-Q1
www.ti.com
SLVSBC2 –AUGUST 2013
LOW IQ, SINGLE-BOOST, FIXED-VOLTAGE DUAL SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS43337-Q1
1
FEATURES
•
•
Peak Gate Drive Current 1.5 A
Thermally Enhanced 38-Pin HTSSOP (DAP)
PowerPAD™ Package
2
•
Qualified for Automotive Applications
•
AEC-Q100 Qualified With the Following
Results:
APPLICATIONS
–
Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
•
Automotive Start-Stop, Infotainment,
Navigation Instrument Cluster Systems
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C2
•
Industrial and Automotive Multi-Rail DC
Power-Distribution Systems and Electronic
Control Units
•
•
•
•
•
Two Synchronous Buck Controllers
BuckA: Fixed Output Voltage of 3.4 V
BuckB: Fixed Output Voltage of 1.235 V
One Pre-Boost Controller
DESCRIPTION
The TPS43337-Q1 includes two current-mode
synchronous buck controllers and a voltage-mode
boost controller. The device is ideally suited as a pre-
regulator stage with low IQ requirements and for
systems that must survive supply drops due to
cranking events. The integrated boost controller
allows the device to operate down to 2 V at the input
without seeing a drop on the buck regulator output
stages. At light loads, the buck controllers enable to
operate automatically in low power-mode, consuming
just 34 µA of quiescent current.
Input Range up to 40 V, (Transients up to 60
V), Operation Down to 2 V When Boost Is
Enabled
•
Low-Power Mode IQ: 34 µA (One Buck On), 43
µA (Two Bucks On)
•
•
•
Low Shutdown Current Ish < 4 µA
Boost Output Selectable: 7 V, 8.85 V, or 10 V
Programmable Frequency and External
Synchronization Range: 150 to 600 kHz
The buck controllers have independent soft-start
capability and power-good indicators. Current
foldback in the buck controllers and cycle-by-cycle
current limitation in the boost controller provide
external MOSFET protection. The switching
frequency is programable over 150 to 600 kHz or is
synchronized to an external clock in the same range
•
•
Separate Enable Inputs (ENA, ENB, ENC)
Selectable Forced Continuous Mode or
Automatic Low-Power Mode at Light Loads
•
•
Sense Resistor or Inductor DCR Sensing for
Buck Controllers
Out-of-Phase Switching Between Buck
Channels
VBAT
VBuckA
TPS43337-Q1
VBuckB
2 V
Figure 1. Typical Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2013, Texas Instruments Incorporated
TPS43337-Q1
SLVSBC2 –AUGUST 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
space
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–0.3
–0.7
–1
MAX UNIT
Voltage
Input voltage: VIN, VBAT
60
60
68
60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
Enable inputs: ENA, ENB
Bootstrap inputs: CBA, CBB
Phase inputs: PHA, PHB
Phase inputs: PHA, PHB (for 150 ns)
Feedback inputs: FBA, FBB
Error amplifier outputs: COMPA, COMPB
High-side MOSFET driver: GA1–PHA, GB1–PHB
Low-side MOSFET drivers: GA2, GB2
Current-sense voltage: SA1, SA2, SB1, SB2
Soft start: SSA, SSB
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
13
13
Voltage
(buck function:
BuckA and BuckB)
8.8
8.8
13
13
Power-good output: PGA, PGB
Power-good delay: DLYAB
13
13
Switching-frequency timing resistor: RT
SYNC, EXTSUP
13
13
Low-side MOSFET driver: GC1
Error amplifier output: COMPC
Enable input: ENC
8.8
13
Voltage
(boost function)
13
Current-limit sense: DS
60
Output-voltage select: DIV
8.8
60
P-channel MOSFET driver: GC2
P-channel MOSFET driver: VIN–GC2
Gate-driver supply: VREG
Voltage
(PMOS driver)
8.8
8.8
150
125
165
Junction temperature: TJ
Temperature
Operating temperature: TA
–40
Storage temperature: TS
–55
Human-body model (HBM) AEC-Q100
Classification Level H2
±2
kV
VBAT, ENC, SYNC, VIN
All other pins
±750
±500
±150
±200
Charged-device model (CDM) AEC-Q100
Classification Level C2
Electrostatic
discharge ratings
V
PGA, PGB
Machine model (MM)
All other pins
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
2
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SLVSBC2 –AUGUST 2013
THERMAL INFORMATION
TPS43337-Q1
THERMAL METRIC(1)
HTSSOP-DAP
38 PINS
27.3
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
19.6
15.9
ψJT
0.24
ψJB
6.6
θJCbot
1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
40
UNIT
Input voltage: VIN, VBAT
Enable inputs: ENA, ENB
Boot inputs: CBA, CBB
Phase inputs: PHA, PHB
Current-sense voltage: SA1, SA2, SB1, SB2
Power-good output: PGA, PGB
SYNC, EXTSUP
4
0
40
4
–0.6
0
48
Buck function:
BuckA and BuckB
voltage
40
V
11
0
11
0
9
Enable input: ENC
0
9
Boost function
Voltage sense: DS
40
V
DIV
0
VREG
125
Operating Temperature: TA
–40
°C
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SLVSBC2 –AUGUST 2013
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DC ELECTRICAL CHARACTERISTICS
VIN = 8 to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.0
Input Supply
Boost controller enabled, after initial start-up
condition is satisfied
1.1
1.2
VBAT
Supply voltage
2
6.5
4
40
40
V
Input voltage required for device
on initial start-up
VIN
V
V
Buck regulator operating range
after initial start-up
40
VIN falling. After a reset, initial start-up conditions
may apply.(1)
3.5
3.6
3.8
1.3
VIN UV
Buck undervoltage lockout
Boost unlock threshold
VIN rising. After a reset, initial start-up conditions
may apply.(1)
3.8
8.5
4
V
V
1.4
1.5
VBOOST_UNLOCK
VBAT rising
8.2
8.8
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 25°C
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 25°C
VIN = 13 V, BuckA, B: LPM, TA = 25°C
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 125°C
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 125°C
VIN = 13 V, BuckA and BuckB: LPM, TA = 125°C
SYNC = 5 V, TA = 25°C
34
43
44
53
46
57
56
67
µA
µA
µA
µA
LPM quiescent current:
IQ_LPM
(2)
LPM quiescent current:
1.6
1.7
IQ_LPM
(2)
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 25°C
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 25°C
VIN = 13 V, BuckA and BuckB: CCM, TA = 25°C
SYNC = 5 V, TA = 125°C
4.85
7
5.3
7.6
5.5
Quiescent current:
IQ_NRM
mA
mA
normal (PWM) mode(2)
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 125°C
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 125°C
VIN = 13 V, BuckA, B: CCM, TA = 125°C
BuckA and BuckB: off, VBat = 13 V , TA = 25°C
BuckA and BuckB: off, VBat = 13 V, TA = 125°C
VIN falling
5
Quiescent current:
1.8
IQ_NRM
normal (PWM) mode(2)
7.5
2.5
3
8
4
1.9
1.10
1.11
1.12
1.13
2.0
Ibat_sh
Shutdown current
Shutdown current
VIN level to exit LPM
µA
µA
V
Ibat_sh
5
VINLPMexit
VINLPMentry
VINLPMhys
7.7
8.2
0.4
8
8.3
8.8
0.6
VIN level to enable entering LPM VIN rising
Hysteresis VIN rising or falling
8.5
0.5
V
V
Input Voltage VBAT - Undervoltage Lockout
VBAT falling. After a reset, initial start-up conditions
may apply.(1)
1.8
1.9
2.5
2
V
V
2.1
VBATUV
Boost-input undervoltage
VBAT rising. After a reset, initial start-up conditions
may apply.(1)
2.4
2.6
2.2
2.3
3.0
UVLOHys
UVLOfilter
Hysteresis
Filter time
500
600
5
700
mV
µs
Input Voltage VIN - Overvoltage Lockout
VIN rising
VIN falling
45
43
1
46
44
2
47
45
3
3.1
VOVLO
Overvoltage shutdown
V
3.2
3.3
OVLOHys
OVLOfilter
Hysteresis
Filter time
V
5
µs
(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
(2) Quiescent current specification includes the current in the internal-feedback resistor divider.
4
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SLVSBC2 –AUGUST 2013
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
4.0
4.1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Boost Controller
Vboost7-VIN
Boost VOUT = 7 V
DIV = low, VBAT = 2 to 7 V
6.8
7.5
7
8
7.3
8.5
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
Boost VOUT = 7 V, VBAT falling
4.2
4.3
4.4
4.5
4.6
Vboost7-th
Boost VOUT = 7 V, VBAT rising
8
8.5
9
V
Boost VOUT = 7 V, VBAT rising or falling
DIV = open, VBAT = 2 to 10 V
0.4
0.5
0.6
Vboost10-VIN
Vboost10-th
Vboost8.85-VIN
Vboost8.85-th
Boost VOUT = 10 V
9.7
10
10.4
11.5
12
V
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
Boost VOUT = 10 V, VBAT falling
Boost VOUT = 10 V, VBAT rising
Boost VOUT = 10 V, VBAT rising or falling
DIV = VREG, VBAT = 2 to 8.85 V
Boost VOUT = 8.85 V, VBAT falling
Boost VOUT = 8.85 V, VBAT rising
Boost VOUT = 8.85 V, VBAT rising or falling
10.5
11
11
11.5
0.5
V
0.4
0.6
Boost VOUT = 8.85 V
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
8.35
9.15
9.65
0.4
8.85
9.85
10.35
0.5
9.35
10.45
10.85
0.6
V
V
Boost-Switch Current Limit
4.7
4.8
VDS
tDS
Current-limit sensing
Leading-edge blanking
DS input with respect to PGNDA
0.175
0.2
0.225
V
200
ns
Gate Driver for Boost Controller
IGC1 Peak Gate-driver peak current
rDS(on) Source and sink driver
Gate Driver for PMOS
4.9
1.5
A
4.10
VREG = 5.8 V, IGC1 current = 200 mA
2
20
10
Ω
4.11
4.12
4.13
rDS(on)
PMOS OFF
10
5
Ω
mA
µs
IPMOS_ON
tdelay_ON
Gate current
Turnon delay
VIN = 13.5 V, Vgs = –5 V
C = 10 nF
10
Boost-Controller Switching Frequency
4.14
4.15
fsw-Boost
DBoost
Boost switching frequency
Boost duty cycle
fSW_Buck / 2
90%
kHz
Error Amplifier (OTA) for Boost Converters
VBAT = 12 V
VBAT = 5 V
0.8
1.35
0.65
4.16
GmBOOST
Forward transconductance
mS
V
0.35
5.0
Buck Controllers
VBuckA_NRM
Fixed output voltage in normal
mode
5.1a
5.1b
5.2a
3.345
3.311
1.216
3.396
3.396
1.235
3.447
3.481
1.253
Included resistor-feedback-divider, measured at
FBA pin
VBuckA_LPM
Fixed output in low-power mode
Fixed output voltage in normal
mode
VBuckB_NRM
Included resistor-feedback-divider, measured at
FBB pin
V
Fixed output voltage in low-
power mode
5.2b
5.4
VBuckB_LPM
1.204
60
1.235
75
1.266
90
V sense for forward-current limit Measured across Sx1 and Sx2, FBx at 94% of
in CCM typical value (low duty-cycle)
mV
Vsense
V sense for reverse-current limit Measured across Sx1 and Sx2, FBx at 125% of
5.5
5.6
5.7
–65
17
–37.5
32.5
–23
48
mV
mV
ns
in CCM
typical value
VI-Foldback
tdead
V sense for output short
Measured across Sx1 and Sx2, FBx = 0 V
Shoot-through delay, blanking
time
20
High-side minimum on-time
100
ns
5.8
5.9
DCNRM
DCLPM
Maximum duty cycle (digitally
controlled)
98.75%
Duty cycle, LPM
80%
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DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LPM entry-threshold load current
as fraction of maximum set load
current
(3)
ILPM_Entry
1%
.
5.10
LPM exit-threshold load current
as fraction of maximum set load
current
(3)
ILPM_Exit
10%
1.5
High-Side External NMOS Gate Drivers for Buck Controller
5.11
5.12
IGX1_peak
rDS(on)
Gate-driver peak current
Source and sink driver
A
VREG = 5.8 V, IGX1 current = 200 mA
VREG = 5.8 V, IGX2 current = 200 mA
2
2
Ω
Low-Side NMOS Gate Drivers for Buck Controller
5.13
5.14
IGX2_peak
RDS ON
Gate driver peak current
Source and sink driver
1.5
1
A
Ω
Error Amplifier (OTA) for Buck Converters
GmBUCK Transconductance
Digital Inputs: ENA, ENB, ENC, SYNC
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
5.15
0.72
1.7
1.35
0.7
2
mS
6.0
6.1
6.2
6.3
6.4
VIH
Higher threshold
VIN = 13 V
VIN = 13 V
VSYNC = 5 V
VENC = 5 V
V
V
VIL
Lower threshold
RIH_SYNC
RIL_ENC
Pulldown resistance on SYNC
Pulldown resistance on ENC
500
500
kΩ
kΩ
Pullup current source on ENA,
ENB
6.5
IIL_ENx
VENx = 0 V
0.5
µA
7.0
7.1
7.2
7.3
8.0
8.1
8.2
Boost Output Voltage: DIV
VIH_DIV
VIL_DIV
Voz_DIV
Higher threshold
VREG = 5.8 V
Vreg – 0.2
V
V
V
Lower threshold
0.2
Voltage on DIV if unconnected
Voltage on DIV if unconnected
Vreg / 2
Switching Parameter – Buck DC-DC Controllers
fSW_Buck
fSW_Buck
Buck switching frequency
Buck switching frequency
RT pin: GND
360
360
400
400
440
440
kHz
kHz
RT pin: 60-kΩ external resistor
Buck adjustable range with
external resistor
8.3
fSW_adj
fSYNC
RT pin: external resistor
External clock input
150
150
600
600
kHz
kHz
8.4
9.0
Buck synchronization range
Internal Gate-Driver Supply
Internal regulated supply
VIN = 8 to 18 V, VEXTSUP = 0 V, SYNC = high
5.5
7.2
5.8
0.2%
7.5
6.1
1%
7.8
1%
V
V
9.1
VREG
IVREG = 0 to 100 mA, VEXTSUP = 0 V,
SYNC = high
Load regulation
Internal regulated supply
Load regulation
VEXTSUP = 8.5 V
9.2
9.3
VREG(EXTSUP)
IEXTSUP = 0 to 125 mA, SYNC = High
VEXTSUP = 8.5 to 13 V
0.2%
EXTSUP switch-over voltage
threshold
IVREG = 0 to 100 mA,
VEXTSUP ramping positive
VEXTSUP-th
4.4
4.6
4.8
V
9.4
9.5
VEXTSUP-Hys
IREG-Limit
EXTSUP switch-over hysteresis
Current limit on VREG
150
100
250
400
mV
mA
VEXTSUP = 0 V, normal mode as well as LPM
Current limit on VREG when
using EXTSUP
IVREG = 0 to 100 mA,
VEXTSUP = 8.5 V, SYNC = High
9.6
IREG_EXTSUP-Limit
125
400
mA
10.0
10.1
11.0
11.1
Soft Start
ISSx
Soft-start source current
VSSA and VSSB = 0 V
40
50
60
µA
V
Oscillator (RT)
VRT
Oscillator reference voltage
1.2
(3) The exit threshold specification must always higher than the entry threshold.
6
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SLVSBC2 –AUGUST 2013
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12.0
Power Good / Delay
12.1a PGthA
12.1b PGthB
FBA falling
FBB falling
3.09
3.158
1.148
2%
3.226
1.173
Power-good threshold
V
1.124
12.2
12.3
12.4
12.5
12.6
PGhys
Hysteresis
PGdrop
Voltage drop
IPGA = 5 mA
IPGA = 1 mA
450
100
1
mV
mV
µA
µs
PGleak
tdeglitch
Power-good leakage
Sx2 = PGx = 13 V
Power-good deglitch time
2
16
External capacitor = 1 nF
VBUCKx < PGthx
12.7
12.8
12.9
tdelay
tdelay_fix
IOH
Reset delay
1
20
40
ms
µs
Fixed reset delay
No external capacitor, pin open
50
50
Activate current source (current
to charge external capacitor)
30
30
µA
Activate current sink (current to
discharge external capacitor)
12.10 IIL
40
50
µA
13.0
13.1
13.2
Overtemperature Protection
Junction-temperature shutdown
threshold
Tshutdown
Thys
150
165
15
°C
°C
Junction-temperature hysteresis
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DEVICE INFORMATION
DAP PACKAGE
(TOP VIEW)
1
2
3
4
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VBAT
DS
VIN
EXTSUP
DIV
GC1
GC2
VREG
CBB
5
6
7
8
CBA
GA1
GB1
PHA
PHB
GA2
GB2
9
PGNDA
SA1
PGNDB
SB1
10
11
SA2
SB2
12
13
14
15
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
16
17
18
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
19
20
PIN FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
AGND
23
O
Analog ground reference
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBA
5
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
13
26
I
Error-amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckA. Clamping this voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPA
COMPB
O
O
Error-amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckB. Clamping this voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPC
DIV
18
36
O
I
Error-amplifier output and loop-compensation node of the boost regulator
The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter
at 8.85 V, a low input sets the value at 7 V, and a floating pin sets 10 V.
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-
good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 μs, typical.
DLYAB
DS
21
2
O
I
This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An
alternative connection for better noise immunity is to place a sense resistor between the source of the low-side
MOSFET and ground via a filter network.
Enable inputs for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current.
ENA
16
I
8
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PIN FUNCTIONS (continued)
NAME
NO.
I/O
DESCRIPTION
Enable inputs for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current.
ENB
17
I
This input enables and disables the boost regulator. An input voltage higher than 1.5 V enables the controller.
Voltages lower than 0.7 V disable the controller. When enabled, the controller starts switching as soon as VBAT
falls below the boost threshold, depending upon the programmed output voltage.
ENC
19
37
I
I
One uses EXTSUP to supply the VREG regulator from one of the TPS43337-Q1 buck regulator rails to reduce
power dissipation in cases where there is an expectation of high VIN. When EXTSUP is open or lower than 4.6 V,
the regulator power comes from VIN.
EXTSUP
Feedback voltage pin for BuckA. The buck controller regulates this feedback voltage to 3.4 V through the internal
resistor-divider network. Connect FBA to the output voltage of BuckA.
FBA
FBB
12
27
I
I
Feedback voltage pin for BuckB. The buck controller regulates this feedback voltage to 1.235 V through the
internal resistor-divider network. Connect FBB to the output voltage of BuckB.
This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high
peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has
a voltage swing provided by CBA.
GA1
GA2
GB1
6
8
O
O
O
This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high
peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHB that has
a voltage swing provided by CBB.
33
This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GB2
GC1
31
3
O
O
This output drives an external low-side N-channel MOSFET for the boost regulator. This output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET
bypasses the boost rectifier diode or a reverse-protection diode when the boost status is non-switching or
disabled, and thus reduces power losses.
GC2
PGA
PGB
4
O
O
O
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below the respective undervoltage threshold.
15
24
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below the respective undervoltage threshold.
PGNDA
PGNDB
9
O
O
Power-ground connection to the source of the low-side N-channel MOSFETs of BuckA.
Power-ground connection to the source of the low-side N-channel MOSFETs of BuckB.
30
Switching terminal of buck regulator BuckA; provides a floating ground reference for the high-side MOSFET gate-
driver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired.
PHA
PHB
7
O
O
Switching terminal of buck regulator BuckB; provides a floating ground reference for the high-side MOSFET gate-
driver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired.
32
Connecting a resistor to ground on this pin sets the operating switching frequency of the buck and boost
controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz
for the boost controller.
RT
22
O
SA1
SA2
SB1
SB2
10
11
29
28
I
I
I
I
High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SA1 positive node, SA2 negative node)
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SB1 positive node, SB2 negative node)
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 50 μA is present at the pin. Connect an
appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another
supply to provide a tracking input to this pin.
SSA
SSB
14
25
O
O
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 50 μA is present at the pin. Connect an
appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another
supply to provide a tracking input to this pin.
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PIN FUNCTIONS (continued)
NAME
NO.
I/O
DESCRIPTION
If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock.
This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits
transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power
mode at light loads.
SYNC
20
I
Battery input sense for the boost controller. With the boost controller enabled, if the voltage at VBAT falls below
the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed
boost output voltage.
VBAT
VIN
1
I
I
Main input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, VIN
powers the internal control circuits of the device.
38
35
This pin requires an external capacitor to provide a regulated supply for the gate drivers of the buck and boost
controllers. TI recommends a capacitance on the order of 4.7 μF. Either VIN or EXTSUP can power the regulator.
This pin has current-limit protection, so do not use it to drive any other loads.
VREG
O
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5
6
7
8
9
CBA
GA1
PHA
GA2
Duplicate for second
Buck controller channel
Internal ref
(Band gap)
38
VIN
Gate Driver
Supply
37
35
EXTSUP
VREG
PWM
Logic
VREG
PGNDA
Internal
Oscillator
22
20
Slope
Comp
RT
Current sense
Amp
10
11
SA1
SA2
PWM
comp
SYNC and
LPM
SYNC
OTA
Gm
12
FBA
0.8 V
Source
and
Sink
SSA
4
GC2
Logic
13
COMPA
FBA
ENC
50 µA
15
PGA
14
16
25
SSA
ENA
SSB
VIN
ENA
Filter Timer
500 nA
40 µA
40 µA
VIN
50 µA
21
DLYAB
ENB
500 nA
34
33
32
31
30
29
28
27
26
24
CBB
17
2
ENB
DS
GB1
OCP
OTA
Gm
VIN
VboostxV
PHB
0.2 V
18
36
COMPC
DIV
GB2
Second
Buck
Controller
Channel
PGNDB
SB1
Ramp
Vboost7V-th
Vboost8.85V-th
Vboost10V-th
1
VBAT
SB2
MUX
FBB
COMPB
PGB
PWM
comp
VREG
3
GC1
ENC
PWM
Logic
19
23
PGNDA
AGND
Figure 2. Functional Block Diagram
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TYPICAL CHARACTERISTICS
BuckA EFFICIENCY AND POWER LOSSES
BuckB EFFICIENCY AND POWER LOSSES
VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, Switching
VIN = 12 V, Inductor = 10 µH, Rsense = 20 mΩ, Switching
Frequency = 400 kHz, EXTSUP open
Frequency = 400 kHz, EXTSUP open
100
90
80
70
60
50
40
30
20
10
0
10
100
10
Efficiency, SYNC=HIGH
Efficiency, SYNC=HIGH
Efficiency, SYNC=LOW
Power Loss, SYNC=HIGH
Power Loss, SYNC=LOW
Efficiency, SYNC=LOW
90
80
70
60
50
40
30
20
10
Power Loss, SYNC=HIGH
Power Loss, SYNC=LOW
1
1
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
0
1.00E-07
1.00E-05
1.00E-03
I_Load (A)
Figure 3.
1.00E-01
1.00E-07
1.00E-05
1.00E-03
I_Load (A)
Figure 4.
1.00E-01
C001
C002
BuckA LOAD STEP 1 A - 2 A
BuckB LOAD STEP 1 A - 2 A
VIN = 12 V, Inductor = 10 µH, Rsense = 20 mΩ, COUT = 100 µF,
VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, COUT = 320 µF,
Switching Frequency = 400 kHz
Switching Frequency = 400 kHz
VOUT BuckA - AC Coupled
50 mV / DIV
VOUT BuckB - AC Coupled
100 mV / DIV
IIND
1 A / DIV
IIND
1 A / DIV
1 ms / DIV
1 ms / DIV
Figure 5.
Figure 6.
BuckB LOAD STEP UP 0 A - 1 A
BuckB LOAD STEP DOWN 1 A - 0 A
VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, COUT = 320 µF,
VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, COUT = 320 µF,
Switching Frequency = 400 kHz
Switching Frequency = 400 kHz
IIND
50 mV / DIV
VOUT BuckB - AC Coupled
50 mV / DIV
VOUT BuckB - AC Coupled
IIND
0.2 A / DIV
0.2 A / DIV
100 ꢀs / DIV
100 ꢀs / DIV
Figure 7.
Figure 8.
12
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TYPICAL CHARACTERISTICS (continued)
SOFT-START OUTPUTS
BuckA and BuckB
VIN (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW
100
90
VOUT BuckA, 1V / DIV
VBAT = 8 V
80
70
VBAT = 5 V
60
VOUT BuckB, 0.5 V / DIV
VBAT = 3 V
50
40
30
20
10
0
5 ms / DIV
0.01
1
10
Output Current (A)
Figure 10.
Figure 9.
VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
BuckB = 3.3 V AT 3.5 A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V,
SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,
RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
VBAT (BOOST INPUT)
5 V/DIV
500 mV/DIV
VIN (BOOST OUTPUT) AC-COUPLED
0 V
200 mV/DIV
200 mV/DIV
VOUT BuckA AC-COUPLED
VOUT BuckB AC-COUPLED
5 A/DIV
10 A/DIV
0 A
IIND
IIND
2 ms/DIV
20 ms/DIV
Figure 11.
Figure 12.
VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
BuckB = 3.3V AT 3.5A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V,
SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,
RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
VBAT (BOOST INPUT)
5 V/DIV
3-A LOAD
5 A/DIV
0 V
VIN (BOOST OUTPUT)
5 V/DIV
100-mA LOAD
0V
10 A/DIV
5 A/DIV
IIND
0 A
2 µs/DIV
20 ms/DIV
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
75
62.5
50
150°C
37.5
25
12.5
SYNC = LOW
0
–12.5
–25
25°C
–0.1
–0.2
–0.3
SYNC = HIGH
0.8 0.95
–37.5
0
1
2
3
4
5
6
7
8
9
10 11 12
0.65
1.1
1.25
1.4
1.55
Output Voltage (V)
COMPx Voltage (V)
Figure 15.
Figure 16.
80
70
60
50
40
30
20
10
0
FOLDBACK CURRENT LIMIT (BUCK)
80
70
60
50
40
30
20
10
0
VIN = 8 V
VIN = 12 V
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
0
0.25
0.5
0.75
1
Normalized VOUT
Figure 17.
Figure 18.
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DETAILED DESCRIPTION
BUCK CONTROLLERS: NORMAL-MODE PWM OPERATION
Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. the frequency is also set by a resistor at RT according to Equation 1.
X
fSW
=
(X = 24 kW´MHz)
RT
109
fSW = 24´
(1)
For example,
600 kHz requires 40 kΩ.
150 kHz requires 160 kΩ.
Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 to 600 kHz is also
possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device also detects a loss of clock at this pin, and on detecting this loss, the device sets the
switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies,
180 degrees out of phase.
Enable Inputs
Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,
with a threshold of 1.5 V for high level, and with direct connection directly to the battery for self-bias. The low
threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on
these pins enables the respective buck controllers. When both buck controllers are disabled, the device shuts
down and consumes a current less than 4 µA.
Feedback Inputs
An internal voltage divider presets the output voltage. Connect each FBx pin to the output of the respective
regulator of the pin.
Soft-Start Inputs
In order to avoid large inrush currents, each buck controller has an independent, programmable soft-start timer.
The voltage at the SSx pins acts as the soft-start reference voltage. A 50-µA pullup current available at the SSx
pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After
start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V; 0.8 V then
becomes the reference for the buck controllers. Equation 2 calculates the soft-start ramp time.
I
SS ´ Dt
CSS
=
(Farads)
DV
where,
•
•
•
ISS = 50 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time.
(2)
Alternatively, the soft-start pins are used as tracking inputs. In this case, connect these pins to the supply to be
tracked via a suitable resistor-divider network.
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Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at the
set value. The error between the feedback voltage at FBx and the internal voltage divider produces a signal at
the output of the error amplifier (COMPx), which serves as the target for the peak inductor current. The device
senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares the voltage with this
target during each cycle. A fall or rise in load current produces a fall or rise in voltage at FBx, causing COMPx to
fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current
matches the load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches the peak value. When this MOSFET turns off, and after a small delay (shoot-through delay), the lower
N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the
bootstrap capacitor at CBx, which allows a maximum duty cycle of 98.75% for the buck regulators. During
dropout, the buck regulator switches at one-fourth of its normal frequency.
Current Sensing and Current Limit With Foldback
Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a
specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value
due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus
providing current foldback protection, which protects the high-side external MOSFET from excess current
(forward-direction current limit).
Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully
on, the COMPx node drops low. A clamp is on the lower end as well, in order to limit the maximum current in the
low-side MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum
forward-peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified typical
value is for low duty cycles only. At typical duty-cycle conditions around 28% (assuming 3.4 V output and 12 V
input), 55 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics
(see Figure 18) provide a guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range,
thus allowing DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 19 shows
DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter
components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,
it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.
Hence using the more-accurate sense resistor for current sensing is advantageous.
Inductor L
TPS43337-Q1
VBuckX
DCR
R11
C11
Sx22
VC
Sx11
Figure 19. DCR Sensing Configuration
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Slope Compensation
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable
operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor
according to Equation 3.
L ´ fSW
= 200
RS
where
•
•
•
L is the buck regulator inductor in henries.
RS is the sense resistor in ohms.
fsw is the buck regulator switching frequency in hertz.
(3)
Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-
drain output at the PGx pins. Shutdown of a buck controller causes an internal pulldown of the power-good
indicator. Connecting the external pullup resistor to a rail other than the output of that particular buck channel
causes a constant current flow through the external resistor during a powered-down state of the buck controller.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value
after a long negative transient, assertiohn of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program
the delay of this circuit by using a suitable capacitor at the DLYAB pin according to Equation 4.
tDELAY
1 msec
=
CDLYAB
1 nF
(4)
When the DLYAB pin is open, the delay is set to a default value of 20 µs (typical). The power-good delay timing
is common to both the buck rails, but the power-good comparators and indicators function independently.
Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks.
When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light
loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected.
In discontinuous mode, as the load decreases, the duration of the clock-period when both the high-side as well
the low-side MOSFET is turned-off, increases (deep discontinuous mode). In case the duration exceeds 60% of
the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design
ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have
been chosen appropriately as recommended in the Slope Compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8 V internal reference
voltage through the internal voltage divider. Whenever the FBx value falls below the internal threshold, the high-
side MOSFET is turned on for a pulse duration inversely proportional to the difference VIN – Sx2. At the end of
this on-time, the high-side MOSFET is turned off and the current in the inductor decays until it becomes zero.
The low-side MOSFET is not turned on. The next pulse occurs the next time FBx falls below the threshold value
which results in a constant volt-second ton hysteretic operation with a total-device quiescent-current consumption
of 34 µA when a single buck channel is active and 43 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
During low-power mode, the TPS43337-Q1 supports the full-current load until the transition to normal mode
takes place. The design ensures the low-power-mode exit occurs at 10% (typical) of full-load current if the
inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis
between the entry and exit thresholds to avoid oscillating between the two modes.
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In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for entry into low-power mode. When the boost controller is enabled, low-
power mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set
to GND. If DIV is high (VREG), low-power mode is inhibited.
Boost Controller
The boost controller has a fixed-frequency voltage-mode architecture and includes a cycle-by-cycle current-limit
protection for the external N-channel MOSFET. The switching frequency is derived from and set to one-half of
the buck-controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an
internal resistor-divider network and is programmable to 7 V, 8.85 V, and 10 V based on the low, open, and high
status of the DIV pin, respectively. A change of the DIV setting is not recognized while the device is in low-power
mode.
The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin
has crossed the unlock threshold of 8.5 V at least once. After that, the boost controller is armed and starts
switching as soon as VIN falls below the value set by the DIV pin, and regulates the VIN voltage. Thus, the boost
regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking
pulse at VBAT.
Whenever the voltage at the DS pin exceeds 200 mV, the boost-external MOSFET is turned off by pulling the
CG1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET
source and ground, cycle-by-cycle overcurrent protection for the MOSFET can be achieved. The on-resistance of
the MOSFET or the value of the sense resistor must be chosen in such a way that the on-state voltage at DS
does not exceed 200 mV at the maximum load and minimum input-voltage conditions. When a sense resistor is
used, connecting a filter network between the DS pin and the sense resistor is recommended for better noise
immunity.
The boost output (VIN) is also used to supply other circuits in the system, however, they should be high-voltage
tolerant. The boost output is regulated to the programmed value only when VIN is low, and so VIN can reach
battery levels.
Vbat
VIN
DS
TPS43337-Q1
GC1
Figure 20. External Drain-Source Voltage Sensing
Vbat
VIN
TPS43337-Q1
GC1
RIFLT
DS
CIFLT
RISEN
Figure 21. External Current Shunt Resistor
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Table 1. Mode Control
SYNC
Terminal
Comments
External clock
Device in forced into continuous mode, internal PLL locks into the external clock between 150 kHz and 600 kHz
Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions
Device in forced into continuous mode
Low or open
High
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
DRIVER STATUS
DEVICE STATUS
QUIESCENT CURRENT
ENA ENB ENC SYNC BUCK CONTROLLERS
BOOST CONTROLLER
Disabled
Low
Low
Low
X
Shutdown
Shutdown
Approximately 4 µA
Approximately 34 µA (light loads)
mA range
Low
High
Low
High
BuckB: LPM enabled
BuckB: LPM inhibited
BuckA: LPM enabled
BuckA: LPM inhibited
Low
High
Low
BuckB running
Disabled
Disabled
Approximately 34 µA (light loads)
mA range
High
High
Low
Low
Low
BuckA running
BuckA and BuckB: LPM
enabled
Low
Approximately 43 µA (light loads)
BuckA and BuckB
running
High
Disabled
Disabled
BuckA and BuckB: LPM
inhibited
High
X
mA range
Low
Low
Low
Low
Shutdown
Shutdown
Approximately 4 µA
Approximately 54 µA (no boost,
light loads)
Low
High
Low
High
Low
BuckB: LPM enabled
BuckB: LPM inhibited
BuckA: LPM enabled
BuckA: LPM inhibited
Boost running for VIN < set
boost output
High
High
BuckB running
mA range
Approximately 54 µA (no boost,
light loads)
Boost running for VIN < set
boost output
High
High
Low
High
High
BuckA running
mA range
BuckA and BuckB: LPM
enabled
Approximately 68 µA (no boost,
light loads)
BuckA and BuckB
running
Boost running for VIN < set
boost output
High
BuckA and BuckB: LPM
inhibited
High
mA range
Gate Driver Supply (VREG, EXTSUP)
The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output
(5.8 V, typical) is available at the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3
µF to 10 µF. This pin has internal current-limit protection and should not be used to power any other circuits.
The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V
(typical). In case VIN is expected to go to high levels, there can be excessive power dissipation in this regulator,
especially at high switching frequencies and when using large external MOSFETs. In this case, powering this
regulator from the EXTSUP pin is advantageous, which can be connected to a supply lower than VIN but high
enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear
regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are
possible when one of the switching regulator rails from the TPS43337-Q1 or any other voltage available in the
system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is 9 V.
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VIN
EXTSUP
LDO
VIN
LDO
EXTSUP
typ 5.8 V
typ 7.5 V
typ 4.6 V
VREG
Figure 22. Internal Gate-Driver Supply
Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous as it provides a large gate drive and
therefore better on-resistance of the external MOSFETs.
During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt
regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in
low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.
External P-Channel Drive (GC2) and Reverse Battery Protection
The TPS43337-Q1 includes a gate driver for an external P-channel MOSFET, which can be connected across
the rectifier diode of the boost regulator which is useful to reduce power losses when the boost controller is not
switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel
MOSFET. When VBAT falls below the boost enable threshold, the gate driver turns off the P-channel MOSFET,
and the diode is no longer bypassed.
The gate driver can also be used to bypass any additional protection diodes connected in series as shown in
Figure 23. Figure 24 also shows a different scheme of reverse battery protection which may require only a
smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching
cycle. Because the diode is not always in the series path, the system efficiency improves.
R10
GC2
TPS43337-Q1
D3
Q7
Q6
L3
Fuse (S1)
Vbat
VIN
DS
D1
D2
C17
C15
C16
C14
GC1
COMPC
C13
R9
VBAT
Figure 23. Reverse-Battery-Protection Option for Buck-Boost Configuration
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GC2
VIN
VBAT
Fuse
TPS43337-Q1
DS
GC1
COMPC
VBAT
Figure 24. Reverse-Battery-Protection Option for Buck-Boost Configuration
Undervoltage Lockout and Overvoltage Protection
The TPS43337-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once
the has started up, it operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout
disables the device.
NOTE
If VIN drops, VREG drops as well, reducing the gate-drive voltage, while the digital logic
remains fully functional. Even if ENC is high, exceeding the boost-unlock voltage of
typically 8.5 V one time is required before boost activation takes place (see the Boost
Controller section).
A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent
transient spikes from shutting down the device, the undervoltage and overvoltage protection have filter times of 5
µs (typical).
When the voltages return to the normal-operating region, the enabled switching regulators start including a new
soft-start ramp for the buck regulators.
When the boost controller is enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage
lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN
falls at a rate dependent on the capacitor and load, eventually triggering VIN undervoltage. A short falling
transient at VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is
discharged to the undervoltage threshold.
Thermal Protection
The TPS43337-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die
temperature exceeds the thermal shutdown threshold of 165°C due to excessive power dissipation (for example,
due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned off, and
then restarted when the temperature has fallen by 15°C.
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for the TPS43337-Q1. The design
goal parameters are given in Table 3.
Table 3. Design Goal Parameters Example
PARAMETER
VBUCKA
VBUCKB
BOOST
VIN 6 to 30 V
12 V - typical
VIN 6 to 30 V
12 V - typical
VBAT = 5 (cranking pulse
input) to 30 V
Input voltage
Output voltage, VOUTx
3.396 V
3 A
1.235 V
2 A
10 V
Maximum output current, IOUTx
2.5 A
Load step output tolerance, ∆VOUT
ΔVOUT(Ripple)
+
±0.2 V
±0.12 V
±0.5 V
Current output load step, ∆IOUTx
0.1 to 3 A
400 kHz
0.1 to 2 A
400 kHz
0.1 to 2.5 A
200 kHz
Converter switching frequency, fSW
This example is a starting point and theoretical representation of the values to be used for the application; further
optimization of the components derived may be required to improve the performance of the device.
Boost Component Selection
A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in the
transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to
the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the
bandwidth is too close to the RHP zero frequency, the regulator may become unstable.
Thus, for high-power systems with low input voltages, a low inductor value is chosen. This value increases the
amplitude of the ripple currents in the N-channel MOSFET, the inductor and the capacitors for the boost
regulator. They must be designed with the ripple/RHP zero trade-off in mind and considering the power
dissipation effects in the components due to parasitic series resistance.
A boost converter that operates in the discontinuous mode does not contain the RHP-zero in transfer function.
However, designing for the discontinuous mode demands an even lower inductor value that has high ripple
currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, the regulator
becomes unstable.
VIN
C O
7V
OTA-gmEA
COMPx
R ESR
-
8.85
V
C 1
R3
+
VREF
C 2
10V
Figure 25. Boost Compensation Components
This design is done assuming continuous-conduction mode. During light load conditions, the boost converter
operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for
stability.
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Boost Maximum Input Current IIN_MAX
The maximum input current is drawn at the minimum input voltage and maximum load. The efficiency for VBAT =
5 V at 2.3 A is 80%, based on the typical characteristics plot.
POUT
25 W
0.8
P
=
=
= 31.3 W
INmax
Efficiency
(5)
(6)
Hence,
31.3 W
I
(at VBAT = 5 V) =
= 6.3 A
INmax
5 V
Boost Inductor Selection, L
Allow input ripple current of 40% of IIN max at VBAT = 5 V
V
BAT ´ tON
VBAT
5 V
L =
=
=
= 4.9 mH
I
I
INripplemax ´ 2´ fSW
2.52 A ´ 2´ 200 kHz
INripplemax
(7)
Choose a lower value of 3.9 µH in order to ensure a high RHP-zero frequency while making a compromise that
expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous
conduction mode, where it is easier to compensate.
The inductor saturation current must be higher than the peak inductor current and some percentage higher than
the maximum current-limit value set by the external resistive sensing element.
This rating should be determined at the minimum input voltage, maximum output current, and maximum core
temperature for the application.
Inductor Ripple Current, IRIPPLE
Based on an Inductor value of 3.9 µH, the ripple current is approximately 3.1 A.
Peak Current in Low-Side FET, IPEAK
IRIPPLE
3.1 A
IPEAK = IINmax
+
= 6.3 A +
= 7.85 A
2
2
(8)
Based on this peak current value (see Equation 8), the external current-sense resistor RSENSE is calculated in .
0.2 V
RSENSE
=
= 25 mW
7.85 A
Select 20 mΩ, allowing for tolerance.
The filter component values RIFLT and CIFLT for current sense are 1.5 kΩ and 1 nF, respectively, which allows for
good noise immunity.
Right Half-Plane Zero RHP Frequency, fRHP
VBAT min
fRHP
=
= 32 kHz
2p´IIn max ´L
(9)
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Output Capacitor, CO
To ensure stability, the output capacitor CO is chosen such that
f
RHP
fLC
£
10
VBATmin
10
£
2p´IINmax ´L
2p´ L ´ COUTx
ö2
÷
æ
ç
è
ö2
÷
ø
10´I
æ
10´ 6.3 A
5 V
INmax
COUTx
³
´L =
´ 3.9 mH
ç
VBATmin
è
ø
COUTxmin ³ 635 mF
(10)
Select COUTx = 680 µF.
This capacitor is usually aluminum electrolytic with ESR in the tens-of-milliohms which is good for loop stability,
because it provides a phase boost due to the ESR. The output filter components L and C create a double pole
(180 degree phase-shift) at a frequency fLC, and the ESR of the output capacitor RESR creates a zero for the
modulator at frequency fESR. These frequencies can be determined by Equation 11.
1
fESR
=
Hz, assume RESR = 40 mW
2p´ COUTx ´RESR
1
fESR
=
= 6 kHz
2p´ 680 mF´ 0.04
1
1
fLC
=
=
= 3.1 kHz
2p´ L ´ COUTx
2p´ 4 mH´ 680 mF
(11)
This satisfies fLC ≤ 0.1 fRHP
.
Bandwidth of Boost Converter, fC
Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response:
fLC < fESR< fC< fRHP Zero
fC < fRHP Zero / 3
fC < fSW / 6
fLC < fC / 3
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Output Ripple Voltage Due to Load Transients, ∆VO
Assume a bandwidth of fC = 10 kHz.
DI
OUTx
DVOUTx = RESR ´ DIOUTx
+
4 ´ C
´ fC
OUTx
2.5 A
= 0.04 W ´ 2.5 A +
= 0.19 V
4 ´ 660 mF´10 kHz
(12)
Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters
are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,
smaller component choices for the boost output may be used.
Selection of Components for Type II Compensation
The required loop gain for unity gain bandwidth (UGB) is shown in Equation 13.
æ
ö
æ
ö
fC
fC
G = 40 log
G = 40 log
- 20 log
ç
÷
ç
÷
ç
÷
ç
÷
fLC
fESR
è
ø
è
ø
æ
ç
è
ö
æ
ö
10 kHz
3.1kHz
10 kHz
6 kHz
- 20 log
= 15.9 dB
÷
ç
÷
ø
è
ø
(13)
The boost converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage which allows a
constant loop response across the input voltage range and makes it easier to compensate by removing the
dependency on VBAT
.
10G/20
85 ´10-6 A / V2 ´ VOUTx
R3 =
C1=
C2 =
= 7.2 kW
10
10
=
= 22 nF
2p´ fC ´R3 2p´10 kHz ´ 7.2 kW
C1
22 nF
=
= 223 pF
choose 220 pF
f
200 kHz
2
æ
ö
æ
ö
SW
2p´ 7.2 kW ´ 22nF ´
-1
2p´R3 ´ C1´
-1
ç
÷
ç
÷
2
è
ø
è
ø
(14)
Input Capacitor, CIN
The input ripple required is lower than 50 mV.
IRIPPLE
DVC1
=
= 10 mV
8´ fSW ´CIN
IRIPPLE
CIN
=
= 194-μF
8´ fSW ´ DVC1
DVESR = IRIPPLE ´RESR = 40 mV
(15)
25
Therefore, TI recommends 220 µF with 10-mΩ ESR.
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Output Schottky Diode D1 Selection
A Schottky diode with low forward-conducting voltage VF over temperature and fast switching characteristics is
required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input
voltage, and the component should have low reverse-leakage current. Additionally, the peak forward current
should be higher than the peak inductor current. The power dissipation in the Schottky diode is given in
Equation 16.
P = ID(PEAK) ´ VF ´(1- D)
D
V
5V
INMIN
D = 1-
= 1-
= 0.53
VOUT + VF
10V + 0.6V
P = 7.85 A ´ 0.6 V ´(1- 0.53) = 2.2 W
D
(16)
Low-Side MOSFET (BOT_SW3)
V ´I
æ
ö
= (IPk )2 ´rDS(on)(1+ TC)´D +
´(tr + tf )´ fsw
I
Pk
P
BOOSTFET
ç
÷
2
è
ø
V ´I
æ
ö
= (7.85 A)2 ´ 0.02 W ´(1+ 0.4)´ 0.53 +
´(20 ns + 20 ns)´ 200 kHz = 1.07 W
I
Pk
P
BOOSTFET
ç
÷
2
è
ø
(17)
The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver
strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction
losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the
transition losses which arise due to the full application of the input voltage across the drain-source of the
MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large
input peak current) and when the switching time is low.
NOTE: The on-resistance rDS(on) has a positive temperature coefficient, which produces the (TC = d × ΔT) term
that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from
MOSFET data sheets and can be assumed to be 0.005 / ºC as a starting value.)
BuckA Component Selection
Minimum ON Time, tON min
VO
3.4 V
tON min
=
=
= 283 ns
VIN max ´ fSW 30 V ´ 400 kHz
(18)
As shown in Equation 18, tON min is higher than the minimum duty cycle specified (100 ns, typical). Hence the
minimum duty cycle is achievable at this frequency.
Current-Sense Resistor RSENSE
Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 70
mV (at VIN = 12 V and duty cycle of 3.4 V / 12 V = 0.283). Allowing for tolerances and ripple currents, choose
VSENSE maximum of 55 mV.
55 mV
RSENSE
=
= 18 mW
3 A
Select 18 mΩ.
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Inductor Selection L
As explained in the description of the buck controllers (see Detailed Description), for optimal slope compensation
and loop response, the inductor should be chosen such that:
RSENSE
18 mW
L = KFLR
´
= 200´
= 9.2mH
fSW
400 kHz
•
KFLR = Coil selection constant = 200
(19)
Choose a standard value of 10 µH. For the buck converter, the inductor saturation currents and core should be
chosen to sustain the maximum currents.
Inductor Ripple Current IRIPPLE
At the nominal input voltage of 12 V, this gives a ripple current of 25% of IOUTmax ≈ 1 A.
Output Capacitor CO
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈ 15 mV
and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the
required limits.
2´ DIOUTA
=
fSW ´ DVOUTA 400 kHz ´0.2 V
2´ 2.9 A
COUTA
»
= 72.5 mF
(20)
(21)
(22)
IOUTA(Ripple)
1 A
VOUTA(Ripple)
=
+ IOUTA(Ripple) ´ESR =
+1 A ´10 mW = 13.1mV
8´ fSW ´ COUTA
8´ 400 kHz ´100 mF
DIOUTA
2.9 A
4´ 50 kHz ´100 mF
DVOUTA
=
+ DIOUTA ´ESR =
+ 2.9 A ´10 mW = 174 mV
4´ fC ´ COUTA
Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response.
•
•
•
Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
Select the zero fz ≈ fC / 10
Make the second pole fP2 ≈ fSW / 2
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Selection of Components for Type II Compensation
VOUT
F
Bx
RESR
COUT
RL
COMP
Type 2A
GmBUCK
VREF
R3
R0
C2
C1
Figure 26. Buck Compensation Components
2p´ fC ´ VOUTA ´ COUTA
GmBUCK ´KCFB ´ VREF
2p´ 50 kHz ´ 3.4 V ´100 mF
GmBUCK ´KCFB ´ VREF
R3 =
=
= 19 kW
Use standard value of R3 = 18 kΩ
where:
•
•
•
•
•
VO = 3.4 V
CO = 100 µF
Gm = 1 mS
VREF = 0.8 V
KCFB = 0.125 / RSENSE = 6.9 (0.125 is an internal constant)
(23)
(24)
Use standard value of 1.8 nF.
C1
1.8 nF
C2 =
=
= 45 pF
f
400 kHz
2
æ
ç
ö
æ
ç
ö
SW
2p´18 kW ´1.8 nF
-1
2p´R3 ´ C1
-1
÷
÷
2
è
ø
è
ø
(25)
Use standard value of 47 pF.
The resulting bandwidth of buck converter fC
GmBUCK ´R3´KCFB VREF
fC =
´
2p´COUTA
VOUT
1mS´18 kW´ 6.9 S´0.8 V
2p´100 μF´ 3.4 V
fC =
= 46.5 kHz
(26)
(27)
fC is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3 ´ C1 2p´18 kW ´1.8 nF
= 4.9 kHz
= 188 kHz
fZ1 is close to the fC / 10 guideline of 5 kHz
The second pole frequency fP2
1
1
fP2
=
=
2p´R3 ´ C2 2p´18 kW ´ 47 pF
(28)
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fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied.
BuckB Component Selection
Using the same method as VBUCKA, the following parameters and components are realized in Equation 29.
VOUTB
1.235 V
tON min
=
=
= 103 ns
V
IN max ´ fSW 30 V ´ 400 kHz
(29)
This tONmin is on the edge of the minimum duty cycle specified (100 ns, typical); expect pulse-skipping at high VIN.
60 mV
RSENSE
=
= 30 mW
2A
30 mW
L = 200 ´
= 15 mH
400 kHz
choose 30 mΩ, 15 µH.
•
∆Iripple current ≈ 0.4 A (approx. 20% of IO max)
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO (ripple) ≈ 7.5 mV
and ∆V drop of ≈ 120 mV during a load step.
Assume fC = 50 kHz.
2´ DIOUTB
=
fSW ´ DVOUTB 400 kHz ´ 0.12 V
2´1.9 A
COUTB
»
= 46 mF
(30)
(31)
(32)
IOUTB(Ripple)
0.4 A
VOUTB(Ripple)
=
+ IOUTB(Ripple) ´ESR =
+ 0.4 A ´10 mW = 5.3 mV
8´ fSW ´ COUTB
8´ 400 kHz ´100 mF
DIOUTB
1.9 A
DVOUTB
=
+ DIOUTB ´ESR =
+1.9 A ´10 mW = 114 mV
4´ fC ´ COUTB
4´ 50 kHz ´100 mF
2p´ fC ´ VOUTB ´ COUTB
GmBUCK ´KCFB ´ VREF
R3 =
2p´ 50 kHz ´1.235 V ´100 mF
1mS 4.16S 0.8V
=
= 11.7 kW
(33)
(34)
Use standard value of R3 = 12 kΩ.
10
10
C1=
=
2p´R3 ´ fC 2p´12 kW ´ 50 kHz
= 2.7 nF,
choose 2.7nF
C1
C2 =
f
æ
ö
SW
2p´R3 ´ C1´
-1
ç
÷
2
è
ø
2.7 nF
=
= 68 pF, choose 68 pF
400 kHz
2
æ
ö
2p´12 kW ´ 2.7 nF ´
-1
ç
÷
è
GmBUCK ´R3 ´KCFB VREF
ø
(35)
fC =
´
2p´ COUTB
VO
1mS ´12 kW ´ 4.16 ´ 0.8
2p´100 mF´1.235 V
fC =
= 51.5 kHz
(36)
29
fC is close to the target bandwidth of 50 kHz.
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The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3 ´ C1 2p´12 kW ´ 2.7 nF
= 4.9 kHz
fZ1 is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2
=
=
2p´R3 ´ C2 2p´12kW ´ 68 pF
= 195 kHz
(37)
fP2 is close to the fSW / 2 guideline of 200 kHz.
Hence, all requirements for a good loop response are satisfied.
BuckX High-Side and Low-Side N-Channel MOSFETs
The gate-drive supply for these MOSFETs is supplied by an internal supply which is 5.8 V (typical) under normal
operating conditions. The output is a totem pole, allowing full voltage drive of VREG to the gate with peak output
current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx) and the
low-side MOSFET is referenced to the power ground (PGx) terminal. For a particular application, these
MOSFETs should be selected with consideration for the following parameters: rds(on), gate charge Qg, drain-to-
source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver
strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction
losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the
transition losses, which arise due to the full application of the input voltage across the drain-source of the
MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.
V ´I
æ
ö
= (IOUT )2 ´rDS(on)(1+ TC)´D +
´(tr + tf )´ fSW
IN
OUT
P
BuckTOPFET
ç
÷
2
è
ø
(38)
(39)
P
= (IOUT )2 ´rDS(on)(1+ TC)´(1-D) + VF ´IOUT ´(2´ td )´ fSW
BuckLOWERFET
In addition, during the dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses which is denoted by the second term in the Equation 39. Using external Schottky
diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.
Note that rDS(on) has a positive temperature coefficient which is accounted for in the TC term for rDS(on), TC = d ×
ΔT[°C]. The temperature coefficient, d, is available as a normalized value from MOSFET data sheets and can be
assumed to be 0.005 / ºC as a starting value.
30
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Schematic
The following section summarizes the previously calculated example and gives a schematic and component
proposals.
Table 4. Application Example
PARAMETER
VBUCKA
VBUCKB
BOOST
VIN = 6 to 30 V
12 V - typical
VIN = 6 to 30 V
12 V - typical
VBAT = 5 (cranking pulse
input) to 30 V
Input voltage
Output voltage, VOUTx
3.396 V
3 A
1.235 V
2 A
10 V
2.5 A
Maximum output current, IOUTx
Load-step output tolerance, ∆VOUT + ΔVOUT(Ripple)
Current output load step, ∆IOUTx
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 to 2 A
400 kHz
±0.5 V
0.1 to 3 A
400 kHz
0.1 to 2.5 A
200 kHz
5 V to 30 V
VBAT
L1
D1
BOOST — 10V, 25W
3.9 µH
680 µF
COUT1
10µF
CIN
220 µF
TOP-SW3
1kΩ
VBAT
DS
VIN
EXTSUP
DIV
BOT-SW3
0.025Ω
1.5 kΩ
1nF
GC1
GC2
VREG
CBB
CBA
TOP-SW2
L3
TOP-SW1
L2
0.1µF
0.1 µF
VBuckA — 3.4 V, 10.2 W 0.018 Ω
VBuckB — 1.235 V, 2 W
0.03 Ω
GA1
GB1
10 µH
15 µH
100µF
COUTA
100 µF
COUTB
PHA
PHB
BOT-SW2
BOT-SW1
GA2
GB2
PGNDA
SA1
PGNDB
SB1
TPS43337-Q1
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
47 pF
68 pF
1.8 nF
2.7 nF
12 kΩ
18 kΩ
PGA
ENA
PGB
5k Ω
5k Ω
500 nF
500 nF
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
220 pF
22 nF
1 nF
7.2 kΩ
Figure 27. Schematic - Application Example
Table 5. Application Example - Component Proposals
Name
Component Proposal
Value
3.9 µH
10 µH
15 µH
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
MSS1278T-103ML (Coilcraft)
MSS1278T-153ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
IRFR3504ZTRPBF (International Rectifier)
EEVFK1J681M (Panasonic)
ECASD91A107M010K00 (Murata)
EEVFK1J221Q (Panasonic)
680 µF
100 µF
220 µF
COUTA, COUTB
CIN
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Power Dissipation Derating Profile, 38-Pin HTTSOP Package With PowerPAD Package
Figure 28. Power Dissipation Derating Profile Based on High-K JEDEC PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
Boost Converter
1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense
resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to
the Schottky diode D1 to the COUT1 capacitors. The negative terminal of the input capacitor and the
negative terminal of the sense resistor must be connected together with short trace lengths.
2. The overcurrent-sensing shunt resistor may require noise filtering, and this capacitor should be close to the
IC pin.
Buck Converter
1. Connect the drains of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor
COUT1. The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.
3. The Kelvin-current sensing traces for the shunt resistor should have minimum trace spacing and be routed
parallel to each other. Any filtering capacitors for noise should be placed near the IC pins.
4. Connect the positive terminal of the respective output capacitor COUTA or COUTB to the respective feedback
input FBA or FBB. Do not connect these traces near any switching nodes or high-current traces.
Other Considerations
1. PGNDx and AGND should be shorted to the thermal pad. Use a star-ground configuration if connecting to a
non-ground-plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and
voltage-sense-feedback ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits
should not be located near nodes showing high dv/dt; these include the gate-drive outputs, phase pins, and
boost circuits (bootstrap).
3. Reduce the surface area of the high-current-carrying loops to a minimum, by ensuring optimal component
placement. Ensure the bypass capacitors are located as close as possible to their respective power and
ground pins.
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PCB Layout
POWER
INPUT
Power L ines
Connection to GND P lane ofPCB through vias
Connection to top /bottom ofPCB through vias
Vo ltage Ra ilOutputs
VBOOST
VBAT
DS
V IN
EXTSUP
D IV
GC1
GC2
CBA
VREG
CBB
GA1
PHA
GB1
PHB
GA2
PGNDA
SA1
GB2
PGNDB
SB1
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
Exposed Pad
connected to GND
P lane
M icrocontro ller
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS43337QDAPQ1
TPS43337QDAPRQ1
PREVIEW
ACTIVE
HTSSOP
HTSSOP
DAP
38
38
40
TBD
Call TI
Call TI
-40 to 125
-40 to 125
DAP
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS43337
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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相关型号：
TPS43351QDAPQ1
IC 0.4 A DUAL SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO38, PLASTIC, HTSSOP-38, Switching Regulator or Controller
TI
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