TPS43340QPHPQ1 [TI]
LOW IQ, 30 μA, HIGH VIN QUAD-OUTPUT POWER SUPPLY; 低智商， 30 μA ，高VIN四路输出电源
| 型号： | TPS43340QPHPQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW IQ, 30 μA, HIGH VIN QUAD-OUTPUT POWER SUPPLY |
| 文件： | 总38页 (文件大小：1122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS43340-Q1
www.ti.com
SLVSB16B –NOVEMBER 2011–REVISED APRIL 2012
LOW IQ, 30 µA, HIGH V QUAD-OUTPUT POWER SUPPLY
IN
Check for Samples: TPS43340-Q1
1
FEATURES
2
•
Input Voltage Range: 4 V to 40 V, Transients
•
Short Circuit, Over Current, and Thermal
up to 60 V
Protection on Buck Regulator Gate Drive,
Buck Reg Converter, and Linear Regulator
Output
•
Dual Output Synchronous Buck Controller
–
–
–
–
Peak Gate Drive Current 0.6 A
Separate Enable Inputs (EN1, EN2)
Automatic Low-Power Mode Operation
Low Current Consumption
•
•
Internal Thermal Overload Protection
Thermally Enhanced PowerPAD™ Package
–
48-Pin HTQFP (PHP)
–
30 µA (Typ) With Single Output
Operation in Low Power Mode
APPLICATIONS
•
•
•
•
•
•
Infotainment
–
35 µA (Typ) With Dual Output Operation
in Low Power Mode
Navigation
TFT Cluster Display
•
•
Low Shutdown Current, Ish = 5 μA Typ
Automotive ECU
Single Synchronous Buck Regulator Converter
BUCK3
Advanced Driver Information Systems
Multi Rail DC Power Distribution Systems
–
–
Max Output Current 2 A
Enable Input EN3
Simplified Schematic
•
•
Linear Regulator LREG1
Enable Input EN4
LReg
1
–
Internal Oscillator, Programmable via External
Resistor, 150 kHz to 600 kHz for Switching
Frequency fSW_BUCK1,2,3
VReg
2
VReg
1
TPS 43340
•
•
•
Integrated PLL, External Synchronization
Frequency: 150 kHz to 600 kHz
Switch Mode Regulators Operate with 180°
Phase-Shift
Soft Start Input for Switchmode Supplies (SS1,
SS2, SS3)
VReg
3
•
•
•
Reset Output for All Output Rails
Reset Delay, Programmable with Capacitor
Supply Under Voltage/Over Voltage Detection
and Shutdown
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS43340-Q1
SLVSB16B –NOVEMBER 2011–REVISED APRIL 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The TPS43340 is a dual buck regulator controller (BUCK1, BUCK2), single Buck regulator converter (BUCK3)
and linear regulator (LREG1) designed for powering the Texas Instruments family of DSPs and Microcontrollers
or general market MCU products. The device features integrated short-circuit and over-current protection on the
gate drive outputs for the Buck regulator controllers. Independent current fold back control for each Buck
regulator supply during regulator output short to ground. A soft start is incorporated on each output supply to
ensure on initial power up these regulated outputs are not in current limit. Reset delay is implemented on power
up to allow the outputs of BUCK1, BUCK2, BUCK3 and Linear regulator to get to stable regulation. The delay is
programmed with an external capacitor to a maximum range of 300 ms. Each power supply output has
adjustable output voltage based on the external resistor network settings. The device has sequencing control
during power up and down of the output rails based on the enable/disable control or soft start.
BUCK1 EFFICIENCY
vs
OUTPUT CURRENT
VIN = 12 V, BUCK1 = 5 V,
SWITCHING FREQUENCY = 400 kHz
10000
100
EFFICIENCY,
SYNC = LOW
90
80
70
60
50
40
30
20
10
0
1000
100
10
POWER LOSS,
SYNC = HIGH
POWER LOSS,
SYNC = LOW
1
EFFICIENCY,
SYNC = HIGH
0.1
0.0001
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
Figure 1.
Spacer
ORDERING INFORMATION(1)
PACKAGE(2)
TA
-40ºC to 125ºC
ORDERABLE PART NUMBER
HTQFP - PHP
TPS43340QPHPRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS43340-Q1
TPS43340-Q1
www.ti.com
SLVSB16B –NOVEMBER 2011–REVISED APRIL 2012
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–0.3
MAX UNIT
Supply inputs
Input voltage
VIN
60
60
68
V
V
V
Enable inputs
EN1, EN2
BOOT1, BOOT2
Bootstrap supplies
BOOT1-PH1,BOOT2-PH2,
BOOT3-PH3
Bootstrap supplies
Phase inputs
–0.3
8.8
60
V
PH1, PH2
–1.0
–2.0
–0.3
–0.3
V
V
V
V
PH1, PH2 (for 100 ns)
VSENSE1, VSENSE2
COMP1, COMP2
Feedback inputs
13
13
Error amplifier outputs
External MOSFET driver peak output
currents
GU1,GU2, GL1,GL2
1.0
A
V
Buck controller
Buck1 and Buck2
GL1-PGND1,GL2-PGND2
GU1-PH1,GU2-PH2
S1, S2, S3, S4
|S1-S2| , |S3-S4|
SS1, SS2
RST1, RST2
RT
–0.3
–0.3
–0.3
8.8
8.8
13
2
External MOSFET driver
Current sense voltage
Absolute differential Voltage
Soft start
V
V
V
V
V
V
V
V
V
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
13
13
13
13
13
13
13
13
20
13
Power good outputs
Switching frequency oscillator
External input clock
External input supply for gate drive
Input supply
SYNC
EXTSUP
VSUP
Slew rate setting
SLEW
Enable input
EN3
Bootstrap supply
BOOT3
PH3
–1
Buck converter
Buck3
Phase inputs
V
PH3 (for 100 ns)
VSENSE3
SS3
–2
Feedback input
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
13
13
V
V
Soft start
Power good output
Error amplifier output
Input voltage
RST3
13
V
COMP3
13
V
VLR1
60
V
Output voltage
LREG1
7
V
Linear regulator
LREG1
Enable input
EN4
60
V
Power good output
Feedback inputs
PMOS driver
RST4
8.8
13
V
VSENSE4
GPULL
V
60
V
Zener clamp current
Internal regulator
Reset delay
GPULL
0.2
8.8
8.8
60
mA
V
GPULL, Rdelay, VREG,
VIN2SENSE
VREG
–0.3
–0.3
–0.3
–40
–40
–55
Rdelay
V
Supply sense input
Junction temperature: TJ
Operating temperature: TA
Storage temperature: TS
VIN2SENSE
V
150
125
165
°C
°C
°C
Temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
Copyright © 2011–2012, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1) (continued)
MIN
MAX UNIT
except VLR1
VLR1
±2
±1
kV
kV
V
Human Body Model (HBM)
Electrostatic discharge
except RSTx
RSTx
±200
±100
±500
±750
ratings
(ESD)
Machine Model (MM)
V
all pins
V
Charged Device Model (CDM)
corner pins
V
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNIT
Input voltage
Supply inputs
VIN
4
4
40
40
40
48
40
V
V
V
V
V
V
V
V
A
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Input voltage for Buck 2
VIN2SENSE
Enable inputs
EN1, EN2
BOOT1, BOOT2
PH1, PH2
PH1, PH2 (for 50 ns)
VSENSE1, VSENSE2
COMP1, COMP2
GU1,GU2, GL1,GL2
S1, S2, S3, S4
SS1, SS2
RST1, RST2
RT
0
Bootstrap inputs
4
–0.6
–2.0
0
Phase inputs
Feedback inputs
6
6
Error amplifier outputs:
0
Buck controller
Buck1 and Buck2
External MOSFET driver peak output currents
0.75
11
Current sense voltage
Soft start
0
0
6
Power good outputs
Switching frequency setting
External input clock
External input supply for gate drive
Input supply
0
11
0
1.2
9
SYNC
0
EXTSUP
VSUP
0
9
4
10
Slew rate setting
SLEW
0
VREG
6
Enable input
EN3
0
Boot inputs
BOOT3
0
18
PH3
–1
–2
0
11
Buck converter
Phase inputs
Buck3
PH3 (for 50 ns)
VSENSE3
SS3
Feedback input
Soft start
6
6
0
Power good output
Error amplifier output
Input voltage
RST3
0
11
6
COMP3
0
VLR1
4
40
5.25
40
5.25
6
Output voltage
Linear regulator
Enable input
LREG1
LREG1
0.8
0
EN4
Power good output
RST4
0
Feedback inputs
VSENSE4
GPULL
0
PMOS driver
PMOS driver
4
40
6
Internal regulator
VREG
0
Thermal resistance junction to ambient(1), θJA
Thermal resistance junction to pad(2), θJC
31 °C/W
1.8 °C/W
Temperature ratings
Operating temperature, TA
–40
125
°C
(1) This assumes a JEDEC JESD 51-5 standard board with thermal vias – See PowerPAD™ Thermally Enhanced Package application
note from Texas Instruments (TI literature number SLMA002) for more information.
(2) This assumes junction to exposed pad.
4
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Product Folder Link(s): TPS43340-Q1
TPS43340-Q1
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SLVSB16B –NOVEMBER 2011–REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS
VIN = VLR1 = 8 V to 18 V, VSUP = 4 V to 10 V, VIN2SENSE = 4V to 40V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply
Input voltage required for device on initial start up
Operating range after initial start up
VIN falling
6.5
4.0
3.5
40
V
V
V
V
V
VIN
Device operating range
Undervoltage lockout
3.6
3.8
3.8
4
VIN UV
VLR1
VIN rising
Device operating range for linear reg Recommended operation range
EN1 = 1, LPM; EN2,3,4 = 0
4.0
40
30
40
EN2 = 1, LPM; EN1,3,4 = 0
µA
mA
µA
Quiescent current:
EN4 = 1, LPM; EN1,2,3 = 0
TA = 25°C
Iq
48
35
4
60
45
EN1,2 = 1, LPM; EN3,4 = 0
EN3,4 = 1, EN1,2 = 0
4.5
EN1 = 1, LPM; EN2,3,4 = 0
EN2 = 1, LPM; EN1,3,4 = 0
Quiescent current:
EN4 = 1, LPM; EN1,2,3 = 0
TA = 125°C
40
50
Iq
52
40
5
60
45
EN1,2 = 1, LPM; EN3,4 = 0
EN3,4 = 1, EN1,2 = 0
mA
mA
VIN = 13 V, Buck1: CCM, Buck2: off or
VIN = 13 V, Buck2: CCM, Buck1: off or
VIN = 13 V, Buck1/2: CCM
Quiescent current:
TA = 25°C
IVIN
5
Normal operation, SYNC = 5 V
5
5
5
7
5
VIN = 13V, Buck1: CCM, Buck2: off
Quiescent current:
IVIN
mA
TA = 125°C
VIN = 13V, Buck2: CCM, Buck1: off
VIN = 13V, Buck1, 2: CCM
IVIN-SD
IVIN-SD
IVLRI-SD
Shutdown current at TA = 25°C
Shutdown current at TA = 125°C
Shutdown current at TA = 125°C
EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V
EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V
EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V
10
20
5
µA
µA
µA
Internal Supply VREG
Internal regulated supply
VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High
EXTSUP = 0 V, SYNC = High IVREG = 0 mA to 100 mA
EXTSUP = 8.5 V, normal mode
5.5.
7.2.
5.8
0.2
7.5
6.1
1
V
%
V
VREG
Load regulation
Internal regulated supply
7.8
VREG-EXTSUP
EXTSUP = 8.5 V to 13 V, normal mode IVREG = 0 mA to
125 mA
Load regulation
0.2
4.6
1
%
IVREG = 0 mA to 100 mA, EXTSUP ramping positive,
normal mode
VEXTSUP-VREG
VEXTSUP-HYS
IREG-LIM
Switch over voltage
Switch over hysteresis
Current limit on VREG
4.4
150
100
4.8
250
400
V
Normal mode
mV
mA
EXTSUP = 0 V normal mode as well as LPM,
VREG=0V
Current limit on VREG when using
EXTSUP
IVREG = 0 mA to 100 mA, EXTSUP = 8.5 V, normal
mode, VREG=0V
IREG-EXTSUP-LIM
125
400
mA
Input voltage VIN - Overvoltage Lock Out and Reverse Polarity Protection
VIN rising
45
43
1
46
44
2
47
45
3
V
V
VOVLO
Overvoltage shutdown
VIN falling
OVLOHys
OVLOfilter
VGD
Hysteresis
V
Filter time
5
µs
V
Clamping voltage of ext. FET
Internal resistance to GND
VIN - GPULL
17
500
RGPULL
kΩ
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ELECTRICAL CHARACTERISTICS (continued)
VIN = VLR1 = 8 V to 18 V, VSUP = 4 V to 10 V, VIN2SENSE = 4V to 40V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Buck Controllers
VBuck1/2
Adjustable output voltage range
Internal reference voltage
Closed loop
0.9
0.792
-1
11
0.808
1
V
V
VSENSE1/2 pin, load = 0 mA
Internal tolerance on reference
VSENSE1/2 pin, load = 0 mA
Tolerance
0.800
0.800
Vref,
%
V
0.784
-2
0.816
2
Internal reference voltage in low
power mode
Vref, LPM
%
Maximum peak forward current
sense voltage in CCM
S1-S2 respectively S3-S4 VSENSEx = 0.75 V, low duty
cycles
60
-65
17
75
-37.5
43.8
90
-23
48
mV
mV
mV
Vsense
Minimum peak forward current
sense voltage in CCM
S1-S2 respectively S3-S4 VSENSEx = 1 V
Maximum peak forward current
sense voltage during output short
VI-Foldback
tdead
S1-S2 respectively S3-S4 VSENSEx =0V (foldback)
Shoot through delay, blanking time
Minimum on time
20
100
ns
ns
%
%
High side minimum on time
Maximum duty cycle
DCNRM
Duty cycle
98.75
DCLPM
Duty cycle LPM
80
LPM entry threshold load current as
fraction of maximum set load current
ILPM_Entry
1
%
%
The exit threshold is specified to be always higher than
entry threshold
LPM exit threshold load current as
fraction of maximum set load current
VLPM_Exit
10
High-Side External NMOS Gate Drivers for Buck Controllers
IGUx_peak
RDS_ON
Gate driver peak current
Source and sink driver
0.6
5
A
IVREG = 5.8 V, IGUx current = 200 mA
VREG = 5.8V, IGLx current = 200 mA
Ω
Low-Side NMOS Gate Drivers for Buck Controllers
IGLx_peak
RDS_ON
Gate driver peak current
Source and sink driver
0.6
5
A
Ω
Internal Oscillator (RT)
fSW
Buck switching frequency
RT pin: GND
360
360
150
150
400
400
440
440
600
600
kHz
kHz
kHz
kHz
V
fSW
Buck switching frequency
Buck adjustable range
Buck synch. range
RT pin: 60 kΩ external resistor
Using external resistor on RT (see equation)
External clock input on SYNC
fSW-adj
fsync
VRT
Oscillator reference voltage
1.2
20
SYNC rising edge to PH rising edge
delay
fSW-Prop dly
0
40
ns
µs
Last SYNC rising edge to return to
resistor mode if CLK is not present
on SYNC pin
fSW-Trans-delay
20
Error Amplifier (OTA) for Buck Controllers and Buck Converter
IPULLUP_VSENSEx
gm
Pull-up current at VSENSEx pins
Forward transconductance
VSENSEx = 0 V
50
100
0.9
200
nA
COMP1, COMP2 = 0.8 V; source/sink = 5 µA, Test in
feedback loop
0.7
1.35
mS
6
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Product Folder Link(s): TPS43340-Q1
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SLVSB16B –NOVEMBER 2011–REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS (continued)
VIN = VLR1 = 8 V to 18 V, VSUP = 4 V to 10 V, VIN2SENSE = 4V to 40V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
External Clock and Enable Inputs: SYNC. EN1, EN2, EN3, EN4
VIH
Higher threshold
Lower threshold
Pull-down resistance
Pull-up current
VIN = 13 V
VIN = 13 V
1.7
V
V
VIL
0.7
2
RIH
VSYNC = 5 V, SYNC pull-down resistance
VENx = 0V ENx pull up current source
500
0.5
kΩ
µA
IiL_ENx
Linear Regulator LREG1
VLREG1 Regulated output range
VRef
IL = 10 µA to 300 mA
0.8
5.25
2.5
15
V
Internal reference voltage tolerance Referred to 0.8 V VREF, measured at VSENSE4
-2.5
%
∆VOUT, Vout = 5 V
VIN = VLR1: 6 V to
28 V, IOUT 4 = 10 mA,
Vline-reg
Line reg
∆VOUT, Vout = 3.3 V
∆VOUT, Vout = 1.5 V
∆VOUT, Vout = 5 V
∆VOUT, Vout = 3.3 V
∆VOUT, Vout = 1.5 V
15
mV
15
10
IOUT4 = 10 mA to
300 mA, VIN = 14 V
Vload-reg
Load reg
10
mV
mV
10
VIN = VLR1 = 4 V: Iout = 250 mA
VIN = 9 V, VLR1 = 4 V: Iout = 150 mA
VOUT in regulation
500
300
300
1000
VDropout
Drop out voltage
IOUT4
Output current
0.01
400
mA
mA
ILREG1-CL
dVLREG1/dt
Output current limit
Output soft start slew rate
VOUT = 0 V
Response of regulator on enable IOUT = 0 to Iout (max)
5
60
25
V/ms
Freq = 100 Hz
Vripple = 0.5 VPP, IOUT
= 300 mA
PSRR
Power supply ripple rejection
dB
Freq = 150 kHz
COUT4
Output capacitor range
Charge pump turn-off voltage
Hysteresis
Ceramic capacitor, COUT_ESR = 10 mΩ to 1 Ω
1
47
µF
V
VIN rising
9.4
0.18
2
VTH-CP ONp
V
IOUT4 falling
Hysteresis
ITH-CP-OFF
Low load current detection threshold
mA
4
Soft Start SSx
ISSx
Soft start source current
SSx = 0 V
0.75
-5
1
1.25
µA
Reset RSTx
RSTpullup
RSTxth1
RST1, RST2, RST4 Pullup
Reset threshold
Internal pullup to S2 respectively S4, LREG1
VSENSEx falling
50
-7
2
kΩ
-9.5 %VREF
%VREF
RSTxhys
Hysteresis
IRSTx = 5 mA
450
100
1
mV
mV
µA
µs
RSTxdrop
Voltage drop
IRSTx = 1 mA
RSTxleak
tdeglitch
tdelay
Leakage
VS2 = VS4 = VRSTx = 13 V / 8V for RST4
Power good deglitch
Deglitch time
2
16
Reset release delay
Fixed reset delay
Charge current source
Discharge current sink
External capacitor = 1 nF
1
20
40
40
ms
µs
tdelay_fix
Ioh
No external capacitor, Rdelay pin open
Current to charge external capacitor
Current to discharge external capacitor
50
50
50
30
30
µA
µA
Iil
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ELECTRICAL CHARACTERISTICS (continued)
VIN = VLR1 = 8 V to 18 V, VSUP = 4 V to 10 V, VIN2SENSE = 4V to 40V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronous Buck Converter VBUCK3
VSUP
VBUCK3 supply voltage
4
3.6
3.7
10
3.8
V
V
VSUP falling
VSUP rising
3.7
3.8
VSUPUV
VBUCK3 undervoltage lockout
3.9
V
High-side switch
VSUP = 9 V, VBoot3 –PH3 = 5.8 V
VSUP = 9 V, VVREG-PGND3 = 5.8 V
DC test
0.14
0.15
0.28
0.28
Ω
RDS(on)
Low-side switch
Ω
IHS-Limit
ILS-Limit
VSUPLkg
IFB3
High-side switch
2.5
A
Low-side switch
DC test, current into PH3
VSUP = 10 V for high side, EN3 = Low. TJ = 100°C
VSENSE3 = 0 V
2.38
A
VSUP leakage current
Current foldback
1
µA
A
1.9
fSW-adj
VSense
Buck3 switching freq range
Feedback voltage
Using external resistor on RT/CLK
Internal ref = 0.8 V
150
-1.5
600
1.5
kHz
%
2-times - frequency foldback exit
threshold
VSENSE3 rising
VSENSE3 falling
0.65
0.60
fSW-f-back
V
2-times - frequency foldback entry
threshold
Gm3
DC3
Current loop transconductance
Minimum duty cycle
ΔIpeakPH3/ΔVCOMP3
5.4
10
S
%
%
fSW = 400 kHz, SLEW = LOW or OPEN
Maximum duty cycle
98.75
170
15
BUCK3 FETs deactivate threshold
Hysteresis
TOT-BUCK3
Overtemperature sensor
Shutdown threshold
°C
Thermal Shutdown
Tshutdown
Junction temperature
Hysteresis
150
170
15
°C
°C
Thys
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DEVICE INFORMATION
TPS43340-Q1
PHP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
36
GU 1
PH1
1
2
3
4
5
6
7
8
9
GU2
PH2
35
34
GL2
GL1
PGND 1
S2
33
32
31
30
29
28
27
26
25
PGND 2
S4
S1
S3
VSENSE 1
COMP 1
RST 1
VSENSE 2
COMP 2
RST 2
SS2
SS1
10
11
GND
RT
VSUP
PGND 3
12
13
14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTIONS
PIN
NO. NAME
I/O
DESCRIPTION
1
GU1
O
O
External high-side N-channel MOSFET gate drive for the buck regulator BUCK 1. The output provides
high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference
provided by the PH1 and has a voltage swing provided by BOOT1
2
PH1
Switching terminal of the buck regulator BUCK 1, providing a floating ground reference for the high-side
MOSFET gate driver circuitry and is used to sense current reversal in the inductor when discontinuous
mode operation is desired.
3
4
GL1
O
O
External low-side N-channel MOSFET gate drive for the buck regulator BUCK 1. The output provides high
peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
PGND1
Power ground connection for GL1 driver. Connect to the source of the low-side N-channel MOSFET of
BUCK 1.
5
6
7
8
S2
I
High Impedance differential voltage inputs from the current sense element (sense resistor or inductor
DCR) for buck controller. For details, see section Functional Description.
S1
I
VSENSE1
COMP1
I
Feedback voltage pin for BUCK1 . For details, see Application Information.
O
Error amplifier output of BUCK 1 and compensation node for voltage loop stability. The voltage at this
node sets the target for the peak current through the respective inductor. This voltage is clamped on the
upper and lower ends to provide current limit protection for the external MOSFETs.
9
RST1
SS1
O
O
Open drain power good output for BUCK 1 with a 50kΩ pull-up resistor to S2. An internal power good
comparator monitors the voltage at the feedback pin and pull this output low when the output voltage falls
by RSTxth1 of the set value.
10
Soft-start or tracking input for the buck controller BUCK 1. The buck controller regulates the VSENSE1
voltage to the lower of 0.8V or the SS1 pin voltage. An internal pull-up current source of 1μA is present at
the pin and an appropriate capacitor connected here can be used to set the soft-start ramp duration. A
resistor divider from another supply can also be used to provide a tracking input to this pin.
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PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NO. NAME
11
VSUP
I
Power supply for BUCK3 regulator. Provide good decoupling to PGND3 with ceramic capacitor close to
pins.
12
13
PGND3
PH3
O
O
BUCK3 power ground
Switching terminal of buck converter BUCK 3. Also provides a floating ground reference for the high-side
MOSFET gate driver circuitry .
14
BOOT3
I
A capacitor between BOOT3 and PH3 acts as the voltage supply for the high-side N-channel MOSFET
gate drive circuitry in the buck converter BUCK 3.When the buck is in a dropout condition, the device
automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth
cycle to allow the capacitor to re-charge.
15
SS3
O
Soft-start or tracking input for the buck converter BUCK 3. The buck converter regulates the VSENSE3
voltage to the lower of 0.8V or the SS3 pin voltage. An internal pull-up current source of 1μA is present at
the pin and an appropriate capacitor connected here can be used to set the soft-start ramp duration. A
resistor divider connected to another supply can also be used to provide a tracking input to this pin
16
17
RST3
O
I
Open drain power good output for BUCK 3. An internal power good comparator monitors the voltage at
the feedback pin and pull this output low when the output voltage falls by RSTxth1 of the set value
VSENSE3
Feedback voltage pin for BUCK 3. The buck controller regulates the feedback voltage to the internal
reference of 0.8V. A suitable resistor divider network between the buck output and the feedback pin sets
the desired output voltage
18
19
COMP3
SLEW
O
I
Error amplifier output of BUCK 3 and compensation node for voltage loop stability. The voltage at this
node sets the target for the peak current through the respective inductor.
Slew rate (dv/dt) selector of the internal high side switching MOSFET for BUCK3. For details, see
Application Information.
20
21
22
23
EN3
I
I
I
I
Enable input for BUCK 3. This input has an internal pull up with approximately 0.5µA current.
Enable inputs for BUCK 2. This input has an internal pull up with approximately 0.5µA current.
Enable inputs for BUCK 1. This input has an internal pull up with approximately 0.5µA current.
EN2
EN1
SYNC
PLL synchronization, low power mode control pin. If an external clock is present on this pin the device
detects it and the internal PLL locks on to the external clock. This overrides the internal oscillator
frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. For details, see
Application Information.
24
25
Rdelay
RT
O
O
The capacitor at the Rdelay pin sets the power good delay interval used to de-glitch the outputs of the
power good comparators. When this pin is left open, the power good delay is set to an internal default
value of 20μs typical.
The operating switching frequency of the buck controllers and converter is set by connecting a resistor to
analog ground on this pin. Shorting this pin to ground or leaving it open defaults operation to 400 kHz for
the buck controllers and the converter.
26
27
GND
SS2
O
O
Analog Ground Reference
Soft-start or tracking input for the buck converter BUCK 2. The buck controller regulates the VSENSE2
voltage to the lower of 0.8V or the SS2 pin voltage. An internal pull-up current source of 1μA is present at
the pin and an appropriate capacitor connected here can be used to set the soft-start ramp interval. A
resistor divider connected to another supply can also be used to provide a tracking input to this pin
28
29
30
RST2
O
O
I
Open drain power good output for BUCK 2 with a 50kΩ pull-up resistor to S4. An internal power good
comparator monitors the voltage at the feedback pin and pull this output low when the output voltage falls
by RSTxth1 of the set value
COMP2
VSENSE2
Error amplifier output of BUCK 2 and compensation node for voltage loop stability. The voltage at this
node sets the target for the peak current through the respective inductor. This voltage is clamped on the
upper and lower ends to provide current limit protection for the external MOSFETs
Feedback voltage pin for BUCK 2. The buck controller regulates the feedback voltage to the internal
reference of 0.8V. A suitable resistor divider network between the buck output and the feedback pin sets
the desired output voltage.
31
32
33
34
S3
I
High Impedance differential voltage inputs from the current sense element (sense resistor or inductor
DCR) for buck controller BUCK2. For Details, see section Functional Description.
S4
I
PGND2
GL2
O
O
Power ground connection to the source of the low-side N-channel MOSFETs of BUCK 2
External low-side N-channel MOSFET for the buck regulator BUCK 2 can be driven from this output. The
output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by
VREG
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PIN FUNCTIONS (continued)
PIN
NO. NAME
I/O
DESCRIPTION
35
36
37
PH2
O
O
I
Switching terminal of the buck regulator BUCK 2, providing a floating ground reference for the high-side
MOSFET gate driver circuitry and is used to sense current reversal in the inductor when discontinuous
mode operation is desired.
GU2
External high-side N-channel MOSFET for the buck regulator BUCK 2 can be driven from this output. The
output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground
reference provided by the PH2 and has a voltage swing provided by BOOT2.
BOOT2
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry
in the buck converter BUCK 2. When the buck is in a dropout condition, the device automatically reduces
the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor
to re-charge.
38
VREG
O
An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck
controllers and converter. The regulator can be used such that it is either powered from VIN or EXTSUP.
This pin has a current limit protection and should not be used to drive any other loads.
39
40
GPULL
O
I
Gate driver output to implement the reverse-battery protection by an external PMOS. See Application
Information for more details.
EXTSUP
EXTSUP can be used to supply the VREG regulator from one of the TPS43340 buck regulator rails to
reduce power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower
than 4.6V, the regulator is powered from VIN.
41
VIN
I
Main Input pin. This is the buck controller and buck converter input pin. Additionally it powers the internal
control circuits of the device. A bypass capacitor should be connected to filter noise between this pin and
signal ground.
42
43
44
VLR1
I
The VLR1 terminal is the input voltage source for the linear regulator supply. An input capacitor to ground
is required to filter any noise present on the line.
VIN2SENSE
RST4
I
Supply voltage sense input for current mode of BUCK2. Connect to Drain of High-Side-FET of Buck2.
Cascading Buck1 as supply for Buck2 configuration does not support LPM on Buck2.
O
Open drain power good indicator pin for LREG1 with a 50kΩ pull-up resistor to LREG1. An internal power
good comparator monitors the voltage at the feedback pin and pull this output low when the output
voltage falls by RSTxth1 of the set value
45
VSENSE4
I
Feedback voltage pin for Linear regulator LREG1. LREG1 regulates the feedback voltage to the internal
reference. A suitable resistor divider network between the LDO output and the feedback pin sets the
desired output voltage. See LREG1 parameters above and Application Information.
46
47
LREG1
EN4
O
I
Linear regulator output. Decouple with a low ESR ceramic output capacitor connected from this terminal
to ground.
Enable input for LREG1 (active high with an internal pull up current source). An input voltage higher than
Vih enables the regulator, while an input voltage lower than Vil disables the regulator. This input has an
internal pull up with approximately 0.5µA current.
48
BOOT1
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry
in the buck converter BUCK 1. When the buck is in a dropout condition, the device automatically reduces
the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor
to re-charge.
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48
47
46
45
44
43
42
41
40
39
38
37
1 -
BUCK
Channel
36
35
34
33
2
GU
VIN
Filter
2 –
BUCK
Channel
Internal
supply
1
2
3
GU1
PH1
PH2
GL2
-
Thermal
sensor
+
PWM logic
(duplicate of
BUCK 1-Channel )
Over
current
Int Reg
Int Reg supply
VIN
PGND 2
S4
1
GL
EN
32
31
30
29
28
27
Control
+
-
PGND 1
4
Current sense
Amp
Slope Comp
0.8V
S3
5
6
S2
S1
-
PWM
-
2
+
VSENSE
comp
-
+
-
OTA
gm
2
COMP
-
PWM
comp
+
7
8
1
VSENSE
+
0.8V
2
RST
Slope
Comp
Filter timer
+
-
2
SS
COMP 1
PWM logic
-
-
-
+
Phasing
Vref
Current
sense
+
O -C
9
OTA
26
25
+
1
-
GND
RT
RST
Buck3 Buck2 Buck1
Amp
Vref
gm
+
+
-
Filter timer
Osc
10
-
SS1
+
-
0.8 V
11
12
Control Logic
VSUP
PGND3
23
24
14
20
21
22
13
15
16
17
18
19
Figure 2. Internal Functional Blocks
12
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FUNCTIONAL DESCRIPTION
Enable Inputs
All regulators are enabled using independent enable inputs at the EN1.. EN4 pins. These pins have internal pull-
up currents of 0.5 µA (typical). As a result, an open circuit on these pins enables the respective
regulators.EN1,EN2,EN4 are high voltage pins and can be connected directly to the battery for self-bias. When
all regulators are disabled, the device is shut down and consumes a current of 5 µA typical.
BUCK CONTROLLERS: NORMAL MODE PWM OPERATION
Setting the Operating Frequency
The buck controllers operate using constant frequency peak current mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz
depending upon the resistor value at the RT pin. Tying this pin to ground at this pin sets the default switching
frequency to 400 kHz. The frequency can also be set by a resistor at RT according to the formula
ƒsw = 24 x 109 /RT
Switching Frequency
For example,
(1)
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to
600 kHz. The device detects clock pulses at this pin and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin and when this is detected for fSW-Trans-delay it
sets the switching frequency to the internal oscillator. The two buck controllers operate at the same switching
frequency 180 degrees out of phase.
Feedback Inputs
The output voltages are set by choosing the right resistor feedback divider networks connected to the VSENSEx
(feedback) pins. This is to be chosen such that the regulated voltages at the VSENSEx pins equals 0.8V. The
VSENSEx pins have 100nA pull up current sources as a protection feature in case the pins open up as a result
of physical damage.
R
TOP
VBUCKx = 0.8(1+
)V
RBOTTOM
Output Voltage
(2)
Where, RTOP is the resistor from VBUCKx to VSENSEx and RBOTTOM is the resistor from VSENSEx to ground
Soft-Start Inputs
In order to avoid large inrush currents, both buck controllers have independent programmable soft-start timing.
The voltage at the SSx pins acts as the soft-start reference voltage. A 1 µA pull-up current is available at the SSx
pins and by choosing a suitable capacitor a desired soft-start ramp speed can be generated. After start-up, the
pull-up current ensures that pins SSx are higher than the internal reference of 0.8V which then becomes the
reference for the buck controllers. The required capacitor for ∆t, the desired soft-start time is given by:
ISS x Δt
CSS
=
DV
Soft Start Ramp Capacitor
where:
(3)
ISS = 1 µA (typical)
∆V = 0.8 V
Alternatively the soft-start pins can be used as tracking inputs. In this case, the pins should be connected to the
supply to be tracked via a suitable resistor divider network.
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Current Mode Operation
Peak current-mode control regulates the peak current through the inductor such that the output voltage is
maintained to its set value. The error between the feedback voltage at VSENSEx and the internal reference
produces a signal at the output of the error amplifier (COMPx) which serves as target for the peak inductor
current. The current through the inductor is sensed as a differential voltage at S1-S2/S3-S4 and compared with
this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at VSENSEx causing
COMPx to fall or rise respectively, thus increasing/decreasing the current through the inductor until the average
current matches the load. In this way the output voltage is maintained in regulation.
The High-Side N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the
inductor current reaches its peak value. Once this MOSFET is turned off, and after a small delay (shoot-through
delay) the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation the
high-side MOSFET stays on 100%. In every fourth clock cycle the duty cycle is limited to 95% in order to charge
the bootstrap capacitor at BOOTx. This allows a maximum duty cycle of 98.75% for the buck regulators. Thus
during dropout the buck regulators switch at one-fourth of the normal frequency.
Current Sensing and Current Limit with Foldback
The maximum value of COMPx is clamped such that the maximum current through the inductor is limited to a
specified value. When the output of the buck regulator (and hence the feedback value at VSENSEx) falls to a low
value due to a short circuit/over-current condition, the clamping voltage at the COMPx successively decreases,
thus providing current fold back protection. This protects the high-side external MOSFET from excess current
(forward direction current limit).
Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully
on, the COMPx node will drop low. It is clamped on the lower end as well in order to limit the maximum current in
the low-side MOSFET (reverse direction current limit).
The current through the inductor is sensed by an external resistor. The sense resistor should be chosen such
that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This
value is specified at low duty cycles only. At typical duty cycle conditions around 40% (assuming 5 V output and
12V input), 50 mV is a more reasonable value, considering the slope compensation and tolerances. The typical
characteristics in Figure 4 and Figure 19 provide a guide for using the correct current limit sense voltage.
The current sense pins Sx are high impedance pins with low leakage across the entire output range. This allows
DCR current sensing using the DC resistance of the inductor for higher efficiency. DCR sensing is shown in the
below figure. Here the series resistance (DCR) of the inductor is used as the sense element. The filter
components should be placed close to the device for noise immunity. It should be remembered that while the
DCR sensing gives high efficiency, it is less accurate due to the temperature sensitivity and a wide variation of
the parasitic inductor series resistance. Hence it may often be advantageous to use the more accurate sense
resistor for current sensing.
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V
IN
HS DCRSensing
L
R
L
VOUT
VPH
PWM
Gate
Drivers
Logic
COUT
LS
RDCR
CDCR
Summing
Comparator
S1
S2
Current
Sensing
VSENSE
VSENSE,EXT
VSLOPE
Slope
Compensation
R
1
FB
gm
V
c
Error
Amp
R
2
Current Loop
(Inner Loop)
VoltageLoop(Outer Loop)
Figure 3. Overcurrent Sensing and Control
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Slope Compensation
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable current
mode operation at all conditions. For optimal performance of this circuit, the following condition must be satisfied
in the choice of inductor and sense resistor:
200
L =
x RS
f
SW
Inductor and Sense Resistor Choice
Where
(4)
L is the buck regulator inductor in Henry
RS is the sense resistor in Ω
fsw is the buck regulator switching frequency in Hz
80
70
60
50
40
30
20
10
0
AVERAGE CURRENT
RIPPLE CURRENT
AVERAGE CURRENT
RIPPLE CURRENT
VIN = 12V
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
EXAMPLE WITH 40% DC, MAX SENSE
EXAMPLE WITH 70% DC, MAX SENSE
-VOLTAGE ~64mV AT VIN=12V, VOUT=4.8V
-VOLTAGE ~43mV AT VIN=12V, VOUT=8.4V
Figure 4. Peak Current Sense Voltage vs Duty Cycle
Reset Outputs and Filter Delays
Each buck controller has an independent reset comparator monitoring the feedback voltage at the VSENSEx
pins and indicating whether the output voltage has fallen below the specified reset threshold. The reset indicator
is available as an open drain output at the RSTx pins. An internal 50 kΩ pull-up resistor to S2/S4 is available or
an external resistor can be used. When a buck controller is shut down, the power good outputs are pulled down
internally. Connecting the pull-up resistor to a rail other than the output of that particular buck channel will cause
a constant current flow through the resistor when the buck controller is powered down.
In order to avoid triggering the power good indicators due to noise or fast transients on the output voltage, an
internal delay of tdeglitch for de-glitching is used. When the output voltage reaches its set value after a start-up
ramp or negative transient, the power good indicator will be asserted high (the open-drain pin released) after a
delay of tdelay, at least tdelay_fix. This can be used to delay the reset to the circuits being powered from the buck
regulator rail. The delay of this circuit can be programmed by using a suitable capacitor at the Rdelay pin
according to Equation 5:
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Power Good Output Delay
tRdelay = 106 x CRdelay (seconds)
(5)
Where
CRdelay is the capacitor value in Farad on Rdelay pin.
When the Rdelay pin is open the delay is set to a default value of 20 µs typical. The power good delay timing is
common to all supply rails but the power good comparators and outputs function independently.
Light Load PFM Mode
An external clock or a high level on the SYNC pin or enabling BUCK3 results in forced continuous mode
operation of the bucks. When the SYNC pin is low or open, the buck controllers will be allowed to operate in
discontinuous mode at light loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor
current is detected.
In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side as well
the low-side MOSFET is turned off increases (deep discontinuous mode). In case the duration exceeds 60% of
the clock period and VBAT >8V, the buck controller switches to a low power operation mode. The design
ensures that this typically occurs at 1% of the set full load current if the inductor and the sense resistor have
been chosen appropriately as recommended in the slope compensation section.
Normal Mode
High Load
Time
0
Normal to DCM
Boundary Condition
0
Time
Time
t
LS
0
t
Moves Closer as
Load Increases
Low Power Mode
(LPM) Operation
0
0
Time
t
ON
Entering Normal
Mode
Time
Figure 5.
In Low Power PFM Mode, the buck controllers monitor the VSENSEx voltage and compare it with the 0.8 V
internal reference. Whenever the VSENSEx value falls below the reference, the high-side MOSFET is turned on
for a pulse-duration inversely proportional to the difference VIN-S2/S4. At the end of this on-time, the high-side
MOSFET is turned off and the current in the inductor decays until it becomes zero. The low-side MOSFET is not
turned on. The next pulse occurs the next time VSENSEx falls below the reference value. This results in a
constant volt-second TON hysteretic operation with a total device quiescent current consumption of 30 µA when a
single buck channel is active and 35 µA when both channels are active.
As the load increases, the pulse become more and more frequent until the current in the inductor becomes
continuous. At this point, the buck controller returns to normal fixed frequency current mode control. Another
criterion to exit the low power mode is when VIN falls low enough to require higher than 80% duty cycle of the
high-side MOSFET.
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The TPS43340-Q1 can support the full current load during low power mode until the transition to normal mode
takes place. The design ensures the low power mode exit occurs at 10% (typical) of full load current if the
inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis
between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low power mode is only possible when both buck controllers
have light loads that are low enough for low power mode entry.
Gate Driver Supply (VREG, EXTSUP)
The gate drivers of the buck controllers and the buck converter are supplied from an internal linear regulator
whose output (5.8 V typical) is available at the VREG pin and should be decoupled using at least a 3.3 µF
ceramic capacitor. This pin has an internal current limit protection and should not be used to power any other
circuits.
The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V
(typical). If VIN is expected to go to high levels, there can be excessive power dissipation in this regulator,
especially at high switching frequencies and when using large external MOSFET's. In this case, it is
advantageous to power this regulator from the EXTSUP pin which can be connected to a supply lower than VIN
but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear
regulator automatically switches to EXTSUP. Efficiency improvements are thus possible when one of the
switching regulator rails from the TPS43340-Q1 or any other voltage available in the system is used to power the
EXTSUP.
VIN
EXTSUP
LDO
EXTSUP
LDO
VIN
typ 5.8 V
typ 7.5 V
typ 4.6 V
VREG
Figure 6. Internal Gate Driver Supply
Using a large value for EXTSUP is advantageous as it provides a large gate drive and hence better on-
resistance of the external MOSFETs. The EXTSUP pin should be tied to ground when not being used.
During low power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt
regulator powered from VIN and has a typical value of 7.2 V. Current limit protection for VREG is available in low
power mode as well.
External P-Channel Drive (GPULL) and Reverse Battery Protection
The TPS43340-Q1 includes a gate driver for an external P-channel MOSFET which can be used for reverse
battery protection. This is useful to reduce the voltage drop across the protection element compared to using a
series diode to VIN. The gate – source voltage of the external PMOS is clamped by an internal Zener diode to
17 V typical.
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VBAT ≤ VF → | VGS | = 0 V → FET and Diode NOT conducting
VF ≤ VBAT ≤ VT (FET) → | VGS | = VBAT → FET NOT conducting and Diode conducting
VT (FET) ≤ VBAT ≤ 17 V → | VGS | = VBAT → FET conducting
VBAT ≥ 17 V → | VGS | = 17 V → FET conducting
Spacer
VF
VBAT
VGS
If the FET has
GPULL
VIN
significant leakage
between GPULL and
VBAT, an external resistor
is recommended in parallel
to the internal one
17V
(GPULL - GND)
Electrical Source of FET is
at higher portential (even
though symbol would
indicate Source on the
right Pin of FET ). Voltages
500kOhm
refer to VGS as shown
TPS43340-Q1
GND
Figure 7. Internal Circuit of GPULL Output
NOTE
An implementation without the PMOS will block the current coming from Buck-outputs
(improper OR-ing, etc.) which may cause the Absolute Maximum ratings to be exceeded.
Undervoltage Lockout and Overvoltage Protection
The TPS43340-Q1 will start up at a VIN voltage of 6.5 V (max). Once it has started up, the device operates down
to a VIN undervoltage lockout level of 3.6 V or until VREG undervoltage of 3.6V is reached. A voltage above 46
V at VIN shuts down the device. In order to prevent transient spikes from shutting down the device, the under
and overvoltage protection have filter times of 5 µs (typical). Overvoltage protection is is not supported in LPM.
When the voltages return to the normal operating region, the enabled regulators start including new soft-start
ramps.
Thermal Protection
The TPS43340-Q1 is protected from over-temperature using an internal thermal shutdown circuit. If the die
temperature exceeds the thermal shutdown threshold (e.g. due to fault conditions such as a short circuit at the
gate drivers or VREG), the device is turned off and restarted when the temperature has fallen by the hysteresis.
Table 1. Low Power Mode Operation of the System
QUIESCENT CURRENT
SETUP
SYNC
(TYP),
DESCRIPTION
NO LOAD, 25°C
BUCK1 or BUCK2 in LPM mode
BUCK1 and BUCK2 in LPM mode
BUCK1 or BUCK2 in PWM mode
BUCK1 and BUCK2 in PWM mode
LREG1
~30 µA
~35 µA
Configuration for Ignition off applications with
standby functionality
Low
~30-40 mA
~30-40 mA
~50 µA
Including switching currents
Including switching currents
High
N/A
Configuration for Ignition off applications with
standby functionality
LREG1 and BUCK1 or 2 in LPM mode
LREG1 and BUCK1 and 2 in LPM mode
LREG1 and BUCK1 or 2 in PWM mode
LREG1 and BUCK1 and 2 in PWM mode
~55 µA
Low
~60 µA
30-40 mA
30-40 mA
Including switching currents
Including switching currents
High
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The synchronous Buck Converter VBUCK3 with the integrated FETs does not support LPM. If VBUCK3 is turned
on the system will be forced to operate in normal mode and the quiescent current consumption will increase.
Table 2. Input Voltage and Low Power Mode Operation
BUCK
INPUT
LOAD
VIN QUIESCENT
CURRENT (TYP),
NO LOAD, 25°C
CHARGE PUMP
OF LREG1
CONTROLLER
VBUCK1 AND
VBUCK2
VOLTAGE AT CURRENT OF
DESCRIPTION
VIN PIN
LREG1
VIN > 9 V
N/A
OFF
OFF
ON
LPM allowed
LPM allowed
LPM allowed
55 µA
55 µA
Lowest current consumption of the
system at VIN (LREG1, VBUCK1&2
enabled), typ. ignition off stay alive mode
with up to 3 voltage rails active
< 2mA
> 6mA
7.5 V < VIN <
9 V
260 µA
If VIN drops below 7.5 V, the Buck
Controllers VBUCK1&2 will leave Low
Power Mode (LPM) and start PWM
operation, quiescent current of the
system will increase. For applications
that use the LREG1 only as standby
keep alive supply, quiescent current is
still low.
VIN < 7.5 V
N/A
ON
LPM not allowed
2.6 mA
The threshold for the charge pump of the low quiescent linear regulator LREG1 to be turned on is monitored at
the VIN pin. If LREG1 is used as post regulator with an input voltage VLR1 of less than 7.5 V, the charge pump
will still stay off as long as the required conditions for VIN and the load current are met. The sampling interval for
the above voltage thresholds at the VIN pin is typically 60 µs.
Phase Configuration
The IC is configured with Buck controller 1 and Buck controller switching 180 degrees out of phase. Buck
converter (Buck 3) switches in phase with Buck controller 1.
CONFIGURATION
VBUCK1
VBUCK2
VBUCK3
DESCRIPTION
Phase
0 deg
180 deg
0 deg
VBUCK1 and 2 out of phase, VBUCK 1
and 3 in phase
SYNCHRONOUS BUCK CONVERTER BUCK3
This regulator operates with the switching frequency set on the RT terminal or an external clock input on SYNC
terminal. The internal power FETs are switched out of phase to regulate the output voltage operating in a pulse
width modulation. The converter utilizes a peak current mode control loop with external frequency compensation.
The synchronous operation mode improves the overall efficiency.
Softstart and Foldback Functions
The converter soft start is set by a capacitor on the SS3 terminal and is activated when the enable pin on EN3 is
pulled high. During soft start or whenever the voltage on VSENSE3 falls below limits given by ƒSW-f-back the
converter will switch to frequency foldback of ƒsw/2 to help control the coil current. In addition to the frequency
foldback, the converter is protected against output short to ground by implementation of current fold back to
reduce power dissipation . Like in the BUCK controllers, the current foldback reduces the maximum peak current
limit depending on the voltage on the VSENSE3 pin. The characteristic of the current foldback is shown in
Figure 16.
Current Mode Control and Current Limit Protection
The coil peak current is measured using the high side integrated FET and is regulated in each switching cycle in
accordance to the voltage on the COMP3 pin. Similarly to BUCK controllers 1 and 2, COMP3 is an output of an
transconductance error amplifier of the voltage feedback loop and sets the target for the peak current comparator
(inner current loop). COMP3 is used for frequency compensation of the voltage loop utilizing a type II
compensation network.
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By clamping the voltage on the COMP3 node, the positive current limit is realized. The positive clamping level
depends on the voltage on the VSENSE3 pin, as described above. Clamping is also implemented for low voltage
on the COMP3 pin, which speeds up the transient response after output overshoot. The current limit set by
COMP3 is adjusted during the switching cycle by the internal slope compensation for stability of the current loop.
For correct operation of the slope compensation, the coil used for BUCK3 must satisfy the following:
LBUCK3 = 3.7/ƒsw
(6)
Where:
LBUCK3 is the inductance in Henry
ƒsw is the switching frequency in Hz
When the positive current limit is reached during the high PWM phase, PWM is reset. The high side FET is
turned off and the low part of the cycle is initiated. If an overcurrent condition is detected during the PWM low
phase, such as during an output short to a supply, the lowside FET is turned off till the end of the given cycle, to
allow the coil current to flow through the body diode of the high side FET.
Operation in Dropout and Undervoltage Protection
This converter is capable of operating with low input to output voltage difference. In dropout operation the
integrated high-side MOSFET stays on 100%. In every fourth clock cycle the duty cycle is limited to 95% in order
to charge the bootstrap capacitor at BOOT3. This allows a maximum duty cycle of 98.75% for the buck
converter. In this mode the output will track the input until the internal under voltage lock out is initiated due to
low supply voltage on the VSUP pin.
Thermal shutdown monitors the virtual junction temperature of the integrated FETs. When TJ = 170°C is
exceeded, both the high and low side switches are turned off. The converter will return to normal operation when
the temperature decreases to the acceptable level (typically TJ = 150°C)
Slew Rate Control (SLEW)
The slew for BUCK3 is set by digital setting on this terminal. Setting the slew rate to logic high (slowest slew
rate) extends the minimum on time of the BUCK converter by 5% of the clock period.
SLEW TERMINAL SETTING
tr (TYP) ns
tf (TYP) ns
Slew > VREG – 0.2 V (low slew
rate, logic high)
24
11
8
7
3
2
Slew pin open – medium slew rate
Slew < 0.2 V (fast slew rate, logic
low)
LINEAR REGULATOR (LREG1)
The linear regulator is an NMOS output low drop out regulator with output load current up to 300mA. It can be
operated directly from the battery. When EN4 is tied high or open, LREG1 will turn on its output following an
internally generated softstart ramp. The regulation loop uses internal frequency compensation. If the output is
shorted to ground the device will protect by limiting the current. For VIN lower than 9V then LREG1 will control
the internal charge pump depending on VIN and the load current in accordance with Table 2. An internal voltage
selector selects the higher available supply for the error amplifier between VIN and the charge pump voltage.
The output voltage of the low-dropout regulator is monitored for undervoltage and its state is signaled on pin
RST4.
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TYPICAL CHARACTERISTICS
BUCK2 EFFICIENCY
vs
BUCK3 EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
VOUT = 3.3 V, VIN = 5V, continuous mode
VIN = 14 V, VOUT = 3.3 V, VSUP = 4 V, 400 kHz 25°C
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
high
30
low
20
10
0
1
10
100
1000
10000
0
500
1000
1500
2000
2500
OUTPUT CURRENT (mA)
CURRENT (mA)
Figure 8.
Figure 9.
VIN SHUTDOWN CURRENT
REGULATED VSENSEx VOLTAGE
vs
vs
VIN
TEMPERATURE (BUCK1/2)
60
805
804
803
802
801
800
799
798
797
796
795
50
40
30
20
10
0
-5
5
10
15
20
25
30
35
-40 -15 10
35
60
85 110 135 160
VIN (V)
TEMPERATURE (°C)
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
BUCK1/2 LOAD STEP: LOW POWER MODE ENTRY
BUCK1/2 LOAD STEP: LOW POWER MODE EXIT
(0.09 mA TO 4 A AT 2.5 A/µs)
(0.09 mA TO 4 A AT 2.5 A/µs)
VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400
kHz
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400
kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mΩ
INDUCTOR = 4.7 µH, RSENSE = 10 mΩ
100mV/DIV
100mV/DIV
VOUT AC-COUPLED
VOUT AC-COUPLED
2A/DIV
IIND
2A/DIV
IIND
50µs/DIV
50µs/DIV
Figure 12.
Figure 13.
INDUCTOR CURRENTS (BUCK1/2)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mΩ
FORCED CONTINUOUS MODE (SYNC=1), 200mA LOAD
1A/DIV
DISCONTINUOUS MODE (SYNC=0), 200mA LOAD
1A/DIV
1A/DIV
LOW POWER MODE (SYNC=0), 20mA LOAD
2µs/DIV
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
f
FOLDBACK CURRENT LIMIT (BUCK1/2)
FOLDBACK CURRENT LIMIT (BUCK3)
80
70
60
50
40
30
20
3.5
3
2.5
2
1.5
1
0.5
0
10
0
0
0.2
0.4
0.6
0.8
0
0.2
0.4
0.6
0.8
1
VSENSEx VOLTAGE (V)
VSENSE (V)
Figure 15.
Figure 16.
GPULL VOLTAGE
vs
CURRENT SENSE PINS INPUT CURRENT (BUCK1/2)
VIN
45
40
35
30
25
20
15
10
5
0.9
0.8
150°C
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
25°C
-0.1
-0.2
-0.3
0
0
10
20
30
40
50
60
70
0
1
2
3
4
5
6
7
8
9
10 11 12
VIN (V)
OUTPUT VOLTAGE (V)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
BUCK3 MAX PEAK INDUCTOR CURRENT
vs
CURRENT LIMIT
vs
DUTY CYCLE
VSUP = 4/5/6 V, SWITCHING FREQUENCY = 400 kHz,
DUTY CYCLE (BUCK1/2)
INDUCTOR = 10 µH, VSENSE3 = 0.75 V
3.5
80
3
70
60
50
40
30
20
10
0
4V
2.5
VIN = 8V
5V
6V
2
1.5
VIN = 12V
1
0.5
0
0
20%
40%
60%
80%
100%
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
DUTY CYCLE
Figure 19.
Figure 20.
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APPLICATION INFORMATION
High- and Low-Side Power NMOS Selection for the BUCK Converters
The gate drive supply for these MOSFET is supplied by an internal supply which is 5.8 V typical under normal
operating conditions. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output
current of 0.6 A. The high-side MOSFET is referenced to the phase terminal (PHx) and the low-side MOSFET is
referenced to power ground (PGNDx) terminal. For a particular applications these MOSFETs should be selected
with consideration for the following parameters RDS(ON), gate charge Qg, drain to source breakdown voltage
BVDSS, Maximum DC current IDC(max) and thermal resistance for the package.
Power dissipation on the High-side FET (PD_HS):
æ
ç
ç
ö
V x IO
(IO )2 x RDS(on)(1 + TC) x D +
÷ x t + t x f
( )
f
I
÷
r
SW
÷
ç
è
÷
2
ø
(7)
(8)
First term is conduction losses
Second term is switching losses
Power dissipation on the Low-side FET (PD_LS):
(IO )2 x RDS(on)(1 + TC) x 1 - D + V x I (tdead ) x fSW
(
)
f
O
First term is conduction losses
Second term is switching losses FET body diode losses during deadtime
NOTE: The RDS(ON), has a positive temperature coefficient TC which is typically 0.4%/°C
Gate losses for highside and lowside FETs:
PBUCKx GATE = 2 x fsw x Qg x VVREG
(9)
Design Guide - Step-by-Step Design Procedure
The following example illustrates the design process and component selection for the TPS43340-Q1. The design
goal parameters are given in Table 3.
Table 3.
PARAMETER
BUCK1
BUCK2
BUCK3
6 V to 18 V
14 V - typ
6 V to 18 V
14 V - typ
4 V to 10 V
5 V - typ
Input voltage, VI
Output ripple voltage
Output voltage, VO
±0.2 V
5 V ±2%
4.5 A
±0.2 V
3.3 V ±2%
4.5 A
±0.1 V
1.8 V ±2%
2.2 A
Max - output current, IO
Min – output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
0.1 A
0.1 A
0.1 A
±0.2 V
±0.2 V
±0.75 V
0.1 A to 4.5 A
0.1 A to 4.5 A
0.1 A to 2.2 A
Converter switching frequency,
fSW
400 kHz
125°C
400 kHz
125°C
400 kHz
125°C
Junction Temperature, TJ
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Power Switch
6 V to 18V
Main Supply
(PMOS
)
TOP _SW
3
10 k
80. 6k
3.3V, 1W
2k
0.1uf
10 k
10uf
LREG
1
VIN or other supply connect to
VIN2SENSE via 10k resistor
48
47
46
45
44
43
42
41
40
39
38
37
TOP _SW 2
GU 2 36
VIN 0.1uf
3.3V, 6.6W
L2
0 .03
PH 2 35
GL 2 34
VReg 2
100 uf
TOP _SW
1
1
2
GU 1
PH 1
22 uH
5V, 15W
VReg 1
L 1
BOT _SW 2
C BUCK
2
0.02
PGND
2
33
32
15uH
100 uf
C BUCK
3
4
GL 1
BOT _SW
1
S4
1
PGND
1
S3 31
255
k
VSENSE
COMP
2
2
30
29
330 pf
5
6
S2
S1
VSENSE
422 k
TPS43340-Q1
7 .87k
80.6 k
8200 pf
2K
7
8
1
28
RST 2
330 pf
11 k
80.5 k
SS 2 27
26
COMP
1
0.01 uf
5600 pf
GND
2k
9
RST 1
SS 1
RT 25
10
0.01 uf
100
k
11
12
VSUP
PGND
VReg 1 Input supply
10 uf
3
14
20
21
22
24
13
15
16
17
18
19
23
1.8V, 1.8W
VReg 3
15 uH
L3
0.01 uf
0.01 uf
0.01 uf
2 k
0 .1uf
10 k
10 k
10 k
8. 1k
100 uf
C BUCK
3
102
k
80.6k
Optional
Clock Input
L1, L2, L3: DR127-8R2-R (Coiltronics)
TOP_SW3: IRF7663TRPBF (International Rectifier)
TOP_SW1, BOT_SW2: Si4946BEY-T1-E3 (Vishay)
TOP_SW2, BOT_SW2: Si4946BEY-T1-E3 (Vishay)
CBUCK1, CBUCK2, CBUCK3:AVX- TPSD107K016R0060 (AVX)
Figure 21. Application Schematic
Buck1 Component Selection
Duty Cycle
5
D =
= 0.357
14
(10)
(11)
Selection of Current Sensing Resistor
0.075 V
RSENSE
=
= 0.017 W
4.5 A
Use 10 mΩ to allow for ripple-current.
Inductor Selection L
0.01 W
L = 200 x
= 5 mH
400 kHz
(12)
Use 8.2 µH.
Inductor Ripple Current
æ
ö
÷
÷
5 V
5 V
ç
x 1 -
ç
DILRIPPLE
=
= 0.98 A
÷
ø
ç
è
400 kHz x 8.2 mH
14 V
(13)
(14)
Output Capacitor CO
2 x 4.5 A
CO
=
= 112 mF
400 kHz x 0.2 V
Use 100 µF.
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Input Capacitor CI
0.25 x 4.5 A
CI =
= 5.6 mF
400 kHz x 0.5 V
(15)
Use 10 µF, shared between Buck1 and Buck2.
High-Side MOSFET (TOP_SW1)
æ
ö
÷
÷
14 V x 4.5 A
2
(4.5 A) x 0.009 x (1 + 0.4) x 0.357 +
ç
x 20 ns + 20 ns x 400 kHz = 0.59 W
( )
ç
÷
ø
ç
è
2
(16)
(17)
Low-Side MOSFET (BOT_SW1)
(4.5 A)2 x 0.009 x (1 + 0.4) x 1 - 0.357) + 0.6 V x 4.5 A x 2 x 20 ns x 400 kHz = 0.21 W
(
)
Buck2 Component Selection
Duty Cycle
3.3
D =
= 0.236
14
(18)
(19)
Selection of Current Sensing Resistor
0.075 V
RSENSE
=
= 0.017 W
4.5 A
Use 10 mΩ to allow for ripple-current.
Inductor Selection L
0.01 W
L = 200 x
= 5 mH
400 kHz
(20)
Use 8.2 uH.
Inductor Ripple Current
æ
ö
÷
÷
3.3 V
3.3 V
14 V
ç
x 1 -
ç
DILRIPPLE
=
= 0.77 A
÷
ø
ç
è
400 kHz x 8.2 mH
(21)
(22)
Output Capacitor CO
2 x 4.5 A
CO
=
= 112 mF
400 kHz x 0.2 V
Use 100 µF.
Input Capacitor CI
0.25 x 4.5 A
400 kHz x 0.5 V
CI =
= 5.6 mF
(23)
Use 10 µF, shared between Buck1 and Buck2.
High-Side MOSFET (TOP_SW2)
æ
ö
14 V x 4.5 A
2
2
(4.5 A) x 0.009 x (1 + 0.4) x 0.236 +
÷
ç
x 20 ns + 20 ns x 400 kHz = 0.56 W
( )
÷
ç
÷
ç
è
ø
(24)
(25)
Low-Side MOSFET (BOT_SW2)
(4.5 A)2 x 0.009 x (1 + 0.4) x 1 - 0.236) + 0.6 V x 4.5A x 2 x 20 ns x 400 kHz = 0.24 W
(
)
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Buck3 Component Selection
Duty Cycle
1.8
D =
= 0.36
5
(26)
(27)
Inductor Selection LBUCK3
3.7 W
LBUCK3
=
= 9.25 mH
400 kHz
Use 8.2 µH.
Inductor Ripple Current
æ
ö
÷
÷
1.8 V
1.8 V
5 V
ç
x 1 -
ç
DILRIPPLE
=
= 0.46 A
÷
ø
ç
è
400 kHz x 8.2 mH
(28)
(29)
Output Capacitor CO
2 x 4.6 A
CO
=
= 30.7 mF
400 kHz x 0.075 V
Use 100 µF.
Input Capacitor CI
0.25 x 2.2 A
CI =
= 5.76 mF
400 kHz x 0.05 V
(30)
Use 10 µF.
Internal High-Side MOSFET
æ
ö
÷
÷
ø
5 V x 2.2 A
2
(2.2 A) x 0.28W x 0.36 +
ç
x 20 ns + 20 ns x 400 kHz = 0.58 W
( )
÷
ç
ç
è
2
(31)
(32)
Internal Low-Side MOSFET
(2.2 A)2 x 0.28W x (1 - 0.36) 0.6 x 2.2 A x 2 x 20 ns x 400 kHz = 0.89 W
(
)
Power Dissipation
The power dissipation is dependent on the MOSFET drive current and input voltage. The drive current is
proportional to the total gate charge of the external MOSFET.
Power Dissipation BUCK1 and BUCK2 (VBUCK1 and VBUCK2)
PGate drive = Qg x VVREG x fsw (Watts)
(33)
Assuming both high and low side MOSFETs are identical in a synchronous configuration, the total power
dissipation per BUCK is
PBUCK1 = 2 x Qg x fsw x VVREG (Watts)
Power Dissipation of the Buck Converter (VBUCK3)
High-Side Switch
(34)
The power dissipation losses are applicable for positive output currents:
PHS-CON = IOUTr2 x RDS(on) x (VOUT/VIN) (Conduction losses)
PHS_SW = ½ x VSUP x Iout x (tr + tf) x fSW (Switching losses)
PHS_Gate = 1nC x fsw (Gate drive losses, valid at VVREG = 5.8V, VSUP = 4V)
PHS_Total = PHS-CON + PH_SW + PHS_Gate
(35)
(36)
(37)
(38)
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Low-Side Switch
The power dissipation losses are applicable for positive output currents.
PLS-CON = IOUTr2 x RDS(on) x ( 1 - VOUT/VIN) (Conduction losses)
PLS_SW = ½ x VSUP x IO x (tr + tf) x fSW (Switching losses)
(39)
(40)
(41)
(42)
(43)
PLS_Gate = 1 nC x fsw (Gate drive losses, valid at VVREG = 5.8V, VSUP = 4V))
PLS_DIODE = 2 x Vf x Io x fsw x tdead (low side body diode losses during dead time)
PLS_Total = PLS-CON + PL_SW + PLS_Gate + PLS_DIODE
Linear Regulator (LREG1)
PLREG1 = (VVLR1 – VLREG1) x IOUT
(44)
Where
VOUT = Output voltage, VIN = Input voltage
IOUT = Output current, fsw = Switching frequency
tr = rise time of switching node PH3
tf = fall time of switching node PH3
VVREG = FET gate drive voltage
Vf_diode = Low side FET diode drop (conduction during dead time)
IC Power Consumption
PIC = Iq x VIN (Watts)
(45)
(46)
PTotal = PBUCK1 and BUCK2 + PHS_Total + PLS_Total + PLREG1+ PIC (Watts)
(1)(2)
Table 4.
BUCK 1 AND BUCK 2
BUCK 3
COMMENTS
Duty cycle D
Buck 3 will be powered from Buck 1 or Buck 2
VO
VO
D =
D =
VI
VI
Current limit sense
resistor RS
Choose current limit of 25% more than max load
0.075
1.25 x IOmax
RS
=
Not Applicable
Inductor selection L
Rs is chosen based on current limit set for the
application.
200
3.7
L =
x RS
L =
fSW
f
SW
æ
ö
æ
ö
VO
VO
VO
VO
Inductor ripple current
Output Capacitor Co
Typically the ± inductor ripple current is 25% of max
load current
÷
÷
÷
÷
ø
÷
÷
÷
÷
ø
ç
ç
DILRIPPLE
=
x
1 -
DILRIPPLE
=
x 1 -
ç
ç
ç
ç
ç
ç
fSW x L
V
fSW x L
V
è
è
I
I
DIO
DIO
Also consider the ESR of the output capacitor
influences output voltage ripple due to load steps
CO
=
CO =
4 x GBW x ΔVO
4 x GBW x ΔVO
Input Capacitor CIN
Based Input capacitor value on input voltage ripple
desired
0.25 x DIO MAX
0.25 x DIO MAX
CIN
=
CIN =
fSW x ΔV
fSW x ΔV
I
I
Soft Start CSS
Chose the soft start time required ∆t and then
calculate Css
1 mA x Dt
1 mA x Dt
CSS
=
CSS
=
0.8
Qg
0.8
Qg
Bootstrap capacitor CBoot
Chose based on the desired amount of ripple based
on FET gate charge and operating Vin
CBOOT
=
CBOOT
=
DV
DV
Compensation Resistor
for GBW
GBW x 2 p x CO
gm x KCFB x b
GBW x 2 p x CO To determine resistor R3 assume GBW ≈ fsw/5 to
R3 =
R3 =
fsw/20
gm x Gm3 x b
1
1
Compensation Capacitor
for zero
C1 can be also increased 2x for faster small signal
settling at expense of large step response (slew rate
on COMPx).
C1 =
C1 =
2 p x R3 x 0.1 x GBW
2 p x R3 x 0.1 x GBW
(1) KCFB= 0.125/RSENSE
(2) ß= VREF/VOUT
30
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SLVSB16B –NOVEMBER 2011–REVISED APRIL 2012
Table 4. (1)(2) (continued)
BUCK 1 AND BUCK 2
BUCK 3
COMMENTS
Compensation Capacitor
for second pole
The value of C2 is also critical for buffering the noise
on COMPx pin and so the value of capacitance is a
trade off between noise immunity and phase margin.
1
1
C2 =
C2 =
p x fSW x R3
p x fSW x R3
1
1
Pole at low frequency with
high DC gain
ROUT_OTA = 1MΩ min
fP1
=
fP1 =
2 p x C1 x ROUT_OTA
2 p x C1 x ROUT_OTA
Zero at Control loop pole
related to Output filter LC
Place zero at 0.05...0.1 * GBW (see comment on C1
above).
1
1
fZ1
=
fZ1 =
2 p x C1 x R3
1
2 p x C1 x R3
1
Second pole for type 2a
Place second pole at or below half switching
frequency ƒsw observing distance to GBW.
fPZ
=
fPZ =
2 p x C2 x R3
2 p x C2 x R3
Power Dissipation De-Rate Profile 32 pin HTTSOP Package with PowerPAD
3
2
1
25
50
75
100
125
150
Ambient Temperature (C)
Figure 22. Power dissipation de rating profile based on high K Jedec PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
1. Connect the drain of TOP_SW1 and TOP_SW2 together with +ve terminal of the input capacitor COUT1. The
trace length between these terminals should be short.
2. The Kelvin current sensing for the shunt resistor should have minimum trace spacing and routed together.
Any filtering capacitors for noise should be placed near the IC pins.
3. The resistor divider for sensing output voltage is connected between the +ve terminal of the respective
output capacitor CBUCK1 or CBUCK2 or CBUCK3 and the IC signal ground. These components and the traces
should not be routed near any switching nodes or high current traces.
Other Considerations
1. Separate IC signal ground and power ground terminals (GND and PGNDx) pins. Use a star ground
configuration if connecting to non ground plane system. Use tie-ins for EXTSUP capacitor, compensation
network ground and voltage sense feedback ground networks to this start ground
2. Connect compensation network between compensation pins and IC signal ground. Connect the oscillator
resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits should NOT be
located near the dv/dt nodes; these include the gate drive outputs, phase pins and boost circuits (bootstrap).
3. Reduce the surface area of the high current carrying loops to a minimum, by ensuring optimal component
placement. Ensure the bypass capacitors are located as close as possible to their respective power and
ground pins.
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PCB Layout
Main Input Supply
TOP _ SW 3
Power Switch
(PMOS
)
1 kW
10 kW
LREG 1_ Enable
LREG 1_Output
48
47
46
45
44
43
42
41
40
39
37
38
TOP _SW
L2
2
TOP _SW
L1
1
1
GU 2
GU 1
PH 1
36
35
VReg 2_Output
VReg 1_Output
2
PH 2
GL 2
TPS43340-Q1
Thermal Vias use TI recommendation
for implementation
BOT _SW 2
3
4
5
6
7
8
9
GL 1
PGND
S2
34
33
32
31
BOT _SW 1
1
PGND 2
S4
S1
S3
VSENSE
1
VSENSE
COMP
2
2
30
29
COMP
RST 1
1
RST 2 28
Exposed PAD Connected to Ground Plane for
VReg 1
Input supply
27
26
25
10 SS1
SS 2
GND
RT
electrical ground connection and thermal conduction
11 VSUP
PGND
3
12
13
14
15
16
17
18
19
20
21
22
23
24
VReg 3
10 k
10 k
10 k
L3
Connection to backside of PCB through vias
Connection to topside of PCB through vias
Connection to ground plane of PCB through vias
Power bus
Voltage Output rails
Ground termination to ground plane or small
signal ground termination
SPACER
REVISION HISTORY
Changes from Revision A (January 2012) to Revision B
Page
•
•
•
•
Changed Feedback input to Supply sense input in Abs Max Ratings table. ........................................................................ 3
Inserted Input voltage for Buck 2 information in the Recommended Operating Conditions table. ....................................... 4
Added VIN2SENSE = 4V to 40V in Electrical Characteristics table header. ........................................................................ 5
Changed Iq_LPM to Iq, changed LPM quiescent current to Quiescent current, and changed the conditions for EN in
the Electrical Characteristics table. ....................................................................................................................................... 5
•
•
•
Added VIN2SENSE = 4V to 40V in Electrical Characteristics table header. ........................................................................ 6
Added VIN2SENSE = 4V to 40V in Electrical Characteristics table header. ........................................................................ 7
Added VIN2SENSE = 4V to 40V in Electrical Characteristics table header. ........................................................................ 8
32
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS43340QPHPQ1
TPS43340QPHPRQ1
PREVIEW
ACTIVE
HTQFP
HTQFP
PHP
PHP
48
48
250
TBD
Call TI
Call TI
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS43340QPHPRQ1
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PHP 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
TPS43340QPHPRQ1
1000
Pack Materials-Page 2
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相关型号：
TPS43351QDAPQ1
IC 0.4 A DUAL SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO38, PLASTIC, HTSSOP-38, Switching Regulator or Controller
TI
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