TPS43350-Q1_15 [TI]
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLER;
| 型号： | TPS43350-Q1_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLER |
| 文件： | 总33页 (文件大小：1408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS43350-Q1
TPS43351-Q1
www.ti.com
SLVSAR7D –JUNE 2011–REVISED APRIL 2013
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS43350-Q1, TPS43351-Q1
1
FEATURES
2
•
Qualified for Automotive Applications
•
•
Frequency Spread Spectrum (TPS43351-Q1)
•
AEC-Q100 Test Guidance With the Following
Results:
Selectable Forced Continuous Mode or
Automatic Low-Power Mode at Light Loads
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
•
•
Sense Resistor or Inductor DCR Sensing
Out-of-Phase Switching Between Buck
Channels
–
–
Device HBM ESD Classification Level H2
Device HBM CDM Classification Level C2
•
•
Peak Gate Drive Current 1.5 A
•
•
•
Two Synchronous Buck Controllers
Thermally Enhanced, 38-Pin HTSSOP (DAP)
PowerPAD™ Package
Input Range up to 40 V, (Transients up to 60 V)
Low-Power Mode IQ: 30 µA (One Buck On),
35 µA (Two Bucks On)
APPLICATIONS
•
Automotive Infotainment, Navigation, and
Instrument Cluster Systems
•
•
•
Low Shutdown Current Ish < 4 µA
Buck Output Range 0.9 V to 11 V
•
Industrial or Automotive Multi-Rail DC Power
Distribution Systems and Electronic Control
Units
Programmable Frequency and External
Synchronization Range 150 kHz to 600 kHz
•
Separate Enable Inputs (ENA, ENB)
DESCRIPTION
The TPS43350-Q1 and TPS43351-Q1 include two current-mode synchronous buck controllers designed for the
harsh environment in automotive applications. The devices are ideal for use in a multi-rail system with low
quiescent requirements, as they automatically operate in low-power mode (consuming only 30 µA) at light loads.
The devices offer protection features such as thermal, soft-start, and overcurrent protection. During short-circuit
conditions of the regulator output, activation of the current-foldback feature can limit the current through the
MOSFETs for control of power dissipation. The two independent soft-start inputs allow ramp-up of the output
voltage independently during start-up.
The programmable range of the switching frequency is from 150 kHz to 600 kHz, as is the frequency of an
external clock to which the devices can synchronize. Additionally, the TPS43351-Q1 offers frequency-hopping
spread-spectrum operation.
spacer
VBAT
Reverse
Battery
MOSFET
Control
VBuckA
Internal
VREG
BuckA
RCOSC
External
Sync
SYNC
ENA
ENB
SSA
Buck
Enable
VBuckB
SSB
BuckB
SoftStart
DLYAB
Figure 1. Typical Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TPS43350-Q1
TPS43351-Q1
SLVSAR7D –JUNE 2011–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE AND ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.7
–1
MAX UNIT
Voltage
Input voltage: VBAT
60
0.3
60
V
V
Ground: PGNDA–AGND, PGNDB–AGND
Enable inputs: ENA, ENB
V
Bootstrap inputs: CBA, CBB
68
V
Bootstrap inputs: CBA–PHA, CBB–PHB
Phase inputs: PHA, PHB
8.8
60
V
V
Phase inputs: PHA, PHB (for 150 ns)
Feedback inputs: FBA, FBB
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
13
13
V
Voltage
(Buck function:
BuckA and BuckB)
Error amplifier outputs: COMPA, COMPB
High-side MOSFET driver: GA1–PHA, GB1–PHB
Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB
Current-sense voltage: SA1, SA2, SB1, SB2
Soft start: SSA, SSB
V
8.8
8.8
13
V
V
V
13
V
Power-good output: PGA, PGB
Power-good delay: DLYAB
13
V
13
V
Switching-frequency timing resistor: RT
SYNC, EXTSUP
13
V
13
V
P-channel MOSFET driver: GC2
P-channel MOSFET driver: -GC2
Gate-driver supply: VREG
60
V
Voltage
(PMOS driver)
8.8
8.8
150
125
165
V
V
Junction temperature: TJ
°C
°C
°C
Temperature
Operating temperature: TA
–40
Storage temperature: Tstg
–55
Human-body model (HBM) AEC-
Q100 Classification Level H2
±2
kV
FBA, FBB, RT, DLYAB
±400
±750
±500
±150
±200
Charged-device model (CDM)
AEC-Q100 Classification Level C2
Electrostatic
VBAT, SYNC,
discharge ratings
All other pins
V
PGA, PGB
Machine model (MM)
All other pins
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to AGND, unless otherwise stated.
2
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Product Folder Links: TPS43350-Q1 TPS43351-Q1
TPS43350-Q1
TPS43351-Q1
www.ti.com
SLVSAR7D –JUNE 2011–REVISED APRIL 2013
THERMAL INFORMATION
TPS4335x-Q1
THERMAL METRIC(1)
DAP
38 PINS
27.3
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
19.6
15.9
°C/W
ψJT
0.24
ψJB
6.6
θJCbot
1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN
4
MAX
40
UNIT
V
Input voltage: , VBAT
Enable inputs: ENA, ENB
Boot inputs: CBA, CBB
0
40
V
4
48
V
Buck function:
BuckA and BuckB
voltage
Phase inputs: PHA, PHB
Current-sense voltage: SA1, SA2, SB1, SB2
Power-good output: PGA, PGB
SYNC, EXTSUP
–0.6
0
40
V
11
V
0
11
V
0
9
V
Operating temperature: TA
–40
125
°C
Copyright © 2011–2013, Texas Instruments Incorporated
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SLVSAR7D –JUNE 2011–REVISED APRIL 2013
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DC ELECTRICAL CHARACTERISTICS
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
1.0
1.1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply
VBat
Supply voltage
After initial start-up, condition is satisfied.
4
40
40
V
V
Input voltage required for device
on initial start-up
6.5
1.2
1.3
VIN
Buck regulator operating range
after initial start-up
4
40
3.8
4
V
V
V
VIN falling. After a reset, initial start-up conditions
may apply.(1)
3.5
3.6
3.8
VIN UV
Buck undervoltage lockout
VIN rising. After a reset, initial start-up conditions
may apply.(1)
VIN = 13 V, BuckA: LPM, BuckB: off
VIN = 13 V, BuckB: LPM, BuckA: off
VIN = 13 V, BuckA, B: LPM
30
35
40
45
40
45
50
55
µA
µA
µA
µA
LPM quiescent current:
TA = 25°C(2)
1.5
1.6
Iq_LPM_
VIN = 13 V, BuckA: LPM, BuckB: off
VIN = 13 V, BuckB: LPM, BuckA: off
VIN = 13 V, BuckA, B: LPM
LPM quiescent current:
TA = 125°C(2)
Iq_LPM
Normal operation, SYNC = High
VIN = 13 V, BuckA: CCM, BuckB: off
VIN = 13 V, BuckB: CCM, BuckA: off
VIN = 13 V, BuckA, B: CCM
4.85
7
5.3
7.6
5.5
mA
mA
mA
Quiescent current:
TA = 25°C(2)
1.7
1.8
Iq_NRM
Normal operation, SYNC = High
VIN = 13 V, BuckA: CCM, BuckB: off
VIN = 13 V, BuckB: CCM, BuckA: off
VIN = 13 V, BuckA, B: CCM
5
Quiescent current:
TA = 125°C(2)
Iq_NRM
7.5
2.5
8
4
mA
µA
1.9
2.0
IBAT_sh
Shutdown current
BuckA, B: off, VBAT = 13 V
Input Voltage - Overvoltage Lockout
VIN rising
VIN falling
45
43
1
46
44
2
47
45
3
V
V
2.1
VOVLO
Overvoltage shutdown
2.2
2.3
OVLOHys
OVLOfilter
Hysteresis
Filter time
V
5
µs
Gate Driver for PMOS
3.1
3.2
3.3
4.0
4.1
rDS(on)
PMOS OFF
10
5
20
10
Ω
mA
µs
IPMOS_ON
tdelay_ON
Gate current
Turnon delay
VIN = 13.5 V, VGS = –5 V
C = 10 nF
10
Buck Controllers
VBuckA/B
Adjustable output voltage range
0.9
0.792
–1%
11
0.808
1%
V
V
Measure FBX pin
Measure FBX pin
0.8
0.8
Internal reference voltage and
tolerance in normal mode
4.2
4.3
VREF, NRM
0.784
–2%
0.816
2%
V
Internal reference voltage and
tolerance in low-power mode
VREF, LPM
V sense for forward current limit in
CCM
4.4
4.5
FBx = 0.75 V (low duty cycles)
60
75
90
mV
mV
VSENSE
V sense for reverse current limit in
CCM
FBx = 1 V
FBx = 0 V
–65
17
–37.5
–23
48
4.6
4.7
VI-Foldback
tdead
V sense for output short
32.5
100
100
mV
ns
Shoot-through delay, blanking time
High-side minimum on-time
ns
4.8
4.9
DCNRM
DCLPM
Maximum duty cycle (digitally
controlled)
98.75%
Duty cycle LPM
80%
(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
(2) Quiescent current specification is non-switching current consumption without including the current in the external feedback resistor
divider.
4
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SLVSAR7D –JUNE 2011–REVISED APRIL 2013
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LPM entry threshold load current
as fraction of maximum set load
current
(3)
ILPM_Entry
1%
.
The exit threshold is specified to be always higher
than entry threshold
4.10
LPM exit threshold load current as
fraction of maximum set load
current
(3)
ILPM_Exit
10%
1.5
High-Side External NMOS Gate Drivers for Buck Controller
4.11
4.12
IGX1_peak
rDS(on)
Gate driver peak current
Source and sink driver
A
VREG = 5.8 V, IGX1 current = 200 mA
VREG = 5.8 V, IGX2 current = 200 mA
2
2
Ω
Low-Side NMOS Gate Drivers for Buck Controller
4.13
4.14
IGX2_peak
rDS(on)
Gate-driver peak current
Source and sink driver
1.5
A
Ω
Error Amplifier (OTA) for Buck Converters
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
4.15
GmBUCK
Transconductance
0.72
50
1
1.35
200
mS
nA
4.16
5.0
5.1
5.2
5.3
IPULLUP_FBx
Pullup current at FBx pins
FBx = 0 V
100
Digital Inputs: ENA, ENB, SYNC
VIH
Higher threshold
Lower threshold
Resistance
VIN = 13 V
VIN = 13 V
VSYNC = 5 V
1.7
V
V
VIL
0.7
2
RIH_SYNC
500
0.5
kΩ
Pullup current source on ENA,
ENB
5.5
IIL_ENx
VENx = 0 V
µA
6.0
6.1
6.2
Switching Parameters – Buck DC-DC Controllers
fSW_Buck
fSW_Buck
Buck switching frequency
Buck switching frequency
RT pin: GND
360
360
400
400
440
440
kHz
kHz
RT pin: 60-kΩ external resistor
Buck adjustable range with
external resistor
6.3
fSW_adj
RT pin: external resistor
150
150
600
600
kHz
kHz
6.4
6.5
7.0
fSYNC
fSS
Buck synchronization range
Spread-spectrum spreading
External clock input
TPS43351-Q1 only
5%
Internal Gate-Driver Supply
Internal regulated supply
VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High
5.5
7.2
5.8
0.2%
7.5
6.1
1%
7.8
1%
V
V
7.1
VREG
IVREG = 0 mA to 100 mA, EXTSUP = 0 V,
SYNC = High
Load regulation
Internal regulated supply
Load regulation
EXTSUP = 8.5 V
7.2
7.3
VREG(EXTSUP)
IEXTSUP = 0 mA to 125 mA, SYNC = High
EXTSUP = 8.5 V to 13 V
0.2%
EXTSUP switch-over voltage
threshold
IVREG = 0 mA to 100 mA ,
EXTSUP ramping positive
VEXTSUP_th
4.4
4.6
4.8
V
7.4
7.5
VEXTSUP-Hys
IREG-Limit
EXTSUP switch-over hysteresis
Current limit on VREG
150
100
250
400
mV
mA
EXTSUP = 0 V, normal mode as well as LPM
IREG_EXTSUP-
Current limit on VREG when using IVREG = 0 mA to 100 mA,
7.6
125
400
mA
EXTSUP
EXTSUP = 8.5 V, SYNC = High
Limit
8.0
8.1
Soft Start
ISSx
Soft-start source current
Oscillator reference voltage
SSA and SSB = 0 V
0.75
1
1.25
µA
V
9.0
Oscillator (RT)
VRT
9.1
1.2
10.0
10.1
10.2
10.3
10.4
10.5
10.6
Power-Good / Delay
PGpullup
PGth1
Pullup for A and B to Sx2
50
–7%
2%
kΩ
Power-good threshold
Hysteresis
FBx falling
–5%
–9%
PGhys
PGdrop
Voltage drop
IPGA = 5 mA
450
100
1
mV
mV
µA
IPGA = 1 mA
PGleak
Leakage
VSx2 = VPGx = 13 V
(3) The exit threshold specification is to be always higher than the entry threshold.
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DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.7
tdeglitch
tdelay
tdelay_fix
IOH
Power-good deglitch time
2
16
µs
External capacitor = 1 nF
VBuckX < PGth1
10.8
10.9
Reset delay
1
20
40
ms
µs
Fixed reset delay
No external capacitor, pin open
50
50
Activate current source (current to
charge external capacitor)
10.10
30
30
µA
Activate current sink (current to
discharge external capacitor)
10.11
11.0
11.1
11.2
IIL
40
50
µA
Overtemperature Protection
Junction temperature shutdown
Tshutdown
150
165
15
°C
°C
threshold
Thys
Junction temperature hysteresis
6
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SLVSAR7D –JUNE 2011–REVISED APRIL 2013
DEVICE INFORMATION
DAP Package
(Top View)
1
VIN
VBAT
NC
38
EXTSUP
NC
2
3
37
36
NC
4
5
35
34
VREG
CBB
GC2
CBA
GA1
GB1
6
33
PHB
PHA
GA2
7
8
9
32
31
30
GB2
PGNDB
SB1
PGNDA
SA1
10
29
SB2
SA2
11
12
28
27
FBB
FBA
COMPB
SSB
COMPA
SSA
13
14
15
26
25
24
PGB
PGA
ENA
ENB
NC
16
23
AGND
RT
17
18
22
21
DLYAB
SYNC
AGND
19
20
PIN FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
19,
23
AGND
O
Analog ground reference
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBA
5
I
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
13
Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckA. Clamping his voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPA
O
Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckB. Clamping his voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPB
DLYAB
ENA
26
21
16
O
O
I
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-
good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current.
Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current.
ENB
17
37
12
27
I
I
I
I
One can use EXTSUP to supply the VREG regulator from one of the TPS43350-Q1 or TPS43351-Q1 buck
regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is
unused, leave the pin open without a capacitor installed.
EXTSUP
FBA
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
FBB
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PIN FUNCTIONS (continued)
NAME
GA1
NO.
I/O
DESCRIPTION
This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides
high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that
has a voltage swing provided by CBA.
6
O
This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides
high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GA2
GB1
GB2
GC2
8
33
31
4
O
O
O
O
This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides
high peak currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHB that
has a voltage swing provided by CBB.
This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides
high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can
bypass the boost rectifier diode or a reverse-protection diode when the boost is not switching or if boost is
disabled, and thus reduce power losses.
2, 3,
18,
36
NC
–
No connection
PGNDA
PGNDB
9
O
O
Power ground connection to the source of the low-side N-channel MOSFETs of BuckA.
Power ground connection to the source of the low-side N-channel MOSFETs of BuckB
30
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value.
PGA
PGB
PHA
PHB
15
24
7
O
O
O
O
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value.
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
32
Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost
controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz
for the boost controller.
RT
22
O
SA1
SA2
SB1
SB2
10
11
29
28
I
I
I
I
High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SA1 positive node, SA2 negative node).
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SB1 positive node, SB2 negative node).
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
SSA
SSB
14
25
O
O
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of
0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock.
This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits
transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power
mode at light loads. On the TPS43351-Q1, a high level enables frequency-hopping spread spectrum, whereas an
open or a low level disables it.
SYNC
20
I
VBAT
VIN
1
I
I
Supply pin
Main input pin. This is the buck controller input pin. Additionally, it powers the internal control circuits of the
device.
38
The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck
and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtain its power from
either or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
VREG
35
O
8
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Internal ref (Band gap)
Gate Driver Supply
38
1
5
6
7
8
9
VIN
CBA
GA1
VBAT
PWM logic
PHA
VREG
37
35
22
EXTSUP
VREG
RT
GA2
PGNDA
Internal Oscillator
180deg
Slope
Comp
+
10
11
12
SA1
SA2
FBA
SYNC &LPM
+ Current
Sense Amp
20
SYNC
GC2
+
-
-
PWM comp
-
Source/Sink
Logic
4
+
gm OTA
+
0.8
V
SSA
EN
13
15
COMPA
PGA
1µA
SA2
-
FBA
14
SSA
ENA
+
VIN
VIN
500 nA
500 nA
16
ENA
ENB
17
25
34
33
32
31
30
29
28
27
26
24
CBB
GB1
1µA
SSB
PHB
ENB
GB2
VREF
PGNDB
SB1
40 µA
Second Buck Controller Channel
SB2
21
23
DLYAB
AGND
FBB
40 µA
COMPB
PGB
Figure 2. Functional Block Diagram
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TYPICAL CHARACTERISTICS
EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR CURRENTS (BUCK)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
INDUCTOR = 4.7 µH, RSENSE = 10 mW
10000
100
EFFICIENCY,
SYNC = LOW
FORCED CONTINUOUS MODE (SYNC = 1), 200-mA LOAD
90
80
70
60
50
40
30
20
10
0
1 A/DIV
1000
100
10
POWER LOSS,
SYNC = HIGH
DISCONTINUOUS MODE (SYNC = 0), 200-mA LOAD
1 A/DIV
1 A/DIV
POWER LOSS,
SYNC = LOW
1
EFFICIENCY,
SYNC = HIGH
LOW-POWER MODE (SYNC = 0), 20-mA LOAD
0.1
2 µs/DIV
0.0001
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
BUCK LOAD STEP: FORCED CONTINUOUS MODE
(0 TO 4 A AT 2.5 A/µs)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
SOFT-START OUTPUTS (BUCK)
INDUCTOR = 4.7 µH, RSENSE = 10 mW
VOUTA
VOUT AC-COUPLED
100 mV/DIV
VOUTB
1 V/DIV
2 A/DIV
IIND
2 ms/DIV
50 µs/DIV
Figure 5.
Figure 6.
BUCK LOAD STEP: LOW-POWER-MODE ENTRY
4 A TO 90 mA AT 2.5 A/µs
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
BUCK LOAD STEP: LOW-POWER-MODE EXIT
90 mA TO 4 A AT 2.5 A/µs
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
INDUCTOR = 4.7 µH, RSENSE = 10 mW
100 mV/DIV
100 mV/DIV
VOUT AC-COUPLED
VOUT AC-COUPLED
2 A/DIV
IIND
2 A/DIV
IIND
50 µs/DIV
Figure 8.
50 µs/DIV
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
NO-LOAD QUIESCENT CURRENT
ACROSS TEMPERATURE
BUCKx PEAK CURRENT LIMIT versus COMPx VOLTAGE
75
60
50
40
30
20
10
0
62.5
50
BOTH BUCKS ON
37.5
25
12.5
0
SYNC = LOW
ONE BUCK ON
–12.5
–25
NEITHER BUCK ON
SYNC = HIGH
0.8 0.95
–37.5
-40 -15 10
35
60
85 110 135 160
0.65
1.1
1.25
1.4
1.55
Temperature (°C)
COMPx Voltage (V)
Figure 10.
Figure 9.
CURRENT-SENSE PINS INPUT CURRENT (BUCK)
0.9
FOLDBACK CURRENT LIMIT (BUCK)
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
150°C
25°C
–0.1
–0.2
–0.3
0
1
2
3
4
5
6
7
8
9
10 11 12
0
0.2
0.4
0.6
0.8
Output Voltage (V)
FBx Voltage (V)
Figure 12.
Figure 11.
REGULATED FBx VOLTAGE versus TEMPERATURE
(BUCK)
CURRENT LIMIT versus DUTY CYCLE (BUCK)
80
70
60
50
40
30
20
10
0
805
804
803
802
801
800
799
798
797
796
795
VIN = 8 V
VIN = 12 V
0
10 20 30 40 50 60 70 80 90 100
–40 –15 10
35
60
85 110 135 160
Duty Cycle (%)
Temperature (°C)
Figure 13.
Figure 14.
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DETAILED DESCRIPTION
BUCK CONTROLLERS: NORMAL MODE PWM OPERATION
Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. Using a resistor at RT, one can set another frequency according to the formula:
X
fSW
=
(X = 24 kW´MHz)
RT
109
fSW = 24´
For example,
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to
600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin, and on detection of this condition, the
device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical
switching frequencies, 180 degrees out of phase.
Enable Inputs
Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,
with a threshold of 1.7 V for the high level, and with direct connection to the battery permissible for self-bias. The
low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open
circuit on these pins enables the respective buck controllers. But with both buck controllers disabled, the device
shuts down and consumes a current less than 4 µA.
Feedback Inputs
The right resistor feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose
this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup
current source as a protection feature in case the pins open up as a result of physical damage.
Soft-Start Inputs
In order to avoid large inrush currents, the buck controllers have independent programmable soft-start timers.
The voltage at the SSx pins acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx
pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After
start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V, which then
becomes the reference for the buck controllers. The following equation calculates the soft-start ramp time:
I
SS ´ Dt
CSS
=
(Farads)
D
where,
ISS = 1 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time.
An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be
tracked via a suitable resistor-divider network.
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Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its
set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the
output of the error amplifier (COMPx) which serves as a target for the peak inductor current. The device senses
the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this target during
each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise
respectively, thus increasing or decreasing the current through the inductor until the average current matches the
load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-
channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the
bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout,
the buck regulator switches at one-fourth of its normal frequency.
Current Sensing and Current Limit With Foldback
Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a
specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value
due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus
providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-
direction current limit).
Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the
COMPx node drops low. A clamp is on its lower end as well, in order to limit the maximum current in the low-side
MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum
forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is
for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input), 50
mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a
guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range.
This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 15 shows
DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter
components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,
it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.
Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.
Inductor L
TPS43350-Q1
or
TPS43351-Q1
VBuckX
DCR
R11
C11
Sx22
VC
Sx11
Figure 15. DCR Sensing Configuration
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Slope Compensation
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable
operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor
according to the following:
L ´ fSW
= 200
RS
where
L is the buck regulator inductor in henries.
RS is the sense resistor in ohms.
fsw is the buck-regulator switching frequency in hertz.
Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-
drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is
possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is in the powered-down state.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program
the duration of the delay of by using a suitable capacitor at the DLYAB pin according to the equation:
tDELAY
1 ms
=
CDLYAB
1 nF
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1%
of the set full-load current if the inductor and the sense resistor have been chosen appropriately as
recommended in the Slope Compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference – Sx2. At the end of this on-time, the high-side MOSFET turns off and the current in
the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the
next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic operation with
a total device quiescent current consumption of 30 µA when a single buck channel is active and 35 µA when
both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
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The TPS43350-Q1 and TPS43351-Q1 can support the full current load during low-power mode until the
transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10%
(typical) of full-load current if the selection of inductor and sense resistor is as recommended. Moreover, there is
always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power-mode entry.
Frequency-Hopping Spread Spectrum (TPS43351-Q1 Only)
The TPS43351-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this
device, whenever the SYNC pin is high, the internal oscillator frequency varies from one cycle to the next within
a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linear
feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift
register is long enough to make the hops pseudo-random in nature and is designed in such a way that the
frequency shifts only by one step at each cycle to avoid large jumps in the buck switching frequencies.
Table 1. Frequency Hopping Control
SYNC
TERMINAL
FREQUENCY SPREAD SPECTRUM (FSS)
COMMENTS
Device in forced continuous mode, internal PLL locks into external clock
between 150 kHz and 600 kHz.
External clock
Not active
Not active
Device can enter discontinuous mode. Automatic LPM entry and exit,
depending on load conditions
Low or open
High
TPS43350-Q1: FSS not active
TPS43351-Q1: FSS active
Device in forced continuous mode
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
BUCK CONTROLLER STATUS
DEVICE STATUS
QUIESCENT CURRENT
Approximately 4 µA
ENA
Low
ENB
SYNC
Low
X
Shutdown
Shutdown
Low
High
Low
High
Low
High
BuckB: LPM enabled
BuckB: LPM inhibited
BuckA: LPM enabled
BuckA: LPM inhibited
BuckA and BuckB: LPM enabled
BuckA and BuckB: LPM inhibited
Approximately 30 µA (light loads)
mA range
Low
High
High
High
Low
High
BuckB running
Approximately 30 µA (light loads)
mA range
BuckA running
Approximately 35 µA (light loads)
mA range
BuckA and BuckB running
Gate-Driver Supply (VREG, EXTSUP)
The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8
V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 µF to 10 µF.
This pin has internal current-limit protection; do not use it to power any other circuits.
VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). In case
VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high
switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power this
regulator from the EXTSUP pin, which can be connected to a supply lower than VIN but high enough to provide
the gate drive. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically switches to
EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using one of the
switching regulator rails from the TPS4335x-Q1 or any other voltage available in the system to power EXTSUP.
The maximum voltage for application to EXTSUP is 9 V.
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VIN
EXTSUP
LDO
VIN
LDO
EXTSUP
typ 5.8 V
typ 7.5 V
typ 4.6 V
VREG
Figure 16. Internal Gate-Driver Supply
Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as it provides a large gate drive
and hence better on-resistance of the external MOSFETs. When using EXTSUP, always keep the buck rail
supplying EXTSUP enabled. Alternatively, if it is necessary to switch off the buck rail supplying EXTSUP, place a
diode between the buck rail and EXTSUP. During low-power mode, the EXTSUP functionality is not available.
The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current-
limit protection for VREG is available in low-power mode as well. If EXTSUP is unused, leave the pin open
without a capacitor installed.
External P-Channel Drive (GC2) and Reverse-Battery Protection
The TPS4335x-Q1 includes a gate driver for an external P-channel MOSFET which can be connected across the
reverse-battery diode. This is useful to reduce power losses and the voltage drop over a typical diode. The gate
driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET.
GC2
VBAT
TPS43350-Q1
VIN
or
Fuse
TPS43351-Q1
VBAT
Figure 17. Reverse-Battery Protection Option
Undervoltage Lockout and Overvoltage Protection
The TPS4335x-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once it
has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage
lockout disables the device. Note: if VIN drops, VREG drops as well; hence, the gate-drive voltage decreases,
whereas the digital logic is fully functional. A voltage of 46 V at VIN triggers the overvoltage comparator, which
shuts down the device. In order to prevent transient spikes from shutting down the device, under- and
overvoltage protection have filter times of 5 µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators start including a new
soft-start ramp for the buck regulators.
Thermal Protection
The TPS4335x-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die
temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for example,
due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers turn off and then
restart when the temperature has fallen by 15ºC.
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for the TPS43350-Q1. Table 3
lists the design-goal parameters.
Table 3. Application Example
PARAMETER
VBuckA
VBuckB
VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
Input voltage
Output voltage, VOUTx
5 V
3 A
3.3 V
2 A
Maximum output current, IOUTx
Load step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load step, ∆IOUTx
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
0.1 A to 3 A
400 kHz
Converter switching frequency, fSW
This is a starting point, and theoretical representation of the values to be used for the application; improving the
performance of the device may require further optimization of the derived components.
BuckA Component Selection
Minimum ON Time, tON min
VOUTA
5 V
tON min
=
=
= 416 ns
VIN max ´ fSW 30 V ´ 400 kHz
This is higher than the minimum on-time specified (100 ns typical). Hence, the minimum duty cycle is achievable
at this frequency.
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Current-Sense Resistor RSENSE
Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65
mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose
VSENSE with a maximum of 50 mV.
50 mV
RSENSE
=
= 17 mW
3 A
Select 15 mΩ.
Inductor Selection L
As explained in the description of the buck controllers, for optimal slope compensation and loop response, the
inductor should be chosen such that:
RSENSE
15 mW
L = KFLR
´
= 200´
= 7.5 mH
fSW
400 kHz
KFLR = Coil selection constant = 200
Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be
chosen to sustain the maximum currents.
Inductor Ripple Current IRIPPLE
At nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IO max ≈ 1 A.
Output Capacitor COUTA
Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈ 15
mV and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within
the required limits.
2´ DIOUTA
=
fSW ´ DVOUTA 400 kHz ´0.2 V
2´ 2.9 A
COUTA
»
= 72.5 mF
IOUTA(Ripple)
1 A
VOUTA(Ripple)
=
+ IOUTA(Ripple) ´ESR =
+1 A ´10 mW = 13.1mV
8´ fSW ´ COUTA
8´ 400 kHz ´100 mF
DIOUTA
2.9 A
4´ 50 kHz ´100 mF
DVOUTA
=
+ DIOUTA ´ESR =
+ 2.9 A ´10 mW = 174 mV
4´ fC ´ COUTA
Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes and crossover values for a tradeoff between stability
and transient response.
•
•
•
Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
Select the zero fz ≈ fC / 10.
Make the second pole fP2 ≈ fSW / 2.
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Selection of Components for Type II Compensation
VOUT
RESR
COUT
R1
R2
VSENSE
RL
COMP
Type 2A
GmBUCK
VREF
R3
C1
R0
C2
Figure 18. Buck Compensation Components
2p´ fC ´ VOUT ´ COUTx
GmBUCK ´KCFB ´ VREF
2p´ 50 kHz ´ 5 V ´100μF
GmBUCK ´KCFB ´ VREF
R3 =
=
= 23.57 kW
Use the standard value of R3 = 24 kΩ,
Where VOUT = 5 V, COUTx = 100 µF, GmBUCK = 1 mS, VREF = 0.8 V
KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)
10
10
C1=
=
2p´R3 ´ fC 2p´ 24 kW ´ 50 kHz
= 1.33 nF
Use the standard value of 1.5 nF.
C1
1.5 nF
C2 =
=
= 33 pF
f
400 kHz
æ
ç
ö
÷
æ
ö
SW
2p´ 24kW´1.5 nF
-1
2p´R3´ C1
-1
ç
÷
2
2
è
ø
è
ø
The resulting bandwidth of buck converter, fC
GmBUCK ´R3´KCFB VREF
fC =
´
2p´COUTx
VOUT
1mS´ 24 kW´8.33 S´0.8 V
2p´100 μF´ 5 V
fC =
= 50.9 kHz
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3´ C1 2p´ 24 kW ´1.5 nF
= 4.42 kHz
This is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2
=
=
2p´R3´ C2 2p´ 24 kW ´33 pF
= 201kHz
This is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.
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Resistor Divider Selection for Setting VOUTA Voltage
VREF
0.8 V
b =
=
= 0.16
VOUTA
5 V
Choose the divider current through R1 and R2 to be 50 µA. Then
5 V
R1+ R2 =
= 66 kW
50 mA
and
R2
= 0.16
R1+ R2
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
BuckB Component Selection
Using the same method as for VBuckA produces the following parameters and components.
VOUTB
5 V
tON min
=
=
= 416 ns
V
IN max ´ fSW 30 V ´ 400 kHz
This is higher than the minimum duty cycle specified (100 ns typical).
60 mV
RSENSE
=
= 30 mW
2 A
30 mW
400 kHz
L = 200´
= 15 mH
∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max
)
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. Assume fC = 50 kHz.
2´ DIOUTB
2´1.9 A
COUTB
»
=
fSW ´ DVOUTB 400 kHz ´ 0.12 V
= 46 mF
IOUTB(Ripple)
0.4 A
VOUTB(Ripple)
=
+ IOUTB(Ripple) ´ESR =
+ 0.4 A ´10 mW = 5.3 mV
8´ fSW ´ COUTB
8´ 400 kHz ´100 mF
DIOUTB
1.9 A
4´ 50 kHz ´100 mF
DVOUTB
=
+ DIOUTB ´ESR =
+1.9 A ´10 mW = 114 mV
4´ fC ´ COUTB
2p´ fC ´ VOUTB ´ COUTB
GmBUCK ´KCFB ´ VREF
R3 =
2p´ 50 kHz ´ 3.3 V ´100 mF
1mS ´ 4.16 S ´ 0.8 V
=
= 31kW
Use the standard value of R3 = 30 kΩ.
10
10
C1=
=
2p´R3 ´ fC 2p´ 30 kW ´ 50 kHz
= 1.1nF
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C1
C2 =
f
æ
ö
SW
2p´R3 ´ C1´
-1
ç
÷
2
è
ø
1.1nF
=
= 27 pF
400 kHz
2
æ
ç
ö
2p´ 30 kW ´1.1nF´
-1
÷
è
ø
GmBUCK ´R3 ´KCFB
VREF
fC =
´
2p´ COUTB
VOUTB
1mS ´ 30 kW ´ 4.16 S ´ 0.8 V
2p´100 μF ´ 3.3 V
=
= 48 kHz
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3 ´ C1 2p´ 30 kW ´1.1nF
= 4.8 kHz
This is close to the fC guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2
=
=
2p´R3 ´ C2 2p´ 30 kW ´ 27 pF
= 196 kHz
This is close to the fSW / 2 guideline of 200 kHz.
Hence, the design satisfies all requirements for a good loop.
Resistor Divider Selection for Setting VOUT Voltage
VREF
=
VOUT 3.3 V
0.8 V
b =
= 0.242
Choose the divider current through R1 and R2 to be 50 µA. Then
3.3 V
R1+ R2 =
= 66 kW
50 mA
and
R2
= 0.242
R1+ R2
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
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BuckX High-Side and Low-Side N-Channel MOSFETs
An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for
these MOSFETs. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output
current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the
reference for the low-side MOSFET is the power-ground (PGx) terminal. For a particular application, select these
MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source breakdown
voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and have a relationship to the gate-
driver strength of the TPS43350x-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the
conduction losses, which are minimal when the on-resistance of the MOSFET is low. The second term denotes
the transition losses, which arise due to the full application of the input voltage across the drain-source of the
MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.
V ´I
æ
ö
= (IOUT )2 ´rDS(on)(1+ TC)´D +
´(tr + tf )´ fSW
IN
OUT
P
BuckTOPFET
ç
÷
2
è
ø
P
= (IOUT )2 ´rDS(on)(1+ TC)´(1-D) + VF ´IOUT ´(2´ td )´ fSW
BuckLOWERFET
In addition, during dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. The second term in the foregoing equation denotes this. Using external Schottky
diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.
Note: The rDS(on) has a positive temperature coefficient, and TC term for rDS(on) accounts for that fact. TC = d ×
delta T[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can
be assumed to be 0.005 / °C as a starting value.
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SLVSAR7D –JUNE 2011–REVISED APRIL 2013
Schematic
The following section summarizes the previously calculated example and gives schematic and component
proposals. Table 3.
Table 4. Application Example
PARAMETER
VBuckA
VBuckB
VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
Input voltage
Output voltage, VOUTx
5 V
3 A
3.3 V
2 A
Maximum output current, IO
Load step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load step, ∆IOUTx
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
0.1 A to 3 A
400 kHz
Converter switching frequency, fSW
4V to 40V
VBAT
D1
680µF
COUT1
10µF
CIN
220µF
SWRB
1kΩ
VBAT
ENA
VIN
EXTSUP
RT
ENB
GC2
VREG
4.7µF
CBA
CBB
SWBH
L2
SWAH
0.1µF
0.1µF
VBuckA — 5V, 15W
0.015Ω
VBuckB — 3.3V, 6.6W
L1
0.03Ω
GA1
GB1
PHB
GB2
8.2µH
15µH
100µF
COUTA
100µF
COUTB
PHA
SWBL
SWAL
GA2
TPS43350-Q1
or
TPS43351-Q1
PGNDA
SA1
PGNDB
SB1
50kΩ
84kΩ
PGA
SA2
PGB
5kΩ
5kΩ
SB2
FBA
FBB
16kΩ
16kΩ
COMPA
SSA
COMPB
SSB
27pF
33pF
1.5nF
1.1nF
30kΩ
10nF
24kΩ
10nF
SYNC
AGND
DLYAB
1nF
Figure 19. Simplified Application Schematic Example
Table 5. Application Example – Component Proposals
NAME
COMPONENT PROPOSAL
VALUE
8.2 µH
15 µH
L1
MSS1278T-822ML (Coilcraft)
L2
MSS1278T-153ML (Coilcraft)
D1
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
SWRB
SWAH, SWAL, SWBH,
SWBL
Si4840DY-T1-E3 (Vishay)
COUTA, COUTB
CIN
ECASD91A107M010K00 (Murata)
EEEFK1V331P (Panasonic)
100 µF
330 µF
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Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
Figure 20. Power Dissipation Derating Profile Based on High-K JEDEC PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
Buck Converter
1. Connect the drain of SWAH and SWBH MOSFETs together with the positive terminal of the input capacitor
COUTA. The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of SWxH and source of SWxL.
3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitors for noise near the IC pins.
4. The resistor divider for sensing output voltage connects between the positive terminal of the respective
output capacitor and COUTA or COUTB and the IC signal ground. Do not locate these components and their
traces near any switching nodes or high-current traces.
Other Considerations
1. Short PGNDx and AGND to the thermal pad. Use a star ground configuration if connecting to a nonground
plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense
feedback-ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. Do not locate these sensitive
circuits near the dv/dt nodes; these include the gate-drive outputs and phase pins.
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component
placement. Ensure the bypass capacitors are located as close as possible to their respective power and
ground pins.
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SLVSAR7D –JUNE 2011–REVISED APRIL 2013
PCB Layout
POWER
INPUT
Power Lines
Connection to GND Plane of PCB through vias
Connection to top/bottom of PCB through vias
Voltage Rail Outputs
VIN
EXTSUP
NC
VBAT
NC
NC
VREG
CBB
GC2
CBA
GA1
PHA
GA2
PGNDA
SA1
GB1
PHB
GB2
PGNDB
SB1
SB2
SA2
FBB
FBA
COMPB
SSB
COMPA
SSA
PGA
ENA
ENB
NC
PGB
AGND
RT
DLYAB
SYNC
Exposed Pad
connected to GND
Plane
AGND
Microcontroller
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REVISION HISTORY
Changes from Revision C (September 2012) to Revision D
Page
•
•
•
Deleted Ordering Information table ....................................................................................................................................... 2
Revised Absolute Maximum Ratings table ........................................................................................................................... 2
Changed pinout diagram ...................................................................................................................................................... 7
Changes from Revision B (June 2011) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Corrected AEC specification in ESD ratings ......................................................................................................................... 2
Multiple changes throughout Electrical Characteristics table ............................................................................................... 4
Changed input-voltage value for pins ENA and ENB ........................................................................................................... 7
Added a sentence to EXTSUP pin description ..................................................................................................................... 7
Changed upper threshold voltage for ENx pins to 1.7 V .................................................................................................... 12
Text deletion from second paragraph of Light-Load PFM Mode section ............................................................................ 14
Changed value of gate-driver decoupling capacitor ........................................................................................................... 15
Added upper voltage limit for EXTSUP pin ......................................................................................................................... 15
Replaced paragraphs following the figure at end of Gate-Driver Supply section ............................................................... 16
Clarified parameter definition in Application Example table ............................................................................................... 17
Added equations for Output Capacitor COUTA section ......................................................................................................... 18
Added equations for BuckB Component Selection sectiion ............................................................................................... 20
Changed peak output current in BuckX High-Side and Low-Side N-Channel MOSFETs section ..................................... 22
Clarified parameter description in Application Example table ............................................................................................ 23
Revised diagram of Simplified Application Schematic Example ......................................................................................... 23
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS43350QDAPRQ1
TPS43351QDAPRQ1
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
HTSSOP
HTSSOP
DAP
38
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
TPS43350Q1
ACTIVE
DAP
2000
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
-40 to 125
TPS43351Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS43350QDAPRQ1 HTSSOP
TPS43351QDAPRQ1 HTSSOP
DAP
DAP
38
38
2000
2000
330.0
330.0
24.4
24.4
8.6
8.6
13.0
13.0
1.8
1.8
12.0
12.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS43350QDAPRQ1
TPS43351QDAPRQ1
HTSSOP
HTSSOP
DAP
DAP
38
38
2000
2000
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
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相关型号：
TPS43351QDAPQ1
IC 0.4 A DUAL SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO38, PLASTIC, HTSSOP-38, Switching Regulator or Controller
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