TPS51125RGETG4_技术文档

TPS51125

www.ti.com

SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

Dual-Synchronous, Step-Down Controller with Out-of-Audio™ Operation and 100-mA

LDOs for Notebook System Power

1

FEATURES

DESCRIPTION

2

•

Wide Input Voltage Range: 5.5 V to 28 V

Output Voltage Range: 2 V to 5.5 V

Built-in 100-mA 5-V/3.3-V LDO with Switches

Built-in 1% 2-V Reference Output

•

The TPS51125 is a cost effective, dual-synchronous

buck controller targeted for notebook system power

supply solutions. It provides 5-V and 3.3-V LDOs and

requires few external components. The 270-kHz

VCLK output can be used to drive an external charge

pump, generating gate drive voltage for the load

switches without reducing the main converter’s

efficiency. The TPS51125 supports high efficiency,

fast transient response and provides a combined

power-good signal. Out-of-Audio™ mode light-load

operation enables low acoustic noise at much higher

efficiency than conventional forced PWM operation.

Adaptive on-time D-CAP™ control provides

convenient and efficient operation. The part operates

with supply input voltages ranging from 5.5 V to 28 V

and supports output voltages from 2 V to 5.5 V. The

TPS51125 is available in a 24-pin QFN package and

is specified from -40°C to 85°C ambient temperature

range.

With/Without Out-of-Audio™ Mode Selectable

Light Load and PWM only Operation

•

Internal 1.6-ms Voltage Servo Softstart

Adaptive On-Time Control Architecture with

Four Selectable Frequency Setting

•

4500 ppm/°C R_DS(on)Current Sensing

Built-In Output Discharge

Power Good Output

Built-in OVP/UVP/OCP

Thermal Shutdown (Non-latch)

QFN24 (RGE)

APPLICATIONS

•

Notebook Computers

I/O Supplies

System Power Supplies

Typical Application Diagram

SGND

C0

0.22mF

R3

13kW

R1

30kW

R6

110kW

R4

20kW

R2

20kW

R5

110kW

3.3V/100mA

-

SGND

VIN

6

2

5

2

4

3

2

1

VIN

5.5

+

L

E

S

F

E

1

P

I

~

28V

B

F

R

T

R

T

F

V

R

N

V

C7

10mF

C8

10mF

C5

10mF

C6

10mF

N

E

N

E

O

T

7

8

9

VO2

VO1 24

PG

R7

100kW

C20

10mF

VREG5

VREG3

VBST2

PGOOD 23

VBST1 22

DRVH1 21

LL1 20

PGND

C3

0.1mF

Q3

IRF7821

C4

0.1mF

R8

5.1W

R9

5.1W

Q1

IRF7821

TPS51125RGE

(QFN24)

L2

3.3mH

L1

3.3mH

10 DRVH2

11 LL2

VO2

3.3V/6A

VO1

5V/6A

+

PowerPAD

Q4

IRF7821

Q2

IRF7821

CO2

POSCAP

330mF

CO1

POSCAP

330mF

12 DRVL2

DRVL1 19

L

E

5

G

S

K

L

E

D

P

I

0

R

V

N

I

K

S

C

V

N

E

G

V

13

14

15

16

17

18

VO2_GND

EN0

-

VO1_GND

SGND

PGND

VREG5

PGND

-

5V/100mA

15V/10mA

C11

100n

F

C13

100n

F

C21

10mF

VO1

R10

620kW

VREF

D0

D1

D2

C12

D4

C10

100n

F

C14

1uF

100n

F

PGND

SGND

PGND

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

Out-of-Audio, D-CAP are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS51125

www.ti.com

SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

ORDERING INFORMATION

OUTPUT

SUPPLY

MIN

QUANTITY

T_A

PACKAGE

PART NUMBER

PINS

ECO PLAN

Tape

-and-Reel

TPS51125RGET

TPS51125RGER

250

Green

(RoHS and

no Sb/Br)

Plastic Quad Flat Pack

(QFN)

-40°C to 85°C

24

Tape

-and-Reel

3000

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER

VALUE

-0.3 to 36

-0.3 to 30

-2.0 to 30

-0.3 to 6

UNIT

VBST1, VBST2

VIN

(1)

Input voltage range

Output voltage range

LL1, LL2

(2)

VBST1, VBST2

V

EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL

DRVH1, DRVH2

-0.3 to 6

-1.0 to 36

-0.3 to 6

(1)

(2)

DRVH1, DRVH2

PGOOD, VCLK, VREG3, VREG5, VREF, DRVL1, DRVL2

Junction temperature range

-0.3 to 6

T_J

-40 to 125

-55 to 150

°C

T_stg

Storage temperature

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage values are with respect to the corresponding LLx terminal.

DISSIPATION RATINGS

2-oz. trace and copper pad with solder.

DERATING FACTOR ABOVE T_A

PACKAGE

T_A< 25°C POWER RATING

T_A= 85°C POWER RATING

= 25°C

24 pin RGE⁽¹⁾

1.85 W

18.5 mW/°C

0.74 W

(1) Enhanced thermal conductance by 3x3 thermal vias beneath thermal pad.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

5.5

TYP

MAX

UNIT

Supply voltage

VIN

28

34

Input voltage range

VBST1, VBST2

VBST1, VBST2 (wrt LLx)

-0.1

5.5

EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2,

TONSEL, SKIPSEL

-0.1

5.5

V

Output voltage range

DRVH1, DRVH2

-0.8

-0.1

-1.8

-0.1

-40

34

5.5

28

DRVH1, DRVH2 (wrt LLx)

LL1, LL2

VREF, VREG3, VREG5

PGOOD, VCLK, DRVL1, DRVL2

Operating free-air temperature

5.5

85

T_A

°C

2

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supply Current

VIN current, T_A= 25°C, no load, VO1 = 0 V, VO2 =

0 V, EN0=open, ENTRIPx = 5 V,

VFB1 = VFB2 = 2.05 V

I_VIN1

VIN supply current1

VIN supply current2

VO1 current

0.55

1

mA

µA

VIN current, T_A= 25°C, no load, VO1 = 5 V, VO2 =

3.3 V, EN0=open, ENTRIPx = 5 V,

VFB1 = VFB2 = 2.05 V

I_VIN2

4

0.8

12

6.5

1.5

VO1 current, T_A= 25°C, no load, VO1 = 5 V, VO2

= 3.3 V, EN0=open, ENTRIPx = 5 V,

VFB1 = VFB2 = 2.05 V

I_VO1

mA

VO2 current, T_A= 25°C, no load, VO1 = 5 V, VO2

= 3.3 V, EN0=open, ENTRIPx = 5 V,

VFB1 = VFB2 = 2.05 V

I_VO2

VO2 current

100

VIN current, T_A= 25°C, no load,

EN0 = 1.2 V, ENTRIPx = 0 V

µA

I_VINSTBY

VIN standby current

VIN shutdown current

95

10

250

25

VIN current, T_A= 25°C, no load,

EN0 = ENTRIPx = 0 V

I_VINSDN

VREF Output

I_VREF= 0 A

1.98

2.00

2.02

2.03

V_VREF

VREF output voltage

V

-5 µA < I_VREF< 100 µA

1.97

VREG5 Output

VO1 = 0 V, I_VREG5< 100 mA, T_A= 25°C

VO1 = 0 V, I_VREG5< 100 mA, 6.5 V < VIN < 28 V

VO1 = 0 V, I_VREG5< 50 mA, 5.5 V < VIN < 28 V

VO1 = 0 V, VREG5 = 4.5 V

4.8

4.75

4. 75

100

5

5.2

5.25

250

4.85

0.3

V_VREG5

VREG5 output voltage

5

I_VREG5

VREG5 output current

Switch over threshold

5 V SW R_ON

175

4.7

0.25

1

mA

V

Turns on

4.55

0.15

V_TH5VSW

Hysteresis

R_5VSW

VO1 = 5 V, I_VREG5= 100 mA

3

Ω

VREG3 Output

VO2 = 0 V, I_VREG3< 100 mA, T_A= 25°C

VO2 = 0 V, I_VREG3< 100 mA, 6.5 V < VIN < 28 V

VO2 = 0 V, I_VREG3< 50 mA, 5.5 V < VIN < 28 V

VO2 = 0 V, VREG3 = 3 V

3.2

3.13

100

3.05

0.1

3.33

175

3.15

0.2

3.46

3.5

V_VREG3

VREG3 output voltage

V

3.5

I_VREG3

VREG3 output current

Switch over threshold

3 V SW R_ON

250

3.25

0.25

4

mA

V

Turns on

V_TH3VSW

Hysteresis

R_3VSW

VO2 = 3.3 V, I_VREG3= 100 mA

1.5

Ω

Internal Reference Voltage

V_IREF

V_VFB

I_VFB

Internal reference voltage

I_VREF= 0 A, beginning of ON state

FB voltage, I_VREF= 0 A, skip mode

1.95

1.98

2.00

1.98

2.01

2.04

2.07

V

(1)

VFB regulation voltage

VFB input current

FB voltage, I_VREF= 0 A, OOA mode

2.035

2.00

(1)

FB voltage, I_VREF= 0 A, continuous conduction

VFBx = 2.0 V, T_A= 25°C

-20

20

nA

(1) Ensured by design. Not production tested.

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

V_OUTDischarge

I_Dischg

VOUT discharge current

ENTRIPx = 0 V, VOx = 0.5 V

10

60

mA

Output Drivers

Source, V_{BSTx - DRVHx}= 100 mV

Sink, V_{DRVHx - LLx}= 100 mV

Source, V_{VREG5 - DRVLx}= 100 mV

Sink, V_DRVLx= 100 mV

4

1.5

4

8

4

8

4

R_DRVH

R_DRVL

T_D

DRVH resistance

DRVL resistance

Dead time

Ω

1.5

10

30

DRVHx-off to DRVLx-on

ns

DRVLx-off to DRVHx-on

Clock Output

V_CLKH

High level voltage

Low level voltage

Clock frequency

I_VCLK= -10 mA, VO1 = 5 V, T_A= 25 °C

I_VCLK= 10 mA, VO1 = 5 V, T_A= 25 °C

T_A= 25 °C

4.84

175

0.7

4.92

0.06

270

V

V_CLKL

0.12

325

f_CLK

kHz

Internal BST Diode

V_FBST

Forward voltage

VBST leakage current

V_VREG5-VBSTx, I_F= 10 mA, T_A= 25 °C

VBSTx = 34 V, LLx = 28 V, T_A= 25 °C

0.8

0.1

0.9

1

V

I_VBSTLK

µA

Duty and Frequency Control

T_ON11

CH1 on time 1

CH1 on time 2

CH1 on time 3

CH1 on time 4

CH2 on time 1

CH2 on time 2

CH2 on time 3

CH2 on time 4

Minimum on time

Minimum off time

V_IN= 12 V, VO1 = 5 V, 200 kHz setting

V_IN= 12 V, VO1 = 5 V, 245 kHz setting

V_IN= 12 V, VO1 = 5 V, 300 kHz setting

V_IN= 12 V, VO1 = 5 V, 365 kHz setting

V_IN= 12 V, VO2 = 3.3 V, 250 kHz setting

V_IN= 12 V, VO2 = 3.3 V, 305 kHz setting

V_IN= 12 V, VO2 = 3.3 V, 375 kHz setting

V_IN= 12 V, VO2 = 3.3 V, 460 kHz setting

T_A= 25 °C

2080

1700

1390

1140

1100

900

T_ON12

T_ON13

T_ON14

T_ON21

ns

T_ON22

T_ON23

730

T_ON24

600

T_ON(min)

T_OFF(min)

Softstart

T_SS

80

T_A= 25 °C

300

Internal SS time

Internal soft start

1.1

1.6

2.1

ms

Powergood

PG in from lower

PG in from higher

92.50%

95% 97.50%

102.50

%

107.50

V_THPG

PG threshold

105%

%

PG hysteresis

PGOOD = 0.5 V

Delay for PG in

2.50%

5

5%

12

7.50%

670

I_PGMAX

T_PGDEL

PG sink current

PG delay

mA

350

510

µs

4

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Logic Threshold and Setting Conditions

Shutdown

0.4

V_EN0

EN0 setting voltage

EN0 current

Enable, VCLK = off

Enable, VCLK = on

V_EN0= 0.2 V

0.8

1.6

V

2.4

2

3.5

5

2.5

450

60

I_EN0

µA

V_EN0= 1.5 V

1

1.75

400

30

Shutdown

350

10

ENTRIP1, ENTRIP2

threshold

V_EN

mV

Hysteresis

200 kHz/250 kHz

245 kHz/305 kHz

300 kHz/375 kHz

365 kHz/460 kHz

PWM only

1.5

2.1

3.6

1.9

2.7

4.7

V_TONSEL

TONSEL setting voltage

SKIPSEL setting voltage

V

1.5

2.1

V_SKIPSEL

Auto skip

1.9

2.7

OOA auto skip

Protection: Current Sense

I_ENTRIP

ENTRIPx source current

V_ENTRIPx= 920 mV, T_A= 25°C

On the basis of 25°C

9.4

10

10.6

µA

ENTRIPx current temperature

coefficient

TC_IENTRIP

4500

ppm/°C

((V_ENTRIPx-GND/9)-24 mV -V_GND-LLx) voltage,

V_ENTRIPx-GND= 920 mV

V_OCLoff

V_OCL(max)

V_ZC

OCP comparator offset

Maximum OCL setting

-8

185

0

205

0

8

225

5

V_ENTRIPx= 5 V

mV

V

Zero cross detection

comparator offset

V_GND-LLxvoltage

-5

(2)

V_ENTRIP

Current limit threshold

V_ENTRIPx-GNDvoltage,

0.515

2

Protection: UVP & OVP

V_OVP

OVP trip threshold

OVP detect

110%

55%

115%

2

120%

65%

T_OVPDEL

OVP prop delay

µs

UVP detect

Hysteresis

60%

10%

32

V_UVP

Output UVP trip threshold

T_UVPDEL

T_UVPEN

UVLO

Output UVP prop delay

Output UVP enable delay

20

40

µs

1.4

2

2.6

ms

Wake up

4.1

4.2

0.43

4.3

V_UVVREG5

V_UVVREG3

VREG5 UVLO threshold

VREG3 UVLO threshold

Hysteresis

0.38

0.48

V

(2)

Shutdown

VO2-1

Thermal Shutdown

(2)

Shutdown temperature

150

10

T_SDN

Thermal shutdown threshold

°C

(2)

Hysteresis

(2) Ensured by design. Not production tested.

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

DEVICE INFORMATION

Table 1. TERMINAL FUNCTIONS TABLE

TERMINAL

NAME NO.

VIN

I/O

DESCRIPTION

16

15

8

I

High voltage power supply input for 5-V/3.3-V LDO.

Ground.

GND

-

VREG3

VREG5

VREF

O

3.3-V power supply output.

17

3

5-V power supply output.

2-V reference voltage output.

Master enable input.

Open : LDOs on, and ready to turn on VCLK and switcher channels.

620 kΩ to GND : enable both LDOs, VCLK off and ready to turn on switcher channels. Power

consumption is almost the same as the case of VCLK = ON. 330 pF to 1 nF should be connected to

GND near the device

EN0

13

I/O

GND : disable all circuit

Channel 1 and Channel 2 enable and OCL trip setting pins.

ENTRIP1,

ENTRIP2

1, 6

I/O

Connect resistor from this pin to GND to set threshold for synchronous R_DS(on)sense. Short to ground

to shutdown a switcher channel.

Output connection to SMPS. These terminals work as fixed voltage inputs and output discharge

inputs. VO1 and VO2 also work as 5 V and 3.3 V switch over return power input respectively.

VO1, VO2

24, 7

VFB1,

VFB2

SMPS feedback inputs. Connect with feedback resistor divider.

2, 5

23

I

PGOOD

O

Power Good window comparator output for channel 1 and 2. (Logical AND)

Selection pin for operation mode:

OOA auto skip : Connect to VREG3 or VREG5

Auto skip : Connect to VREF

SKIPSEL

14

I

PWM only : Connect to GND

On-time adjustment pin.

365 kHz/460 kHz setting : connect to VREG5

300 kHz/375 kHz setting : connect to VREG3

245 kHz/305 kHz setting : connect to VREF

200 kHz/250 kHz setting : connect to GND

Low-side N-channel MOSFET driver outputs. GND referenced drivers.

TONSEL

4

DRVL1,

DRVL2

19, 12

22, 9

O

I

VBST1,

VBST2

Supply input for high-side N-channel MOSFET driver (boost terminal).

High-side N-channel MOSFET driver outputs. LL referenced drivers.

DRVH1,

DRVH2

21, 10

O

LL1, LL2

VCLK

20, 11

18

I

Switch node connections for high-side drivers, current limit and control circuitry.

270-kHz clock output for 15-V charge pump.

O

6

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

QFN Package (top view)

ENTRIP1

VFB1

1

2

3

4

5

6

18 VCLK

17 VREG5

16 VIN

VREF

TONSEL

VFB2

15 GND

14 SKIPSEL

13 EN0

ENTRIP2

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

Functional Block Diagram

8

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

Switcher Controller Block

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

TYPICAL CHARACTERISTICS

VIN SUPPLY CURRENT1

vs

VIN SUPPLY CURRENT1

vs

JUNCTION TEMPERATURE

INPUT VOLTAGE

800

700

600

500

400

300

200

100

0

800

700

600

500

400

300

200

100

0

-50

0

50

100

150

5

10

15

20

25

T

- Junction Temperature - °C

J

V

- Input Voltage - V

IN

Figure 1.

Figure 2.

VIN SUPPLY CURRENT2

vs

VIN SUPPLY CURRENT2

vs

JUNCTION TEMPERATURE

INPUT VOLTAGE

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

5

10

15

20

25

-50

0

50

100

150

V

- Input Voltage - V

IN

T

- Junction Temperature - °C

J

Figure 3.

Figure 4.

10

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

TYPICAL CHARACTERISTICS (continued)

VIN STANDBY CURRENT

vs

VIN STANDBY CURRENT

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

250

200

150

100

50

250

200

150

100

50

0

5

10

15

20

25

-50

0

50

100

150

T

- Junction Temperature - °C

V

- Input Voltage - V

J

IN

Figure 5.

Figure 6.

VIN SHUTDOWN CURRENT

vs

VIN SHUTDOWN CURRENT

vs

JUNCTION TEMPERATURE

INPUT VOLTAGE

25

20

15

10

5

25

20

15

10

5

0

5

10

15

20

25

-50

0

50

100

150

V

- Input Voltage - V

T

- Junction Temperature - °C

IN

J

Figure 7.

Figure 8.

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

TYPICAL CHARACTERISTICS (continued)

CURRENT SENSE CURRENT

vs

VCLK FREQUENCY

vs

JUNCTION TEMPERATURE

14

13

12

11

10

9

325

300

275

250

225

200

175

8

7

6

-50

0

50

100

150

-50

0

50

100

150

T - Junction Temperature - °C

J

T

- Junction Temperature - °C

J

Figure 9.

Figure 10.

SWITCHING FREQUENCY

vs

SWITCHING FREQUENCY

vs

INPUT VOLTAGE

500

TONSEL = GND

TONSEL = 2V

400

300

200

100

0

400

300

200

100

0

CH2

CH1

CH2

CH1

6

8

10 12 14 16 18 20 22 24 26

_IN- Input Voltage - V

6

8

10 12 14 16 18 20 22 24 26

_IN- Input Voltage - V

V

Figure 11.

Figure 12.

12

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SLUS786A–OCTOBER 2007–REVISED NOVEMBER 2007

TYPICAL CHARACTERISTICS (continued)

SWITCHING FREQUENCY

vs

SWITCHING FREQUENCY

vs

INPUT VOLTAGE

500

400

300

200

100

0

500

TONSEL = 3.3V

CH2

CH1

TONSEL = 5V

CH2

CH1

400

300

200

100

0

6

8

10 12 14 16 18 20 22 24 26

V_IN- Input Voltage - V

6

8

10 12 14 16 18 20 22 24 26

V_IN- Input Voltage - V

Figure 13.

Figure 14.

SWITCHING FREQUENCY

vs

SWITCHING FREQUENCY

vs

OUTPUT CURRENT

500

400

300

200

100

0

500

400

300

200

100

0

TONSEL = GND

TONSEL = 2V

CH2 PWM Only

CH1 PWM Only

CH2 PWM Only

CH1 PWM Only

CH1 OOA

CH2 Auto-skip

CH2 OOA

CH2 Auto-skip

CH2 OOA

CH1 OOA

CH1 Auto-skip

1 10

CH1 Auto-skip

1 10

0.001

0.01

0.1

0.001

0.01

0.1

I_OUT- Output Current - A

Figure 15.

Figure 16.

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TYPICAL CHARACTERISTICS (continued)

SWITCHING FREQUENCY

vs

SWITCHING FREQUENCY

vs

OUTPUT CURRENT

500

400

300

200

100

0

500

400

300

200

100

0

TONSEL = 3.3V

TONSEL = 5V

CH2 PWM Only

CH1 PWM Only

CH2 Auto-skip

CH2 OOA

CH1 OOA

CH2 OOA

CH1 OOA

CH1 Auto-skip

1

CH1 Auto-skip

1

0.001

0.01

0.1

10

0.001

0.01

0.1

10

I_OUT- Output Current - A

Figure 17.

Figure 18.

OVP/UVP THRESHOLD VOLTAGE

vs

VREG5 OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

OUTPUT CURRENT

150

5.05

5.00

4.95

4.90

140

130

120

110

100

90

80

70

60

50

40

-50

0

50

100

150

T

- Junction Temperature - °C

J

0

20

40

60

80

100

I

- VREG5 Output Current - mA

VREG5

Figure 19.

Figure 20.

14

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TYPICAL CHARACTERISTICS (continued)

VREG3 OUTPUT VOLTAGE

vs

VREF OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.35

2.020

2.015

2.010

2.005

2.000

1.995

1.990

1.985

1.980

3.3

3.25

3.2

0

20

40

60

80

100

0

20

40

60

80

100

I

- VREG3 Output Current - mA

VREG3

I

- VREF Output Current - mA

VREF

Figure 21.

Figure 22.

5-V OUTPUT VOLTAGE

vs

3.3-V OUTPUT VOLTAGE

vs

OUTPUT CURRENT

5.075

3.360

OOA

5.050

3.330

3.300

3.270

3.240

Auto-skip

PWM Only

5.025

5.000

4.975

4.950

Auto-skip

PWM Only

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

I_OUT1- 5-V Output Current - A

I_OUT2- 3.3-V Output Current - A

Figure 23.

Figure 24.

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TYPICAL CHARACTERISTICS (continued)

5-V OUTPUT VOLTAGE

vs

3.3-V OUTPUT VOLTAGE

vs

INPUT VOLTAGE

5.075

5.050

5.025

5.000

4.975

4.950

3.360

3.330

3.300

3.270

3.240

I_O= 0A

I_O= 6A

I_O= 0A

I_O= 6A

6

8

10 12 14 16 18 20 22 24 26

6

8

10 12 14 16 18 20 22 24 26

V

_IN- Input Voltage - V

V

_IN- Input Voltage - V

Figure 25.

Figure 26.

5-V EFFICIENCY

vs

3.3-V EFFICIENCY

vs

OUTPUT CURRENT

100

80

60

40

20

0

100

80

60

40

20

0

Auto-skip

VIN=8V

VIN=12V

VIN=20V

VIN=12V

VIN=20V

OOA

PWM Only 5-V Switcher ON

0.1 10

PWM Only

0.01

0.001

0.01

1

0.001

0.1

1

10

I_OUT2- 3.3-V Output Current - A

I_OUT1- 5-V Output Current - A

Figure 27.

Figure 28.

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TYPICAL CHARACTERISTICS (continued)

5-V Load Transient Response

3.3-V Load Transient Response

V

OUT2

(100mV/div)

V

OUT1

(100mV/div)

I

(5A/div)

I

(5A/div)

IND

I

(5A/div)

I

(5A/div)

OUT2

OUT1

Figure 29.

5-V Startup Waveforms

Figure 30.

3.3-V Startup Waveforms

ENTRIP2 (2V/div)

ENTRIP1 (2V/div)

V

OUT1

(2V/div)

V

OUT2

(2V/div)

PGOOD (2V/div)

Figure 31.

Figure 32.

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TYPICAL CHARACTERISTICS (continued)

5-V Switchover Waveforms

3.3-V Switchover Waveforms

VREG5 (200mV/div)

VREG3 (200mV/div)

V

OUT2

(200mV/div)

V

OUT1

(200mV/div)

Figure 33.

5-V Soft-stop Waveforms

ENTRIP1 (5V/div)

Figure 34.

3.3-V Soft-stop Waveforms

ENTRIP2 (5V/div)

V

OUT1

(2V/div)

V

OUT2

(2V/div)

PGOOD (5V/div)

DRVL1 (5V/div)

PGOOD (5V/div)

DRVL2 (5V/div)

Figure 35.

Figure 36.

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APPLICATION INFORMATION

PWM Operations

The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width

modulation (PWM) controller. It supports a proprietary D-CAP™ mode. D-CAP™ mode does not require external

compensation circuit and is suitable for low external component count configuration when used with appropriate

amount of ESR at the output capacitor(s).

At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ‘ON’ state. This

MOSFET is turned off, or becomes ‘OFF’ state, after internal one shot timer expires. This one shot is determined

by V_INand V_OUTto keep frequency fairly constant over input voltage range, hence it is called adaptive on-time

control. The MOSFET is turned on again when the feedback point voltage, VFB, decreased to match with internal

2-V reference. The inductor current information is also monitored and should be below the over current threshold

to initiate this new cycle. Repeating operation in this manner, the controller regulates the output voltage. The

synchronous bottom or the “rectifying” MOSFET is turned on at the beginning of each ‘OFF’ state to keep the

conduction loss minimum.The rectifying MOSFET is turned off before the top MOSFET turns on at next switching

cycle or when inductor current information detects zero level. In the auto-skip mode or the OOA skip mode, this

enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is

kept over broad range of load current.

Adaptive On-Time Control and PWM Frequency

TPS51125 does not have a dedicated oscillator on board. However, the part runs with pseudo-constant

frequency by feed-forwarding the input and output voltage into the on-time, one-shot timer. The on-time is

controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio will

be kept as VOUT/VIN technically with the same cycle time. The frequencies are set by TONSEL terminal

connection as Table 2.

Table 2. TONSEL Connection and Switching Frequency

SWITCHING FREQUENCY

TONSEL CONNECTION

CH1

CH2

GND

VREF

200 kHz

245 kHz

300 kHz

365 kHz

250 kHz

305 kHz

375 kHz

460 kHz

VREG3

VREG5

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Loop Compensation

From small-signal loop analysis, a buck converter using D-CAP^TMmode can be simplified as below.

VIN

R1

DRVH

DRVL

Lx

I_L

PWM

Control

logic

&

VFB

Ic

Io

+

Driver

+

R2

2V

ESR

Co

Vc

RL

Voltage Divider

Switching Modulator

Output Capacitor

Figure 37. Simplifying the Modulator

The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM

comparator determines the timing to turn on high-side MOSFET. The gain and speed of the comparator is high

enough to keep the voltage at the beginning of each on cycle substantially constant. For the loop stability, the

0dB frequency, f₀, defined below need to be lower than 1/4 of the switching frequency.

1

f_sw

f =

£

0

2p ´ ESR´Co

4

(1)

As f₀is determined solely by the output capacitor's characteristics, loop stability of D-CAP^TMmode is determined

by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of

several 100 µF and ESR in range of 10 mΩ. These will make f₀in the order of 100 kHz or less and the loop will

be stable. However, ceramic capacitors have f₀at more than 700 kHz, which is not suitable for this operational

mode.

Ramp Signal

The TPS51125 adds a ramp signal to the 2-V reference in order to improve its jitter performance. As described in

the previous section, the feedback voltage is compared with the reference information to keep the output voltage

in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle

is improved. Therefore the operation becomes less jitter and stable. The ramp signal is controlled to start with

-20mV at the beginning of ON-cycle and to become 0 mV at the end of OFF-cycle in steady state. By using this

scheme, the TPS51125 improve jitter performance without sacrificing the reference accuracy.

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Light Load Condition in Auto-Skip Operation

The TPS51125 automatically reduces switching frequency at light load conditions to maintain high efficiency.

This reduction of frequency is achieved smoothly and without increase of V_OUTripple. Detail operation is

described as follows. As the output current decreases from heavy load condition, the inductor current is also

reduced and eventually comes to the point that its ‘valley’ touches zero current, which is the boundary between

continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero

inductor current is detected. As the load current further decreased, the converter runs in discontinuous

conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next

‘ON’ cycle. The ON time is kept the same as that in the heavy load condition. In reverse, when the output current

increase from light load to heavy load, switching frequency increases to the preset value as the inductor current

reaches to the continuous conduction. The transition load point to the light load operation I_OUT(LL)(i.e. the

threshold between continuous and discontinuous conduction mode) can be calculated as follows;

-

)´

⁽V _INV _OUT

V _IN

V

1

OUT

=

´

I_{OUT( LL )}

2´ L´ f

(2)

where f is the PWM switching frequency.

Switching frequency versus output current in the light load condition is a function of L, V_INand V_OUT, but it

decreases almost proportional to the output current from the I_OUT(LL)given above. For example, it will be 60 kHz

at I_OUT(LL)/5 if the frequency setting is 300 kHz.

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Out-of-Audio™ Light-Load Operation

Out-of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above

acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion

efficiency. When the Out-of-Audio™ operation is selected, OOA control circuit monitors the states of both

MOSFET and force to change into the ‘ON’ state if both of MOSFETs are off for more than 32 µs. This means

that the top MOSFET is turned on even if the output voltage is higher than the target value so that the output

capacitor is tends to be overcharged.

The OOA control circuit detects the over-voltage condition and begins to modulate the on time to keep the output

voltage regulated. As a result, the output voltage becomes 0.5% higher than normal light-load operation.

Enable and Soft Start

EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those

three regulators and minimize the shutdown supply current to 10 µA. Pulling this node up to 3.3 V or 5 V will turn

the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become

ready to enable at this standby mode. The TPS51125 has an internal, 1.6 ms, voltage servo softstart for each

channel. When the ENTRIPx pin becomes higher than the enable threshold voltage, which is typically 430 mV,

an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output

voltage is maintained during start up. As TPS51125 shares one DAC with both channels, if ENTRIPx pin

becomes higher than the enable threshold voltage while another channel is starting up, soft start is postponed

until another channel soft start has completed. If both of ENTRIP1 and ENTRIP2 become higher than the enable

threshold voltage at a same time (within 60 µs), both channels start up at same time.

Table 3. Enabling State

EN0

GND

ENTRIP1

ENTRIP2

VREF

Off

VREG5

Off

VREG3

Off

CH1

Off

On

Off

On

Off

On

Off

On

CH2

Off

On

Off

On

VCLK

Off

Don’t Care

Off

Don’t Care

Off

R to GND

Open

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

Open

On

Off

On

Open

Off

On

Off

Open

On

VREG5/VREG3 Linear Regulators

There are two sets of 100-mA standby linear regulators which outputs 5 V and 3.3 V, respectively. The VREG5

serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers.

The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode.

Add a ceramic capacitor with a value between 10 µF and 22 µF placed close to the VREG5 and VREG3 pins to

stabilize LDOs.

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VREG5 Switch Over

When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal

5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The

510-µs powergood delay helps a switch over without glitch.

VREG3 Switch Over

When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated,

internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over

MOSFET. The 510-µs powergood delay helps a switch over without glitch.

Powergood

The TPS51125 has one powergood output that indicates 'high' when both switcher outputs are within the targets

(AND gated). The powergood function is activated with 2-ms internal delay after ENTRIPx goes high. If the

output voltage becomes within +/-5% of the target value, internal comparators detect power good state and the

powergood signal becomes high after 510-µs internal delay. Therefore PGOOD goes high around 2.5 ms after

ENTRIPx goes high. If the output voltage goes outside of +/-10% of the target value, the powergood signal

becomes low after 2-µs internal delay. The powergood output is an open drain output and is needed to be pulled

up outside.

Output Discharge Control

When ENTRIPx is low, the TPS51125 discharges outputs using internal MOSFET which is connected to VOx

and GND. The current capability of these MOSFETs is limited to discharge slowly.

Low-Side Driver

The low-side driver is designed to drive high current low R_DS(on)N-channel MOSFET(s). The drive capability is

represented by its internal resistance, which are 4 Ω for VREG5 to DRVLx and 1.5 Ω for DRVLx to GND. A dead

time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and

bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from VREG5 supply. The instantaneous

drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current

is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current as well as the

high-side gate drive current times 5 V makes the driving power which need to be dissipated from TPS51125

package.

High-Side Driver

The high-side driver is designed to drive high current, low R_DS(on)N-channel MOSFET(s). When configured as a

floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by

the gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying

capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance, which are 4

Ω for VBSTx to DRVHx and 1.5Ω for DRVHx to LLx.

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VCLK for Charge Pump

270-kHz clock signal can be used for charge pump circuit to generate approximately 15-V dc voltage. The clock

signal becomes available when EN0 becomes higher than 2.4 V or open state. Note that the clock driver uses

VO1 as its power supply. Regardless of enable or disable of VCLK, power consumption of the TPS51125 is

almost the same. Therefore even if VCLK is not used, one can let EN0 pin open or supply logic ‘high’, as shown

in Figure 38, and let VCLK pin open. This approach further reduces the external part count.

3.3V

TPS51125

EN0

13

EN0

13

Control

Input

GND

15

GND

15

Control

Input

(b) Control by Logic

(a) Control by MOSFET switch

Figure 38. Control Example of EN0 Master Enable

VCLK 18

VO1 (5V)

100nF

-

15V/10mA

D2

D0

D1

D4

1uF

100nF

PGND

Figure 39. 15-V / 10-mA Charge Pump Configuration

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Current Protection

TPS51125 has cycle-by-cycle over current limiting control. The inductor current is monitored during the ‘OFF’

state and the controller keeps the ‘OFF’ state during the inductor current is larger than the over current trip level.

In order to provide both good accuracy and cost effective solution, TPS51125 supports temperature

compensated MOSFET R_DS(on)sensing. ENTRIPx pin should be connected to GND through the trip voltage

setting resistor, R_TRIP. ENTRIPx terminal sources I_TRIPcurrent, which is 10 µA typically at room temperature, and

the trip level is set to the OCL trip voltage V_TRIPas below. Note that the V_TRIPis limited up to about 205 mV

internally.

R ( kW )´ I_trip( mA)

trip

V ( mV ) =

- 24( mV )

trip

9

(3)

The inductor current is monitored by the voltage between GND pin and LLx pin so that LLx pin should be

connected to the drain terminal of the bottom MOSFET properly. Itrip has 4500 ppm/°C temperature slope to

compensate the temperature dependency of the R_DS(on). GND is used as the positive current sensing node so

that GND should be connected to the proper current sensing device, i.e. the source terminal of the bottom

MOSFET.

As the comparison is done during the ‘OFF’ state, V_TRIPsets valley level of the inductor current. Thus, the load

current at over current threshold, I_OCP, can be calculated as follows;

I_ocp=V

R_dson+ I_ripple

2

trip

(4)

V

1

(V_IN-V_OUT)´V_OUT

trip

=

+

R_dson2´ L´ f

´

V_IN

(5)

In an over current condition, the current to the load exceeds the current to the output capacitor thus the output

voltage tends to fall down. Eventually, it ends up with crossing the under voltage protection threshold and

shutdown both channels.

Over/Under Voltage Protection

TPS51125 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback

voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit

latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.

Also, TPS51125 monitors VOx voltage directly and if it becomes greater than 5.75 V the TPS51125 turns off the

top MOSFET driver.

When the feedback voltage becomes lower than 60% of the target voltage, the UVP comparator output goes

high and an internal UVP delay counter begins counting. After 32 µs, TPS51125 latches OFF both top and

bottom MOSFETs drivers, and shut off both drivers of another channel. This function is enabled after 2 ms

following ENTRIPx has become high.

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UVLO Protection

TPS51125 has VREG5 under voltage lock out protection (UVLO). When the VREG5 voltage is lower than UVLO

threshold voltage both switch mode power supplies are shut off. This is non-latch protection. When the VREG3

voltage is lower than (VO2 - 1 V), both switch mode power supplies are also shut off

Thermal Shutdown

TPS51125 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150°C),

TPS51125 is shut off including LDOs. This is non-latch protection.

External Parts Selection

The external components selection is much simple in D-CAP™ Mode.

1. Determine the Value of R1 and R2

Recommended R2 value is from 10 kΩ to 20 kΩ. Determine R1 using equation as below.

(

V

^{- 2.0})

out

2.0

R1=

´ R2

(6)

2. Choose the Inductor

The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum

output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable

operation.

-

V _IN(max)V _OUTV _OUT

´

-

)

V _IN(max)V _OUTV _OUT

´

(

)

(

1

3

L =

´

=

´

´ f

V _IN(max)

I _{IND( ripple )}

I_OUT(max)

(7)

The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak

inductor current before saturation. The peak inductor current can be estimated as follows.

V

(V_IN(max)-V_OUT)´V_OUT

1

trip

=

+

R_{DS( on )}L´ f

´

I _{IND( peak )}

V_IN(max)

(8)

3. Choose the Output Capacitor(s)

Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet

required ripple voltage above. A quick approximation is as shown in Equation 9. This equation is based on that

required output ripple slope is approximately 20 mV per T_SW(switching period) in terms of VFB terminal voltage.

D stands for duty factor.

´20[ mV ] ´(1- D )

2[V ] ´

20[ mV ] ´ L´ f

2[V ]

_{ESR =}V _OUT

=

I

ripple

(9)

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Layout Considerations

Certain points must be considered before starting a layout work using the TPS51125.

•

TPS51125 has only one GND pin and special care of GND trace design makes operation stable, especially

when both channels operate. Group GND terminals of output voltage divider of both channels and the VREF

capacitor as close as possible, connect them to an inner GND plane with PowerPad, overcurrent setting

resistor, EN0 pull-down resistor and EN0 bypass capacitor as shown in the thin GND line of Figure 40. This

trace is named Signal Ground (SGND). Group ground terminals of VIN capacitor(s), VOUT capacitor(s) and

source of low-side MOSFETs as close as possible, and connect them to another inner GND plane with GND

pin of the device, GND terminal of VREG3 and VREG5 capacitors as shown in the bold GND line of

Figure 40. This trace is named Power Ground (PGND). SGND and 15-V charge-pump circuit should be

connected to PGND at the middle point between ground terminal of VOUT capacitors.

•

Inductor, VOUT capacitor(s), VIN capacitor(s) and MOSFETs are the power components and should be

placed on one side of the PCB (solder side). Power components of each channel should be at the same

distance from the TPS51125. Other small signal parts should be placed on another side (component side).

Inner GND planes above should shield and isolate the small signal traces from noisy power lines.

•

PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side MOSFET

and high-voltage side of the inductor, should be as short and wide as possible.

VREG5 and VREG3 require at least 10-µF, VREF requires a 220-nF ceramic bypass capacitor which should

be placed close to the device and traces should be no longer than 10 mm.

Connect the overcurrent setting resistors from ENTRIPx to SGND and close to the device, right next to the

device if possible.

The discharge path (VOx) should have a dedicated trace to the output capacitor; separate from the output

voltage sensing trace. When LDO5 is switched over Vo1 trace should be 1.5 mm with no loops. When LDO3

is switched over and loaded Vo2 trace should also be 1.5 mm with no loops. There is no restriction for just

monitoring Vox. Make the feedback current setting resistor (the resistor between VFBx to SGND close to the

device. Place on the component side and avoid vias between this resistor and the device.

•

Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use 0.65-mm (25 mils) or wider trace and via(s) of at least 0.5

mm (20 mils) diameter along this trace.

All sensitive analog traces and components such as VOx, VFBx, VREF, GND, EN0, ENTRIPx, PGOOD,

TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx,

DRVHx and VCLK nodes to avoid coupling. Connect 330-pF to 1-nF ceramic bypass capacitor to EN0 in

parallel with 620-kΩ resistor when VCLK is disabled.

•

Traces for VFB1 and VFB2 should be short and laid apart each other to avoid channel to channel

interference.

In order to effectively remove heat from the package, prepare thermal land and solder to the package’s

thermal pad. Three by three or more vias with a 0.33-mm (13 mils) diameter connected from the thermal land

to the internal ground plane should be used to help dissipation. This thermal land underneath the package

should be connected to SGND, and should NOT be connected to PGND.

SGND

VIN

220n

F

VIN

TPS51125

3

5

2

VFB2

VREF

VFB1

Vout2

Vout1

DRVL2

DRVL1

12

19

PGND

PowerPAD

VREG5

17

GND

VREG3

15V Out

15

8

Charge-

pump

10u

F

10u

F

VCLK

SGND

Figure 40. GND system of DC/DC converter using the TPS51125

Submit Documentation Feedback

27

Product Folder Link(s): TPS51125

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Nov-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

12

TPS51125RGER

TPS51125RGET

RGE

24

SITE 41

4.3

1.5

8

12

Q2

180

12

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Nov-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TPS51125RGER

TPS51125RGET

RGE

24

SITE 41

346.0

190.0

346.0

212.7

29.0

31.75

Pack Materials-Page 2

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Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

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Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

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interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS51125RGETG4
厂家：	TEXAS INSTRUMENTS
描述：	具有 100mA LDO 和 Out-of-Audio™ 的 4.5V 至 28V 双通道同步降压控制器 \| RGE \| 24 \| -40 to 85 开关控制器开关式稳压器开关式控制器电源电路开关式稳压器或控制器
文件：	总33页 (文件大小：871K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS51125RGETG4 [TI]

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