TPS5210PWP [TI]
PROGRAMMABLE SYNCHRONOUS-BUCK REGULATOR CONTROLLER; 可编程同步降压稳压器控制器型号: | TPS5210PWP |
厂家: | TEXAS INSTRUMENTS |
描述: | PROGRAMMABLE SYNCHRONOUS-BUCK REGULATOR CONTROLLER |
文件: | 总29页 (文件大小:417K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS5210
PROGRAMMABLE SYNCHRONOUS-BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
DW OR PWP PACKAGE
±1% Reference Over Full Operating
Temperature Range
(TOP VIEW)
Synchronous Rectifier Driver for Greater
Than 90% Efficiency
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IOUT
DROOP
OCP
VHYST
VREFB
VSENSE
ANAGND
SLOWST
BIAS
LODRV
LOHIB
DRVGND
LOWDR
DRV
PWRGD
VID0
VID1
VID2
VID3
2
3
Programmable Reference Voltage Range of
1.3 V to 3.5 V
4
5
User–Selectable Hysteretic Type Control
6
VID4
Droop Compensation for Improved Load
Transient Regulation
7
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
8
9
Adjustable Overcurrent Protection
Programmable Softstart
10
11
12
13
14
Overvoltage Protection
Active Deadtime Control
V
CC
Power Good Output
Internal Bootstrap Schottky Diode
Low Supply Current . . . 3-mA Typ
description
The TPS5210 is a synchronous-buck regulator controller which provides an accurate, programmable supply
voltage to microprocessors. An internal 5-bit DAC is used to program the reference voltage to within a range
of 1.3 V to 3.5 V. The output voltage can be set to be equal to the reference voltage or to some multiple of the
reference voltage. A hysteretic controller with user-selectable hysteresis and programmable droop
compensation is used to dramatically reduce overshoot and undershoot caused by load transients. Propagation
delay from the comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover
protection for the output drivers combine to eliminate destructive faults in the output FETs. The softstart current
source is proportional to the reference voltage, thereby eliminating variation of the softstart timing when
changes are made to the output voltage. PWRGD monitors the output voltage and pulls the open-collector
output low when the output drops 7% below the nominal output voltage. An overvoltage circuit disables the
output drivers if the output voltage rises 15% above the nominal value. The inhibit pin can be used to control
powersequencing. Inhibitandundervoltagelockoutassuresthe12-Vsupplyvoltageandsystemsupplyvoltage
(5 V or 3.3 V) are within proper operating limits before the controller starts. Single-supply (12 V) operation is
easily accomplished using a low-current divider for the required 5-V signals. The output driver circuits include
2-A drivers with internal 8-V gate-voltage regulators. The high-side driver can be configured either as a
ground-referenced driver or as a floating bootstrap driver. The TPS5210 is available in a 28-pin SOIC package
and a 28-pin TSSOP PowerPAD package. It operates over a junction temperature range of 0°C to 125°C.
AVAILABLE OPTIONS
PACKAGES
T
J
SOIC
(DW)
TSSOP
(PWP)
0°C to 125°C
TPS5210DW
TPS5210PWPR
The DW package is available taped and reeled. Add R suffix to device
type (e.g., TPS5210DWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
ANAGND
7
PWRGD
28
LOSENSE
20
IOUTLO HISENSE
CC
VID0
VID1
VID2
VID3
VID4
15
21
19
11111
Decode
NOCPU
UVLO
2 V
+
1
22
3
IOUT
INHIBIT
OCP
–
2x
Shutdown
10 V
S
R
Q
V
CC
Fault
Rising
Edge
Delay
Deglitch
+
100 mV
HIGHDR
Deglitch
V
PGD
HIGHIN
0.93 V
ref
V
OVP
1.15 V
V
CC
ref
VSENSE
Analog Bias
Analog
Bias
PREREG
DRV REG
8
9
SLOWST
BIAS
DRV
I
VREFB
14
Slowstart
Comp
5
–
+
+
–
Bandgap
Shutdown
VID
MUX
and
16
17
CM Filters
BOOT
HIGHDR
VREF
+
Σ
+
–
200 kΩ
18
–
Decoder
Hysteresis
Comp
BOOTLO
200 kΩ
+ –
Shutdown
Hysteresis
Setting
13
12
LOWDR
DRVGND
27 26
25
24 23
5
2
4
6
11
10
LODRV
VID0 VID1 VID2 VID3 VID4 VREFB DROOP VHYST VSENSE
LOHIB
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
7
ANAGND
BIAS
Analog ground
9
O
I
Analog BIAS pin. A 1-µF ceramic capacitor should be connected from BIAS to ANAGND.
Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO.
BOOT
16
18
BOOTLO
O
Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTLO to PGND for ground reference drive configuration.
DROOP
2
I
Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load
current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND.
DRV
14
12
17
19
O
Drive regulator for the FET drivers. A 1-µF ceramic capacitor should be connected from DRV to DRVGND.
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
DRVGND
HIGHDR
HISENSE
O
I
High drive. Output drive to high-side power switching FETs
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT
IOUT
22
1
I
Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V
or 5 V).
O
Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
high-side FETs. The voltage on this pin equals 2×Rds(on)×IOUT. In applications where very accurate current
sensingisrequired, asenseresistorshouldbeconnectedbetweentheinputsupplyandthedrainofthehigh-side
FETs.
IOUTLO
21
O
Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic
capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs
are off. Capacitance range should be between 0.033 µF and 0.1 µF.
LODRV
LOHIB
10
11
I
I
Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE
20
I
Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
LOWDR
OCP
13
3
O
I
Low drive. Output drive to synchronous rectifier FETs
Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
PWRGD
28
O
Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SLOWST
8
O
I
Slow Start (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
Slowstart current = I
/5
VREFB
V
15
4
12-V supply. A 1-µF ceramic capacitor should be connected from V
to DRVGND.
CC
CC
VHYST
HYSTERESIS set pin. The hysteresis is set with a resistor divider from V to ANAGND.
REFB
The hysteresis window = 2 × (V
Voltage Identification input 0
Voltage Identification input 1
Voltage Identification input 2
Voltage Identification input 3
– V
)
HYST
REFB
VID0
VID1
VID2
VID3
VID4
27
26
25
24
23
I
I
I
I
I
Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for
settingthe output voltage is located in Table 1. Internally pulled up to 5 V with a resistor divider biased from V
.
CC
VREFB
5
6
O
I
Buffered reference voltage from VID network
VSENSE
Voltage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended an RC low pass filter be connected at this pin to filter noise.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
detailed description
V
REF
The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to V . The VID codes conform
CC
to the Intel VRM 8.3 DC-DC Converter Specification for voltage settings between 1.8 V and 3.5 V, and they are
decrementedby50mV,downto1.3V,forthelowerVIDsettings.VoltageshigherthanV
usinganexternaldivider. RefertoTable1fortheVIDcodesettings. TheoutputvoltageoftheVIDnetwork, V
canbeimplemented
REF
,
REF
is within ±1% of the nominal setting over the VID range of 1.3 V to 2.5 V, including a junction temperature range
of 5°C to +125°C, and a V supply voltage range of 11.4 V to 12.6 V. The output of the reference/VID network
CC
is indirectly brought out through a buffer to the V
pin. The voltage on this pin will be within 2% of V
. It
REFB
REF
is not recommended to drive loads with V
because the current drawn from V
, other than setting the hysteresis of the hysteretic comparator,
sets the charging current for the slowstart capacitor. Refer to the
REFB
REFB
slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on V . The 2 external resistors form a resistor divider from V
REF
REFB
toANAGND, withtheoutputvoltageconnectingtotheV
to twice the voltagedifferencebetween the V
pin. The hysteresis of the comparator will be equal
HYST
and V
pins. The propagation delay from the comparator
REFB
HYST
inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to eitherDRV or V
.
CC
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 60-Ω switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls
the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
detailed description (continued)
droop compensation
The droop compensation network reduces the load transient overshoot/undershoot on V , relative to V
. V
O
O
REF
is programmed to a voltage greater than V
by an external resistor divider from V to VSENSE to reduce the
REF
O
undershoot on V during a low-to-high load transient. The overshoot during a high-to-low load transient is
O
reduced by subtracting the voltage on DROOP from V
resistor divider, and connected to DROOP.
. The voltage on IOUT is divided with an external
REF
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
V
undervoltage lockout (UVLO)
CC
The undervoltage lockout circuit disables the controller while the V
supply is below the 10-V start threshold
CC
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When V exceeds the start threshold, the short across the slowstart capacitor is released and
CC
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which V powers up. A capacitor is connected between SLOWST and
O
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of C
is proportional to the reference voltage. By making the charging
slowst
currentproportionaltoV
, thepower-uptimeforV willbeindependentofV
. Thus, C
canremain
REF
O
REF
SLOWST
the same value for all VID settings. The slowstart charging current is determined by the following equation:
I
= I(V ) / 5 (amps)
slowstart
REFB
Where I(V
) is the current flowing out of V
.
REFB
REFB
It is recommended that no additional loads be connected to V
hysteresis voltage. The maximum current that can be sourced by the V
setting the slowstart time is:
, other than the resistor divider for setting the
REFB
circuit is 500 µA. The equation for
REFB
t
= 5 × C
× R
(seconds)
SLOWST
SLOWST
VREFB
Where R
is the total external resistance from V to ANAGND.
REFB
VREFB
power good
The power-good circuit monitors for an undervoltage condition on V . If V is7%belowV , thenthePWRGD
REF
O
O
pin is pulled low. PWRGD is an open-drain output.
overvoltage protection
The overvoltage protection (OVP) circuit monitors V for an overvoltage condition. If V is 15% above V ,
REF
O
O
then a fault latch is set and both output drivers are turned off. The latch will remain set until V goes below the
CC
undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section
for information on how to protect the microprocessor against overvoltages due to a shorted fault across the
high-side power FET.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
detailed description (continued)
overcurrent protection
The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage
connected to the OCP pin. If the voltage on OCP exceeds 100 mV, then a fault latch is set and the output drivers
are turned off. The latch will remain set until V
goes below the undervoltage lockout value. A 3-µs deglitch
CC
timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against
a short-to-ground fault on the terminal common to both power FETs.
drive regulator
The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V. The minimum
short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND.
LODRV
TheLODRVcircuitisdesignedtoprotectthemicroprocessoragainstovervoltagesthatcanoccurifthehigh-side
power FETs become shorted. External components to sense an overvoltage condition are required to use this
feature. When an overvoltage fault occurs, the low-side FETs are used as a crowbar. LODRV is pulled low and
the low-side FET will be turned on, overriding all control signals inside the TPS5210 controller. The crowbar
action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse
in series with V should be added to disconnect the short-circuit.
in
Table 1. Voltage Identification Codes
VID TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
V
REF
VID4
0
VID3
1
VID2
1
VID1
1
VID0
1
(Vdc)
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
No CPU
2.10
2.20
2.30
2.40
2.50
2.60
0
1
1
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
0
1
1
0
0
1
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
Table 1. Voltage Identification Codes (Continued)
VID TERMINALS
V
REF
(0 = GND, 1 = floating or pull-up to 5 V)
VID4
VID3
VID2
VID1
VID0
(Vdc)
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
†
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)
Supply voltage range, V
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
CC
Input voltage range: BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
INHIBIT, VIDx, LODRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7.3 V
PWRGD, OCP, DROOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
LOHIB, LOSENSE, IOUTLO, HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V
Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Output current, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mA
REFB
Short circuit duration, DRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DW
1200 mW
12 mW/°C
660 mW
630 mW
480 mW
460 mW
PWP
1150 mW
11.5 mW/°C
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
recommended operating conditions
MIN
11.4
0
MAX
13
UNIT
V
Supply voltage, V
CC
Input voltage, BOOT to DRVGND
28
V
Input voltage, BOOT to BOOTLO
0
13
V
Input voltage, INHIBIT, VIDx, LODRV, PWRGD, OCP, DROOP
Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE
Input voltage, VSENSE
0
6
V
0
13
V
0
4.5
±0.2
0.4
V
Voltage difference between ANAGND and DRVGND
0
V
†
Output current, V
0
mA
REFB
Not recommended to load V
†
other than to set hystersis since I
sets slowstart time.
VREFB
REFB
electrical characteristics over recommended operating virtual junction temperature range,
= 12 V, I = 0 A (unless otherwise noted)
V
CC
DRV
reference/voltage identification
PARAMETER
TEST CONDITIONS
= 11.4 to 12.6 V, 1.3 V ≤ V
MIN
–0.01
TYP
MAX
0.01
UNIT
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V
V
V
V
V
V
V
V
V
V
V
V
V
≤ 2.5 V
REF
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
REF
REF
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 11.4 to 12.6 V, V
= 2.6 V
= 2.7 V
= 2.8 V
= 2.9 V
= 3 V
–0.0104
–0.0108
–0.0112
–0.0116
–0.0120
–0.0124
–0.0128
–0.0132
–0.0136
–0.0140
–0.011
0.0104
0.0108
0.0112
0.0116
0.0120
0.0124
0.0128
0.0132
0.0136
0.0140
0.011
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Reference voltage accuracy, (Includes
offset of droop compensation net-
work)
= 3.1 V
= 3.2 V
= 3.3 V
= 3.4 V
= 3.5 V
V
REF
= 1.3 V, Hysteresis window = 30 mV
=1.3 V, Hysteresis,
T = 60°C window = 30 mV (see Note 3)
–0.008
0.008
0.0090
0.0115
J
Cumulative reference accuracy
(see Note 2)
V/V
V
= 1.9 Vv, Hysteresis,
REF
T = 60°C window = 30 mV (see Note 3)
–0.0090
J
V
= 3.5 V, Hysteresis,
REF
T = 60°C window = 30 mV (see Note 3)
–0.0115
2.25
J
VIDx
VIDx
High-level input voltage
Low-level input voltage
Output voltage
V
V
1
I
= 50 µA
V
–2%
REF
V
V +2%
REF
V
VREFB
REF
2
V
REFB
Output regulation
10 µA ≤ I ≤ 500 µA
mV
kΩ
V
O
Input resistance
VIDx = 0 V
36
73
95
5
VIDx
Input pull-up voltage divider
4.8
4.9
NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.
3. This parameter is ensured by design and is not production tested.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
electrical characteristics over recommended operating virtual junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted) (continued)
CC
DRV
power good
PARAMETER
TEST CONDITIONS
MIN
TYP
93
MAX
UNIT
REF
Undervoltage trip threshold
Low-level output voltage
High-level input current
Hysteresis voltage
90
95 %V
V
I
= 5 mA
0.5
1
0.75
V
OL
O
I
V
= 6 V
µA
OH
PWRGD
V
hys
1.3
2.9
4.5 %V
REF
slowstart
PARAMETER
TEST CONDITIONS
MIN
TYP
13
3
MAX
UNIT
V
= 0.5 V,
= 65 µA
V
= 1.3 V,
SLOWST
VREFB
Charge current
10.4
15.6
µA
I
VREFB
Discharge current
V
= 1 V
mA
mV
nA
SLOWST
Comparator input offset voltage
Comparator input bias current
Comparator hysteresis
10
100
7.5
See Note 3
10
–7.5
mV
NOTE 3: This parameter is ensured by design and is not production tested.
hysteretic comparator
PARAMETER
Input offset voltage
TEST CONDITIONS
MIN
TYP
MAX
2.5
UNIT
mV
nA
V
= 0 V (see Note 3)
–2.5
DROOP
See Note 3
– V
Input bias current
500
3.5
Hysteresis accuracy
V
= 15 mV
REFB HYST
(Hysteresis window = 30 mV)
–3.5
mV
Maximum hysteresis setting
V
REFB
– V = 30 mV
60
mV
HYST
NOTE 3: This parameter is ensured by design and is not production tested.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
electrical characteristics over recommended operating virtual junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted) (continued)
CC
DRV
high-side VDS sensing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain
2
V/V
V
= 12 V,
V
= 11.9 V,
LOSENSE
HISENSE
Differential input to V sensing amp = 100 mV
Initial accuracy
Sink current
Source current
194
206
250
mV
nA
µA
ds
≤ 13 V
IOUTLO
IOUT
5 V ≤ V
IOUTLO
= 0.5 V,
V
V
V
= 12 V,
HISENSE
IOUT
IOUTLO
500
50
= 11.5 V
V
V
= 0.05 V, V
= 12 V,
HISENSE
IOUT
IOUTLO
IOUT
Sink current
µA
= 12 V
V
V
V
= 11 V, R
IOUT
= 10 kΩ
= 10 kΩ
0
0
2
1.5
V
V
V
V
V
HISENSE
HISENSE
HISENSE
Output voltage swing
= 4.5 V, R
IOUT
= 3 V, R
= 10 kΩ
0
0.75
IOUT
High-level input voltage
Low-level input voltage
2.85
LOSENSE
V
= 4.5 V (see Note 3)
HISENSE
2.4
80
11.4 V ≤ V
≤ 12.6 V,
HISENSE
LOSENSE connected to HISENSE,
– V = 0.15 V
50
62
60
85
V
HISENSE
4.5 V ≤ V
IOUTLO
≤ 5.5 V,
HISENSE
LOSENSE connected to HISENSE,
123
144
Sample/hold resistance
Ω
V
– V
= 0.15 V
HISENSE
IOUTLO
3 V ≤ V
≤ 3.6 V,
HISENSE
LOSENSE connected to HISENSE,
V
67
69
95
75
– V
= 0.15 V
HISENSE
IOUTLO
V
V
= 12.6 V to 3 V,
HISENSE
HISENSE
CMRR
dB
– V
= 100 mV
OUTLO
NOTE 3. This parameter is ensured by design and is not production tested.
inhibit
PARAMETER
Start threshold
Hysteresis
TEST CONDITIONS
MIN
1.9
TYP
2.1
MAX
2.35
0.12
UNIT
V
V
V
0.08
1.85
0.1
Stop threshold
overvoltage protection
PARAMETER
Overvoltage trip threshold
TEST CONDITIONS
MIN
TYP
115
10
MAX
UNIT
112
120 %V
REF
Hysteresis
See Note 3
mV
NOTE 3: This parameter is ensured by design and is not production tested.
overcurrent protection
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
110
UNIT
OCP trip threshold
Input bias current
90
100
mV
nA
100
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
electrical characteristics over recommended operating virtual junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted) (continued)
CC
DRV
deadtime
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.4
UNIT
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
2.4
LOHIB
V
See Note 3
See Note 3
3
LOWDR
V
1.7
NOTE 3: This parameter is ensured by design and is not production tested.
LODRV
PARAMETER
TEST CONDITIONS
MIN
TYP
TYP
MAX
UNIT
High-level input voltage
LODRV
1.85
V
Low-level input voltage
0.95
droop compensation
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Initial accuracy
V
= 50 mV
46
54
mV
DROOP
drive regulator
PARAMETER
Output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
11.4 V ≤ V
≤ 12.6 V,
≤ 50 mA
I
= 50 mA
7
9
CC
DRV
Output regulation
1 mA ≤ I
100
mV
mA
DRV
Short-circuit current
100
bias regulator
PARAMETER
Output voltage
TEST CONDITIONS
≤ 12.6 V, See Note 4
MIN
TYP
MAX
UNIT
11.4 V ≤ V
6
V
CC
NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS5210 controller. External loads should not be driven by the bias
regulator.
input undervoltage lockout
PARAMETER
Start threshold
TEST CONDITIONS
MIN
9.25
1.9
TYP
10 10.75
2.2
MAX
UNIT
V
V
V
Hysteresis
2
Stop threshold
7.5
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
electrical characteristics over recommended operating virtual junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted) (continued)
CC
DRV
output drivers
PARAMETER
TEST CONDITIONS
Duty cycle < 2%, < 100 µs,
T = 125°C,
MIN
TYP
MAX
UNIT
t
V
pw
High-side sink
High-side source
Low-side sink
2
– V
= 6.5 V,
BOOTLO
J
BOOT
= 1.5 V (source) or 6 V (sink),
V
HIGHDR
See Note 3
2
2
2
Peak output
current
(see Note 5)
A
Duty Cycle < 2%,
T = 125°C,
t
V
< 100 µs,
= 6.5 V,
pw
J
DRV
= 1.5 V (source) or 5 V (sink),
V
LOWDR
See Note 3
Low-side source
High-side sink
High-side source
Low-side sink
3
45
T = 125°C,
V
– V
= 6.5 V,
BOOTLO
J
BOOT
= 6 V (source) or 0.5 V (sink)
Output
resistance
(see Note 5)
V
HIGHDR
Ω
5.7
45
T = 125°C,
V
= 6.5 V,
J
DRV
= 6 V (source) or 0.5 V (sink)
V
LOWDR
Low-side source
NOTES: 3. This parameter is ensured by design and is not production tested.
5. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the R
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
of the MOSFET transistor when
ds(on)
supply current
PARAMETER
TEST CONDITIONS
MIN
11.4
TYP
MAX
UNIT
Supply voltage
range
V
12
13
V
CC
CC
V
V
= 5 V,
> 10.75 V at startup,
VID code ≠ 11111,
INHIBIT
CC
3
5
10
V
= 0 V
BOOTLO
Quiescent
current
V
V
C
= 5 V,
> 10.75 V at startup,
= 50 pF,
HIGHDR
= 200 kHz,
VID code ≠ 11111,
INHIBIT
CC
V
mA
V
C
= 0 V,
= 50 pF,
LOWDR
BOOTLO
f
See Note 3
SWX
V
V
= 0 V or VID code = 11111 or V
< 9.25 V at startup,
CC
INHIBIT
BOOT
80
µA
High-side
driver
quiescent
= 13 V,
V
= 0 V
BOOTLO
V
V
C
= 5 V,
VID code ≠ 11111, V
> 10.75 V at startup,
CC
INHIBIT
BOOT
= 13 V,
= 50 pF,
V
= 0 V,
2
mA
BOOTLO
f = 200 kHz (see Note 3)
SWX
current
HIGHDR
NOTE 3: This parameter is ensured by design and is not production tested.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
switching characteristics over recommended operating virtual-junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted)
CC
DRV
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSENSE to HIGHDR or
LOWDR (excluding dead-
time)
1.3 V ≤ V
VREF
(see Note 3)
≤ 3.5 V, 10 mV overdrive
150
250
ns
OCP comparator
1
1
Propagation delay
OVP comparator
See Note 3
µs
PWRGD comparator
SLOWST comparator
1
Overdrive = 10 mV (see Note 3)
560
900
60
ns
C
= 9 nF,
V
= 6.5 V,
L
BOOT
T = 125°C
HIGHDR output
LOWDR output
HIGHDR output
LOWDR output
V
= 0 V,
BOOTLO
= 9 nF,
J
Rise time
Fall time
ns
C
V
= 6.5 V,
DRV
L
60
60
60
T = 125°C
J
C
= 9 nF,
V
= 6.5 V,
BOOT
L
V
= 0 V,
T = 125°C
J
BOOTLO
= 9 nF,
ns
C
V
= 6.5 V,
DRV
L
T = 125°C
J
Deglitch time (Includes
comparator propagation
delay)
OCP
OVP
2
2
5
5
See Note 3
µs
V
V
= 12 V,
pulsed from 12 V to 11.9 V,
HISENSE
IOUTLO
2
3
3
100 ns rise/fall times
(see Note 3)
V
V
= 4.5 V,
HISENSE
pulsed from 4.5 V to 4.4 V,
Response time
High-side VDS sensing
µs
IOUTLO
100 ns rise/fall times (see Note 3)
V
V
= 3 V,
HISENSE
pulsed from 3 V to 2.9 V,
IOUTLO
100 ns rise/fall times (see Note 3)
Short-circuit protection
rising-edge delay
SCP
LOSENSE = 0 V (see Note 3)
300
30
500
100
100
ns
ns
ns
V
sensing sample/hold
3 V ≤ V
≤ 11 V,
HISENSE
DS
Turn-on/turn-off delay
Crossover delay time
switch
V
= V
(see Note 3)
LOSENSE
HISENSE
LOWDR to HIGHDRV, and
LOHIB to LOWDR
See Note 3
30
Prefilter pole frequency
Propagation delay
Hysteretic comparator
LODRV
See Note 3
See Note 3
5
MHz
ns
400
NOTE 3: This parameter is ensured by design and is not production tested.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
TYPICAL CHARACTERISTICS
SLOWSTART TIME
vs
SLOWSTART CAPACITANCE
SLOWSTART TIME
vs
SUPPLY CURRENT (VREFB)
100
10
1000
100
V
I
= 2 V
= 100 µA
(VREFB)
(VREFB)
V
= 2 V
= 0.1 µF
(VREFB)
C
S
J
T
J
= 25°C
T
= 25°C
1
0.1
0
10
1
0.0001
0.0010
0.0100
0.1000
1
1
10
100
1000
Slowstart Capacitance – µF
I
– Supply Current (VREFB) – µA
CC
Figure 1
Figure 2
DRIVER
OUTPUT RISE TIME
vs
DRIVER
OUTPUT FALL TIME
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
100
1000
100
T
J
= 25°C
T
J
= 25°C
High Side
Low Side
High Side
Low Side
10
10
1
0.1
1
0.1
1
10
100
1
10
100
C
– Load Capacitance – nF
C
– Load Capacitance – nF
L
L
Figure 3
Figure 4
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
TYPICAL CHARACTERISTICS
OVP THRESHOLD
vs
JUNCTION TEMPERATURE
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
118
117
105
103
101
99
116
115
114
97
113
112
95
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 5
Figure 6
INHIBIT START THRESHOLD VOLTAGE
INHIBIT HYSTERESIS VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.1
150
125
2.05
2
100
75
1.95
1.9
50
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 7
Figure 8
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
TYPICAL CHARACTERISTICS
UVLO START THRESHOLD VOLTAGE
UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
10.5
2.5
V = 12 V
I
V = 12 V
I
2.3
2.1
1.9
1.7
1.5
10
9.5
9
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 9
Figure 10
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
POWERGOOD THRESHOLD
vs
JUNCTION TEMPERATURE
6
4
2
95
V = 12 V
I
94
93
92
91
90
0
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 11
Figure 12
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
TYPICAL CHARACTERISTICS
DRIVER
SLOW START CHARGE CURRENT
REGULATOR VOLTAGE
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
15
14
13
8.5
V
R
= 1.3 V
= 20 kΩ
(VREFB)
(VREFB)
8.25
8
7.75
7.5
12
11
10
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 13
Figure 14
DRIVER
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
vs
LOW-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
5
4
3
6
4
2
1
0
2
0
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 15
Figure 16
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
TYPICAL CHARACTERISTICS
SENSING SAMPLE/HOLD RESISTANCE
vs
JUNCTION TEMPERATURE
100
V
= 12 V
(HISENSE)
75
50
25
0
0
25
50
75
100
125
T
J
– Junction Temperature – °C
Figure 17
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
The following figure is a typical application schematic. The circuit can be divided into the power-stage section
and the control-circuit section. The power stage must be tailored to the input/output requirements of the
application. The control circuit is basically the same for all applications with some minor tweaking of specific
values. Table 2 shows the values of the power stage components for various output-current options.
L102
L101
Q101
12V
Vo
R102
C104
Q102
+
+
C105
C106
C101 C102 C103
R101
GND
RTN
Power Stage
Control Section
C2
1 uF
C1
1 uF
VCC
DRV
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
C3
BOOT
LOWDR
DRVGND
LOHIB
R2
150
C4
1 uF
1 uF
HIGHDR
BOOTLO
HISENSE
LOSENSE
IOUTLO
INHIBIT
VID4
R1
LODRV
BIAS
C5
0.1 uF
C7
3.40 k
1%
C6
SLOWST
ANAGND
VSENSE
VREFB
VHYST
OCP
8
0.033 uF
1000 pF
7
R3 10.0 k
R5
100
ENABLE
6
VID3
5
R6
VID2
R4
2.55 k
1%
20.0 k
C8
2200 pF
4
R7
3.92 k
R8
1.00 k
VID1
3
VID0
DROOP
IOUT
2
PWRGD
1
R9
R10
1.00 k
4.32 k
TPS5210
U1
Figure 18. Standard Application Schematic
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
Table 2. Power Stage Components
12-V–Input Power Stage Components
Ref
Function
Des
4–A Out
8–A Out
12–A Out
20–A Out
40–A Out
Sanyo,
16SV100M,
100–uF, 16–V, 20%
Sanyo,
16SA470M,
2 x 470–uF, 16–V, 20%
Sanyo,
16SA470M,
2 x 470–uF, 16–V, 20%
Sanyo,
16SA470M,
3 x 470–uF, 16–V, 20%
Sanyo,
16SA470M,
4 x 470–uF, 16–V, 20%
Input Bulk
Capacitor
C101
muRata,
muRata,
muRata,
muRata,
muRata,
Input
GRM42–6Y5V105Z025A GRM42–6Y5V225Z016A GRM42–6Y5V225Z016A GRM42–6Y5V105Z025A GRM42–6Y5V105Z025A
C102 Mid–Freq
Capacitor
1.0–uF, 25–V,
+80%–20%,
Y5V
2.2–uF, 16–V,
+80%–20%,
Y5V
2.2–uF, 16–V,
+80%–20%,
Y5V
3 x 1.0–uF, 25–V,
+80%–20%,
Y5V
4 x 1.0–uF, 25–V,
+80%–20%,
Y5V
Input
Hi–Freq
Bypass
Capacitor
muRata,
GRM39X7R104K016A
0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
2 x 0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
3 x 0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
4 x 0.1–uF, 16–V, X7R
C103
muRata,
GRM39X7R102K050A,
1000–pF, 50–V, X7R
muRata,
GRM39X7R102K050A,
1000–pF, 50–V, X7R
muRata,
GRM39X7R102K050A,
2 x 1000–pF, 50–V, X7R
muRata,
GRM39X7R102K050A,
3 x 1000–pF, 50–V, X7R
muRata,
GRM39X7R102K050A,
4 x 1000–pF, 50–V, X7R
Snubber
C104
Capacitor
Sanyo,
6TPB150M,
3 x 150–uF, 6.3–V, 20%
Sanyo,
4SP820M,
820–uF, 4–V, 20%
Sanyo,
4SP820M,
2 x 820–uF, 4–V, 20%
Sanyo,
4SP820M,
3 x 820–uF, 4–V, 20%
Sanyo,
4SP820M,
4 x 820–uF, 4–V, 20%
Output Bulk
C105
Capacitor
Output
Hi–Freq
Bypass
Capacitor
muRata,
GRM39X7R104K016A,
0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
2 x 0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
3 x 0.1–uF, 16–V, X7R
muRata,
GRM39X7R104K016A,
4 x 0.1–uF, 16–V, X7R
C106
Input
Filter
Inductor
CoilCraft,
DO1608C–332,
3.3–uH, 2.0–A
Coiltronics,
UP2B–2R2,
2.2–uH, 7.2–A
Coiltronics,
UP2B–2R2,
2.2–uH, 7.2–A
Coiltronics,
UP3B–1R0,
1–uH, 12.5–A
Coiltronics,
UP3B–1R0,
1–uH, 12.5–A
L101
L102
Output
Filter
Inductor
CoilCraft,
DO3316P–332,
3.3–uH, 6.1–A
Coiltronics,
UP3B–2R2,
2.2–uH, 9.2–A
Coiltronics,
UP4B–1R5,
1.5–uH, 13.4–A
MicroMetals,
T68–8/90 Core w/7T
#16, 1.0–uH, 25–A
Pulse Engineering,
P1605,
1.0–uH, 50–A
Lo–Side
R101 Gate
Resistor
3.3–Ohm,
1/16–W, 5%
3.3–Ohm,
1/16–W, 5%
2 x 3.3–Ohm,
1/16–W, 5%
3 x 3.3–Ohm,
1/16–W, 5%
4 x 3.3–Ohm,
1/16–W, 5%
Snubber
Resistor
2.7–Ohm,
1/10–W, 5%
2.7–Ohm,
1/10–W, 5%
2 x 2.7–Ohm,
1/10–W, 5%
3 x 2.7–Ohm,
1/10–W, 5%
4 x 2.7–Ohm,
1/10–W, 5%
R102
Q101
Power
Switch
Siliconix, Si4410,
NMOS, 13–mOhm
Siliconix, Si4410,
NMOS, 13–mOhm
Siliconix, 2 x Si4410,
NMOS, 13–mOhm
Siliconix, 2 x Si4410,
NMOS, 13–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
Synchron-
Q102 ous
Switch
Siliconix, Si4410,
NMOS, 13–mOhm
Siliconix, Si4410,
NMOS, 13–mOhm
Siliconix, 2 x Si4410,
NMOS, 13–mOhm
Siliconix, 3 x Si4410,
NMOS, 13–mOhm
IR, 4 x IRF7811,
NMOS, 11–mOhm
†
Nominal Frequency
Hysteresis Window
220 KHz
20 mV
330 KHz
20 mV
240 KHz
20 mV
140 KHz
20 mV
168 KHz
10 mV
†
Nominal frequency measured with Vo set to 2 V.
The values listed above are recommendations based on actual test circuits. Many variations of the above are
possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if not
more, dependent upon the layout than on the specific components, as long as the device parameters are not
exceeded. Fast-response, low-noise circuits require critical attention to the layout details. Even though the
operating frequencies of typical power supplies are relatively low compared to today’s microprocessor circuits,
the power levels and edge rates can cause severe problems both in the supply and the load. The power stage,
having the highest current levels and greatest dv/dt rates, should be given the greatest attention.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
frequency calculation
A detailed derivation of frequency calculation is shown in the application report, “Designing Fast Response
SynchronousBuckRegulatorsUsingtheTPS5210”, TILiteraturenumberSLVA044. Whenlessaccurateresults
are acceptable, the simplified equation shown below can be used:
V
V
V
ESR
O
I
O
f
s
V
L
Hysteresis Window
I
Control Section
Below are the equations needed to select the various components within the control section. Details and the
derivationsoftheequationsusedinthissectionareavailableintheapplicationreport“DesigningFastResponse
Synchronous Buck Regulators Using the TPS5210”, TI Literature number SLVA044.
output voltage selection
Of course the most important function of the power supply is to regulate the output voltage to a specific value.
Values between 1.3 V and 3.5 V can be easily set by shorting the correct VID inputs to ground. Values above
the maximum reference voltage (3.5 V) can be set by setting the reference voltage to any convenient voltage
within its range and selecting values for R2 and R3 to give the correct output. Select R3:
R3 << than V
/I
; a recommended value is 10 kΩ
REF BIAS(VSENSE)
Then, calculate R2 using:
R3
V
V
V
R2
R3
O
REF
V
V
1
or
R2
O
REF
REF
R2 and R3 can also be used to make small adjusts to the output voltage within the reference-voltage range
and/or to adjust for load-current active droop compensation. If there is no need to adjust the output voltage, R3
can be eliminated. R2, R3 (if used), and C7 are used as a noise filter; calculate using:
150 ns
C7
R2 R3
slowstart timing
Slowstart reduces the startup stresses on the power-stage components and reduces the input current surge.
Slowstart timing is a function of the reference-voltage current (determined by R6) and is independent of the
reference voltage. The first step in setting slowstart timing will be to determine R6:
R6 should be between 7 kΩ and 300 kΩ, a recommended value is 20 kΩ.
Set the slowstart timing using the formula:
t
t
SS
SS
)
R6
C5
(
5
5
R
VREFB
Where C5 = Slowstart capacitance in µF
= Slowstart timing in µs
t
R
SS
VREFB
= Resistance from VREFB to GND in ohms (≈ R6)
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
hysteresis voltage
A hysteretic controller regulates by self-oscillation, thus requiring a small ripple voltage on the output which the
input comparator uses for sensing. Once selected, the TPS5210 hysteresis is proportional to the reference
voltage; programming Vref to a new value automatically adjusts the hysteresis to be the same percentage of
Vref. The actual output ripple voltage is the combination of the hysteresis voltage, overshoot caused by internal
delays, and the output capacitor characteristics. Figure 20 shows the hysteresis window voltage (V to V
)
HI
LO
and the output voltage ripple (V
to V
). Since the output current from VREFB should be less than 500 µA,
MAX
MIN
the total divider resistance (R5 + R6) should be greater than 7 KΩ. The hysteresis voltage should be no greater
than 60 mV so R6 will dominate the divider.
VREFB
Hysteresis Window = 2 × V
R5
R6
R5
VHSYT
Figure 19. Hysteresis Divider Circuit
V
O
V
MAX
V
HI
V
REF
V
LO
V
MIN
t
Figure 20. Output Ripple
The upper divider resistor, R5, is calculated using:
0
( )
)
Hysteresis Window
VHYST
(
0
R5 =
× R6
× R6
(
)
2 × VREFB – Hysteresis Window
2 × 100
Where Hysteresis Window = the desired peak-to-peak hysteresis voltage.
VREFB = selected reference voltage.
V
(%) = [(Hysteresis Window)/VREFB] * 100 < V
(%)
HYST
O(Ripple)(P–P)
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
current limit
Current limit can be implemented using the on-resistance of the upper FETs as the sensing elements. Select
R8:
0.1V
100 × 100nA
VOCP
R8 <<
≤
≤ 10 kΩ
(
)
IBias(OCP)
(A recommended value is 1 kΩ)
The IOUT signal is used to drive the current limit and droop-circuit dividers. The voltage at IOUT at the output
current trip point will be:
(
)
2 ×
× TF
RDS(ON)
NumFETs
Where NumFETS = Number of upper FETS in Parallel.
TF = R temperature correction factor.
=
×
IO(Trip)
VIOUT(Trip)
DS(ON)
O(Trip)
I
= Desired output current trip level (A).
Calculate R7 using:
V
IOUT(Trip)
R7
1
R8
0.1 V
NotethatsinceR
ofMOSFETscanvaryfromlottolotandwithtemperature,tightcurrent-limitcontrol(less
DS(ON)
than 1.5 x I ) using this method is not practical. If tight control is required, an external current-sense resistor
O
in series with the drain of the upper FET can be used with HISENSE and LOSENSE connected across the
resistor.
droop compensation
Droop compensation is used to reduce the output voltage range during load transients by increasing the output
voltage setpoint toward the upper tolerance limit during light loads and decreasing the voltage setpoint toward
the lower tolerance limit during heavy loads. This allows the output voltage to swing a greater amount and still
remain within the tolerance window. The maximum droop voltage is set with R9 and R10. Select R10:
VDROOP(Min)
0.01V
100 × 100 nA
R10 <<
≤
≤ 1 kΩ
(
)
IBias(DROOP,Max)
(Again, a value of 1 kΩ is recommended)
The voltage at IOUT during normal operation (0 to 100% load) will vary from 0 V up to:
(
)
2 ×
× TF
RDS(ON)
NumFETs
= Maximum output load current (A).
=
×
IO(Max)
VIOUT(Max)
Where I
O(Max)
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
droop compensation (continued)
Then, calculate R9:
V
IOUT(Max)
R9
1
R10
V
DROOP
Where V
= Desired droop voltage
DROOP
At full load, the output voltage will be:
R2
R3
V
V
1
V
O
REF
DROOP
using the TPS5210 when both 12 V and 5 V are available
When both 12 V and 5 V are available, several components can be removed from the basic schematic shown
above. R1, R4, and C9 are no longer required if 5 V is brought in directly to INHIBIT and LODRV. However, if
undervoltage lockout for the 5-V input is desired, R1 and R4 can be used to set the startup setpoint. TheINHIBIT
pin trip level is 2.1 V. Select R4:
2.1V
100 × 100nA
VINH
R4 <<
≤
≤ 210k Ω
(
)
IINH(Max)
Then, set the 5-V UVLO trip level with R1:
(
)
× R4
– 2V
5VTrip
R1 =
2V
LODRV
INHIBIT
R1
R4
Figure 21. 5-V Input with UVLO
using the TPS5210 when only 5 V is available
The TPS5210 controller requires 12 V for internal control of the device. If an external source for 12 V is not
available, a small on-board source must be included in the design. Total 12-V current is very small, typically
about 20 mA, so even a small charge pump can be used to generate the supply voltage. The power stage is
not voltage dependent, but component values must be selected for 5-V inputs and the frequency of operation
is dependent upon the power stage input voltage.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
L102
L101
Q101
5V
Vo
R102
C104
Q102
+
+
C105
C106
C101
C102 C103
R101
GND
RTN
Power Stage
Control Section
C2
1 uF
C1
0.1 uF
12 V
12-V
VCC
DRV
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
Boost
Circuit
C3
BOOT
LOWDR
DRVGND
LOHIB
R2
150
C4
1 uF
1 uF
HIGHDR
BOOTLO
HISENSE
LOSENSE
IOUTLO
INHIBIT
VID4
LODRV
BIAS
C5
0.1 uF
C7
R1
10.0 k
1%
C6
SLOWST
ANAGND
VSENSE
VREFB
VHYST
OCP
8
0.033 uF
1000 pF
ENABLE
7
R3 10.0 k
R5
6
100
VID3
5
R6
20.0 k
VID2
R4
11.0 k
C8
4
R7
3.92 k
R8
1.00 k
2200 pF
VID1
1%
3
VID0
DROOP
IOUT
2
PWRGD
1
R9
R10
1.00 k
4.32 k
TPS5210
U1
Figure 22. Typical 5-V-Only Application Circuit
application examples
Various application and layout examples using the TPS5210 are available from Texas Instruments. This
information can be downloaded from http://www.ti.com/sc/docs/products/msp/pwrsply/default.htm or received
from your TI representative.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
APPLICATION INFORMATION
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affectnoise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB design. The general design should proceed from the switching node to the output, then
back to the driver section, and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS5210 design begins.
1. All sensitive analog components should be referenced to ANAGND. These include components connected
to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOHIB.
2. Analogground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on V , and drive ground will connect to the main ground
O
plane close to the source of the low-side FET.
3. Connections from the drivers to the gate of the power FETs, should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
4. The bypass capacitor for the DRV regulator should be placed close to the TPS5210 and be connected to
DRVGND.
5. The bypass capacitor for V
should be placed close to the TPS5210 and be connected to DRVGND.
CC
6. When configuring the high-side driver as a floating driver, the connection from BOOTLO to the power FETs
should be as short and as wide as possible. The other pins that also connect to the power FETs, LOHIB
and LOSENSE, should have a separate connection to the FETS since BOOTLO will have large peak
currents flowing through it.
7. When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT
to BOOTLO) should be placed close to the TPS5210.
8. When configuring the high-side driver as a ground-referenced driver, BOOTLO should be connected to
DRVGND.
9. The bulk storage capacitors across V should be placed close to the power FETS. High-frequency bypass
I
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on V .
O
11. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to Vin, to reduce high-frequency noise coupling on HISENSE.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/C 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/E 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号:
TPS5300DAPG4
3.3A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO32, GREEN, PLASTIC, HTSSOP-32
TI
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