TPS54336DDAR [TI]
4.5V to 28V Input, 3A Output, Synchronous SWIFT Step-Down Voltage Regulator; 4.5V至28V输入，3A输出，同步SWIFT降压稳压器
| 型号： | TPS54336DDAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5V to 28V Input, 3A Output, Synchronous SWIFT Step-Down Voltage Regulator |
| 文件： | 总40页 (文件大小：1884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
4.5V to 28V Input, 3A Output, Synchronous SWIFT™ Step-Down Voltage Regulator
Check for Samples: TPS54335, TPS54336
1
FEATURES
DESCRIPTION
The TPS54335/54336 is a 3A, low quiescent supply
current (IQ), synchronous DC-DC converter IC
(integrated circuit) with up to 28V input support.
2
•
Two 128mΩ/84mΩ MOSFETs for 3A
Continuous Output Current
•
•
TPS54335: Internal 2ms Soft-start,
50kHz–1.5MHz Adjustable Frequency
By integrating MOSFETs and by employing current
mode switching control, the TPS54335/54336 offers
compact designs on PCB (printed circuit board)
reducing external component count.
TPS54336: Adjustable Soft-start, Fixed 340kHz
Frequency
•
•
Low 2µA Shutdown Quiescent Current
Efficiency is maximized through the integrated
128mΩ/84mΩ MOSFETs, low IQ and pulse skipping
at light loads. Using the enable pin, shutdown supply
current is reduced to 2 μA by entering a shutdown
mode.
0.8V Internal Voltage Reference with ±0.8%
Accuracy at Room Temperature and ±1.5%
Accuracy Over Temperature
•
•
Fixed-Frequency Current Mode Control
Pulse Skipping Boosts Efficiency at Light
Loads
This step-down (buck) converter provides accurate
regulation for a variety of loads with a well-regulated
voltage reference 1.5% over temperature.
•
•
•
•
Overcurrent Protection for Both MOSFETs
with Hiccup Mode for Severe Fault Conditions
Cycle by cycle current limiting on the high-side
MOSFET protects the TPS54335/54336 in overload
situations and is enhanced by a low-side sourcing
current limit which prevents current runaway. There is
also a low-side sinking current limit which turns off
the low-side MOSFET to prevent excessive reverse
current. Hiccup protection will be triggered if the
overcurrent condition has persisted for longer than
the preset time. Thermal hiccup protection disables
the part when die temperature exceeds thermal
shutdown temperature and enables the part again
after the built-in thermal hiccup time.
Thermal Shutdown and Overvoltage Transition
Protection
Available in Easy-to-Use 8-Pin SOIC
PowerPAD™ and 10-pin SON
Monotonic Start-Up into Pre-biased Outputs
APPLICATIONS
•
Consumer Applications such as a Digital TV
(DTV), Set Top Box (STB, DVD/Blu-ray Player),
LCD Display, CPE (Cable Modem, WiFi
Router), DLP Projectors, Smart Meters
.
.
•
•
•
Battery Chargers
Industrial and Car Audio Power Supplies
5V,12V and 24V Distributed Power Bus Supply
SIMPLIFIED SCHEMATICS
VIN
C1
VIN
VIN
VIN
C1
TPS54335
TPS54336
CBOOT
LO
CBOOT
LO
BOOT
PH
BOOT
PH
EN
EN
VOUT
VOUT
RT
SS
CO
CO
COMP
COMP
RO1
RO1
CC
CC
VSENSE
VSENSE
C2
C2
RRT
RC
RC
RO2
RO2
CSS
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD, SWIFT are trademarks of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1) (2)
TJ
PACKAGE
PART NUMBER
TPS54335DDA
TPS54336DDA
TPS54335DRC
TPS54336DRC
8-Pin SOIC PowerPAD™
–40°C to +150°C
10-pin SON
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54335DDAR). See applications
section of data sheet for layout information.
ABSOLUTE MAXIMUM RATINGS(1) (2)
MIN
–0.3
–0.3
-0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
UNIT
V
VIN
30
EN
6
V
BOOT
(PH+7.5)
V
Input voltage
VSENSE
3
V
COMP
3
V
RT
3
V
SS
3
V
BOOT-PH
PH
7.5
V
Output voltage
–1
30
V
PH 10ns Transient
–3.5
–0.2
100
100
30
V
Vdiff (GND to exposed Thermal Pad)
EN
0.2
V
100
µA
µA
A
Source current
RT
100
PH
Current Limit
PH
Current Limit
A
Sink current
COMP
200
2
200
2
µA
kV
V
Electrostatic discharge (HBM) QSS 009-105 (JESD22-A114A)
Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.01)
Operating junction temperature
500
–40
–65
500
150
150
°C
°C
Storage temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
2
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
THERMAL INFORMATION
TPS54335/6
UNITS
THERMAL METRIC(1)
DDA (8 PINS)
DRC (10 PINS)
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
42.1
50.9
31.8
8
43.9
55.4
18.9
0.7
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
13.5
7.1
19.1
5.3
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
The Electrical Ratings specified in this section will apply to all specifications in this document unless otherwise noted. These
specifications will be interpreted as conditions that will not degrade the device’s parametric or functional specifications for the
life of the product containing it. TJ = –40°C to +150°C, VIN =4.5 TO 28V, (unless otherwise noted)
PARAMETERS
SUPPLY VOLTAGE AND UVLO (VIN PIN)
Operating input voltage
Input UVLO threshold
CONDITIONS
MIN
TYP
MAX
UNIT
4.5
28
4.5
400
10
V
V
Rising Vin
EN = 0V
4
180
2
Input UVLO hysteresis
mV
µA
µA
VIN Shutdown supply current
VIN Operating – Non switching supply current
ENABLE (EN PIN)
VSENSE = 810 mV
310
800
Enable threshold
Rising
1.21
1.17
1.15
3.3
1.28
V
V
Enable threshold
Falling
1.1
Input current
EN= 1.1 V
EN= 1.3 V
µA
µA
Hysteresis current
VOLTAGE REFERENCE
TJ =25°C
0.7936
0.788
0.8 0.8064
Reference
V
0.8
0.812
MOSFET
BOOT-PH= 3 V
BOOT-PH= 6 V
VIN = 12V
160
128
84
280
230
170
mΩ
mΩ
mΩ
High side switch resistance(1)
Low Side Switch Resistance(1)
ERROR AMPLIFIER
Error amplifier transconductance (gm)
Error amplifier source/sink
–2 µA < ICOMP < 2 µA V(COMP) = 1 V
V(COMP) = 1 V, 100 mV Overdrive
1300
100
0.5
8
µmhos
µA
Start switching peak current threshold
COMP to Iswitch gm
A
A/V
CURRENT LIMIT
High side switch current limit threshold
Low side switch sourcing current limit
Low side switch sinking current limit
Hiccup wait time
4
4.9
4.7
6.5
6.1
A
A
3.5
0
A
512
16384
Cycles
Cycles
Hiccup time before re-start
(1) Measured at pins
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
The Electrical Ratings specified in this section will apply to all specifications in this document unless otherwise noted. These
specifications will be interpreted as conditions that will not degrade the device’s parametric or functional specifications for the
life of the product containing it. TJ = –40°C to +150°C, VIN =4.5 TO 28V, (unless otherwise noted)
PARAMETERS
THERMAL SHUTDOWN
CONDITIONS
MIN
TYP
MAX
UNIT
Thermal shutdown
160
175
10
°C
°C
Thermal shutdown hysterisis
Thermal shutdown hiccup time
PH (PH PIN)
32768
Cycles
Minimum on time
Measured at 90% to 90% of VIN, IPH = 2A
94
0
145
3
ns
%
Minimum off time
BOOT-PH ≥ 3V
BOOT (BOOT PIN)
BOOT-PH UVLO
2.1
V
SWITCHING FREQUENCY
TPS54335
50
384
40
1500
576
60
kHz
kHz
kHz
kHz
kHz
TPS54335, Rrt = 100 kΩ
TPS54335, Rrt = 1000 kΩ, –40°C~105°C
TPS54335, Rrt = 30 kΩ
TPS54336
480
50
Switching frequency range
1200
272
1500
340
1800
408
Internal switching frequency
SLOW START
Internal slow start time
Slow start charge current
TPS54335
TPS54336
2
ms
µA
2.3
PIN ASSIGNMENTS
8-PIN SOIC WITH THERMAL PAD
(TOP VIEW)
TPS54335
TPS54336
8
7
6
5
SS
EN
8
7
6
5
BOOT
1
2
3
4
BOOT
RT
EN
1
2
3
4
VIN
PH
VIN
PH
PowerPAD
(9)
PowerPAD
(9)
COMP
COMP
VSENSE
GND
VSENSE
GND
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NUMBER
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is
refreshed.
BOOT
1
Vin
2
3
4
5
Input supply voltage, 4.5 V to 28 V.
The source of the internal high side power MOSFET.
Ground.
PH
GND
VSENSE
COMP
EN
Inverting node of the gm error amplifier.
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
6
7
Enable pin. Float to enable.
4
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NAME
NUMBER
RT (TPS54335)
8
Connect to an external timing resistor to adjust the switching frequency of the device.
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference
rise time. The voltage on this pin overrides the internal reference.
SS (TPS54336)
8
GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad
should be connected to any internal PCB ground plane using multiple vias for good thermal
performance.
PowerPAD™
9
10-PIN SON WITH THERMAL PAD
(TOP VIEW)
TPS54335
TPS54336
DRC PACKAGE
(TOP VIEW)
DRC PACKAGE
(TOP VIEW)
1
2
3
10
9
1
VIN
PH
SS
BOOT
EN
10
9
VIN
RT
BOOT
EN
2
3
PH
Exposed
Thermal Pad
(11)
Exposed
Thermal Pad
(11)
8
GND
8
GND
4
5
7
GND
GND
COMP
4
5
7
GND
GND
COMP
6 VSENSE
6 VSENSE
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
VIN
NUMBER
1
Input supply voltage, 4.5 V to 28 V.
PH
2
3, 4, 5
6
The source of the internal high side power MOSFET.
Ground.
GND
VSENSE
Inverting node of the gm error amplifier.
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
COMP
EN
7
8
Enable pin. Float to enable.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is
refreshed.
BOOT
9
RT (TPS54335)
SS (TPS54336)
10
10
Connect to an external timing resistor to adjust the switching frequency of the device.
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference
rise time. The voltage on this pin overrides the internal reference.
GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad
should be connected to any internal PCB ground plane using multiple vias for good thermal
performance.
PowerPAD™
11
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
Thermal
Hiccup
UVLO
Enable
Ip
Ih
Comparator
Shutdown
Logic
Hiccup
Shutdown
Enable
Threshold
OV
Boot
Charge
Current
Sense
Minimum Clamp
Pulse Skip
ERROR
AMPLIFIER
VSENSE
BOOT
Boot
UVLO
SS
(TPS54336)
HS MOSFET
Current
Comparator
Voltage
Reference
Power Stage
& Deadtime
Control
PH
Logic
Slope
Compensation
VIN
Regulator
Hiccup
Shutdown
LS MOSFET
Current Limit
Maximum
Clamp
Overload
Recovery
Oscillator
Current
Sense
GND
RT
COMP
EXPOSED THERMAL PAD
(TPS54335)
6
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
TYPICAL CHARACTERISTICS
HIGH-SIDE MOSFET ON RESISTANCE
LOW-SIDE MOSFET ON RESISTANCE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
210
190
170
150
130
110
90
140
130
120
110
100
90
80
70
60
VIN = 12 V
VIN = 12 V
70
50
±50
±50
±50
±25
±25
±25
0
25
50
75
100
125
150
±50
±50
±50
±25
±25
±25
0
25
50
75
100
125
150
C001
C002
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
Figure 1.
Figure 2.
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
0.808
0.804
0.800
0.796
0.792
495
490
485
480
475
470
465
0
25
50
75
100
125
150
0
25
50
75
100
125
150
C003
C004
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
Figure 3.
Figure 4.
UVLO THRESHOLD
vs
HYSTERESIS CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.230
1.225
1.220
1.215
1.210
3.50
3.45
3.40
3.35
3.30
3.25
3.20
VIN = 12 V
125
VIN = 12 V
0
25
50
75
100
150
0
25
50
75
100
125
150
C005
C006
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
Figure 5.
Figure 6.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
PULLUP CURRENT
vs
JUNCTION TEMPERATURE
NON-SWITCHING OPERATING QUIESCENT CURRENT
vs
INPUT VOLTAGE
1.2
1.175
1.15
400
350
300
250
200
1.125
1.1
T = -40C
J
T = 25C
J
VIN = 12 V
100 125
T = 150C
J
±50
±25
0
25
50
75
150
4
8
12
16
20
24
28
C007
C008
TJ - Junction Temperature (C)
VIN - Input Voltage (V)
Figure 7.
Figure 8.
SHUTDOWN QUIESCENT CURRENT
SS CHARGE CURRENT
vs
JUNCTION TEMPERATURE
vs
INPUT VOLTAGE
10
8
2.40
2.35
2.30
2.25
2.20
T=-40C
J
T = 25C
J
T = 150C
J
6
4
2
EN = 0 V
0
4
8
12
16
20
24
28
±50
±25
0
25
50
75
100
125
150
C009
C010
VIN - Input Voltage (V)
TJ - Junction Temperature (C)
Figure 9.
Figure 10.
MINIMUM CONTROLLABLE ON TIME
MINIMUM CONTROLLABLE DUTY RATIO
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
120
110
100
90
6.0
5.0
4.0
3.0
80
VIN = 12 V
125
VIN = 12 V
125
70
±50
±25
0
25
50
75
100
150
±50
±25
0
25
50
75
100
150
C011
C012
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
Figure 11.
Figure 12.
8
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
TYPICAL CHARACTERISTICS (continued)
BOOT-PH UVLO THRESHOLD
vs
JUNCTION TEMPERATURE
CURRENT LIMIT THRESHOLD
vs
INPUT VOLTAGE
2.300
2.200
2.100
2.000
6.0
5.5
5.0
4.5
4.0
TJ=-40C
T = 25C
J
T = 150C
J
±50
±25
0
25
50
75
100
125
150
4
8
12
16
20
24
28
C013
C014
TJ - Junction Temperature (C)
VIN - Input Voltage (V)
Figure 13.
Figure 14.
OVERVIEW
The device is a 28-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To
improve performance during line and load transients the device implements a constant frequency, peak current
mode control which reduces output capacitance and simplifies external frequency compensation design.
The device has been designed for safe monotonic startup into pre-biased loads. It has a typical default start up
voltage of 4.0 V. The EN pin has an internal pull-up current source that can provide a default condition when the
EN pin is floating for the device to operate. The total operating current for the device is typically 310µA when not
switching and under no load. When the device is disabled, the supply current is less than 5μA.
The integrated 128mΩ/84mΩ MOSFETs allow for high efficiency power supply designs with continuous output
currents up to 3 amperes.
The device reduces the external component count by integrating the boot recharge diode. The bias voltage for
the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor
voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a
preset threshold. The output voltage can be stepped down to as low as the 0.8 V reference.
The device minimizes excessive output over-voltage transients by taking advantage of the over-voltage power
good comparator. When the regulated output voltage is greater than 106% of the nominal voltage, the over-
voltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until the
output voltage is lower than 104%.
The TPS54335 has wide switching frequency of 50 kHz to 1500 kHz which allows for efficiency and size
optimization when selecting the output filter components. The internal 2ms slow start time is implemented to
minimize inrush currents.
The TPS54336 is fixed at 340kHz. It is able to adjust the slow start time by the SS pin.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The device uses a fixed frequency, peak current mode control. The output voltage is compared through external
resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin.
An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to
the high side power switch current. When the power switch current reaches the COMP voltage level the high side
power switch is turned off and the low side power switch is turned on. The COMP pin voltage increases and
decreases as the output current increases and decreases. The device implements a current limit by clamping the
COMP pin voltage to a maximum level and also implements a minimum clamp for improved transient response
performance.
LIGHT LOAD OPERATION
The device monitors the peak switch current of the high-side MOSFET. Once the peak switch current is lower
than typically 0.5A, the device stops switching to boost the efficiency until the peak switch current again rises
higher than typically 0.5A.
VOLTAGE REFERENCE
The voltage reference system produces a precise ±1.5% voltage reference over temperature by scaling the
output of a temperature stable bandgap circuit.
ADJUSTING THE OUTPUT VOLTAGE
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use divider resistors with 1% tolerance or better. Start with a 10 kΩ for the upper resistor divider, R1 and
useEquation 1 to calculate R2. To improve efficiency at light loads consider using larger value resistors. If the
values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current
are noticeable.
VREF
R2 =
´R1
VOUT - VREF
(1)
ENABLE AND ADJUSTING UNDERVOLTAGE LOCKOUT
The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state.
The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If
an application requires controlling the EN pin, use open drain or open collector output logic to interface with the
pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 180mV.
If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown
in Figure 15. When using the external UVLO function it is recommended to set the hysteresis to be greater than
500mV.
The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 2, and Equation 3.
10
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
TPS54335/6
VIN
EN
ip
i
h
R 1
R 2
Figure 15. Adjustable VIN Undervoltage Lock Out
æ
ç
è
ö
÷
ø
VENFALLING
VENRISING
VSTART
- VSTOP
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+I
p ç
h
VENRISING
è
(2)
(3)
R1´ VENFALLING
VSTOP - VENFALLING + R1(Ip + Ih )
R2 =
Where Ih = 3.3 μA, Ip = 1.15 μA, VENRISING = 1.21 V, VENFALLING = 1.17 V
ERROR AMPLIFIER
The device has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower of
the internal slow start voltage or the internal 0.8 V voltage reference. The transconductance of the error amplifier
is 1300μA/V typically. The frequency compensation components are placed between the COMP pin and ground.
SLOPE COMPENSATION AND OUTPUT CURRENT
The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full
duty cycle range.
SAFE START-UP INTO PRE-BIASED OUTPUTS
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During
monotonic pre-biased startup, both high-side and low-side MOSFETs are not allowed to be turned on until the
internal slow-start voltage (TPS54335), or SS pin voltage (TPS54336) is higher than VSENSE pin voltage.
BOOTSTRAP VOLTAGE (BOOT)
The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH
pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT
pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor
should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher
is recommended because of the stable characteristics over temperature and voltage. When the voltage between
BOOT and PH drops below the BOOT-PH UVLO threshold, which is typically 2.1V, the high-side MOSFET is
turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged.
ADJUSTABLE SWITCHING FREQUENCY (TPS54335 ONLY)
To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 16. To
reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply
efficiency and minimum controllable on time should be considered.
Rrt(kW) = 55300´Fsw(kHz)-1.025
(4)
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
RT SET RESISTOR
vs
OSCILLATOR FREQUENCY
1000
800
600
400
200
0
0
250
500
750
1000
1250
1500
Fsw - Oscillator Frequency - kHz
Figure 16. RT Set Resistor vs Switching Frequency
SLOW START (TPS54336 ONLY)
The device uses the lower voltage of the internal voltage reference or the SS pin voltage as the reference
voltage and regulates the output accordingly. A capacitor on the SS pin to ground implements a slow start time.
The device has an internal pull-up current source of 2.3 μA that charges the external slow start capacitor. The
calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in Equation 5.
The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3μA.
Css(nF) ´ Vref(V)
Tss(ms) =
Iss(mA)
(5)
When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the
device stops switching and enters low current operation. At the subsequent power up, when the shutdown
condition is removed, the device does not start switching until it has discharged its SS pin to ground ensuring
proper soft start behavior.
OUTPUT OVERVOLTAGE PROTECTION (OVP)
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier demands maximum output current. Once the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some
applications with small output capacitance, the power supply output voltage can respond faster than the error
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP
threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to
turn on at the next clock cycle.
OVERCURRENT PROTECTION
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
High-side MOSFET overcurrent protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-
side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference the high-side switch is turned off.
12
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
Low-side MOSFET overcurrent protection
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current limit is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on
for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side
sourcing current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart
after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under
severe overcurrent conditions.
THERMAL SHUTDOWN
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will
start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time
(32768 cycles) is over.
SMALL SIGNAL MODEL FOR LOOP RESPONSE
Figure 17 shows an equivalent model for the device control loop which can be modeled in a circuit simulation
program to check frequency response and transient responses. The error amplifier is a transconductance
amplifier with a gm of 1300μA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Roea (3.07 MΩ) and capacitor Coea (20.7 pF) model the open loop gain and frequency
response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the
control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of
the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the
overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the
appropriate load step amplitude and step rate in a time domain analysis.
PH
VOUT
Power Stage
8 A/V
a
b
RESR
R1
RL
COMP
c
C
O
VSENSE
R2
0.8V
Coea
Roea
R3
C1
gm
1300 mA/V
C2
Figure 17. Small Signal Model for Loop Response
SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL
Figure 18 is a simple small signal model that can be used to understand how to design the frequency
compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 6 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 17) is the power stage
transconductance (gmps) which is 8 A/V for the device. The DC gain of the power stage is the product of gmps
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
and the load resistance, R , as shown in Equation 7 with resistive loads. As the load current increases, the DC
L
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole
moves with load current (see Equation 8). The combined effect is highlighted by the dashed line in Figure 19. As
the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
VOUT
VC
RESR
RL
gm
ps
CO
Figure 18. Simplified Small Signal Model for Peak Current Mode Control
VOUT
Adc
VC
RESR
fp
RL
gm
ps
CO
fz
Figure 19. Simplified Frequency Response for Peak Current Mode Control
æ
ç
è
s
ö
÷
ø
1+
2p ´ ¦z
VOUT
VC
= Adc ´
æ
ö
÷
ø
s
1+
ç
2p ´ ¦p
è
(6)
(7)
Adc = gmps ´ RL
1
¦p =
C
´ R ´ 2p
O
L
(8)
(9)
1
¦z =
C
´ R
´ 2p
ESR
O
Where
gmea is the GM amplifier gain (1300μA/V)
gmps is the power stage gain (8 A/V).
RL is the load resistance
CO is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
14
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly
used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 20. In
Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise. In Type III, one
additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III
Compensation for Current Mode Step-Down Converters (SLVA352) for a complete explanation of Type III
compensation.
The design guidelines below are provided for advanced users who prefer to compensate using the general
method. The below equations only apply to designs whose ESR zero is above the bandwidth of the control loop.
This is usually true with ceramic output capacitors.
VOUT
C11
R8
VSENSE
Type 2A
Type 2B
COMP
Coea
Type 3
Vref
R4
C4
gm
C6
R4
C4
ea
Roea
R9
Figure 20. Types of Frequency Compensation
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency, fc. A good starting point is 1/10th of the switching frequency, fsw.
2. R4 can be determined by:
2p ´ ¦c ´ VOUT ´ Co
R4 =
gmea ´ Vref ´ gmps
(10)
Where:
gmea is the GM amplifier gain (1300 μA/V)
gmps is the power stage gain (8 A/V)
Vref is the reference voltage (0.8 V)
æ
ç
è
ö
÷
ø
1
¦p =
CO ´ RL ´ 2p
3. Place a compensation zero at the dominant pole:
C4 can be determined by:
RL ´ Co
C4 =
R4
(11)
4. C6 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output
capacitor Co.
RESR ´ Co
C6 =
R4
(12)
5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C11 is calculated from Equation 13.
1
C11=
2×p ×R8×fc
(
)
(13)
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
APPLICATION INFORMATION
TPS54335 APPLICATION SCHEMATIC
U1
TPS54335DDA
L1 15µH
VIN = 8 - 28 V
C3 0.1µF
VOUT = 5 V, 3 A max
2
1
3
6
4
VIN
VIN
BOOT
PH
VOUT
5
7
8
VSENSE
VSENSE
EN
C1
10µF
C2
0.1µF
C6
47µF
C7
47µF
R4
51.1
COMP
R1
220k
RT
GND
PAD
R3
3.74k
R5
100k
C5
120pF
VSENSE
R2
43.2k
R7
143k
C4
0.012µF
R6
19.1k
Figure 21. Typical Application Schematic, TPS54335
STEP BY STEP DESIGN PROCEDURE
The following design procedure can be used to select component values for the TPS54335 and TPS54336.
Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. This section presents a simplified discussion of the design process using the TPS54335.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
•
•
•
•
•
•
Input voltage range
Output voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
For this design example, use the following as the input parameters
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
8 V to 28V
5 V
Output voltage
Transient response, 1.5 A load step
Input ripple voltage
ΔVout = +/- 5 %
400 mV
Output ripple voltage
Output current rating
Operating Frequency
30 mV
3 A
340 kHz
SWITCHING FREQUENCY
The switching frequency of the TPS54335 is set at 340 kHz to match the internally set frequency of the
TPS54336 for this design. Use Equation 4 to calculate the required value for R7. The calculated value is 140.6
kΩ. Use the next higher standard value of 143 kΩ.
16
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
OUTPUT VOLTAGE SET POINT
The output voltage of the TPS54335 is externally adjustable using a resistor divider network. In the application
circuit of Figure 21, this divider network is comprised of R5 and R6. The relationship of the output voltage to the
resistor divider is given by Equation 14 and Equation 15:
R5 ´ VREF
R6 =
VOUT - VREF
(14)
R5
é
ù
VOUT = VREF
´
+1
ê
ú
R6
ë
û
(15)
Choose R5 to be approximately 100 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage
matching when using standard value resistors. In this design, R5 = 100 kΩ and R6 = 19.1 kΩ, resulting in a
4.988 V output voltage. The 51.1 ohm resistor R4 is provided as a convenient place to break the control loop for
stability testing.
Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2.
R1 is connected between VIN and the EN pin of the TPS54335 and R2 is connected between EN and GND .
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brown outs when the input voltage is falling. For the example design, the minimum input voltage is 8 V, so the
start voltage threshold is set to 7.15 V with 1 V hysteresis. Equation 2 and Equation 3 can be used to calculate
the values for the upper and lower resistor values of R1 and R2.
INPUT CAPACITORS
The TPS54335 requires an input decoupling capacitor and depending on the application, a bulk input capacitor.
The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be
used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of
circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54335 circuit is not located
within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated
to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple
voltage is acceptable. For this design, a 10 μF, X7R dielectric capacitor rated for 35 V is used for the input
decoupling capacitor. . The equivalent series resistance (ESR) is approximately 2mΩ, and the current rating is 3
A. Additionally, a small 0.1 μF capacitor is included for high frequency filtering.
This input ripple voltage can be approximated by Equation 16
IOUT(MAX) ´ 0.25
DV
=
+ IOUT(MAX) ´ ESRMAX
(
)
IN
CBULK ´ fSW
(16)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CBULK is the bulk capacitor value
and ESRMAX is the maximum series resistance of the bulk capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 17
IOUT(MAX)
ICIN
=
2
(17)
In this case, the input ripple voltage would be 227 mV and the RMS ripple current would be 1.5 A. It is also
important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the
layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in
Design Parameters and is larger than the calculated value. This measured value is still below the specified input
limit of 400 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen
bypass capacitor is rated for 35 V and the ripple current capacity is greater than 3 A, both providing ample
margin. It is very important that the maximum ratings for voltage and current are not exceeded under any
circumstance.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
OUTPUT FILTER COMPONENTS
Two components need to be selected for the output filter, LOUT and COUT. Since the TPS54335 is an externally
compensated device, a wide range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 18
VOUT
´
VIN(MAX) - VOUT
(
)
´ KIND ´IOUT ´FSW
LMIN
=
V
IN(MAX)
(18)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
In general, this value is at the discretion of the designer; however, the following guidelines may be used. For
designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When
using higher ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 13.4 μH. For this
design, a close standard value was chosen: 15 μH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 19
æ
ç
ç
è
ö2
÷
VOUT
´
V
- VOUT
(
)
IN(MAX)
1
IL(RMS)
=
I2OUT(MAX)
+
´
÷
12
V
´ LOUT ´ FSW ´ 0.8
IN(MAX)
ø
(19)
and the peak inductor current can be determined with Equation 20
VOUT
´
V
- VOUT
(
IN(MAX)
)
IN(MAX)
IL(PK) = IOUT(MAX)
+
1.6 ´ V
´ LOUT ´ FSW
(20)
For this design, the RMS inductor current is 3.002 A and the peak inductor current is 3.503 A. The chosen
inductor is a Coilcraft 15 μH, XAL6060-153MEB. It has a saturation current rating of 5.8 A and an RMS current
rating of 6.0 A, meeting these requirements. Smaller or larger inductor values can be used depending on the
amount of ripple current the designer wishes to allow so long as the other design requirements are met. Larger
value inductors will have lower ac current and result in lower output voltage ripple, while smaller inductor values
will increase ac current and output voltage ripple. In general, inductor values for use with the TPS54335 are in
the range of 0.68 μH to 100 μH.
Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of drop in the output voltage. Equation 21 shows the minimum output capacitance necessary to
accomplish this.
2×DIout
Co >
f sw ×DVout
(21)
18
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage. For this example, the transient load response is specified as a 5%
change in Vout for a load step of 1.5 A. For this example, ΔIout = 1.5 A and ΔVout = 0.05 x 5.0 = 0.250 V. Using
these numbers gives a minimum capacitance of 35.3 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation.
Equation 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement
Equation 22, yields 12.3 µF.
1
1
Co >
×
Voripple
Iripple
8× f sw
(22)
Equation 23 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 23 indicates the ESR should be less than 29.8 mΩ. In this case, the ceramic caps’ ESR is
much smaller than 29.8 mΩ.
Voripple
Resr <
Iripple
(23)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 47 μF 10V X5R ceramic capacitor with 3 mΩ of ESR are used. Capacitors
generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An
output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets
specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 24 can be used to calculate
the RMS ripple current the output capacitor needs to support. For this application, Equation 24 yields 116.2 mA
for each capacitor.
æ
ç
ö
÷
VOUT × V
- VOUT
(
)
× LOUT × FSW × NC
IN(MAX)
1
ICOUT(RMS)
=
×
ç
÷
V
12
IN(MAX)
è
ø
(24)
COMPENSATION COMPONENTS
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 25
Ioutmax
¦p mod =
2p ´ Vout ´ Cout
(25)
For the TPS54335 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice to accurately model the power stage gain and phase so that a reliable
compensation circuit can be designed. Alternately, a direct measurement of the power stage characteristics can
be used. That is the technique used in this design procedure. For this design, L1 = 15 µH. C6 and C7 are set to
47µF each, and the ESR is 3 mΩ. Now the power stage characteristics are shown in Figure 22.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
60
40
20
0
180
120
60
Gain
Gain = 2.23 dB
@ F = 31.62 kHz
0
-20
-40
-60
-120
-180
Phase
-60
10
100
1000
10000
100000
C020
Frequency - Hz
Figure 22. Power Stage Gain and Phase Characteristics
For this design, the intended crossover frequency is 31.62 kHz (there is an actual measured data point for that
frequency). From the power stage gain and phase plots, the gain at 31.62 kHz is 2.23 dB and the phase is about
-106 degrees. For 60 degrees of phase margin, additional phase boost from a feed forward capacitor in parallel
with the upper resistor of the voltage set point divider is not needed. R3 sets the gain of the compensated error
amplifier to be equal and opposite the power stage gain at crossover. The required value of R3 can be calculated
from Equation 26 .
-GPWRSTG
20
VOUT
VREF
10
R3 =
×
gmEA
(26)
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 31.62
kHz. The required value for C4 is given by Equation 27.
1
C4 =
FCO
2× p×R3×
10
(27)
To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 31.62
kHz. The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. The value for C5
can be calculated from Equation 28.
1
C5 =
2× p ×R3×10×FCO
(28)
For this design the calculated values for the compensation components are R3 = 3.74 kΩ ,C4 = 0.012 µF and C5
= 120 pF.
BOOTSTRAP CAPACITOR
Every TPS54335 design requires a bootstrap capacitor, C3. The bootstrap capacitor must be 0.1 μF. The
bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a high-
quality ceramic type with X7R or X5R grade dielectric for temperature stability.
POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or
pulse skipping Eco-modeTM
.
The device power dissipation includes:
1) Conduction loss: Pcon = Iout2 x RDS(on) x VOUT/VIN
2) Switching loss: Psw = 0.5 x 10-9 x VIN 2 x IOUT x Fsw
20
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
3) Gate charge loss: Pgc = 22.8 x 10-9 x Fsw
4) Quiescent current loss: Pq = 0.11 x 10-3 x VIN
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
Fsw is the switching frequency (Hz).
So
Ptot = Pcon + Psw + Pgc + Pq
For given TA , TJ = TA + Rth x Ptot.
For given TJMAX = 150°C, TAMAX = TJMAX– Rth x Ptot.
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C) .
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
PCB LAYOUT
The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor connection. the VIN pin, and the GND pin of the IC. The
typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum
placement is closest to the VIN and GND pins of the device. See Figure 23 for a PCB layout example. The GND
pin should be tied to the PCB ground plane at the pin of the IC. To facilitate close placement of the input bypass
capacitors, The PH pin should be routed to a small copper area directly adjacent to the pin. Use vias to rout the
PH signal to the bottom side or an inner layer. If necessary you can allow the top side copper area to extend
slightly under the body of the closest input bypass capacitor. Make the copper trace on the bottom or internal
layer short and wide as practical to reduce EMI issues. Connect the trace with vias back to the top side to
connect with the output inductor as shown after the GND pin. In the same way use a bottom or internal layer
trace to rout the PH signal across the VIN pin to connect to the BOOT capacitor as shown. Make the circulating
loop from PH to the output inductor, output capacitors and back to GND as tight as possible while preserving
adequate etch width to reduce conduction losses in the copper . For operation at full rated load, the ground area
near the IC must provide adequate heat dissipating area. Connect the exposed thermal pad to bottom or internal
layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top side copper to
the internal or bottom layer copper. The additional external components can be placed approximately as shown.
Use a separate ground trace to connect the feed back, compensation, UVLO and RT (SS for TPS54336) returns.
Connect this ground trace to the main power ground at a single point to minimize circulating currents. It may be
possible to obtain acceptable performance with alternate layout schemes, however this layout has been shown to
produce good results and is intended as a guideline.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
VIA to Power Ground Plane
VIA to SW Copper Pour on Bottom
or Internal Layer
Connect to VIN on
internal or bottom
layer
ANALOG
GROUND
TRACE
VIN
VIN
INPUT
BYPASS
VIN
HIGH FREQUENCY
BOOT
BYPASS
FREQUENCY
SET RESISTOR
CAPACITOR
CAPACITOR CAPACITOR
BOOT
RT
EN
UVLO
RESISTORS
VIN
PH
COMP
VSENSE
GND
COMPENSATION
NETWORK
EXPOSED
THERMAL PAD
AREA
POWER
GROUND
FEEDBACK
RESISTORS
OUTPUT
INDUCTOR
SW node copper pour
area on internal or
bottom layer
POWER
GROUND
Note: Pin 8 for TPS54336
is SS. Connect SS capacitor
instead of RT resistor from
pin 8 to GND.
OUTPUT
FILTER
CAPACITOR
VOUT
Figure 23. TPS54335DDA Board Layout
22
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
TPS54335 APPLICATION CURVES
spacer
100
90
100
90
80
70
60
50
40
30
20
10
0
80
VIN = 12 V
70
60
50
40
30
20
10
0
VIN = 24 V
VIN = 24 V
VIN = 12 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.001
0.01
0.1
1
10
C015
C016
Output Current - A
Output Current - A
Figure 24. TPS54335 Efficiency
Figure 25. TPS54335 Low Current Efficiency
spacer
spacer
0.5
0.4
0.10
0.08
0.3
0.06
IOUT = 1.5 A
0.2
0.04
0.02
VIN = 12 V
0.1
0.0
0.00
±0.1
±0.2
±0.3
±0.4
±0.5
±0.02
±0.04
±0.06
±0.08
±0.10
VIN = 24 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
8
10
12
14
16
18
20
22
24
26
28
C017
C018
Output Current - A
Input Voltage - V
Figure 26. TPS54335 Load Regulation
Figure 27. TPS54335 Line Regulation
spacer
spacer
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
60
40
20
0
180
120
60
Phase
V
= 200 mV/div (ac coupled)
OUT
0
-20
-40
-60
Gain
-60
-120
-180
I
= 1 A/div
OUT
0.75 A to 2.25 A load step,
slew rate = 500 mA / µsec
10
100
1000
10000
100000
1000000
C019
Frequency - Hz
Time = 200 µs/div
Figure 28. TPS54335 Transient Response
Figure 29. TPS54335 Loop Response
spacer
spacer
V
= 20 mV/div (ac coupled)
OUT
V
= 20 mV/div (ac coupled)
OUT
PH = 10 V/div
PH = 10 V/div
Time = 2 µs/div
Time = 2 µs/div
Figure 30. TPS54335 Full Load Output Ripple
Figure 31. TPS54335 100 mA Output Ripple
spacer
spacer
V
= 200 mV/div (ac coupled)
IN
V
= 20 mV/div (ac coupled)
OUT
PH = 10 V/div
PH = 10 V/div
Time = 100 µs/div
Time = 2 µs/div
Figure 32. TPS54335 No Load Output Ripple
Figure 33. TPS54335 Full Load Input Ripple
spacer
24
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
spacer
V
= 10 V/div
IN
V
= 10 V/div
IN
EN = 2 V/div
EN = 2 V/div
V
= 2 V/div
V
= 2 V/div
OUT
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 34. TPS54335 Start Up Relative to VIN
Figure 35. TPS54335 Start-up Relative to Enable
spacer
spacer
V
= 10 V/div
V
= 10 V/div
IN
IN
EN = 2 V/div
EN = 2 V/div
V
= 2 V/div
V
= 2 V/div
OUT
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 36. TPS54335 Shut Down Relative to VIN
Figure 37. TPS54335 Shut Down Relative to EN
TPS54336 APPLICATION SCHEMATIC
U1
TPS54336DDA
L1 15µH
VIN = 8 - 28 V
C3 0.1µF
VOUT = 5 V, 3 A max
2
1
3
6
4
VIN
VIN
BOOT
PH
VOUT
5
7
8
VSENSE
VSENSE
EN
C1
10µF
C2
0.1µF
C6
47µF
C7
47µF
R4
51.1
COMP
R1
220k
SS
GND
PAD
R3
3.74k
R5
100k
C5
120pF
VSENSE
R2
43.2k
C8
0.01µF
C4
0.012µF
R6
19.1k
Figure 38. Typical Application Schematic, TPS54336
TPS54336 DESIGN
The design procedure for the TPS54336 is identical to the TPS54335, except the TPS54336 utilizes a slow start
circuit rather than an externally set switching frequency at pin 8. The switching frequency is internally set for 340
kHz.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate.
This is also used if the output capacitance is very large and would require large amounts of current to quickly
charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may
make the TPS54336 reach the current limit or excessive current draw from the input power supply may
cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The
soft start capacitor value can be calculated using Equation 5. For the example circuit, the soft start time is
not too critical since the output capacitor value is 2 x 47 μF which does not require much current to charge to
5 V. The example circuit has the soft start time set to an arbitrary value of 3.5 ms which requires a 10 nF
capacitor. In TPS54336, Iss is 2.3 µA and Vref is 0.8V.
TPS54336 APPLICATION CURVES
spacer
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 12 V
VIN = 24 V
VIN = 24 V
VIN = 12 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.001
0.01
0.1
Output Current - A
1
10
C021
C022
Output Current - A
Figure 39. TPS54336 Efficiency
Figure 40. TPS54336 Low Current Efficiency
spacer
0.5
0.4
0.5
0.4
VIN = 24 V
0.3
0.3
0.2
0.1
0.2
VIN = 12 V
0.1
0.0
0
±0.1
±0.2
±0.3
±0.4
±0.5
-0.1
Vin=12V
-0.2
Vin=24V
-0.3
-0.4
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
C023
Output Current - A
0
0.5
1
1.5
2
2.5
3
Output Current - A
Figure 41. TPS54336 DDA Load Regulation
Figure 42. TPS54336 DRC Load Regulation
spacer
26
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
0.10
0.08
0.1
0.08
0.06
IOUT = 1.5 A
0.06
0.04
0.02
0.04
0.02
0.00
0
-0.02
-0.04
-0.06
-0.08
-0.1
±0.02
±0.04
±0.06
±0.08
±0.10
Iout=1.5A
8
12
16
20
24
28
C024
12
16
20
8
10
14
Input Voltage - V
18
22 24 26 28
Input Voltage - V
Figure 43. TPS54336 DDA Line Regulation
Figure 44. TPS54336 DRC Line Regulation
spacer
spacer
60
40
20
0
180
120
60
Phase
V
= 200 mV/div (ac coupled)
OUT
0
Gain
-20
-40
-60
-60
-120
-180
I
= 1 A/div
OUT
0.75 A to 2.25 A load step,
slew rate = 500 mA / µsec
10
100
1000
10000
100000
1000000
C025
Frequency - Hz
Time = 200 µs/div
Figure 45. TPS54336 Transient Response
Figure 46. TPS54336 Loop Response
spacer
spacer
V
= 20 mV/div (ac coupled)
OUT
V
= 20 mV/div (ac coupled)
OUT
PH = 10 V/div
PH = 10 V/div
Time = 2 µs/div
Time = 2 µs/div
Figure 47. TPS54336 Full Load Output Ripple
Figure 48. TPS54336 100 mA Output Ripple
spacer
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
www.ti.com
spacer
V
= 200 mV/div (ac coupled)
IN
V
= 20 mV/div (ac coupled)
OUT
PH = 10 V/div
PH = 10 V/div
Time = 100 µs/div
Time = 2 µs/div
Figure 49. TPS54336 No Load Output Ripple
Figure 50. TPS54336 Full Load Input Ripple
spacer
spacer
V
= 20 V/div
IN
V
= 20 V/div
IN
EN = 5 V/div
EN = 5 V/div
SS = 2 V/div
SS = 2 V/div
V
= 2 V/div
V
= 2 V/div
OUT
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 51. TPS54336 Start Up Relative to VIN
Figure 52. TPS54336 Start-up Relative to Enable
spacer
spacer
V
= 20 V/div
V
= 20 V/div
IN
IN
EN = 5 V/div
SS = 2 V/div
EN = 5 V/div
SS = 2 V/div
V
= 2 V/div
V
= 2 V/div
OUT
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 53. TPS54336 Shut Down Relative to VIN
Figure 54. TPS54336 Shut Down Relative to EN
28
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54335 TPS54336
TPS54335
TPS54336
www.ti.com
SLVSC03B –MAY 2013–REVISED NOVEMBER 2013
REVISION HISTORY
NOTE: Previous versions may have different page numbers than current version.
Changes from Original (May 2013) to Revision A
Page
•
•
Changed title from "....Step Down SWIFT™ Converter" to "....SWIFT™ Step-Down Voltage Regulator" and changed
product status from "Production Data" to "Product Mix" ....................................................................................................... 1
Changed Feature bullet from "Thermal and Overvoltage Transient Protection" to "Thermal Shutdown and
Overvoltage Transition Protection" ....................................................................................................................................... 1
•
•
Added text "...and 10-pin SON" to Feature bullet ................................................................................................................. 1
Changed Applications bullet from "...such as DTV, Set Top Boxes, LCD displays, CPE Equipment" to "....such as a
Digital TV (DTV), Set Top Box (STB, DVD/Blu-ray Player), LCD Display, CPE (Cable Modem, WiFi Router), DLP
Projectors, Smart Meters" ..................................................................................................................................................... 1
•
•
•
•
•
•
Changed Applications bullet from "...Distributed Power Systems" to "...Distributed Power Bus Supply .............................. 1
Changed Description section for clarification. ....................................................................................................................... 1
Changed Simplified Schematic images for readability ......................................................................................................... 1
Added DRC package option to Ordering Information table. ................................................................................................. 2
Added DRC package to Thermal Information table .............................................................................................................. 3
Changed Reference voltage MIN spec from "0.792" to "0.7936" and MAX from "0.808" to "0.8064" for TJ =25°C
condition ................................................................................................................................................................................ 3
•
•
•
Deleted "Error amplifier dc gain" spec from Electrical Characteristics table ........................................................................ 3
Added SON (DRC) pin assignment drawings and pin descriptions ..................................................................................... 5
Added TPS54336 DRC Load and Line Regulation characteristics graphs ........................................................................ 26
Changes from Revision A (July 2013) to Revision B
Page
•
Corrected Equation 26. ....................................................................................................................................................... 20
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: TPS54335 TPS54336
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2013
PACKAGING INFORMATION
Orderable Device
TPS54335DDA
TPS54335DDAR
TPS54336DDA
TPS54336DDAR
TPS54336DRCR
TPS54336DRCT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE SO PowerPAD
DDA
8
8
75
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
54335
54335
54336
54336
54336
54336
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
DRC
DRC
2500
75
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
8
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
8
2500
3000
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
ACTIVE
ACTIVE
SON
SON
10
10
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54335DDAR
TPS54336DDAR
SO
Power
PAD
DDA
DDA
8
8
330.0
330.0
12.8
12.8
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
SO
Power
PAD
TPS54336DRCR
TPS54336DRCT
SON
SON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54335DDAR
TPS54336DDAR
TPS54336DRCR
TPS54336DRCT
SO PowerPAD
SO PowerPAD
SON
DDA
DDA
DRC
DRC
8
8
2500
2500
3000
250
366.0
366.0
367.0
210.0
364.0
364.0
367.0
185.0
50.0
50.0
35.0
35.0
10
10
SON
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明