TPS548B22RVFR [TI]
具有差分遥感功能的 1.5V 至 18V、25A 同步 SWIFT™ 降压转换器 | RVF | 40 | -40 to 125;
| 型号： | TPS548B22RVFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有差分遥感功能的 1.5V 至 18V、25A 同步 SWIFT™ 降压转换器 | RVF | 40 | -40 to 125 PC 输入元件 开关 输出元件 转换器 |
| 文件： | 总46页 (文件大小：5019K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
TPS548B22 1.5V 至 18V VIN，4.5V 至 22V VDD，具有全差动传感功能的
25A SWIFT™ 同步降压转换器
1 特性
2 应用
1
•
•
•
•
转换输入电压范围 (PVIN)：1.5V 至 18V
•
企业级存储、固态硬盘 (SSD)、网络附属存储
(NAS)
输入偏置电压 (VDD) 范围：4.5V 至 22V
输出电压范围：0.6V 至 5.5V
•
•
无线和有线通信基础设施
工业 PC、自动化、自动测试设备 (ATE)、可编程
逻辑控制器 (PLC)、视频监控
集成型 4.1mΩ 和 1.9mΩ 功率 MOSFET，持续输
出电流为 25A
•
•
企业服务器、交换机、路由器
•
•
基准电压范围：0.6V 至 1.2V（步长为 50mV），
采用 VSEL 引脚
AISIC、SoC、FPGA、DSP 内核和 I/O 导轨
±0.5%，0.9VREF 容限范围：–40°C 至 +125°C（结
温）
3 说明
TPS548B22 器件是一款具有自适应导通时间 D-CAP3
模式控制的紧凑型单相降压转换器。该器件针对空间受
限类电源系统而设计，可实现高精度、高效率和快速瞬
态响应，易于使用，且使用的外部组件较少。
•
•
真正的差分远程感测放大器
D-CAP3™可在无需外部补偿的情况下支持大容量
电容和/或小型 MLCC 的控制环路
•
自适应导通时间控制，具有 4 种频率设置可供选
择：425kHz、650kHz、875kHz 和 1.05MHz
该器件采用 全差动传感和 TI 的集成 FET，高侧导通电
阻为 4.1mΩ，低侧导通电阻为 1.9mΩ。此外，该器件
还具备 0.5% 的精度和 0.9V 基准电压，环境温度范围
介于 –40°C 和 +125°C 之间。具有竞争力的特性 包
括：超低的外部组件数、精准的负载和线路调节、输出
电压设定值精度、自动跳过或 FCCM 工作模式以及内
部软启动控制。
•
•
•
温度补偿，并具有可编程正负电流限制和 OC 钳位
可选断续或闭锁过压保护 (OVP) 或欠压保护 (UVP)
VDD 欠压锁定 (UVLO)，通过精确的 EN 滞后从外
部进行调整
•
•
•
•
预偏置启动支持
Eco-Mode 和 FCCM 可供选择
全套故障保护和 PGOOD
7mm × 5mm × 1.5mm、40 引脚、堆叠削波式
LQFN-CLIP 封装
TPS548B22 器件采用 7mm × 5mm、40 引脚、
LQFN-CLIP (RVF) 封装（RoHs 豁免）。
器件信息(1)
器件型号
TPS548B22
封装
封装尺寸（标称值）
LQFN-CLIP (40)
7.00mm x 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化应用
PVIN
VSEL
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
MODE
PGOOD
REFIN
PGOOD
ILIM
RESV_TRK
RSN
Load
+
œ
RSP
VOSNS
ENABLE
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCE4
TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 16
7.5 Programming........................................................... 16
Applications and Implementation ...................... 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 23
Power Supply Recommendations...................... 33
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 9
6.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 器件和文档支持 ..................................................... 37
11.1 文档支持 ............................................................... 37
11.2 接收文档更新通知 ................................................. 37
11.3 社区资源................................................................ 37
11.4 商标....................................................................... 37
11.5 静电放电警告......................................................... 37
11.6 Glossary................................................................ 37
12 机械、封装和可订购信息....................................... 37
7
4 修订历史记录
Changes from Original (January 2017) to Revision A
Page
•
•
•
•
•
•
Corrected package name in title of pin connection diagram from "DQP" to "RVF"................................................................ 3
Added MIN and MAX values for VDD UVLO rising threshold................................................................................................ 6
Added MIN and MAX for all SS settings and table notes 3 and 4 in Timing Requirements .................................................. 9
Changed "VOUT = 5 V" to "VOUT = 5.5 V" .............................................................................................................................. 13
Added notes for 8 ms and 4 ms in Table 4; added Application Workaround to Support 4-ms and 8-ms SS Settings ....... 19
Added Figure 17 and Figure 18............................................................................................................................................ 19
2
Copyright © 2017, Texas Instruments Incorporated
TPS548B22
www.ti.com.cn
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
5 Pin Configuration and Functions
RVF Package
40-Pin LQFN-CLIP With Thermal Pad
Top View
32
26
27
21
31 30 29 28
25 24 23 22
PGND
PGND
20
19
18
17
16
15
33
34
35
36
37
38
VSEL
MODE
PGND
PGND
PGND
PGND
PGND
PGND
PGOOD
ILIM
RESV_TRK
RSN
Thermal Pad
14
13
39
40
RSP
VOSNS
6
7
8
9
10 11 12
1
2
3
4
5
Pin Functions
PIN
I/O/P(1)
DESCRIPTION
NO.
NAME
1, 2, 3
NU
O
I
Not used pins.
Enable pin that can turn on the DC/DC switching converter. Use also to program the required
PVIN UVLO when PVIN and VDD are connected together.
4
5
EN_UVLO
BOOT
NC
Supply rail for high-side gate driver (boot terminal). Connect boot capacitor from this pin to SW
node. Internally connected to BP via bootstrap PMOS switch.
P
6, 7, 26,
27
No connect.
8, 9, 10,
11, 12
SW
I/O
P
Output switching terminal of power converter. Connect the pins to the output inductor.
13, 14, 15,
16, 17, 18, PGND
19, 20
Power ground of internal FETs.
21, 22, 23,
PVIN
P
Power supply input for integrated power MOSFET pair.
24, 25,
28
29
30
31
32
VDD
P
P
G
O
I
Controller power supply input.
DRGND
AGND
BP
Internal gate driver return.
Ground pin for internal analog circuits.
LDO output
FSEL
Program switching frequency, internal ramp amplitude and SKIP or FCCM mode.
Program the initial start-up and or reference voltage without feedback resistor dividers (from
0.6 V to 1.2 V in 50-mV increments).
33
34
VSEL
I
I
Mode selection pin. Select the control mode (DCAP3 or DCAP), internal VREF operation,
external REFIN and tracking operation and soft-start timing selection.
MODE
35
36
37
38
39
40
PGOOD
ILIM
O
Open drain power-good status signal.
I/O
Program overcurrent limit by connecting a resistor to ground.
Do not connect.
RESV_TRK
RSN
I
I
I
I
Inverting input of the differential remote sense amplifier.
Non-inverting input of the differential remote sense amplifier.
Output voltage monitor input pin.
RSP
VOSNS
(1) I = input, O = output, G = GND
Copyright © 2017, Texas Instruments Incorporated
3
TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–5
MAX
UNIT
PVIN
VDD
25
25
BOOT
34
DC
BOOT to SW
7.7
9.0
6
< 10 ns
NU
Input voltage
V
EN_UVLO, VOSNS, MODE, FSEL, ILIM
7.7
3.6
0.3
0.3
25
RSP, RESV_TRK, VSEL
RSN
PGND, AGND, DRGND
DC
SW
< 10 ns
27
Output voltage
PGOOD, BP
–0.3
–55
7.7
150
150
Junction temperature, TJ
Storage temperature, Tstg
°C
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2017, Texas Instruments Incorporated
TPS548B22
www.ti.com.cn
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
PVIN with no snubber circuit:
SW ringing peak voltage equals 23 V at 25-A output
1.5
14
PVIN with snubber circuit:
SW ringing peak voltage equals 23 V at 25-A output
1.5
18
VDD
4.5
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–5
22
24.5
6.5
7
BOOT
DC
BOOT to SW
< 10 ns
Input voltage
V
NU
5.5
5.5
3.3
0.1
0.1
18
EN_UVLO, VOSNS, MODE, FSEL, ILIM
RSP, RESV_TRK, VSEL
RSN
PGND, AGND, DRGND
DC
SW
< 10 ns
27
Output voltage
PGOOD, BP
–0.1
–40
7
V
Junction temperature, TJ
125
°C
6.4 Thermal Information
TPS548B22
RVF (QFN)
40 PINS
28.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
18.3
3.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.96
ψJB
3.6
RθJC(bot)
0.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
5
TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
www.ti.com.cn
6.5 Electrical Characteristics
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
MOSFET ON-RESISTANCE (RDS(on)
)
High-side FET
(VBOOT – VSW) = 5 V, ID = 25 A, TJ = 25°C
VVDD = 5 V, ID = 25 A, TJ = 25°C
4.1
1.9
mΩ
mΩ
RDS(on)
Low-side FET
INPUT SUPPLY AND CURRENT
VVDD
VDD supply voltage
Nominal VDD voltage range
4.5
22
V
IVDD
VDD bias current
No PVIN, EN_UVLO = High, TA = 25°C,
No PVIN, EN_UVLO = Low, TA = 25°C
2
mA
µA
IVDDSTBY
VDD standby current
700
UNDERVOLTAGE LOCKOUT
VDD UVLO rising
threshold
VVDD_UVLO
4.23
4.25
4.34
V
VVDD_UVLO(HYS)
VEN_ON_TH
VEN_HYS
VDD UVLO hysteresis
EN_UVLO on threshold
EN_UVLO hysteresis
0.2
1.6
V
V
1.45
270
1.75
340
300
mV
EN_UVLO input leakage
current
IEN_LKG
VEN_UVLO = 5 V
–1
0
1
µA
INTERNAL REFERENCE VOLTAGE, EXTERNAL REFIN, AND TRACKING RANGE
VINTREF
Internal REF voltage
900.4
mV
Internal REF voltage
tolerance
VINTREFTOL
–40°C ≤ TJ ≤ 125°C
–0.5%
0.6
0.5%
1.2
Internal REF voltage
range
VINTREF
V
OUTPUT VOLTAGE
VIOS_LPCMP
Loop comparator input
offset voltage(1)
–2.5
2.5
1
mV
IRSP
RSP input current
VRSP = 600 mV
–1
8
µA
IVO(dis)
VO discharge current
VVO = 0.5 V, power conversion disabled
12
7
mA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
fUGBW
A0
Unity gain bandwidth(1)
Open loop gain(1)
Slew rate(1)
Input range(1)
Input offset voltage(1)
5
MHz
dB
75
SR
±4.7
V/µsec
V
VIRNG
VOFFSET
–0.2
–3.5
1.8
3.5
mV
INTERNAL BOOT STRAP SWITCH
VF
Forward voltage
VBP-BOOT, IF = 10 mA, TA = 25°C
0.1
0.2
1.5
V
IBOOT
VBST leakage current
VBOOT = 30 V, VSW = 25 V, TA = 25°C
0.01
µA
(1) Specified by design. Not production tested.
6
Copyright © 2017, Texas Instruments Incorporated
TPS548B22
www.ti.com.cn
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
MODE, VSEL, FSEL DETECTION
Open
VBP
1.9091
1.8243
1.7438
1.6725
1.6042
1.5348
1.465
RLOW = 187 kΩ
RLOW = 165 kΩ
RLOW = 147 kΩ
RLOW = 133 kΩ
RLOW = 121 kΩ
RLOW = 110 kΩ
RLOW = 100 kΩ
RLOW = 90.9 kΩ
RLOW = 82.5 kΩ
RLOW = 75 kΩ
1.3952
1.3245
1.2557
1.187
RLOW = 68.1 kΩ
RLOW = 60.4 kΩ
RLOW = 53.6 kΩ
RLOW = 47.5 kΩ
RLOW = 42.2 kΩ
RLOW = 37.4 kΩ
RLOW = 33.2 kΩ
RLOW = 29.4 kΩ
RLOW = 25.5 kΩ
RLOW = 22.1 kΩ
RLOW = 19.1 kΩ
RLOW = 16.5 kΩ
RLOW = 14.3 kΩ
RLOW = 12.1 kΩ
RLOW = 10 kΩ
1.1033
1.0224
0.9436
0.8695
0.7975
0.7303
0.6657
0.5953
0.5303
0.4699
0.415
VBP = 2.93 V,
RHIGH = 100 kΩ
MODE, VSEL, and FSEL
detection voltage
VDETECT_TH
V
0.3666
0.3163
0.2664
0.2138
0.1708
0.1299
0.0898
0.0512
GND
RLOW = 7.87 kΩ
RLOW = 6.19 kΩ
RLOW = 4.64 kΩ
RLOW = 3.16 kΩ
RLOW = 1.78 kΩ
RLOW = 0 Ω
PGOOD COMPARATOR
PGOOD in from higher
PGOOD in from lower
PGOOD out to higher
PGOOD out to lower
VPGOOD = 0.5 V
105
89
108
92
111
95
VPGTH
PGOOD threshold
%VREF
120
68
IPG
PGOOD sink current
6.9
0
mA
IPGLK
PGOOD leakage current VPGOOD = 5 V
–1
1
μA
Copyright © 2017, Texas Instruments Incorporated
7
TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
CURRENT DETECTION
VILM
VILIM voltage range
On-resistance (RDS(on)) sensing
0.1
1.2
V
A
RLIM = 61.9 kΩ
OC tolerance
RLIM = 51.1 kΩ
OC tolerance
RLIM = 40.2 kΩ
RLIM = 61.9 kΩ
RLIM = 51.1 kΩ
RLIM = 40.2 kΩ
30
±15%
25
Valley current limit
threshold
IOCL_VA
A
A
A
±15%
20
17
23
–30
Negative valley current
limit threshold
IOCL_VA_N
–25
–20
Clamp current at VLIM
clamp at lowest
ICLMP_LO
ICLMP_HI
VZC
VILIM_CLMP = 0.1 V, TA = 25°C
VILIM_CLMP = 1.2 V, TA = 25°C
5
50
0
A
A
Clamp current at VLIM
clamp at highest
Zero cross detection
offset
mV
PROTECTIONS AND OOB
Wake-up
3.32
3.11
120%
68%
8%
V
BP UVLO threshold
voltage
VBPUVLO
Shutdown
VOVP
OVP threshold voltage
UVP threshold voltage
OOB threshold voltage
OVP detect voltage
UVP detect voltage
117%
65%
123%
71%
VREF
VREF
VREF
VUVP
VOOB
BP VOLTAGE
VBP
BP LDO output voltage
VIN = 12 V, 0 A ≤ ILOAD ≤ 10 mA,
5.07
100
165
V
VBPDO
BP LDO drop-out voltage VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C
365
30
mV
BP LDO over-current
VIN = 12 V, TA = 25°C
limit
IBPMAX
mA
°C
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
155
Built-In thermal shutdown
TSDN
threshold(1)
8
Copyright © 2017, Texas Instruments Incorporated
TPS548B22
www.ti.com.cn
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
SWITCHING FREQUENCY
380
585
790
950
425
650
875
1050
60
475
740
VO switching
fSW
VIN = 12 V, VVO = 1 V, TA = 25°C
DRVH falling to rising
kHz
frequency(1)
995
1250
tON(min)
Minimum on time(2)
Minimum off time(2)
ns
ns
tOFF(min)
300
SOFT-START
RMODE_LOW = 60.4 kΩ
7
3.6
1.6
0.8
8(3)
4(4)
2
10
5.2
2.8
1.6
ms
ms
ms
ms
VOUT rising from 0 V to
95% of final set point,
RMODE_HIGH = 100 kΩ
RMODE_LOW = 53.6 kΩ
RMODE_LOW = 47.5 kΩ
RMODE_LOW = 42.2 kΩ
tSS
Soft-start time
1
PGOOD COMPARATOR
Delay for PGOOD going in
1
ms
µs
tPGDLY
PGOOD delay time
Delay for PGOOD coming out
2
1
POWER-ON DELAY
tPODLY
Power-on delay time
1.024
ms
PROTECTIONS AND OOB
tOVPDLY
tUVPDLY
OVP response time
100-mV over drive
µs
ms
ms
ms
ms
ms
UVP delay filter delay time
1
16
24
38
67
tSS = 1 ms
tSS = 2 ms
tSS = 4 ms
tSS = 8 ms
tHICDLY
Hiccup blanking time
(1) Correlated with closed-loop EVM measurement at load current of 20 A.
(2) Specified by design. Not production tested.
(3) In order to use the 8-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.
(4) In order to use the 4-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.
Copyright © 2017, Texas Instruments Incorporated
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TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
www.ti.com.cn
6.7 Typical Characteristics
100%
95%
90%
85%
80%
75%
70%
65%
60%
100%
95%
90%
85%
80%
75%
70%
65%
60%
VIN = 5 V
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
0
5
10
15
20
25
0
5
10
15
20
25
Output Current (A)
Output Current (A)
D001
D002
VOUT = 1 V
VDD = VIN
SKIP Mode
VOUT = 1 V
fSW = 650 kHz
VDD = VIN
FCCM Mode
fSW = 650 kHz
Figure 1. Efficiency vs Output Current
Figure 2. Efficiency vs Output Current
4.5
4
1.01
1.005
1
3.5
3
2.5
2
1.5
1
0.995
0.99
VIN = 5 V
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
0.5
0
0
5
10
15
20
25
0
5
10
15
20
25
Output Current (A)
Output Current (A)
D003
D004
VOUT = 1 V
VDD = VIN
SKIP Mode
VOUT = 1 V
VDD = VIN
FCCM Mode
fSW = 650 kHz
fSW = 650 kHz
Figure 3. Converter Power Loss vs Output Current
Figure 4. Output Voltage Regulation vs Output Current
2.525
100%
95%
90%
85%
80%
2.52
2.515
2.51
2.505
2.5
2.495
2.49
VIN = 5 V
VIN = 5 V
2.485
2.48
VIN = 12 V
VIN = 14 V
VIN = 18 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
2.475
0
5
10
15
20
25
0
5
10
15
20
SKIP Mode
25
Output Current (A)
Output Current (A)
D005
D006
VDD = VIN
fSW = 650 kHz
L= 820 nH, 0.9 mΩ
SKIP Mode
VDD = VIN
fSW = 650 kHz
L= 820 nH, 0.9 mΩ
VOUT = 2.5 V
VOUT = 2.5 V
Figure 5. Efficiency vs Output Current
Figure 6. Output Voltage Regulation vs Output Current
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Typical Characteristics (continued)
100%
6
5
4
3
2
1
0
95%
90%
85%
80%
VIN = 9 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
0
5
10
15
20
FCCM Mode
25
0
5
10
15
20
25
Output Current (A)
Output Current (A)
D007
D008
VDD = VIN
fSW = 650 kHz
L= 820 nH, 0.9 mΩ
VDD = VIN
fSW = 650 kHz
FCCM Mode
VOUT = 5 V
VOUT = 5 V
L= 820 nH, 0.9 mΩ
Figure 7. Efficiency vs Output Current
Figure 8. Power Loss vs Output Current
IOUT = 25 A
IOUT = 25 A
VDD = VIN = 12 V
VOUT = 1 V
fSW = 650 kHz
VDD = VIN = 18 V
VOUT = 1 V
fSW = 650 kHz
Natural convection at room temperature
Natural convection at room temperature
Figure 9. Thermal Image
Figure 10. Thermal Image
IOUT = 25 A
VDD = VIN = 12 V
VOUT = 2.5 V
fSW = 650 kHz
IOUT = 25 A
VDD = VIN = 12 V
VOUT = 5 V
fSW = 650 kHz
Natural convection at room temperature
Natural convection at room temperature
Figure 11. Thermal Image
Figure 12. Thermal Image
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7 Detailed Description
7.1 Overview
The TPS548B22 device is a high-efficiency, single-channel, FET-integrated, synchronous buck converter. It is
suitable for point-of-load applications with 25 A or lower output current in storage, telecomm and similar digital
applications. The device features proprietary D-CAP3 mode control combined with adaptive on-time architecture.
This combination is ideal for building modern high/low duty ratio, ultra-fast load step response DC-DC converters.
The TPS548B22 device has integrated MOSFETs rated at 25-A TDC.
The converter input voltage range is from 1.5 V up to 18 V, and the VDD input voltage range is from 4.5 V to
22 V. The output voltage ranges from 0.6 V to 5.5 V.
Stable operation with all ceramic output capacitors is supported, because the D-CAP3 mode uses emulated
current information to control the modulation. An advantage of this control scheme is that it does not require
phase compensation network outside which makes it easy to use and also enables low external component
count. The designer selects the switching frequency from 4 preset values via resistor settings by FSEL pin.
Adaptive on-time control tracks the preset switching frequency over a wide range of input and output voltage
while increasing switching frequency as needed during load step transient.
7.2 Functional Block Diagram
External
soft-start
RESV_TRK
VREF + 8/16 %
PGOOD
VREF œ 32%
+
UV
+
MUX
Internal
soft-start
EN_UVLO
Delay
Control
+
+
OV
BOOT
PVIN
VREF + 20%
RSN
RSP
VREF œ 8/16 %
+
PWM
+
+
+
XCON
D-CAP3TM
Ramp Generator
VOUT
VOSNS
VREF
tON
One-Shot
SW
Reference
Generator
Control
Logic
VSEL
FSEL
Switching
Frequency
Programmer
BP
+
ZC
x
(1/16)
PGND
ILIM
x
+
LDO
Regulator
(œ1/16)
AGND
VDD
OCP
DRGND
MODE
MODE Logic
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7.3 Feature Description
7.3.1 25-A FET
The TPS548B22 device is a high-performance, integrated FET converter supporting current rating up to 25 A
thermally. It integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB
layout area. The drain-to-source breakdown voltage for these FETs is 25 V DC and 27 V transient for 10 ns.
Avalanche breakdown occurs if the absolute maximum voltage rating exceeds 27 V. In order to limit the switch
node ringing of the device, TI recommends adding a R-C snubber from the SW node to the PGND pins. Refer to
the Layout Guidelines section for the detailed recommendations.
7.3.2 On-Resistance
The typical on-resistance (RDS(on)) for the high-side MOSFET is 4.1 mΩ and typical on-resistance for the low-side
MOSFET is 1.9 mΩ with a nominal gate voltage (VGS) of 5 V.
7.3.3 Package Size, Efficiency and Thermal Performance
The TPS548B22 device is available in a 7 mm × 5 mm VQFN package with 40 power and I/O pins. It employs TI
proprietary MCM packaging technology with thermal pad. With a properly designed system layout, applications
achieve optimized safe operating area (SOA) performance. The curves shown in Figure 13 and Figure 14 are
based on the orderable evaluation module design. (See SLUUBI9 to order the EVM.)
110
100
90
110
100
90
80
80
70
70
60
60
50
50
Nat Conv
100 LFM
200 LFM
400 LFM
Nat Conv
100 LFM
200 LFM
400 LFM
40
40
30
30
0
5
10
15
20
25
0
5
10
15
20
25
Output Current (A)
Output Current (A)
D012
D011
VIN = 12 V
VOUT = 5.5 V
fSW = 650 kHz
VIN = 12 V
VOUT = 1 V
fSW = 650 kHz
Figure 13. Safe Operating Area
Figure 14. Safe Operating Area
7.3.4 Soft-Start Operation
In the TPS548B22 device the soft-start time controls the inrush current required to charge the output capacitor
bank during start-up. The device offers selectable soft-start options of 1 ms, 2 ms, 4 ms and 8 ms. When the
device is enabled (either by EN or VDD UVLO), the reference voltage ramps from 0 V to the final level defined by
VSEL pin strap configuration, in a given soft-start time. The TPS548B22 device supports several soft-start times
between 1 msec and 8 msec selected by MODE pin configuration. Refer to Table 4 for details.
7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
The TPS548B22 device provides fixed VDD undervoltage lockout threshold and hysteresis. The typical VDD
turn-on threshold is 4.25 V, and hysteresis is 0.2 V. The VDD UVLO can be used in conjunction with the
EN_UVLO signal to provide proper power sequence to the converter design. UVLO is a non-latched protection.
7.3.6 EN_UVLO Pin Functionality
The EN_UVLO pin drives an input buffer with accurate threshold and can be used to program the exact required
turnon and turnoff thresholds for switcher enable, VDD UVLO, or VIN UVLO (if VIN and VDD are tied together). If
desired, an external resistor divider can be used to set and program the turn-on threshold for VDD or VIN UVLO.
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Feature Description (continued)
Figure 15 shows how to program the input voltage UVLO using the EN_UVLO pin.
PVIN
29
28
26 25 24 23 22 21
PGND 20
PGND 19
PGND 18
PGND 17
PGND 16
PGND 15
PGND 14
PGND 13
TPS548B22
4
PVIN
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Programming the UVLO Voltage
7.3.7 Fault Protections
This section describes positive and negative overcurrent limits, overvoltage protections, out-of-bounds limits,
undervoltage protections and over temperature protections.
7.3.7.1 Current Limit (ILIM) Functionality
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
40
Output Current (A)
D010
Figure 16. Current Limit Resistance vs OCP Valley Overcurrent Limit
14
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Feature Description (continued)
The ILIM pin sets the OCP level. Connect the ILIM pin to GND through the voltage setting resistor, RILIM. In order
to provide both good accuracy and cost effective solution, TPS548B22 supports temperature compensated
internal MOSFET RDS(on) sensing.
Also, the device performs both positive and negative inductor current limiting with the same magnitudes. The
positive current limit normally protects the inductor from saturation that causes damage to the high-side FET and
low-side FET. The negative current limit protects the low-side FET during OVP discharge.
The voltage between GND pin and SW pin during the OFF time monitors the inductor current. The current limit
has 1200 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance (RDS(on)).
The GND pin is used as the positive current sensing node.
TPS548B22 uses cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent ILIM level. VILIM sets the valley level of the inductor current.
7.3.7.2 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
Table 1. Overvoltage Protection Details
REFERENCE
VOLTAGE
START-UP
OVP
THRESHOLD
OPERATING
OVP
THRESHOLD
OVP DELAY
100 mV OD
(µs)
SOFT-START
RAMP
OVP RESET
(VREF
)
Internal
Internal
1.2 × Internal VREF
1
UVP
The device monitors a feedback voltage to detect overvoltage and undervoltage. When the feedback voltage
becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay
counter begins counting. After 1 ms, the device latches OFF both high-side and low-side MOSFETs drivers. The
UVP function enables after soft start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS548B22 device operates in this cycle until the output
voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side
FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the
EN pin.
7.3.7.3 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so
the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-
protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning
on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output
capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-by-
cycle negative current limit is also activated to ensure the safe operation of the internal FETs.
7.3.7.4 Overtemperature Protection
TPS548B22 has overtemperature protection (OTP) by monitoring the die temperature. If the temperature
exceeds the threshold value (default value 165°C), the device is shut off. When the temperature falls about 25°C
below the threshold value, the device turns on again. The OTP is a non-latch protection.
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7.4 Device Functional Modes
7.4.1 DCAP3 Control Topology
The TPS548B22 employs an artificial ramp generator that stabilizes the loop. The ramp amplitude is
automatically adjusted as a function of selected switching frequency (fSW). The ramp amplitude is a function of
duty cycle (VOUT-to-VIN ratio). Consequently, two additional pin-strap bits (FSEL[2:1]) are provided for fine tuning
the internal ramp amplitude. The device uses an improved DCAP3 control loop architecture that incorporates a
steady-state error integrator. The slow integrator improves the output voltage DC accuracy greatly and presents
minimal impact to small signal transient response. To further enhance the small signal stability of the control
loop, the device uses a modified ramp generator that supports a wider range of output LC stage.
7.4.2 DCAP Control Topology
For advanced users of this device, the internal DCAP3 ramp can be disabled using the MODE[4] pin strap bit.
This situation requires an external RCC network to ensure control loop stability. Place this RCC network across
the output inductor. Use a range between 10 mV and 15 mV of injected RSP pin ripple. If no feedback resistor
divider network is used, insert a 10-kΩ resistor between the VOUT pin and the RSP pin.
7.5 Programming
7.5.1 Programmable Pin-Strap Settings
FSEL, VSEL and MODE. Description: a 1% or better 100-kΩ resistor is needed from BP to each of the three
pins. The bottom resistor from each pin to ground (see Table 2) in conjunction with the top resistor defines each
pin strap selection. The pin detection checks for external resistor divider ratio during initial power up (VDD is
brought down below approximately 3 V) when BP LDO output is at approximately 2.9 V.
7.5.1.1 Frequency Selection (FSEL) Pin
The TPS548B22 device allows users to select the switching frequency, light load and internal ramp amplitude by
using FSEL pin. Table 2 lists the divider resistor values for the selection. The 1% tolerance resistors with typical
temperature coefficient of ±100ppm/°C are recommended. Higher performance resistors can be used if tighter
noise margin is required for more reliable frequency selection detection.
FSEL pin strap configuration programs the switching frequency, internal ramp compensation and light load
conduction mode.
.
16
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Programming (continued)
Table 2. FSEL Pin Strap Configurations
FSEL[4]
FSEL[3]
FSEL[2]
FSE[L1]
FSEL[0]
CM
(1)
RFSEL (kΩ)
FSEL[1:0]
RCSP_FSEL[1:0]
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
1: FCCM
0: SKIP
Open
187
165
147
133
121
110
100
90.9
82.5
75
11: R × 3
10: R × 2
01: R × 1
00: R/2
11: 1.05 MHz
11: R × 3
10: R×2
01: R × 1
00: R/2
68.1
60.4
53.6
47.5
42.2
37.4
33.2
29.4
25.5
22.1
19.1
16.5
14.3
12.1
10
10: 875 kHz
01: 650 kHz
00: 425 kHz
11: R × 3
10: R × 2
01: R × 1
00: R/2
11: R × 3
10: R × 2
01: R × 1
00: R/2
7.87
6.19
4.64
3.16
1.78
0
(1) 1% or better and connect to ground
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7.5.1.2 VSEL Pin
VSEL pin strap configuration is used to program initial boot voltage value, hiccup mode and latch off mode. The
initial boot voltage is used to program the main loop voltage reference point. VSEL voltage settings provide TI
designated discrete internal reference voltages. Table 3 lists internal reference voltage selections.
Table 3. Internal Reference Voltage Selections
(1)
VSEL[4]
VSEL[3]
VSE[L2]
VSEL[1]
VSEL[0]
1: Latch-Off
0: Hiccup
RVSEL (kΩ)
Open
187
1111: 0.975 V
1: Latch-Off
0: Hiccup
165
1110: 1.1992 V
1101: 1.1504 V
1100: 1.0996 V
1011: 1.0508 V
1010: 1.0000 V
1001: 0.9492 V
1000: 0.9023 V
0111: 0.9004 V
0110: 0.8496 V
0101: 0.8008 V
0100: 0.7500 V
0011: 0.6992 V
0010: 0.6504 V
0001: 0.5996 V
0000: 0.975 V
147
1: Latch-Off
0: Hiccup
133
121
1: Latch-Off
0: Hiccup
110
100
1: Latch-Off
0: Hiccup
90.9
82.5
75
1: Latch-Off
0: Hiccup
68.1
60.4
53.6
47.5
42.2
37.4
33.2
29.4
25.5
22.1
19.1
16.5
14.3
12.1
10
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
7.87
6.19
4.64
3.16
1.78
0
1: Latch-Off
0: Hiccup
1: Latch-Off
0: Hiccup
(1) 1% or better and connect to ground
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7.5.1.3 DCAP3 Control and Mode Selection
The MODE pinstrap configuration programs the control topology and internal soft-start timing selections. The
device supports both DCAP3 and DCAP operation modes.
MODE[4] selection bit is used to set the control topology. If MODE[4] bit is 0, it selects DCAP operation. If
MODE[4] bit is 1, it selects DCAP3 operation.
MODE[1] and MODE[0] selection bits are used to set the internal soft-start timing.
Table 4. Allowable MODE Pin Selections
(1)
MODE[4]
MODE[3]
MODE[2]
MODE[1]
MODE[0]
RMODE (kΩ)
60.4
11: 8 ms(2)
10: 4 ms(2)
01: 2 ms
53.6
0: Internal
Reference
1: DCAP3
0: Internal SS
47.5
00: 1 ms
42.2
11: 8 ms(2)
10: 4 ms(2)
01: 2 ms
4.64
3.16
0: Internal
Reference
0: DCAP
0: Internal SS
1.78
00: 1 ms
0
(1) RMODE settings in lighter shade are not permitted (24 settings).
(2) See Application Workaround to Support 4-ms and 8-ms SS Settings.
7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings
In order to properly design for 4-ms and 8-ms SS settings, additional application consideration is needed. The
recommended application workaround to support the 4-ms and 8-ms soft-start settings is to ensure sufficient time
delay between the VDD and EN_UVLO signals. The minimum delay between the rising maximum VDD_UVLO
level and the minimum turnon threshold of EN_UVLO is at least TDELAY_MIN
.
TDELAY_MIN = K × VREF
where
•
•
•
K = 9 ms/V for SS setting of 4 ms
K = 18 ms/V for SS setting of 8 ms
VREF is the internal reference voltage programmed by VSEL pin strap
(1)
For example, if SS setting is 4 ms and VREF = 1 V, program the minimum delay at least 9 ms; if SS setting is 8
ms, the minimum delay should be programmed at least 18 ms. See Figure 17 and Figure 18 for detailed timing
requirement.
Figure 17. Proper Sequencing of VDD and EN_UVLO to Support the use of 4-ms SS Setting
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VDD
VDD_UVLO
Maximum Threshold
4.34 V
EN_UVLO
EN_UVLO
Minimum ON Threshold 1.45 V
Minimum
TDELAY_MIN
Figure 18. Minimum Delay Between VDD and EN_UVLO to Support the use of 4-ms and 8-ms SS settings
The workaround/consideration described previously is not required for SS settings of 1 ms and 2 ms.
7.5.2 Programmable Analog Configurations
7.5.2.1 RSP/RSN Remote Sensing Functionality
RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for
output voltage programming, connect the RSP pin to the mid-point of the resistor divider; always connect the
RSN pin to the load return. When feedback resistors are not required as when the VSEL programs the output
voltage setpoint, always connect the RSP pin to the positive sensing point of the load, and always connect the
RSN pin to the load return.
RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier.
The feedback resistor divider must use resistor values much less than 100 kΩ.
7.5.2.1.1 Output Differential Remote Sensing Amplifier
The examples in this section show simplified remote sensing circuitry that each use an internal reference of 1 V.
Figure 19 shows remote sensing without feedback resistors, with an output voltage setpoint of 1 V. Figure 20
shows remote sensing using feedback resistors, with an output voltage set point of 5 V.
20
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TPS548B22
TPS548B22
38 RSN
38 RSN
39 RSP
39 RSP
40 VOSNS
40 VOSNS
BOOT
BOOT
5
5
Load
Load
+
œ
+
œ
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Remote Sensing Without Feedback
Resistors
Figure 20. Remote Sensing With Feedback
Resistors
7.5.2.2 Power Good (PGOOD Pin) Functionality
The TPS548B22 device has power-good output that registers high when switcher output is within the target. The
power-good function is activated after soft-start has finished. When the soft-start ramp reaches 300 mV above
the internal reference voltage, SSend signal goes high to enable the PGOOD detection function. If the output
voltage becomes within ±8% of the target value, internal comparators detect power-good state, and the power-
good signal becomes high after a 1-ms programmable delay. If the output voltage goes outside of ±16% of the
target value, the power good signal becomes low after two microsecond (2-µs) internal delay. The open-drain,
power-good output must be pulled up externally.
The internal N-channel MOSFET does not pull down until the VDD supply is above 1.2 V.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS548B22 device is a highly integrated synchronous step-down DC-DC converters. These devices are
used to convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 25 A.
Use the following design procedure to select key component values for this family of devices.
22
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8.2 Typical Applications
8.2.1 TPS548B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
J1
VIN = 6V - 16V
C1
DNP330uF
C2
22µF
C3
22µF
C4
22µF
C5
22µF
C6
22µF
C7
22µF
C8
22µF
C9
22µF
C10
2200pF
C11
100µF
C12
330uF
C13
22µF
C14
DNP
22uF
C15
DNP
22uF
C16
DNP
22uF
C17
DNP
22uF
C18
DNP
22uF
C19
DNP
22uF
C20
DNP
22µF
DNP
J2
PGND
VDD
TP1
R1
1.00
U1
VDD
28
40
5
VDD
VOSNS
NetC31_1
VOUT = 1V
R10
0
TP2
TP3
J3
BOOT
C34
1uF
C35
1µF TP4
R2
DNP
0
R3
DNP
0
DNP
21
22
23
24
25
PVIN
PVIN
PVIN
PVIN
PVIN
I_OUT = 25A MAX
TP5
SW
C22
0.1µF
L1
8
SW
SW
SW
SW
SW
9
R6
200k
10
11
12
330nH
DRGND
TP6
CHB
R4
0
C21
DNP
470pF
R5
1.50k
DNP
TP9
BP
C23
DNP
470µF
C24
470µF
R11
0
C25
100µF
C26
100µF
C27
DNP
100µF
C28
DNP
100µF
C29
100µF
C30
DNP
100uF
BP
4
R7
0
EN_UVLO
BP
CNTL
CNTL/EN_UVLO
J4
6
TP19
R9
DNP
3.01
NC
NC
NC
NC
TP7
CHA
C32
R8
DNP
1.10k
6800pF
31
7
26
27
C31
DNP
0.1uF
PGOOD
TP8
LOW
R13
C33
100µF
R12
100k
35
34
32
33
36
37
1
C45
4.7µF
PGOOD
MODE
FSEL
VSEL
ILIM
DNPC44
1uF
100k
C36
1000pF
R14
DNP
DNP
MODE
FSEL
VSEL
C37
DNP
470uF
C38
470µF
C39
100µF
C40
100µF
C41
DNP
100µF
C42
100µF
C43
DNP
100uF
39
38
PGND
0
RSP
RSN
R15
10.0k
NetC31_1
DRGND
TP12
ILIM
DRGND
R16
J5
0
TP14
R19
61.9k
RESV_TRK
NU
13
14
15
16
17
18
19
20
TP10
TP11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
R17
DNP
0
R18
DNP
DNPC46
1000pF
ALERT
DATA
CLK
0
2
NU
3
NU
29
30
TP13
PGND
TP18
PGND
PGND
DRGND
AGND
AGND
41
PAD
NT1
NT2
TPS548B22RVFR
Net-Tie
Net-Tie
DRGND AGND
PGND AGND
PGND
DRGND
----- GND NET TIES -----
TP15
VSEL
TP16
MODE
TP17
FSEL
BP
J6
TP20
CLK
TP21
DNP
TP22
DNP
ALERT
DNP
1
3
2
DATA
4
R20
100k
R21
100k
R22
100k
5
6
DNP
7
8
9
10
VSEL
MODE
FSEL
PMBus
R23
37.4k
R24
42.2k
R25
25.5k
AGND
AGND
Figure 21. Typical Application Schematic
Copyright © 2017, Texas Instruments Incorporated
23
TPS548B22
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8.2.2 Design Requirements
For this design example, use the input parameters shown in Table 5.
Table 5. Design Example Specifications
PARAMETER
Input voltage
VIN(ripple) Input ripple voltage
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN
5
12
18
V
V
V
IOUT = 25 A
0.4
VOUT
Output voltage
1
Line regulation
5 V ≤ VIN ≤ 18 V
0 V ≤ IOUT ≤ 25 A
IOUT = 25 A
0.5%
0.5%
Load regulation
VPP
VOVER
VUNDER
IOUT
tSS
Output ripple voltage
Transient response overshoot
Transient response undershoot
Output current
10
30
30
mV
mV
mV
A
ISTEP = 15 A
ISTEP = 15 A
5 V ≤ VIN ≤ 18 V
25
Soft-start time
Overcurrent trip point(1)
1
32
ms
A
IOC
η
Peak efficiency
IOUT = 7 A
90%
650
fSW
Switching frequency
kHz
(1) DC overcurrent level
8.2.3 Design Procedure
8.2.3.1 Switching Frequency Selection
Select a switching frequency for the regulator. There is a trade off between higher and lower switching
frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and
smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher
switching frequency causes extra switching losses, which decrease efficiency and impact thermal performance.
In this design, a moderate switching frequency of 650 kHz achieves both a small solution size and a high-
efficiency operation with the frequency selected.
Select one of four switching frequencies and FSEL resistor values from Table 6. The recommended high-side
RFSEL value is 100 kΩ (1%). Choose a low-side resistor value from Table 6 based on the choice of switching
frequency. For each switching frequency selection, there are multiple values of RFSEL(LS) to choose from. In order
to select the correct value, additional considerations (internal ramp compensation and light load operation) other
than switching frequency need to be included.
24
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TPS548B22
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ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
Table 6. FSEL Pin Selection
SWITCHING
FREQUENCY
fSW (kHz)
HIGH-SIDE RESISTOR
RFSEL(HS)
(kΩ) 1% or better
LOW-SIDE RESISTOR
RFSEL(LS) (kΩ)
FSEL VOLTAGE
VFSEL (V)
1% or better
MAXIMUM
MINIMUM
Open
187
165
147
133
121
110
100
90.9
82.5
75
1050
875
650
425
2.93
1.465
100
100
100
100
68.1
60.4
53.6
47.5
42.2
37.4
33.2
29.4
25.5
22.1
19.1
16.5
14.3
12.1
10
1.396
0.798
0.317
0.869
0.366
0
7.87
6.19
4.64
3.16
1.78
0
There is some limited freedom to choose FSEL resistors that have other than the recommended values. The
criteria is to ensure that for particular selection of switching frequency, the FSEL voltage is within the maximum
and minimum FSEL voltage levels listed in Table 6. Use Equation 2 to calculate the FSEL voltage. Select FSEL
resistors that include tolerances of 1% or better.
2&3%, (,3)
6
& 3%,
= 6"0(§•¥) ×
2&3%,(ꢀ3 ) + 2&3%, ( ,3 )
where
•
VBP(det) is the voltage used by the device to program the level of valid FSEL pin voltage during initial device
start-up (2.9 V typical)
(2)
25
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TPS548B22
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In addition to serving the frequency select purpose, the FSEL pin can also be used to program internal ramp
compensation (DCAP3) and light-load conduction mode. When DCAP3 mode is selected (see section 8.2.3.9),
internal ramp compensation is used for stabilizing the converter design. The internal ramp compensation is a
function of the switching frequency (fSW) and the duty cycle range (the output voltage-to-input voltage ratio).
Table 7 summarizes the ramp choices using these functions.
Table 7. Switching Frequency Selection
VOUT RANGE
(FIXED VIN = 12 V)
DUTY CYCLE RANGE
(VOUT/VIN) (%)
SWITCHING FREQUENCY
SETTING
RAMP
SELECT
OPTION
TIME
CONSTANT
t (µs)
(fSW) (kHz)
MIN
0.6
0.9
1.5
2.5
0.6
0.9
1.5
2.5
0.6
0.9
1.5
2.5
0.6
0.9
1.5
2.5
MAX
0.9
1.5
2.5
5.5
0.9
1.5
2.5
5.5
0.9
1.5
2.5
5.5
0.9
1.5
2.5
5.5
MIN
5
MAX
R/2
9
7.5
12.5
21
R × 1
R × 2
R × 3
R/2
16.8
32.3
55.6
7
7.5
12.5
425
650
>21
5
7.5
7.5
12.5
21
R × 1
R × 2
R × 3
R/2
13.5
25.9
44.5
5.6
12.5
>21
5
7.5
7.5
12.5
21
R × 1
R × 2
R × 3
R/2
10.4
20
875
12.5
34.4
3.8
>21
5
7.5
7.5
12.5
21
R × 1
R × 2
R × 3
7.1
1050
13.6
23.3
12.5
>21
The FSEL pin programs the light-load selection. TPS548B22 device supports either SKIP mode or FCCM
operations. For optimized light-load efficiency, it is recommended to program the device to operate in SKIP
mode. For better load regulation from no load to full load, it is recommended to program the device to operate in
FCCM mode.
RFSEL(LS) can be determined after determining the switching frequency, ramp and light-load operation. Table 2
lists the full range of choices.
8.2.3.2 Inductor Selection
To calculate the value of the output inductor, use Equation 3. The coefficient KIND represents the amount of
inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple
current. Therefore, choosing a high inductor ripple current impacts the selection of the output capacitor since the
output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general,
maintain a KIND coefficient greater than 0 and 0.4 for balanced performance. Using this target ripple current, the
required inductor size can be calculated as shown in Equation 3:
1 V ´ 18 V -1 V
VOUT
IN(max) ´ ¦SW
V
IN - VOUT
(
18 V ´ 650 kHz ´ 25 A ´ 0.2
)
L1 =
´
) (
=
= 0.29 mH
V
(
IOUT(max) ´ KIND
)
(3)
Selecting a KIND of 0.2, the target inductance L1 = 290 nH. Using the next standard value, the 330 nH is chosen
in this application for its high current rating, low DCR, and small size. The inductor ripple current, RMS current,
and peak current can be calculated using Equation 4, Equation 5 and Equation 6. These values should be used
to select an inductor with approximately the target inductance value, and current ratings that allow normal
operation with some margin.
V
- VOUT
1 V ´ 18 V -1 V
VOUT
IN(max) ´ ¦SW
(
)
18 V ´ 650 kHz ´ 330 nH
IN(max)
IRIPPLE
=
´
=
= 4.4 A
L1
V
(
)
(4)
26
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TPS548B22
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ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
1
12
1
2
)
2
)
IL(rms)
=
I
(
+
´
I
= 25 A
(
OUT
RIPPLE
(5)
(6)
IL(PEAK) = (IOUT ) +
´ (IRIPPLE
) = 27.2 A
8.2.3.3 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
affects three criteria:
•
•
•
Stability
Regulator response to a change in load current or load transient
Output voltage ripple
These three considerations are important when designing regulators that must operate where the electrical
conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these
three criteria.
8.2.3.3.1 Minimum Output Capacitance to Ensure Stability
To prevent sub-harmonic multiple pulsing behavior, TPS548B22 application designs must strictly follow the small
signal stability considerations described in Equation 7.
¥
zR
6ꢀ%&
6/54
/.
#
>
×
×
/54 (≠©Æ )
2
,
/54
where
•
•
•
COUT(min) is the minimum output capacitance needed to meet the stability requirement of the design
tON is the on-time information based on the switching frequency and duty cycle (in this design, 128 ns)
τ is the ramp compensation time constant of the design based on the switching frequency and duty cycle, (in
this design, 25.9 µs, refer to Table 7)
•
•
•
LOUT is the output inductance (in the design, 0.33 µH)
VREF is the user-selected reference voltage level (in this design, 1 V)
VOUT is the output voltage (in this design, 1 V)
(7)
The minimum output capacitance calculated from Equation 7 is 40 µF. The stability is ensured when the amount
of the output capacitance is 40 µF or greater. And when all MLCCs (multi-layer ceramic capacitors) are used,
both DC and AC derating effects must be considered to ensure that the minimum output capacitance
requirement is met with sufficient margin.
8.2.3.3.2 Response to a Load Transient
The output capacitance must supply the load with the required current when current is not immediately provided
by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects
the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.
Use Equation 8 and Equation 9 to estimate the amount of capacitance needed for a given dynamic load step and
release.
NOTE
There are other factors that can impact the amount of output capacitance for a specific
design, such as ripple and stability.
2
6/54 × ¥37
,
/54
× k¿),/!$ ≠°∏ ;o × l
+ ¥/&& ≠©Æ ;p
:
:
6
:
;
). ≠©Æ
#
=
;
:
/54 ≠©Æ _µÆ§•≤
6
;ꢀ6
:
6
). ≠©Æ
2 × ¿6,/!$ ©Æ≥•≤¥ ; × Fl
/54 p × ¥37 ꢀ ¥/&& ≠©Æ ;G × 6
:
/54
:
:
;
). ≠©Æ
(8)
27
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TPS548B22
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www.ti.com.cn
,
× k¿),/!$ ≠°∏ ;o2
:
/54
#
=
;
:
/54 ≠©Æ _Ø∂•≤
2 × ¿6,/!$ ≤•¨•°≥• × 6
:
;
/54
where
•
•
•
•
•
•
•
•
•
•
COUT(min_under) is the minimum output capacitance to meet the undershoot requirement
COUT(min_over)is the minimum output capacitance to meet the overshoot requirement
L is the output inductance value (0.33 µH)
∆ILOAD(max) is the maximum transient step (15 A)
VOUT is the output voltage value (1 V)
tSW is the switching period (1.54 µs)
VIN(min) is the minimum input voltage for the design (10.8 V)
tOFF(min) is the minimum off time of the device (300 ns)
∆VLOAD(insert) is the undershoot requirement (30 mV)
∆VLOAD(release) is the overshoot requirement (30 mV)
(9)
Most of the above parameters can be found in Table 5.
The minimum output capacitance to meet the undershoot requirement is 516 µF. The minimum output
capacitance to meet the overshoot requirement is 1238 µF. This example uses a combination of POSCAP and
MLCC capacitors to meet the overshoot requirement.
•
•
POSCAP bank no. 1: 2 × 470 µF, 2.5 V, 6 mΩ per capacitor
MLCC bank no. 2: 7 × 100 µF, 6.3 V, 2 mΩ per capacitor with DC+AC derating factor of 60%
Recalculating the worst case overshoot using the described capacitor bank design, the overshoot is 29 mV,
which meets the 30-mV overshoot specification requirement.
8.2.3.3.3 Output Voltage Ripple
The output voltage ripple is another important design consideration. Equation 10 calculates the minimum output
capacitance required to meet the output voltage ripple specification. This criterion is the requirement when the
impedance of the output capacitance is dominated by ESR.
IRIPPLE
CCOUT(min)RIPPLE
=
= 82 mF
8 ´ ¦SW ´ VOUT(RIPPLE)
(10)
In this case, the maximum output voltage ripple is 10 mV. For this requirement, the minimum capacitance for
ripple requirement yields 82 µF. Because this capacitance value is significantly lower compared to that of
transient requirement, determine the capacitance bank from Response to a Load Transient. Because the output
capacitor bank consists of both POSCAP and MLCC type capacitors, it is important to consider the ripple effect
at the switching frequency due to effective ESR. Use Equation 11 to determine the maximum ESR of the output
capacitor bank for the switching frequency.
V
IRIPPLE
out ripple
(
-
)
8 ´ ¦SW ´ COUT
ESRMAX
=
= 2.2 mW
IRIPPLE
(11)
Estimate the effective ESR at the switching frequency by obtaining the impedance vs frequency characteristics of
the output capacitors. The parallel impedance of capacitor bank #1 and capacitor bank #2 at the switching
frequency of the design example is estimated to be 1.2 mΩ, which is less than that of the maximum ESR value.
Therefore, the output voltage ripple requirement (10 mV) can be met. For detailed calculation on the effective
ESR please contact the factory to obtain a user-friendly Excel based design tool.
28
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ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
8.2.3.4 Input Capacitor Selection
The TPS548B22 requires a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a value of at
least 1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input decoupling
capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high switching
currents demanded when the high-side MOSFET switches on, while providing minimal input voltage ripple as a
result. This effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be
greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the
maximum input current ripple to the device during full load. The input ripple current can be calculated using
Equation 12.
V
(
- VOUT
)
= 10 Arms
VOUT
IN(min)
ICIN(rms) = IOUT(max)
´
´
V
V
IN(min)
IN(min)
(12)
The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are
shown in Equation 13 and Equation 14. The input ripple is composed of a capacitive portion, VRIPPLE(cap), and a
resistive portion, VRIPPLE(esr)
.
IOUT(max) ´ VOUT
CIN(min)
=
= 21.4 mF
VRIPPLE(cap) ´ V
´ ¦ SW
IN(max)
(13)
VRIPPLE(ESR)
ESRCIN(max)
=
= 3.4 mW
I
æ
ö
RIPPLE
IOUT(max)
+
ç
÷
2
è
ø
(14)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at
least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input
ripple for VRIPPLE(cap), and 0.1-V input ripple for VRIPPLE(esr). Using Equation 13 and Equation 14, the minimum
input capacitance for this design is 21.4 µF, and the maximum ESR is 3.4 mΩ. For this example, four 22-μF, 25-
V ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for
the power stage.
8.2.3.5 Bootstrap Capacitor Selection
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper
operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with
a voltage rating of 25 V or higher.
8.2.3.6 BP Pin
Bypass the BP pin to DRGND with 4.7-µF capacitance. In order for the regulator to function properly, it is
important that these capacitors be localized to the , with low-impedance return paths. See Layout Guidelines
section for more information.
8.2.3.7 R-C Snubber and VIN Pin High-Frequency Bypass
Though it is possible to operate the TPS548B22 within absolute maximum ratings without ringing reduction
techniques, some designs may require external components to further reduce ringing levels. This example uses
two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between
the SW area and GND.
The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the
outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and
discharge once the high-side MOSFET is turned on. For this example twoone 2.2-nF, 25-V, 0603-sized high-
frequency capacitors are used. The placement of these capacitors is critical to its effectiveness. Its ideal
placement is shown in Figure 21.
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Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF
capacitor and a 1-Ω resistor are chosen. In this example a 0805-sized resistor is chosen, which is rated for 0.125
W, nearly twice the estimated power dissipation. See SLUP100 for more information about snubber circuits.
8.2.3.8 Optimize Reference Voltage (VSEL)
Optimize the reference voltage by choosing a value for RVSEL. The TPS548B22 device is designed with a wide
range of precision reference voltage support from 0.6 V to 1.2 V with an available step change of 50 mV.
Program these reference voltages using the VSEL pin strap configurations. See Table 3 for internal reference
voltage selections. In addition to providing initial boot voltage value, use the VSEL pin to program hiccup and
latch-off mode.
There are two ways to program the output voltage set point. If the output voltage set point is one of the 16
available reference and boot voltage options, no feedback resistors are required for output voltage programming.
In the case where feedback resistors are not needed, connect the RSP pin to the positive sensing point of the
load. Always connect the RSN pin to the load return sensing point.
In this design example, since the output voltage set point is 1 V, selecting RVSEL(LS) of either 75 kΩ (latch off) or
68.1 kΩ (hiccup). If the output voltage set point is NOT one of the 16 available reference or boot voltage options,
feedback resistors are required for output voltage programming. Connect the RSP pin to the mid-point of the
resistor divider. Always connect the RSN pin to the load return sensing point as shown in Figure 19 and
Figure 20.
The general guideline to select boot and internal reference voltage is to select the reference voltage closest to
the output voltage set point. In addition, because the RSP and RSN pins are extremely high-impedance input
terminals of the true differential remote sense amplifier, use a feedback resistor divider with values much less
than 100 kΩ.
8.2.3.9 MODE Pin Selection
MODE pin strap configuration is used to program control topology and internal soft-start timing selections.
TPS548B22 supports both DCAP3 and DCAP operation. For general POL applications, it is strongly
recommended to configure the control topology to be DCAP3 due to its simple to use and no external
compensation features. In the rare instance where DCAP is needed, an RCC network across the output inductor
is needed to generate sufficient ripple voltage on the RSP pin. In this design example, RMODE(LS) of 22.1 kΩ is
selected for DCAP3 and soft start time of 1 ms.
8.2.3.10 Overcurrent Limit Design.
The TPS548B22 device uses the ILIM pin to set the OCP level. Connect the ILIM pin to GND through the voltage
setting resistor, RILIM. In order to provide both good accuracy and cost effective solution, this device supports
temperature compensated MOSFET on-resistance (RDS(on)) sensing. Also, this device performs both positive and
negative inductor current limiting with the same magnitudes. Positive current limit is normally used to protect the
inductor from saturation therefore causing damage to the high-side and low-side FETs. Negative current limit is
used to protect the low-side FET during OVP discharge.
The inductor current is monitored by the voltage between PGND pin and SW pin during the OFF time. The ILIM
pin has 1200 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance. The
PGND pin is used as the positive current sensing node.
TPS548B22 has cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent ILIM level. The voltage on the ILIM pin (VILIM) sets the valley level of the inductor current. The range
of value of the RILIM resistor is between 9.53 kΩ and 105 kΩ. The range of valley OCL is between 5 A and 50 A
(typical). If the RILIM resistance is outside of the recommended range, OCL accuracy and function cannot be
assured. (see Table 8)
30
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Table 8. OCP Valley Settings
1% RILIM
OVERCURRENT
PROTECTION VALLEY (A)
(kΩ)
82.1
71.5
61.9
51.1
40.2
30.1
20.5
40
35
30
25
20
15
10
Use Equation 15 to relate the valley OCL to the RILIM resistance.
RILIM = 2.0664 x OCLVALLEY – 0.6036
where
•
•
RILIM is in kΩ
OCLVALLEY is in A
(15)
In this design example, the desired valley OCL is 30 A, the calculated RILIM is 61.9 kΩ. Use Equation 16 to
calculate the DC OCL to be 32.1 A.
/#,$# = /#,6!,,%9 + 0.5 × )2)ꢀꢀ,%
where
•
•
RILIM is in kΩ
OCLDC is in A
(16)
In an overcurrent condition, the current to the load exceeds the inductor current and the output voltage falls.
When the output voltage crosses the under-voltage fault threshold for at least 1msec, the behavior of the device
depends on the VSEL pin strap setting. If hiccup mode is selected, the device will restart after 16-ms delay (1-ms
soft-start option). If the overcurrent condition persists, the OC hiccup behavior repeats. During latch-off mode
operation the device shuts down until the EN pin is toggled or VDD pin is power cycled.
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8.2.4 Application Curves
1.01
1.005
1
0.995
0.99
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
0
5
10
15
20
25
Output Current (A)
D009
SKIP Mode
fSW = 650 kHz
0.5 A DC with 15-A step at 40A/µs
VDD = VIN = 5 V
VOUT = 1 V
VDD = VIN
fSW = 650 kHz
SKIP Mode
VOUT = 1 V
Figure 23. Transient Response Peak-to-Peak
Figure 22. Output Voltage Regulation vs Output Current
SKIP Mode
fSW = 650 kHz
0.5 A DC with 15-A step at 40A/µs
FCCM Mode
fSW = 650 kHz
5 A DC with 15-A step at 40A/µs
VDD = VIN = 12 V
VOUT = 1 V
VDD = VIN = 5 V
VOUT = 1 V
Figure 24. Transient Response Peak-to-Peak
Figure 25. Transient Response Peak-to-Peak
FCCM Mode
VDD = VIN = 12 V
VOUT = 1 V
fSW = 650 kHz
5 A DC with 15-A step at 40A/µs
Figure 26. Transient Response Peak-to-Peak
32
Copyright © 2017, Texas Instruments Incorporated
TPS548B22
www.ti.com.cn
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
9 Power Supply Recommendations
This device is designed to operate from an input voltage supply between 1.5 V and 18 V. Ensure the supply is
well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance,
as is the quality of the PCB layout and grounding scheme. See the recommendations in the Layout section.
10 Layout
10.1 Layout Guidelines
Consider these layout guidelines before starting a layout work using TPS548B22.
•
•
•
•
It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14,
15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or
plane.
Include as many thermal vias as possible to support a 25-A thermal operation. For example, a total of 35
thermal vias are used (outer diameter of 20 mil) in the TPS548B22EVM-847 available for purchase at ti.com.
(SLUUBE4)
Place the power components (including input/output capacitors, output inductor and TPS548B22 device) on
one side of the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground,
in order to shield and isolate the small signal traces from noisy power lines.
Place the VIN pin decoupling capacitors as close as possible to the PVIN and PGND pins to minimize the
input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF)
as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps surpress the switch
node ringing.
•
•
Place VDD and BP decoupling capacitors as close as possible to the device pins. Do not use PVIN plane
connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace
connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.
Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output
inductor) are as short and wide as possible. In the TPS548B22EVM-847 design, the SW trace width is 200
mil. Use a separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine
these connections.
•
•
Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and
FSEL) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise
coupling. In addition, place MODE, VSEL and FSEL programming resistors near the device pins.
The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high
impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion.
Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit
uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load
sense point) for accurate output voltage result.
•
Pins 6, 7, and 26 are not connected in the 25-A TPS548B22, while pins 6 and 7 connect to SW and pin 26
connects to PVIN in the 40-A TPS548D22.
Copyright © 2017, Texas Instruments Incorporated
33
TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
www.ti.com.cn
10.2 Layout Example
Figure 27. EVM Top View
Figure 28. EVM Top Layer
Figure 29. EVM Inner Layer 1
Figure 30. EVM Inner Layer 2
34
Copyright © 2017, Texas Instruments Incorporated
TPS548B22
www.ti.com.cn
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
Layout Example (continued)
Figure 31. EVM Inner Layer 3
Figure 32. EVM Inner Layer 4
Figure 33. EVM Bottom Layer
Figure 34. EVM Bottom Symbols
Copyright © 2017, Texas Instruments Incorporated
35
TPS548B22
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
www.ti.com.cn
Layout Example (continued)
10.2.1 Mounting and Thermal Profile Recommendation
Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the
reflow process can affect electrical performance. Figure 35 shows the recommended reflow oven thermal profile.
Proper post-assembly cleaning is also critical to device performance. See TI Application Report QFN/SON PCB
Attachment for more information.
tP
TP
TL
TS(max)
TS(min)
tL
rRAMP(up)
rRAMP(down)
tS
t25P
Time (s)
25
Figure 35. Recommended Reflow Oven Thermal Profile
Table 9. Recommended Thermal Profile Parameters
PARAMETER
MIN
TYP
MAX
UNIT
RAMP UP AND RAMP DOWN
rRAMP(up)
Average ramp-up rate, TS(max) to TP
Average ramp-down rate, TP to TS(max)
3
6
°C/s
°C/s
rRAMP(down)
PRE-HEAT
TS
Pre-heat temperature
150
60
200
180
°C
s
tS
Pre-heat time, TS(min) to TS(max)
REFLOW
TL
TP
tL
Liquidus temperature
217
°C
°C
s
Peak temperature
260
150
40
Time maintained above liquidus temperature, TL
Time maintained within 5 °C of peak temperature, TP
Total time from 25 °C to peak temperature, TP
60
20
tP
s
t25P
480
s
36
版权 © 2017, Texas Instruments Incorporated
TPS548B22
www.ti.com.cn
ZHCSGE7A –JANUARY 2017–REVISED JULY 2017
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
TI 用户指南 TPS548B22EVM-847、25A 单相同步降压转换器
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
D-CAP3, NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
版权 © 2017, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
TPS548B22RVFR
TPS548B22RVFT
ACTIVE
LQFN-CLIP
LQFN-CLIP
RVF
40
40
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
548B22A1
548B22A1
ACTIVE
RVF
RoHS-Exempt
& Green
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS548B22RVFR
TPS548B22RVFT
LQFN-
CLIP
RVF
RVF
40
40
2500
250
330.0
16.4
5.3
7.3
1.8
8.0
16.0
Q1
LQFN-
CLIP
180.0
16.4
5.3
7.3
1.8
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS548B22RVFR
TPS548B22RVFT
LQFN-CLIP
LQFN-CLIP
RVF
RVF
40
40
2500
250
367.0
213.0
367.0
191.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RVF0040A
LQFN-CLIP - 1.52 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
7.1
6.9
C
1.52
1.32
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.3 0.1
EXPOSED
THERMAL PAD
36X 0.5
13
20
12
21
41
SYMM
2X
5.3 0.1
5.5
32
1
0.3
40X
0.2
40
33
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.05
0.5
0.3
40X
4222989/B 10/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220.
www.ti.com
EXAMPLE BOARD LAYOUT
RVF0040A
LQFN-CLIP - 1.52 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.3)
6X (1.4)
40
33
40X (0.6)
1
32
40X (0.25)
2X
(1.12)
36X (0.5)
6X
(1.28)
(6.8)
(5.3)
41
SYMM
(R0.05) TYP
(
0.2) TYP
VIA
12
21
13
20
SYMM
(4.8)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222989/B 10/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RVF0040A
LQFN-CLIP - 1.52 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.815) TYP
40
33
40X (0.6)
1
41
32
40X (0.25)
(1.28)
TYP
36X (0.5)
(0.64)
TYP
SYMM
(6.8)
(R0.05) TYP
8X
(1.08)
12
21
METAL
TYP
20
13
8X (1.43)
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
71% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222989/B 10/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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