TPS54910PWPRG4 [TI]
输入电压为 3V 至 4V 的 9A 同步降压转换器 | PWP | 28 | -40 to 85;型号: | TPS54910PWPRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 输入电压为 3V 至 4V 的 9A 同步降压转换器 | PWP | 28 | -40 to 85 开关 控制器 开关式稳压器 开关式控制器 光电二极管 电源电路 转换器 开关式稳压器或控制器 |
文件: | 总15页 (文件大小:198K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Typical Size
6,4 mm X 9,7 mm
www.ti.com
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
3-V TO 4-V INPUT, 9-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT )
FEATURES
DESCRIPTION
D
15-mΩ MOSFET Switches for High Efficiency
at 9-A Continuous Output
0.9-V to 2.5-V Adjustable Output Voltage
Externally Compensated With 1% Accuracy
Fast Transient Response
Wide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
As a member of the SWIFT family of dc/dc regulators,
the TPS54910 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush currents;
and a power good output useful for processor/logic
reset, fault signaling, and supply sequencing.
D
D
D
D
D
D
APPLICATIONS
The TPS54910 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
D
D
Low-Voltage, High-Density Systems With
Power Distributed at 3.3 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
D
D
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
SIMPLIFIED SCHEMATIC
EFFICIENCY AT 700 kHz
SIMPLIFIED SCHEMATIC
100
95
VIN
PH
Input
Output
90
85
80
75
70
65
60
55
50
TPS54910
BOOT
PGND
VBIAS
COMP
VSENSE
AGND
V
V
= 3.3 V,
I
Compensation
Network
= 2.5 V
O
0
1
2
3
4
5
6
7
8
9
10 11 12
I
– Output Current – A
O
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of TexasInstruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
www.ti.com
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring
storageor handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
(1)
–40°C to 85°C
0.9 V to 2.5 V
Plastic HTSSOP (PWP)
TPS54910PWP
(1)
ThePWPpackageisalsoavailabletapedandreeled. AddanRsuffix to the device type(i.e.,TPS54910PWPR).Seetheapplicationsectionof
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
overoperating free-air temperature range unless otherwise noted
(1)
TPS54910
–0.3 to 7
–0.3 to 6
–0.3 to 4
–0.3 to 4.5
–0.3 to 10
–0.3 to 7
–0.6 to 6
UNIT
SS/ENA, SYNC
RT
VSENSE
Input voltage range, V
V
I
VIN
BOOT
VBIAS, COMP, PWRGD
Output voltage range, V
V
O
PH
PH
Internally Limited
Source current, I
O
COMP, VBIAS
PH
6
16
mA
A
COMP
6
Sink current, I
S
mA
SS/ENA, PWRGD
AGND to PGND
10
Voltagedifferential
Operating virtual junction temperature range, T
±0.3
V
–40 to 125
–65 to 150
300
°C
°C
°C
J
Storagetemperature,T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Inputvoltage, V
3
4
V
I
Operatingjunctiontemperature, T
–40
125
°C
J
DISSIPATION RATINGS(1)(2)
THERMALIMPEDANCE
JUNCTION-TO-AMBIENT
T
= 25°C
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING POWER RATING POWER RATING
(3)
28 Pin PWP with solder
14.4°C/W
27.9°C/W
6.94 W
3.81 W
1.97 W
2.77 W
1.43 W
28 Pin PWP without solder
3.58 W
(1)
(2)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
Maximum power dissipation may be limited by over current protection.
(3)
2
www.ti.com
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
ELECTRICAL CHARACTERISTICS
T = –40°C to 125°C, V = 3 V to 4 V (unless otherwise noted)
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
3.0
4.0
V
f
= 350 kHz, SYNC ≤ 0.8 V, RT open,
s
9.8
17.0
PH pin open
f
= 550 kHz, SYNC ≥ 2.5 V, RT open,
I
Quiescentcurrent
mA
s
(Q)
14.0
1
23.0
1.4
PH pin open
Shutdown, SS/ENA = 0 V
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
2.95
2.80
0.16
2.5
3.0
V
V
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.70
0.14
V
(1)
Rising and falling edge deglitch, UVLO
µs
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I
= 0
2.70
2.80
2.90
100
V
(VBIAS)
(2)
µA
CUMULATIVE REFERENCE
V
ref
Accuracy
0.882 0.891
0.900
V
REGULATION
I
L
I
L
I
L
I
L
= 4.5 A, f = 350 kHz,
T
T
= 85°C
= 85°C
0.07
0.07
0.03
0.03
s
J
J
(1)(3)
Lineregulation
%/V
%/A
= 4.5 A, f = 550 kHz,
s
= 0 A to 9 A, f = 350 kHz,
T
T
= 85°C
= 85°C
s
J
J
(1)(3)
Loadregulation
= 0 A to 9 A, f = 550 kHz,
s
OSCILLATOR
Internallyset—freerunningfrequency
SYNC ≤ 0.8 V, RT open
SYNC ≥ 2.5 V, RT open
280
440
252
460
663
2.5
350
550
280
500
700
420
660
308
540
762
kHz
kHz
RT = 180 kΩ (1% resistor to AGND)
RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)
Externally set—free running frequency range
High level threshold, SYNC
V
V
Low level threshold, SYNC
0.8
Pulseduration, externalsynchronization,
SYNC
50
ns
(1)
(1)
Frequency range, SYNC
(1)
330
700
kHz
V
Ramp valley
Rampamplitude(peak-to-peak)
(1)
0.75
1
(1)
V
Minimumcontrollableontime
(1)
200
ns
Maximum duty cycle
90%
(1)
(2)
(3)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10
3
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
T = –40°C to 125°C, V = 3 V to 4 V (unless otherwise noted)
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
(1)
1 kΩ COMP to AGND
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
90
3
110
5
dB
(1)
Parallel 10 kΩ, 160 pF COMP to AGND
MHz
Error amplifier common mode input voltage
range
(1)
Powered by internal LDO
0
VBIAS
250
V
Input bias current, VSENSE
VSENSE = V
ref
60
nA
Output voltage slew rate (symmetric), COMP
1.0
1.4
V/µs
PWM COMPARATOR
PWMcomparatorpropagationdelaytime,
PWM comparator input to PH pin
(excludingdeadtime)
(1)
10-mVoverdrive
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA
0.82
1.2
0.03
2.5
3.35
5
1.4
V
V
(1)
(1)
Falling edge deglitch, SS/ENA
µs
ms
µA
mA
Internal slow-start time
2.6
3
4.1
8
Charge current, SS/ENA
Discharge current, SS/ENA
SS/ENA = 0 V
SS/ENA = 1.3 V, V = 1.5 V
I
1.5
2.3
4.0
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
VSENSEfalling
90
3
%V
%V
ref
(1)
(1)
ref
Power good falling edge deglitch
35
µs
Output saturation voltage, PWRGD
Leakage current, PWRGD
I
= 2.5 mA
0.18
0.3
1
V
(sink)
V = 5.5 V
µA
I
CURRENT LIMIT
Currentlimit
(1)
V = 3.3 V , Output shorted
11
15
100
200
A
I
Current limit leading edge blanking time
Current limit total response time
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip point
(1)
(1)
135
150
10
165
°C
°C
Thermalshutdownhysteresis
OUTPUT POWER MOSFETS
(4)
V = 3 V
15
14
30
28
I
r
Power MOSFET switches
mΩ
DS(on)
(4)
V = 3.6 V
I
(1)
(2)
(3)
(4)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10
MatchedMOSFETs low-side r production tested, high-side r
production tested.
DS(on) DS(on)
4
www.ti.com
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
PWP PACKAGE
(TOP VIEW)
1
28
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
2
27
26
25
24
23
22
21
20
19
18
17
16
15
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
3
4
5
6
7
PH
PH
PH
PH
PH
PH
PH
PH
THERMAL
PAD
8
VIN
VIN
9
10
11
12
13
14
PGND
PGND
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
AGND
NO.
1
Analogground. Returnforcompensationnetwork/outputdivider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT
5
3
Bootstrapoutput. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
PGND
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
15–19 Powerground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
totheinputandoutputsupplyreturns,andnegativeterminalsoftheinputandoutputcapacitors.Asinglepointconnection
to AGND is recommended.
PH
6–14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Powergoodopendrainoutput. HighwhenVSENSE≥ 90% V , otherwise PWRGD is low. Note that output is low when
SS/ENA is low or the internal shutdown signal is active.
ref
RT
28
26
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f .
s
SS/ENA
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitorinput to externally set the start-up time.
SYNC
VBIAS
27
25
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
betweentwo internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connectedto the RT pin.
Internalbias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
20–24 InputsupplyforthepowerMOSFETswitchesandinternalbiasregulator. Bypass VIN pins to PGND pins close todevice
packagewith a high-quality, low-ESR 10-µF ceramic capacitor.
VIN
VSENSE
2
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
5
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
www.ti.com
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VBIAS
VIN
Enable
Comparator
SS/ENA
REG
Falling
Edge
SHUTDOWN
VIN
ILIM
Comparator
1.2 V
3 – 6 V
Deglitch
Thermal
Shutdown
150°C
Hysteresis: 0.03 V
Leading
Edge
2.5 µs
Blanking
VIN UVLO
Comparator
Falling
100 ns
and
Rising
Edge
VIN
BOOT
2.95 V
Deglitch
Hysteresis: 0.16 V
15 mΩ
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
V
O
PH
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
+
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
–
Error
Amplifier
PWM
Comparator
Reference
VIN
VREF = 0.891 V
15 mΩ
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
0.90 V
Falling
Edge
Deglitch
ref
TPS54910
Hysteresis: 0.03 Vref
SHUTDOWN
35 µs
SYNC
VSENSE
COMP
RT
RELATED DC/DC PRODUCTS
D
D
D
TPS40000—dc/dc controller
TPS56300—dc/dc controller
PT6600 series—9 A plugin modules
6
www.ti.com
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
DRAIN-SOURCE
DRAIN-SOURCE
INTERNALLY SET
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
ON-STATE RESISTANCE
OSCILLATOR FREQUENCY
vs
vs
JUNCTION TEMPERATURE
750
JUNCTION TEMPERATURE
25
20
25
VIN = 3.0 V
VIN = 3.6 V
I
= 9 A
O
I
= 9 A
O
20
15
650
SYNC ≥ 2.5 V
15
10
550
10
5
450
SYNC ≤ 0.8 V
5
0
350
250
0
–40
–40
0
25
85
125
0
25
85
125
–40
0
25
85
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 1
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
Figure 2
Figure 3
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
vs
LOAD CURRENT
JUNCTION TEMPERATURE
8
7
6
5
4
3
2
1
0
0.895
0.893
0.891
0.889
800
700
600
V
= 3.3 V
= 125°C
I
T
J
RT = 68 kΩ
RT = 100 kΩ
RT = 180 kΩ
500
400
300
200
0.887
0.885
0
2
4
6
8
10 12 14 16
–40
0
25
85
125
–40
0
25
85
125
I
– Load Current – A
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
L
Figure 6
Figure 4
Figure 5
OUTPUT VOLTAGE REGULATION
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
ERROR AMPLIFIER
OPEN LOOP RESPONSE
vs
INPUT VOLTAGE
0.895
0
140
3.80
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
L
A
–20
120
100
80
3.65
3.50
–40
–60
–80
0.893
0.891
0.889
Phase
Gain
3.35
–100
–120
–140
–160
–180
–200
60
3.20
3.05
40
20
0.887
0.885
2.90
2.75
0
–20
1
10 100 1 k 10 k 100 k 1 M 10 M
3
3.1
3.2
3.3
3.4
3.5
3.6
–40
0
25
85
125
V – Input Voltage – V
I
f – Frequency – Hz
T
J
– Junction Temperature – °C
Figure 7
Figure 8
Figure 9
7
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
www.ti.com
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical
TPS54910 application. The TPS54910 (U1) can provide
up to 9 A of output current at a nominal output voltage of
1.8 V. For proper thermal performance, the exposed
thermal PowerPAD underneath the integrated circuit,
TPS54910, package must be soldered to the
printed-circuit board.
V
I
C10
C12
U1
10 µF
10 µF
TPS54910PWP
R6
28
71.5 kΩ
27
24
23
RT
VIN
VIN
VIN
VIN
VIN
PH
PH
PH
PH
PH
PH
PH
PH
22
21
R7
10 kΩ
SYNC
SS/ENA
26
25
4
20
14
13
C6
0.047 µF
C3
VBIAS
PWRGD
COMP
12
1 µF
C4
11
L1
10
9
0.65 µH
C1
R2
R3
10 kΩ
3
V
O
8
7
6
C8
22 µF
C7
22 µF
C5
22 µF
301 Ω
1000 pF
R1
3300 pF
C2
PH
BOOT
PGND
PGND
C9
150 pF
2
1
5
VSENSE
10 Ω
19
18
17
16
15
0.047 µF
R7
2.4 Ω
R4
9.76 kΩ
PGND
PGND
PGND
AGND
C11
3300 pF
POWERPAD
Analog and Power Grounds Are Tied at the Pad Under the Package of IC
Figure 10. Application Circuit
COMPONENT SELECTION
FEEDBACK CIRCUIT
The values for the components used in this design
example were selected for best load transient response
and small PCB area. Additional design information is
available at www.ti.com.
The values for these components are selected to provide
fast transient response times.
The resistor divider network of R1 and R4 sets the output
voltage for the circuit at 1.8 V. R1 along with R2, R3, C1,
C2, and C4 forms the loop compensation network for the
circuit. For this design, a Type-3 topology is used.
INPUT FILTER
The input voltage is a nominal 3.3 VDC. The input filter
(C10) is a 10-µF ceramic capacitor (Taiyo Yuden). C12 is
also a 10-µF ceramic capacitor (Taiyo Yuden) that
provides high-frequency decoupling of the TPS54910
from the input supply. C12 must be located as close as
possibletothedevice. RipplecurrentiscarriedinbothC10
and C12, and the return path to PGND must avoid the
currentcirculatingintheoutputcapacitorsC5, C7, andC8.
OPERATING FREQUENCY
Intheapplicationcircuit,RTisgroundedthrougha71.5-kΩ
resistor to select the operating frequency of 700 kHz. To
set a differentfrequency, place a 68-kΩ to 180-kΩ resistor
between RT (pin 28) and analog ground or leave RT
floatingtoselectthedefaultof350kHz.Theresistancecan
be approximated using the following equation:
500 kHz
Switching Frequency
R +
100 [kW]
(1)
8
www.ti.com
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
4-layer board. Documentation for the TPS54910
evaluationmodule can be found on the TexasInstruments
web site under the TPS54910 product folder.
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor and
3 x 22-µF capacitor. The inductor is a low dc-resistance
(.017 Ω) type, Pulse Engineering PA0277. The capacitors
used are 22-µF, 6.3-V ceramic types with X5R dielectric.
The feedback loop is compensated so that the unity gain
frequency is approximately 75 kHz.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide an adequate heat dissipating area. A
3-inchby3-inchplaneof1ouncecopperisrecommended,
thoughnotmandatory,dependingonambienttemperature
andairflow. Most applicationshavelargerareasofinternal
ground plane available, and the PowerPAD must be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available must be used when 6 A or greater
operationis desired. Connection from theexposedareaof
the PowerPAD to the analog ground plane layer must be
made using 0.013-inch diameter vias to avoid solder
wicking through the vias.
GROUNDING AND POWERPAD LAYOUT
The TPS54910 has two internal grounds (analog and
power).Inside the TPS54910, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directlyto AGND. Noise injected between the two grounds
can degrade the performance of the TPS54910,
particularly at higher output currents. However, ground
noiseonananaloggroundplanecanalsocauseproblems
with some of the control and bias signals. For these
reasons, separate analog and power ground planes are
recommended. These two planes must tie together
directlyattheICtoreducenoisebetweenthetwogrounds.
The only components that must tie directly to the power
groundplane are the input capacitor, the output capacitor,
theinputvoltagedecouplingcapacitor, andthePGNDpins
of the TPS54910. The layout of the TPS54910 evaluation
module is representative of a recommended layout for a
Eight vias must be in the PowerPAD area with four
additionalviaslocatedunderthedevicepackage.Thesize
of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional
vias beyond the twelve recommended that enhance
thermalperformance must be included in areas not under
the device package.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Ø0.0130
8 PL
4 PL Ø0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3820 0.3478
0.2090
0.0256
0.0500
0.0500
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
0.1700
Larger Area
0.1340
0.0630
Minimum Recommended Top
Side Analog Ground Area
0.0400
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
9
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
www.ti.com
PERFORMANCE GRAPHS
EFFICIENCY
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
LINE REGULATION
vs
INPUT VOLTAGE
100
1.003
1.002
1.001
f
= 700 kHz,
s
95
90
85
80
75
70
65
1.0008
T
A
= 25°C,
V
= 3.3 V,
I
1.0006
1.0004
V
= 1.8 V
O
I
= 9 A
O
O
I
= 0 A
1.001
0
O
1.0002
1
0.9998
0.9996
0.999
0.998
0.997
I
= 4.5 A
f
= 700 kHz,
s
f
V
= 700 kHz,
= 3.3 V,
60
55
50
s
I
0.9994
0.9992
0.999
T
A
= 25°C,
V
= 3.3 V,
I
V
= 2.5 V
O
V
= 1.8 V
O
0
1
2
3
4
5
6
7
8
9
10 11 12
0
2
4
6
8
10
3
3.2
3.4
3.6
3.8
4
I
– Output Current – A
I
– Output Current – A
O
O
V – Input Voltage – V
I
Figure 12
Figure 13
Figure 14
AMBIENTTEMPERATURE
vs
(1)
OUTPUT RIPPLE VOLTAGE
TRANSIENT RESPONSE
LOAD CURRENT
125
115
105
95
V
V
= 3.3 V,
= 1.8 V
f
I
V
= 700 kHz,
= 9 A,
= 3.3 V,
I
O
s
O
I
f
T
V
V
= 700 kHz,
= 125°C,
= 3.3 V,
s
J
I
V
= 1.8 V
O
= 1.8 V
O
85
75
65
55
45
2 A to 6.5 A
35
25
t – Time – 5 µs/div
t – Time – 1 µs/div
0
2
4
6
8
10 12 14 16
I
– Output Current – A
O
Figure 15
Figure 16
Figure 17
SLOW-START TIMING
V
V
= 3.3 V,
I
= 1.8 V
O
0.047 µf
slow-start capacitor
t –Time – 5 ms/div
Figure 18
(1)
Safeoperating area is applicable to the test board conditions in the Dissipation Ratings
10
www.ti.com
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
DETAILED DESCRIPTION
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommendedbecause their values are more stable over
temperature. The bypass capacitor must be placed close
to the VBIAS pin and returned to AGND.
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54910 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
thresholdvoltageof2.95V.OncetheUVLOstartthreshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs
risingandfallingedgedeglitchcircuitreducethelikelihood
of shutting the device down due to noise on VIN.
Externalloading on VBIAS is allowed, with the cautionthat
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
SLOW-START/ENABLE (SS/ENA)
VOLTAGE REFERENCE
Theslow-start/enablepinprovidestwofunctions.First,the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceedsthe enablethreshold, devicestart-upbegins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The voltage reference system produces a precise V
ref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54910, since it cancels
offset errors in the scale and error amplifier circuits.
OSCILLATOR AND PWM RAMP
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is
requiredfortheapplication,theoscillatorfrequencycanbe
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin to ground and floating the
SYNC pin. The switching frequency is approximated by
the following equation, where R is the resistance from RT
to AGND:
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is
proportional to the slow-start capacitor value and lasts
until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
(4)
100 kW
Switching Frequency +
500 [kHz]
R
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose a RT resistor that sets
the free running frequency to 80% of the synchronization
signal. The following table summarizes the frequency
selection configurations:
(2)
1.2 V
t + C
d
(SS)
5 mA
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
SWITCHING
FREQUENCY
SYNC PIN
RT PIN
350kHz, internally set Float or AGND
Float
Float
550kHz, internally set ≥ 2.5 V
(3)
0.7 V
t
+ C
Externally set 280
Float
(SS)
(SS)
R = 68 kΩ to 180 kΩ
5 mA
kHz to 700 kHz
Externally
R = RT value for 80%
of external synchro-
nizationfrequency
Synchronization
synchronized
signal
Theactualslow-starttimeislikelytobelessthantheabove
approximationdue to the brief ramp-up attheinternalrate.
frequency
11
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
www.ti.com
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
doesnotturnonuntilthevoltageatthegateofthelow-side
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54910 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type-2 or Type-3
compensation can be employed using external
compensation components.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWMlatch,
and portions of the adaptive dead-time and control-logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimumduration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reachingthecurrentlimitthreshold. A100-nsleadingedge
blanking circuit prevents current limit false tripping.
Currentlimitdetectionoccursonlywhencurrentflowsfrom
VIN to PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
THERMAL SHUTDOWN
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latchisneverreset, andthehigh-sideFETremainsonuntil
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operatesatitsmaximumdutycycleuntiltheoutputvoltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54910 is capable of sinking current continuously
until the output reaches the regulation set-point.
Thedeviceusesthethermalshutdowntoturnoffthepower
MOSFETs and disable the controller if the junction
temperatureexceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
startingupbycontrolofthesoft-startcircuit,heatingupdue
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
POWER-GOOD (PWRGD)
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-sideFETturnsontodecreasetheenergyintheoutput
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
lessthantheUVLOthresholdor SS/ENA is low. WhenVIN
≥ UVLO threshold, SS/ENA ≥ enable threshold, and
VSENSE > 90% of V , the open drain output of the
PWRGD pin is high. A hysteresis voltage equal to 3% of
ref
DEAD-TIME CONTROL AND MOSFET
DRIVERS
V
ref
and a 35 µs falling edge deglitch circuit prevent
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
tripping of the power good comparator due to high
frequency noise.
12
www.ti.com
TPS54910
SLVS421B – MARCH 2002 – REVISED AUGUST 2002
MECHANICAL DATA
PWP (R-PDSO-G**)
POWERPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
M
0,65
20
0,10
11
ThermalPad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
SeatingPlane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/F10/98
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of TexasInstruments.
13
THERMAL PAD MECHANICAL DATA
PWP (R-PDSO-G28)
PowerPAD™ PLASTIC SMALL-OUTLINE
www.ti.com
IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Copyright 2002, Texas Instruments Incorporated
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