TPS562242 [TI]
3-V to 17-V input voltage, 2-A, 1.4-MHz synchronous buck converter in SOT563;
| 型号： | TPS562242 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-V to 17-V input voltage, 2-A, 1.4-MHz synchronous buck converter in SOT563 |
| 文件： | 总23页 (文件大小：1365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS562242
ZHCSP82A –DECEMBER 2022 –REVISED MAY 2023
TPS562242 采用SOT-563 封装的3V 至17V 输入、2A 同步降压转换器
1 特性
2 应用
• 专用于多种应用
• 电器、录像机
• WLAN、Wi-Fi 接入点、调制解调器（电缆、DSL、
GFAST）、小型企业路由器
• 电视、STB 和DVR
– 3V 至17V 输入电压范围
– 0.8V 至10V 输出电压范围
– 0.8V 基准电压
– 25°C 时，基准精度为±1%
– 在-40°C 至125°C 温度范围内，基准精度为
±1.5%
– 集成55.0mΩ和24.3mΩMOSFET
– 100 µA 低静态电流
3 说明
TPS562242 是一款简单、易用、高效率、高功率密度
的同步降压转换器，输入电压范围为 3V 至 17V，在
0.8V 至 10V 的输出电压范围内，支持高达 2A 的持续
输出电流。
– 1.4MHz 开关频率
– 以最大94% 的高占空比运行
– 精密EN 阈值电压
TPS562242 采用 D-CAP3 控制模式提供快速瞬态响应
并支持低 ESR 输出电容器，无需外部补偿。该器件支
持高达94% 的占空比运行。
– 1.6 ms 固定软启动时间（典型值）
• 解决方案尺寸小巧且易于使用
– 轻负载下采用Eco-mode
– 与TPS562202 引脚对引脚兼容
– D-CAP3™ 控制模式
TPS562242 在 Eco-mode 下运行，可在轻负载时保持
高效率。该器件集成了全面的断续模式 OVP、OCP、
UVLO、OTP 和UVP 保护。
– 支持带预偏置输出的启动
– 非锁存OV、OT 和UVLO 保护
– UV 保护的断续模式
该器件采用1.6mm x 1.6mm SOT-563 封装。额定结温
范围为-40°C 至125°C。
封装信息
封装(1)
– 逐周期OC 保护
封装尺寸（标称值）
器件型号
– 1.6mm × 1.6mm SOT-563 封装
• 使用TPS562242 并借助WEBENCH® Power
Designer 创建定制设计方案
DRL（SOT-563，
6）
TPS562242
1.60mm × 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100%
90%
80%
70%
60%
50%
40%
1
5
4
2
6
VIN
VIN
EN
BST
SW
FB
CBST
L
VOUT
EN
CIN
RFBT
COUT
3
GND
30%
20%
10%
0
Vout = 1.05V
Vout = 3.3V
Vout = 5V
RFBB
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
简化版应用
TPS562242 在VIN = 12V 时的效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEQ4
TPS562242
ZHCSP82A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
8.3 Power Supply Recommendations.............................17
8.4 Layout....................................................................... 17
9 Device and Documentation Support............................18
9.1 Device Support......................................................... 18
9.2 接收文档更新通知..................................................... 18
9.3 支持资源....................................................................18
9.4 Trademarks...............................................................18
9.5 静电放电警告............................................................ 18
9.6 术语表....................................................................... 18
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description...................................................10
Information.................................................................... 18
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2022) to Revision A (May 2023)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
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English Data Sheet: SLUSEQ4
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ZHCSP82A –DECEMBER 2022 –REVISED MAY 2023
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5 Pin Configuration and Functions
1
2
3
VIN
SW
6
5
4
FB
EN
GND
BST
图5-1. 6-Pin SOT563 DRL Package (Top View)
表5-1. Pin Functions
Pin
Type(1)
Description
Name
VIN
SW
NO.
1
P
P
G
P
A
A
Input voltage supply pin. Connect the input decoupling capacitors between VIN and GND.
Switch node pin. Connect the output inductor to this pin.
2
GND
BST
EN
3
GND pin for the controller circuit and the internal circuitry.
4
Connect a 100-nF ceramic capacitor from this pin to the SW pin or leave it floating.
Enable control input. Driving EN high or leaving this pin floating enables the converter.
Converter feedback input. Connect to output voltage with a feedback resistor divider.
5
FB
6
(1) A = Analog, P = Power, G = Ground
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English Data Sheet: SLUSEQ4
TPS562242
ZHCSP82A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–2
MAX
18
UNIT
V
VIN
FB, EN
GND
6
V
0.3
18
V
Pin voltage(2)
SW
V
SW (transient < 20 ns)
BST
20
V
–5.5
–2
18
V
BST (transient < 20 ns)
20
V
–5.5
–40
–55
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground pin.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1), all pins
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX UNIT
VIN
17
5.5
0.1
FB, EN
–0.1
–0.1
–1
–5
–1
–5
0
GND
SW
17
18
Pin voltage
V
SW (transient < 20 ns)
BST
17
BST (transient < 20 ns)
IOUT
18
Output current
Temperature
2
A
Operating junction temperature, TJ
Storage temperature, Tstg
125
150
–40
–40
°C
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6.4 Thermal Information
DRL (SOT-563)
UNIT
THERMAL METRIC(1)
6 PINS
(2)
RθJA
Junction-to-ambient thermal resistance
137.4
74
°C/W
°C/W
RθJA_effective
Junction-to-ambient thermal resistance on EVM board
(3)
RθJC(top)
RθJB
ψJT
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
58.8
29.8
1.3
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.4
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were simulated on a standard JEDEC board. These values do not represent the performance obtained in an actual application.
(3) This RθJA_effective is tested on TPS562242EVM board (2 layer, copper thickness is 2-oz) at VIN = 12 V, VOUT =5 V, IOUT = 2A, TA
25°C.
=
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY VOLTAGE
VIN
IVIN
Input voltage range
VIN
3
17
V
No load, VEN = 5 V, VFB = 0.85 V, non-switching, ECO
version
VIN supply current
100
5
µA
µA
IINSDN
VIN shutdown current
No load, VEN = 0 V
UVLO
Rising threshold
Falling threshold
Hysteresis
2.80
2.60
2.92
2.72
200
3.00
2.85
V
V
Input undervoltage lockout
threshold
VIN_UVLO
mV
FEEDBACK VOLTAGE
VREF FB voltage
TJ = 25°C
792
788
800
800
808
812
mV
mV
TJ = –40°C to 125°C
INTEGRATED POWER MOSFETS
55.0
67.5
24.3
30.2
TJ = 25°C, VIN ≥5 V
TJ = 25°C, VIN = 3 V (1)
TJ = 25°C, VIN ≥5 V
TJ = 25°C, VIN = 3 V
mΩ
mΩ
mΩ
mΩ
High-side MOSFET on-
RDSON_HS
resistance
Low-side MOSFET on-
RDSON_LS
resistance
SWITCHING FREQUENCY
Fsw
Switching frequency
Minimum on time
Minimum off time
TJ = 25°C, VOUT = 3.3 V
VFB = 0.6 V
1.4
60
MHz
ns
(1)
TON(MIN)
(1)
TOFF(MIN)
110
ns
LOGIC THRESHOLD
VENH
VENL
VENHYS
IEN
EN threshold high level
Rising enable threshold
Falling disable threshold
Hysteresis
1.14
0.91
1.17
1.00
170
1.6
1.22
1.09
V
V
EN threshold low level
EN hystersis
mV
uA
EN pull up current
VEN = 1.0 V
CURRENT LIMIT
IOCL_LS
Overcurrent threshold
Valley current set point
2.3
3.0
3.6
A
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English Data Sheet: SLUSEQ4
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ZHCSP82A –DECEMBER 2022 –REVISED MAY 2023
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SOFT START
tSS
Internal soft start time
1.6
ms
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
VOVP
OVP trip threshold
OVP prop deglitch
UVP trip threshold
UVP prop deglitch
Hiccup enable delay time
VFB rising
110
55
115
24
120
65
%
us
%
tOVPDLY
VUVP
tUVPDLY
tUVPEN
VFB falling
60
220
14
us
ms
THERMAL SHUTDOWN
(1)
TSDN
Shutdown temperature
Hysteresis
155
20
Thermal shutdown threshold
°C
(1)
TOTPHSY
(1) Specified by design
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6.6 Typical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
106
105
104
103
102
101
100
99
1.174
1.173
1.172
1.171
1.17
98
97
96
1.169
95
-40
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Junction Temperature (C)
Junction Temperature (C)
图6-2. Enable On Threshold Voltage
图6-1. Quiescent Current
0.995
34
32
30
28
26
24
22
20
18
0.99
0.985
0.98
0.975
0.97
0.965
0.96
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (C)
Junction Temperature (C)
图6-3. Enable Off Threshold Voltage
图6-4. Low-Side RDS(ON)
0.802
0.801
0.8
80
75
70
65
60
55
50
45
40
0.799
0.798
0.797
0.796
0.795
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (C)
Junction Temperature (C)
图6-6. VREF Voltage
图6-5. High-Side RDS(ON)
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6.6 Typical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 3V
Vin = 6V
Vin = 12V
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
图6-7. Efficiency at 0.8 VOUT with a 1-μH Inductor
图6-8. Efficiency at 1.05 VOUT with a 1.2-μH Inductor
100%
90%
80%
70%
60%
50%
40%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
30%
20%
10%
0
Vin = 6V
Vin = 12V
Vin = 6V
Vin = 12V
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
图6-9. Efficiency at 3.3 VOUT with a 2.2-μH Inductor
1400
图6-10. Efficiency at 5 VOUT with a 3.3-μH Inductor
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1300
1200
1100
1000
900
Vout = 1.05V
Vout = 3.3V
Vout = 5V
Vout = 1.05V
Vout = 3.3V
Vout = 5V
800
700
600
2
4
6
8
10
Vin (V)
12
14
16
18
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
图6-11. Frequency vs Input Voltage, IOUT = 2 A
图6-12. Frequency vs Loading, VIN = 12 V
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7 Detailed Description
7.1 Overview
The TPS562242 is a 2-A integrated FET synchronous buck converter that operates from 3-V to 17-V input
voltage and 0.8-V to 10-V output voltage. The device employs a D-CAP3 control mode that provides fast
transient response with no external compensation components and an accurate feedback voltage. The
proprietary D-CAP3 control mode enables low external component count, ease of design, and optimization of the
power design for cost, size, and efficiency. The topology provides a seamless transition between CCM operating
mode at higher load condition and DCM operation mode at lighter load condition.
The Eco-mode version allows the TPS562242 to maintain high efficiency at light load. The TPS562242 is able to
adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-
low ESR ceramic capacitors.
7.2 Functional Block Diagram
UV threshold
+
UV
OV
VIN
+
+
LDO
OV threshold
VREGOK
2.92 V /
2.72 V
6
FB
VREF
Internal
VCC
+
+
Internal
BST
BST
VIN
4
1
PWM
+
+
Control Logic
SS
Internal
Compensation
· On/Off time
· Minimum On/Off
· Light load
Internal SS
2
3
SW
XCON
· OCP/OVP/UVP/TSD
· Soft-Start
Clock
GND
+
EN
5
EN Threshold
+
OCL
+
THOK
+
+
155°C /20°C
ZC
NOCL
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control Mode
The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports
a proprietary D-CAP3 control mode. The D-CAP3 control mode combines adaptive on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. The device is stable even with virtually no ripple at the output. The
TPS562242 also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence, it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage to emulate the output ripple, enabling the use of very low-ESR output capacitors
such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation is
required for D-CAP3 control mode.
7.3.2 Eco-mode Control
The TPS562242 is designed with advanced Eco-mode to maintain high light-load efficiency. As the output
current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point
that its ripple valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction mode. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases, the converter runs into discontinuous conduction mode. The on time is kept almost the
same as it was in continuous conduction mode so that it takes longer time to discharge the output capacitor with
smaller load current to the level of the reference voltage. This makes the switching frequency lower, proportional
to the load current, and keeps the light load efficiency high. Use the below equation to calculate the transition
point to the light load operation IOUT(LL) current.
(V - VOUT ) ì VOUT
1
IN
IOUT(LL)
=
ì
2 ì L ì fSW
V
IN
(1)
7.3.3 Soft Start and Prebiased Soft Start
The TPS562242 has an internal fixed 1.6-ms soft-start time. The internal soft-start function begins ramping up
the reference voltage to the PWM comparator during start-up period.
If the output capacitor is prebiased at start-up, the devices initiate switching and start ramping up only after the
internal reference voltage becomes higher than the feedback voltage, VFB. This scheme makes sure that the
converter ramps up smoothly into the regulation point.
7.3.4 Overvoltage Protection
The TPS562242 has the overvoltage protection feature. When the output voltage becomes higher than the OVP
threshold, the OVP is triggered with a 24-μs deglitch time. Both the high-side MOSFET and the low-side
MOSFET drivers are turned off. When the overvoltage condition is removed, the device returns to switching.
7.3.5 Large Duty Operation
The TPS562242 can support large duty operations up to 94% by smoothly dropping down the switching
frequency. When VIN / VOUT < 1.6 and VFB is lower than internal VREF, the switching frequency is allowed to
smoothly drop to make tON extended to implement the large duty operation and improve the performance of the
load transient. Please refer frequency test waveform in 图 6-11. The minimum switching frequency is limited to
approximately 700 kHz.
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7.3.6 Current Protection and Undervoltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the off state by measuring the low-side FET drain-to-source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by the
following:
• VIN
• VOUT
• On-time
• Output inductor value
During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch
current is the load current, IOUT. If the monitored valley current is above the OCL level, the converter maintains a
low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until
the current level becomes OCL level or lower. In subsequent switching cycles, the on time is set to a fixed value
and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current is higher than
the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current can be higher than the current available
from the converter, which can cause the output voltage to fall. When the FB voltage falls below the UVP
threshold voltage, the UVP comparator detects it and the device shuts down after the UVP delay time (typically
220 µs) and restarts after the hiccup wait time (typically 14 ms). After the device enters the hiccup cycling, the
hiccup on time is typically 2.2 ms.
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.7 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is a non-latch protection.
7.3.8 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value, the device is shut
off. This protection is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Eco-mode Operation
The TPS562242 operates in Eco-mode, which maintains high efficiency at light loading. As the output current
decreases from heavy load conditions, the inductor current is also reduced and eventually comes to a point
where the rippled valley touches zero level, which is the boundary between continuous conduction and
discontinuous conduction mode. The rectifying MOSFET is turned off when the zero inductor current is detected.
As the load current further decreases, the converter runs into discontinuous conduction mode. The on time is
kept almost the same as it was in continuous conduction mode so that it takes longer time to discharge the
output capacitor with smaller load current to the level of the reference voltage. This action makes the switching
frequency lower, proportional to the load current, and keeps the light load efficiency high.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The device is a typical buck DC/DC converter that is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum available output current of 2 A. The following design procedure can be used to select
component values for TPS562242. Alternately, the WEBENCH Power Designer software can be used to
generate a complete design. The WEBENCH Power Designer software uses an iterative design procedure and
accesses a comprehensive database of components when generating a design. This section presents a
simplified discussion of the design process.
8.2 Typical Application
The application schematic in 图 8-1 was developed to meet the requirements in 表 8-1. This circuit is available
as the evaluation module (EVM). The sections provide the design procedure.
图8-1 shows the TPS562242 5-V to 17-V input, 1.05-V output converter schematic.
图8-1. Schematic
8.2.1 Design Requirements
表8-1 shows the design parameters for this application.
表8-1. Design Parameters
Parameter
Output voltage
Output current
Conditions
MIN
TYP
1.05
2
MAX
Unit
V
VOUT
IOUT
A
0.2-A –1.8-A load step, 0.8-A/μs
slew rate
Transient response
±2% × VOUT
V
ΔVOUT
VIN
Input voltage
5
12
6
17
V
VOUT(ripple)
FSW
Output voltage ripple
Switching frequency
Ambient temperature
CCM condition
mV
MHz
°C
1.4
25
TA
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS562242 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using 方程式2 to calculate VOUT
.
To improve efficiency at very light loads, consider using larger value resistors. If the values are too high, the
regulator is more susceptible to noise and voltage errors from the FB input current are noticeable. Use a 10-kΩ
resistor for R5 to start the design.
R
4
V
= 0 . 8 × 1 +
(2)
OUT
R
5
8.2.2.3 Output Filter Selection
The LC filter used as the output filter has a double pole at 方程式 3. In this equation, COUT uses its effective
value after derating, not its nominal value.
1
fP
=
2p LOUT ì COUT
(3)
For any control topology that is compensated internally, there is a range of the output filter it can support. At low
frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the
device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per
decade rate and the phase drops has a 180 degree drop. The internal ripple generation network introduces a
high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and leads the 90 degree
phase boost. The internal ripple injection high-frequency zero is about 156 kHz. TI recommends the inductor and
capacitor selected for the output filter such that the double pole is located approximately 40 kHz, so that the
phase boost provided by this high-frequency zero provides adequate phase margin for the stability requirement.
The crossover frequency of the overall system is usually targeted to be less than one-third of the switching
frequency (fSW). For high output voltage condition, TI recommends to use 10-100pF feedforward capacitor for
enough phase margin.
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表8-2. Recommended Component Values
Typical L1
(μH)
Typical COUT
Typical COUT
Category
Output Voltage
(V)
Typical C6
(pF)
Typical COUT (μF)
Nominal Value Range
R4 (kΩ)
R5 (kΩ)
(μF)
0.8
1.05
3.3
5
0
10.0
10.0
30.0
30.0
30.0
1
44
22
22
22
44
22-88
22-66
22-88
22-88
44-88
MLCC, 0805, 10V
MLCC, 0805, 10V
MLCC, 0805, 10V
MLCC, 0805, 10V
MLCC, 0805, 16V
—
—
33
33
47
3.12
94.2
158.0
345.0
1.2
2.2
3.3
4.7
10
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using 方程式 4, 方程式
5, and 方程式 6. Generally, TI recommends the peak-to-peak ripple current to be 20% – 50% of output average
current for a comprehensive benefit of efficiency and inductor volume. The inductor saturation current rating
must be greater than the calculated peak current and the RMS or heating current rating must be greater than the
calculated RMS current.
V
- VOUT
VOUT
IN(MAX)
IlP-P
=
ì
V
LO ì fSW
IN(MAX)
(4)
(5)
IlP-P
IlPEAK = IO
+
2
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(6)
For this design example, the calculated peak current is 2.3 A and the calculated RMS current is 2.00 A. The
inductor used is 74438357012 with 7-A rated current and 8.8-A saturation current.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562242 are intended for
use with ceramic or other low-ESR capacitors. Use 方程式7 to determine the required RMS current rating for the
output capacitor.
VOUT ì V - VOUT
(
)
IN
ICO(RMS)
=
12 ì V ì LO ì fSW
IN
(7)
For this design, one MuRata GRM21BR61A226ME44L 22-µF output capacitors are used. The typical ESR is 2
mΩeach. The calculated RMS current is 0.17 A and each output capacitor is rated for 4 A.
8.2.2.4 Input Capacitor Selection
The TPS562242 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. TI recommends an
additional 0.1-µF capacitor from the VIN pin to ground to provide high frequency filtering. The capacitor voltage
rating must be greater than the maximum input voltage.
8.2.2.5 Bootstrap Capacitor Selection
The real BST is integrated inside by using a special charging high side FET circuit. A typical 0.1-µF ceramic
capacitor can be connected between the BST to SW pin or leave floating.
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8.2.3 Application Curves
The following data is tested with VIN = 12 V, VOUT = 1.05 V, TA = 25°C, unless otherwise specified.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 17V
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
图8-2. Efficiency vs Loading
图8-3. Frequency vs Loading
1%
0.8%
0.6%
0.4%
0.2%
0
1%
0.8%
0.6%
0.4%
0.2%
0
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 17V
-0.2%
-0.4%
-0.6%
-0.8%
-1%
-0.2%
-0.4%
-0.6%
-0.8%
-1%
Iout = 2A
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Vin (V)
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Iout (A)
1
2
图8-5. Line Regulation vs VIN
图8-4. Load Regulation vs Loading
Vout = 20mV/div (AC coupled)
Vout = 20mV/div (AC coupled)
SW = 5V/div
SW = 5V/div
20us/div
1us/div
图8-6. Output Voltage Ripple with 0.01-A Loading
图8-7. Output Voltage Ripple with 2-A Loading
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Vin = 5V/div
EN = 2V/div
Vin = 10V/div
EN = 2V/div
Vout = 500mV/div
Vout = 500mV/div
2ms/div
2ms/div
图8-8. Start-up Through EN, IOUT = 2 A
图8-9. Shutdown Through EN, IOUT = 2 A
Vin = 5V/div
Vin = 5V/div
EN = 5V/div
EN = 5V/div
Vout = 500mV/div
Vout = 500mV/div
2ms/div
10ms/div
图8-10. Start-up with VIN Rising, IOUT = 2 A
图8-11. Shutdown with VIN Falling, IOUT = 2 A
Vout = 50mV/div (AC coupled)
Vout = 50mV/div (AC coupled)
Iout = 1A/div
Iout = 1A/div
200us/div
200us/div
图8-12. Transient Response with 0.2 A to 1.8 A
图8-13. Transient Response with 0.01 A to 2 A
Vout = 1V/div
Vout = 500mV/div
SW = 10V/div
SW = 10V/div
IL = 2A/div
IL = 5A/div
100us/div
10ms/div
图8-14. Normal Operation to Output Hard Short
图8-15. Output Hard Short Hiccup
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8.3 Power Supply Recommendations
The TPS562242 are designed to operate from input supply voltages in the range of 3 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation.
8.4 Layout
8.4.1 Layout Guidelines
• Keep VIN and GND traces as wide as possible to reduce trace impedance. The wide areas are also an
advantage from the view point of heat dissipation.
• Place the input capacitor and output capacitor as close to the device as possible to minimize trace
impedance.
• Provide sufficient vias for the input capacitor and output capacitor.
• Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
• Do not allow switching current to flow under the device.
• Connect a separate VOUT path to the upper feedback resistor.
• Make a Kelvin connection to the GND pin for the feedback path.
• Place a voltage feedback loop away from the high-voltage switching trace, and preferably has ground shield.
• Make the trace of the FB node as small as possible to avoid noise coupling.
• Make the GND trace between the output capacitor and the GND pin as wide as possible to minimize its trace
impedance.
8.4.2 Layout Example
VIN
GND
CIN
RFBB
RFBT
FB
EN
VIN
SW
EN
Control
SW
GND
BST
CBST
VOUT
GND
COUT
VIA (Connected to GND plane at bottom layer)
VIA (Connected to SW)
Copper
图8-16. Suggested Layout
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS562242 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
D-CAP3™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS562242DRLR
ACTIVE
SOT-5X3
DRL
6
4000 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2242
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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