TPS563209 [TI]
采用 SOT-23 封装的 17V 输入、3A 同步降压稳压器;
| 型号： | TPS563209 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-23 封装的 17V 输入、3A 同步降压稳压器 稳压器 |
| 文件： | 总30页 (文件大小：1073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
采用 6 引脚 SOT-23 封装的 TPS56x209 4.5V 至 17V 输入、2A、3A
同步降压稳压器
1 特性
3 说明
1
•
TPS562209 - 集成有 122mΩ 和 72mΩ FET 的 2A
转换器
TPS562209 和 TPS563209 是采用 6 引脚 SOT-23 封
装的简单易用型 2A/3A 同步降压转换器。
•
TPS563209 - 带有集成 68mΩ 和 39mΩ FET 的
3A 转换器
此器件被优化为使用尽可能少的外部组件即可运行，并
且可以实现低待机电流。
•
•
•
•
•
•
•
•
•
•
D-CAP2™针对快速瞬态响应的模式控制
输入电压范围：4.5V 至 17V
输出电压范围：0.76V 至 7V
650kHz 开关频率
这些开关模式电源 (SMPS) 器件采用 D-CAP2™ 模式
控制，从而提供快速瞬态响应，并且在无需外部补偿组
件的情况下支持诸如高分子聚合物等低等效串联电阻
(ESR) 输出电容器以及超低 ESR 陶瓷电容器。
低于 10µA 的低关断电流
1% 反馈电压精度 (25°C)
从预偏置输出电压中启动
逐周期过流限制
TPS562209 和 TPS563209 始终在连续传导模式下运
行，与非连续传导模式相比，该模式可降低轻负载条件
下的输出纹波电压。TPS56x209 采用 6 引脚 1.6mm ×
2.9mm SOT (DDC) 封装，结温范围为 –40°C 至 150°
C。
断续模式欠压保护
非锁存过压保护 (OVP)，欠压闭锁 (UVLO) 和热关
断 (TSD) 保护
器件信息(1)
•
固定软启动时间：1.0ms
器件型号
封装
封装尺寸（标称值）
2 应用
TPS563209，TPS5
62209
SOT (6)
1.60mm x 2.90mm
•
•
•
•
数字电视电源
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
高清 Blu-ray Disc™播放器
网络家庭终端设备
数字机顶盒 (STB)
空白
空白
简化电路原理图
瞬态响应
TPS563209
TPS562209
1
2
3
6
5
GND
SW
VBST
EN
VO = 50 mV / div (ac coupled)
EN
VOUT
4
VIN
VIN
VOUT
VFB
IO = 1 A / div
Copyright © 2016, Texas Instruments Incorporated
Load step = 0.75 A - 2.25 A
Slew rate = 500 mA / µsec
Time = 200 µsec / div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCM5
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ............................................... 13
Power Supply Recommendations...................... 20
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics TPS562209.......................... 6
6.7 Typical Characteristics TPS563209.......................... 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ...................................... 10
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 相关链接................................................................ 22
11.2 接收文档更新通知 ................................................. 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
Changes from Original (September 2014) to Revision A
Page
•
•
•
•
Updated the Pinout image in Pin Configuration and Functions ............................................................................................. 3
Changed the "Handling Ratings" table to the ESD Ratings table .......................................................................................... 4
Changed RθJB for TPS562209 From: 57.3 To: 13.4 in Thermal Information .......................................................................... 4
The Adaptive On-Time Control and PWM Operation, changed text From: "proportional to the converter input
voltage, VIN, and inversely proportional to the output voltage, VO" To: "inversely proportional to the converter input
voltage, VIN, and proportional to the output voltage, VO"...................................................................................................... 11
2
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
5 Pin Configuration and Functions
DDC Package
6 Pin (SOT)
Top View
GND
SW
1
6
5
4
VBST
EN
2
3
VIN
VFB
Pin Functions
PIN
DESCRIPTION
NAME
NO.
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect
sensitive VFB to this GND at a single point.
GND
1
SW
2
3
4
5
6
Switch node connection between high-side NFET and low-side NFET.
VIN
Input voltage supply pin. The drain terminal of high-side power NFET.
VFB
EN
Converter feedback input. Connect to output voltage with feedback resistor divider.
Enable input control. Active high and must be pulled up to enable the device.
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins.
VBST
Copyright © 2014–2016, Texas Instruments Incorporated
3
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
TJ = –40°C to 150°C (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
19
UNIT
V
VIN, EN
VBST
25
V
VBST (10 ns transient)
27.5
6.5
6.5
19
V
Input voltage range
VBST (vs SW)
VFB,
V
V
SW
V
SW (10 ns transient)
–3.5
–40
–55
21
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
MIN
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
2
kV
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-
C101, all pins(2)
500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TJ = -40°C to 150°C (unless otherwise noted)
MIN
MAX
UNIT
VIN
Supply input voltage range
VBST
4.5
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3.5
–40
17
23
26
6.0
17
5.5
17
20
85
V
VBST (10 ns transient)
VBST(vs SW)
Input voltage range EN
VI
V
VFB
SW
SW (10 ns transient)
TA
Operating free-air temperature
°C
6.4 Thermal Information
TPS562209
TPS563209
THERMAL METRIC(1)
UNIT
°C/W
DDC (6 PINS)
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
109.2
44.5
13.4
2.3
87.9
42.2
13.6
1.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
60.4
13.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
6.5 Electrical Characteristics
TJ = -40°C to 150°C, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
µA
µA
µA
IVIN
Operating – non-switching supply current
Shutdown supply current
VIN current, TA = 25°C, EN = 5V, VFB = 0.8 V
VIN current, TA = 25°C, EN = 0 V
650 900
IVINSDN
3.0
10
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
EN
1.6
V
V
EN low-level input voltage
EN pin resistance to GND
EN
0.6
VEN = 12 V
225
450 900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, continuous mode
operation
VFBTH
VFB threshold voltage
VFB input current
758
765 772
mV
mA
IVFB
VFB = 0.8V, TA = 25°C
0
±0.1
MOSFET
TA = 25°C, VBST – SW = 5.5 V (TPS562209)
TA = 25°C, VBST – SW = 5.5 V (TPS563209)
TA = 25°C (TPS562209)
122
68
RDS(on)h
High side switch resistance
Low side switch resistance
mΩ
mΩ
72
RDS(on)l
TA = 25°C (TPS563209)
39
CURRENT LIMIT
DC current, VOUT = 1.05V , L1 = 2.2 µH
DC current, VOUT = 1.05V , L1 = 1.5 µH
2.5
3.5
3.2
4.2
4.3
5.3
Iocl
Current limit(1)
A
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
155
35
TSDN
Thermal shutdown threshold(1)
°C
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
TA = 25°C, VFB = 0.5 V
150
ns
ns
tOFF(MIN) Minimum off time
260 310
SOFT START
Tss
Soft –start time
Internal soft-start time, TA = 25°C
0.7
1.0
1.3
ms
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
125%x
Vfbth
VOVP
VUVP
Output OVP threshold
Output UVP threshold
OVP Detect
65%xVf
bth
Hiccup detect
THiccupOn Hiccup Power On Time
THiccupOff Hiccup Power Off Time
UVLO
Relative to soft start time
Relative to soft start time
1
7
ms
ms
Wake up VIN voltage
Hysteresis VIN voltage
3.45
0.13
3.75 4.05
0.32 0.55
UVLO
UVLO threshold
V
(1) Not production tested.
Copyright © 2014–2016, Texas Instruments Incorporated
5
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
6.6 Typical Characteristics TPS562209
VIN = 12V (unless otherwise noted)
800
700
600
500
400
300
200
100
0
6
5
4
3
2
1
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature (èC)
Junction Temperature (èC)
D001
D002
Figure 1. Supply Current vs Junction Temperature
Figure 2. VIN Shutdown Current vs Junction Temperature
0.780
0.775
0.770
0.765
0.760
0.755
0.750
60
50
40
30
20
10
0
-10
-50
0
50
100
150
0
3
6
9
12
15
18
Junction Temperature (èC)
EN Input Voltage (V)
D003
D004
Figure 3. VFB Voltage vs Junction Temperature
Figure 4. EN Current vs EN Voltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 3.3V
VOUT = 1.8V
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Output Current (A)
Output Current (A)
D005
D006
Figure 5. Efficiency vs Output Current
Figure 6. Efficiency vs Output current (VI = 5 V)
6
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
Typical Characteristics TPS562209 (continued)
VIN = 12V (unless otherwise noted)
800
750
700
650
600
550
500
3.0
2.5
2.0
1.5
1.0
VO = 1.05V
VO = 1.2V
VO = 1.8V
VO = 3.3V
VO = 5V
VO = 0.76 V to 3.3 V
0.5
VO = 5 V
VO = 7 V
0.0
4
6
8
10
12
14
16
18
0
25
50
75
100
Input Voltage (V)
Ambient Temperature (èC)
D007
D008
Figure 7. Output Current vs Ambient Temperature
Figure 8. Switching Frequency vs Input Voltage
900
VO = 1.05V
VO = 1.8V
VO = 3.3V
850
800
750
700
650
600
550
500
0
0.5
1
1.5
2
IO - Output Current (A)
D009
Figure 9. Switching Frequency vs Output Current
Copyright © 2014–2016, Texas Instruments Incorporated
7
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
6.7 Typical Characteristics TPS563209
VIN = 12V (unless otherwise noted)
800
700
600
500
400
300
200
100
0
6
5
4
3
2
1
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature (èC)
Junction Temperature (èC)
D010
D011
Figure 10. Supply Current vs Junction Temperature
Figure 11. VIN Shutdown Current vs Junction Temperature
60
0.780
50
40
30
20
10
0
0.775
0.770
0.765
0.760
0.755
0.750
-10
0
3
6
9
12
15
18
-50
0
50
100
150
EN Input Voltage (V)
Junction Temperature (èC)
D013
D012
Figure 13. EN Current vs EN Voltage
Figure 12. VFB Voltage vs Junction Temperature
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 3.3V
VOUT = 1.8V
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
D014
D015
Figure 14. Efficiency vs Output Current
Figure 15. Efficiency vs Output current (VI = 5 V)
8
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
Typical Characteristics TPS563209 (continued)
VIN = 12V (unless otherwise noted)
800
750
700
650
600
550
500
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VO = 0.76V
VO = 1.05V
VO = 6.5V
VO = 0.76 V to 3.3 V
VO = 5 V
0.5
VO = 7 V
0.0
0
25
50
75
100
4
6
8
10
12
14
16
18
Input Voltage (V)
Ambient Temperature (èC)
D016
D017
Figure 16. Output Current vs Ambient Temperature
Figure 17. Switching Frequency vs Input Voltage
900
VO = 0.76V
VO = 1.05V
VO = 6.5V
850
800
750
700
650
600
550
500
0
0.5
1
1.5
2
2.5
3
IO - Output Current (A)
D018
Figure 18. Switching Frequency vs Output Current
Copyright © 2014–2016, Texas Instruments Incorporated
9
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS562209 and TPS563209 are 2-A and 3-A synchronous step-down converters, respectively. The
proprietary D-CAP2™ mode control supports low ESR output capacitors such as specialty polymer capacitors
and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response
of D-CAP2™ mode control can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
3
VIN
VUVP
+
Hiccup
VREG5
UVP
Control Logic
Regulator
UVLO
+
OVP
VOVP
VFB
4
VBST
SW
6
2
PWM
Voltage
Reference
Ref
+
+
HS
SS
Soft Start
Ton
One-Shot
XCON
VREG5
LS
TSD
OCL
threshold
OCL
+
1
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 19. TPS56x209
10
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
7.3 Feature Description
7.3.1 The Adaptive On-Time Control and PWM Operation
The main control loop of the TPS56x209 are adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control
with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration
with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN, and
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS562209 and TPS563209 have an internal 1.0ms soft-start. When the EN pin becomes high, the internal
soft-start function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.3 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During
the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the
on-time and the output inductor value.
During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch
current is the load current Iout. If the monitored current is above the OCL level, the converter maintains low-side
FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current
level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the
current is monitored in the same manner. If the over current condition exists consecutive switching cycles, the
internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle
occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL
threshold is returned to the higher value.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time
(typically 14µs) and re-start after the hiccup time (typically 12ms).
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.4 Over Voltage Protection
TPS562209 and TPS563209 detect over voltage condition by monitoring the feedback voltage (VFB). When the
feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high and
both the high-side MOSFET and the low-side MOSFET turn off. This function is non-latch operation.
7.3.5 UVLO Protection
Under voltage lock out protection (UVLO) monitors the device input voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut off. This protection is non-latching.
Copyright © 2014–2016, Texas Instruments Incorporated
11
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
Feature Description (continued)
7.3.6 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 155°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS562209 and TPS563209 can operate in their normal switching modes. Normal continuous conduction mode
(CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS562209 and TPS563209 operate
at a quasi-fixed frequency of 650 kHz.
7.4.2 Forced CCM Operation
When the TPS562209 and TPS563209 are in the normal CCM operating mode and the switch current falls below
0 A, the TPS562209 and TPS563209 begin operating in forced CCM.
7.4.3 Standby Operation
When the TPS562209 and TPS563209 are operating in either normal CCM or forced CCM, they may be placed
in standby by asserting the EN pin low.
12
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS562209 and TPS563209 are typically used as step down converters, which convert a voltage from 4.5V
- 17V to a lower voltage. Webench software is available to aid in the design and analysis of circuits
8.2 Typical Applications
8.2.1 TPS562209 4.5-V to 17-V Input, 1.05-V Output Converter
U1
L1 2.2 uH
TPS562209
VOUT = 1.05 V, 2 A
VIN = 4.5 V to 17 V
3
5
4
2
6
1
VIN
VIN
EN
SW
VBST
GND
VOUT
C4
R1 10.0k
R2
3.74k
EN
C1
10µF
C2
10µF
C3
C5
22µF
C6
22µF
0.1µF
VFB
R3
10.0k
Not Installed
Copyright © 2016, Texas Instruments Incorporated
Figure 20. TPS562209 1.05V/2A Reference Design
8.2.1.1 Design Requirements
To begin the design process, you must know a few application parameters:
Table 1. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
4.5 V to 17 V
1.05 V
Output current
2 A
Output voltage ripple
20 mVpp
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 1 to calculate VOUT
.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R2
æ
ö
VOUT = 0.765 ´ 1+
ç
÷
R3
è
ø
(1)
8.2.1.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
F =
P
2p LOUT ´ COUT
(2)
13
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of
Equation 2 is located below the high frequency zero but close enough that the phase boost provided be the high
frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values
recommended in Table 2.
Table 2. Recommended Component Values
OUTPUT
VOLTAGE
(V)
L1 (µH)
TYP
R2
(kΩ)
R3
(kΩ)
C5 + C6 (µF)
MIN
MAX
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
1.5
1.5
1.5
1.5
1.5
2.2
2.2
3.3
3.3
2.2
2.2
2.2
2.2
2.2
3.3
3.3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
6.5
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3,
Equation 4 and Equation 5. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 4 and the RMS
current of Equation 5.
V
- VOUT
VOUT
´
IN(MAX)
IlP-P
=
V
LO ´ ƒSW
IN(MAX)
(3)
(4)
IlP-P
IlPEAK = IO +
2
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(5)
For this design example, the calculated peak current is 2.34 A and the calculated RMS current is 2.01 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5-A and an RMS current rating of 4.3-A
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562209 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20µF to 68µF. Use Equation 6
to determine the required RMS current rating for the output capacitor.
VOUT ´ VIN - VOUT
(
12 ´ V ´LO ´ ƒSW
)
ICO(RMS)
=
IN
(6)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.199A and each output capacitor is rated for 4A.
8.2.1.2.3 Input Capacitor Selection
The TPS562209 and TPS563209 require an input decoupling capacitor and a bulk capacitor is needed
depending on the application. A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An
additional 0.1 µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage.
14
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
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ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
8.2.1.2.4 Bootstrap Capacitor Selection
A 0.1µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.1.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0
0
4
0.5
1
1.5
2
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
Output Current (A)
D024
D025
Figure 21. TPS562209 Efficiency
Figure 22. TPS562209 Light Load Efficiency
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0.5
1
1.5
2
0
0.5
1
1.5
2
Output Current (A)
Output Current (A)
D026
D027
Figure 23. TPS562209 Load Regulation, VI = 5 V
Figure 24. TPS562209 Load Regulation, VI = 12 V
0.5
0.4
0.3
0.2
0.1
0
IO = 2 A
VI = 100 mV / div (ac coupled)
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
6
8
10
12
14
16
18
Time = 1 µsec / div
Input Voltage (V)
D028
Figure 26. TPS562209 Input Voltage Ripple
Figure 25. TPS562209 Line Regulation
Copyright © 2014–2016, Texas Instruments Incorporated
15
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
IO = 2 A
VO = 20 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
IO = 500 mA / div
SW = 5 V / div
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
Time = 200 µsec / div
Time = 1 µsec / div
Figure 27. TPS562209 Output Voltage Ripple
Figure 28. TPS562209 Transient Response
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Figure 29. TPS562209 Start Up Relative to VI
Time = 2 msec / div
Figure 30. TPS562209 Start Up Relative to EN
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Figure 31. TPS562209 Shut Down Relative to VI
Time = 2 msec / div
Figure 32. TPS562209 Shut Down Relative to EN
16
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
8.2.2 TPS563209 4.5-V to 17-V Input, 1.05-V Output Converter
U1
L1 1.5 uH
TPS563209
VOUT = 1.05 V, 3 A
VIN = 4.5 V to 17 V
3
5
4
2
6
1
VIN
VIN
SW
VBST
GND
VOUT
R2
3.74k
C4
R1 10.0k
EN
EN
C1
10µF
C2
10µF
C3
0.1µF
C5
22µF
C6
22µF
C7
22µF
0.1µF
VFB
R3
10.0k
Copyright © 2016, Texas Instruments Incorporated
Figure 33. TPS563209 1.05V/3A Reference Design
8.2.2.1 Design Requirements
To begin the design process, the user must know a few application parameters:
Table 3. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
4.5 V to 17 V
1.05 V
Output current
3 A
Output voltage ripple
20 mVpp
8.2.2.2 Detailed Design Procedures
The detailed design procedure for TPS563209 is the same as for TPS562209 except for inductor selection.
8.2.2.2.1 Output Filter Selection
Table 4. Recommended Component Values
OUTPUT
VOLTAGE
(V)
L1 (µH)
TYP
R2
(kΩ)
R3
(kΩ)
C5 +C6 + C7
(µF)
MIN
MAX
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
2.2
2.2
1.5
1.5
1.5
1.5
2.2
2.2
2.2
3.3
3.3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
6.5
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 7,
Equation 8 and Equation 9. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
ƒSW
.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 8 and the RMS
current of Equation 9.
V
- VOUT
VOUT
´
IN(MAX)
IlP-P
=
V
LO ´ ƒSW
IN(MAX)
(7)
(8)
IlP-P
IlPEAK = IO +
2
Copyright © 2014–2016, Texas Instruments Incorporated
17
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(9)
For this design example, the calculated peak current is 3.505 A and the calculated RMS current is 3.014 A. The
inductor used is a TDK CLF7045T-1R5N with a peak current rating of 7.3-A and an RMS current rating of 4.9-A
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563209 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20µF to 68µF. Use Equation 6
to determine the required RMS current rating for the output capacitor.
VOUT ´ VIN - VOUT
(
12 ´ V ´LO ´ ƒSW
)
ICO(RMS)
=
IN
(10)
For this design three TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.292A and each output capacitor is rated for 4A.
8.2.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0
0.5
1
1.5
2
2.5
3
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
Output Current (A)
D019
D020
Figure 34. TPS563209 Efficiency
Figure 35. TPS563209 Light Load Efficiency
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
D021
D022
Figure 36. TPS563209 Load Regulation, VI = 5 V
Figure 37. TPS563209 Load Regulation, VI = 12 V
18
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
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ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
0.5
0.4
0.3
0.2
0.1
0
IO = 3 A
VI = 50 mV / div (ac coupled)
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10
12
14
16
18
Time = 1 µsec / div
Input Voltage (V)
D029
Figure 39. TPS563209 Input Voltage Ripple
Figure 38. TPS563209 Line Regulation
IO = 3 A
VO = 50 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
SW = 5 V / div
IO = 1 A / div
Load step = 0.75 A - 2.25 A
Slew rate = 500 mA / µsec
Time = 1 µsec / div
Figure 40. TPS563209 Output Voltage Ripple
Time = 200 µsec / div
Figure 41. TPS563209 Transient Response
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 1 msec / div
Time = 1 msec / div
Figure 42. TPS563209 Start Up Relative to VI
Figure 43. TPS563209 Start Up Relative to EN
Copyright © 2014–2016, Texas Instruments Incorporated
19
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
VO = 500 mV / div
EN = 10 V / div
VO = 500 mV / div
Time = 1 msec / div
Time = 1 msec / div
Figure 45. TPS563209 Shut Down Relative to EN
Figure 44. TPS563209 Shut Down Relative to VI
9 Power Supply Recommendations
The TPS562209 and TPS563209 are designed to operate from input supply voltage in the range of 4.5V to 17V.
Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO / 0.65.
20
Copyright © 2014–2016, Texas Instruments Incorporated
TPS562209, TPS563209
www.ti.com.cn
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VOUT
GND
Additional
Vias to the
internal SW
node copper
Vias to the
GND plane
OUTPUT
CAPACITOR
BOOST
CAPACITOR
OUTPUT
INDUCTOR
GND
SW
VBST
EN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
VFB
Vias to the
internal SW
node copper
VIN
VIN
INPUT BYPAS
CAPACITOR
SW node copper
pour area on internal
or bottom layer
Figure 46. TPS562209 and TPS563209 Layout
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21
TPS562209, TPS563209
ZHCSCT6A –SEPTEMBER 2014–REVISED NOVEMBER 2016
www.ti.com.cn
11 器件和文档支持
11.1 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购
买链接。
表 5. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS563209
TPS562209
11.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
D-CAP2, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS562209DDCR
TPS562209DDCT
TPS563209DDCR
TPS563209DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
DDC
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
209
209
309
309
Samples
Samples
Samples
Samples
SN
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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23-Dec-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS562209DDCR
TPS562209DDCT
TPS563209DDCR
TPS563209DDCT
SOT-23-
THIN
DDC
DDC
DDC
DDC
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
SOT-23-
THIN
SOT-23-
THIN
3000
250
SOT-23-
THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS562209DDCR
TPS562209DDCT
TPS563209DDCR
TPS563209DDCT
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
DDC
DDC
DDC
DDC
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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