TPS563219A [TI]
采用 SOT-23 封装且具有电源正常指示和软启动功能的 17V 输入、3A 同步降压稳压器;
| 型号： | TPS563219A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-23 封装且具有电源正常指示和软启动功能的 17V 输入、3A 同步降压稳压器 软启动 稳压器 |
| 文件： | 总28页 (文件大小：1172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
TPS56x219A 采用 8 引脚 SOT-23 封装的 4.5V 至 17V 输入、2A/3A
同步降压稳压器
1 特性
3 说明
1
•
TPS562219A：集成有
133mΩ 和 80mΩ 场效应晶体管 (FET) 的 2A 转换
器
TPS562219A 和 TPS563219A 是采用 8 引脚 SOT-23
封装的简单易用型 2A/3A 同步降压转换器。
两款器件均经过优化，最大限度地减少了运行所需的外
部组件并且可以实现低待机电流。
•
•
TPS563219A：集成有
68mΩ 和 39mΩ FET 的 3A 转换器
D-CAP2™模式控制，此模式控制具有 650kHz 的
开关频率
这些开关模式电源 (SMPS) 器件采用 D-CAP2™ 模式
控制，从而提供快速瞬态响应，并且在无需外部补偿组
件的情况下支持诸如高分子聚合物等低等效串联电阻
(ESR) 输出电容器以及超低 ESR 陶瓷电容器。
•
•
•
•
•
•
•
•
•
输入电压范围：4.5V 至 17V
输出电压范围：0.76V 至 7V
650kHz 开关频率
这些器件始终在连续传导模式下运行，与非连续传导模
式相比，该模式可降低轻负载条件下的输出纹波电压。
TPS562219A 和 TPS563219A 采用 8 引脚 1.6mm ×
2.9mm SOT (DDF) 封装，额定环境温度范围为 –40°C
至 85°C。
低关断电流（低于 10µA）
1% 反馈电压精度 (25°C)
从预偏置输出电压中启动
逐周期过流限制
断续模式欠压保护
器件信息(1)
非锁存过压保护 (OVP)，欠压闭锁 (UVLO) 和热关
断 (TSD) 保护
器件型号
TPS562219A
TPS563219A
封装
封装尺寸（标称值）
•
•
可调软启动
SOT (8)
1.60mm x 2.90mm
电源正常输出
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
数字电视电源
高清 Blu-ray Disc™播放器
网络家庭终端设备
数字机顶盒 (STB)
空白
空白
简化原理图
TPS562219A 瞬态响应
TPS562219A
TPS563219A
VO = 50 mV / div (ac coupled)
1
2
3
4
GND
SW
VIN
PG
VBST
8
7
6
5
VOUT
VOUT
EN
VFB
SS
EN
IO = 500 mA / div
VIN
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
Copyright © 2016, Texas Instruments Incorporated
Time = 200 µsec / div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDT2
TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ...................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
9
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 器件支持 ............................................................... 22
11.2 文档支持 ............................................................... 22
11.3 相关链接................................................................ 22
11.4 接收文档更新通知 ................................................. 22
11.5 社区资源................................................................ 22
11.6 商标....................................................................... 22
11.7 静电放电警告......................................................... 22
11.8 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
日期
修订版本
注释
2016 年 11 月
*
首次发布。
2
Copyright © 2016, Texas Instruments Incorporated
TPS562219A, TPS563219A
www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
5 Pin Configuration and Functions
DDF Package
8 Pin SOT
Top View
GND
SW
1
8
VBST
2
3
7
6
5
EN
VFB
SS
VIN
PG
4
Pin Functions
PIN
DESCRIPTION
NAME
NO.
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect
sensitive VFB to this GND at a single point.
GND
1
SW
VIN
PG
2
3
4
5
6
7
8
Switch node connection between high-side NFET and low-side NFET.
Input voltage supply pin. The drain terminal of high-side power NFET.
Power good open drain output
SS
Soft-start control. An external capacitor should be connected to GND.
Converter feedback input. Connect to output voltage with feedback resistor divider.
Enable input control. Active high and must be pulled up to enable the device.
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins.
VFB
EN
VBST
Copyright © 2016, Texas Instruments Incorporated
3
TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
TJ = -40°C to 150°C (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
19
UNIT
V
VIN, EN
VBST
25
V
VBST (10 ns transient)
27.5
6.5
6.5
5.5
19
V
VBST (vs SW)
Input voltage range
V
VFB, PG
V
SS
SW
V
V
SW (10 ns transient)
Operating junction temperature, TJ
Storage temperature, Tstg
–3.5
–40
–55
21
V
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TJ = –40°C to 150°C (unless otherwise noted)
MIN
MAX
17
23
26
6
UNIT
VIN
Supply input voltage range
VBST
4.5
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3.5
–40
V
VBST (10 ns transient)
VBST(vs SW)
EN
17
5.5
5
VI
Input voltage range
V
VFB, PG
SS
SW
17
20
85
SW (10 ns transient)
TA
Operating free-air temperature
°C
6.4 Thermal Information
TPS562219A
TPS563219A
UNIT
THERMAL METRIC(1)
DDF (SOT)
8 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
106.1
49.1
10.9
8.6
87.0
41.6
14.6
4.7
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
10.8
14.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
TPS562219A, TPS563219A
www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
IVIN
Operating – non-switching supply current
Shutdown supply current
VIN current, TA = 25°C, EN = 5 V, VFB = 0.8 V
VIN current, TA = 25°C, EN = 0 V
650
3
900
10
µA
µA
IVINSDN
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
EN
1.6
V
V
EN low-level input voltage
EN pin resistance to GND
EN
0.6
VEN = 12 V
225
450
765
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V
757
753
751
773
777
779
±0.1
VFBTH
VFB threshold voltage
VFB input current
TA = 0°C to 85°C, VO = 1.05 V(1)
TA = -40°C to 85°C, VO = 1.05 V(1)
VFB = 0.8V, TA = 25°C
mV
µA
IVFB
0
MOSFET
TA = 25°C, VBST – SW = 5.5 V, TPS562219A
TA = 25°C, VBST – SW = 5.5 V, TPS563219A
TA = 25°C, TPS562219A
133
68
RDS(on)h
High side switch resistance
Low side switch resistance
mΩ
mΩ
80
RDS(on)l
TA = 25°C, TPS563219A
39
CURRENT LIMIT
DC current, VOUT = 1.05 V, L1 = 2.2 µH,
TPS562219A
2.5
3.5
3.2
4.2
4.3
5.3
IOCL
Current limit(1)
A
DC current, VOUT = 1.05 V, L1 = 1.5 µH,
TPS563219A
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
155
35
TSDN
Thermal shutdown threshold(1)
°C
SOFT START
ISS
SS charge current
VSS = 1.2 V
4.2
85%
0.5
6
7.8
µA
POWER GOOD
VFB rising (Good)
VFB falling (Fault)
PG = 0.5 V
90%
85%
1
95%
VTHPG
PG threshold
IPG
PG sink current
mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
125%x
Vfbth
VOVP
VUVP
Output OVP threshold
Output UVP threshold
OVP Detect
65%x
Vfbth
Hiccup detect
tHiccupOn
tHiccupOff
UVLO
Hiccup Power On Time
Hiccup Power Off Time
1
7
cycle
V
Wake up VIN voltage
Hysteresis VIN voltage
3.45
0.13
3.75
0.32
4.05
0.55
UVLO
UVLO threshold
(1) Not production tested.
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
TA = 25°C, VFB = 0.5 V
150
260
ns
ns
tOFF(MIN) Minimum off time
310
Copyright © 2016, Texas Instruments Incorporated
5
TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
6.7 Typical Characteristics
6.7.1 TPS562219A Characteristics
VIN = 12V (unless otherwise noted)
800
700
600
500
400
300
200
100
0
6
5
4
3
2
1
0
0
50
100
150
0
50
100
150
œ50
œ50
Junction Temperature(°C)
Junction Temperature (°C)
C011
C012
图 1. Supply Current vs Junction Temperature
图 2. VIN Shutdown Current vs Junction Temperature
0.780
0.775
0.770
0.765
0.760
0.755
0.750
60
50
40
30
20
10
0
œ10
0
50
100
150
0
3
6
9
12
15
18
œ50
Junction Temperature (°C)
EN Input Voltage (V)
C013
C014
图 3. VFB Voltage vs Junction Temperature
图 4. EN Current vs EN Voltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Vout = 5V
Vout = 3.3V
Vout = 1.8V
Vout = 3.3V
Vout = 1.8V
0
0.5
1
1.5
2
0
0.5
1
1.5
2
Output Current (A)
Output Current (A)
C015
C016
图 5. Efficiency vs Output Current
图 6. Efficiency vs Output Current (VI= 5V)
6
版权 © 2016, Texas Instruments Incorporated
TPS562219A, TPS563219A
www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
TPS562219A Characteristics (接下页)
800
800
750
700
650
600
550
500
450
400
Vo = 0.76V
Vo = 0.76V
Vo = 1.05V
Vo = 6.5V
Vo = 1.05V
750
Vo = 6.5V
700
650
600
550
500
450
400
4
6
8
10
12
14
16
18
0
0.5
1
1.5
2
Input Voltage (V)
Output Current (A)
C017
C018
图 7. Switching Frequency vs Input Voltage
图 8. Switching Frequency vs Output Current
版权 © 2016, Texas Instruments Incorporated
7
TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
6.7.2 TPS563219A Characteristics
800
700
600
500
400
300
200
100
0
6
5
4
3
2
1
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature (°C)
Junction Temperature (°C)
C019
C020
图 9. Supply Current vs Junction Temperature
图 10. VIN Shutdown Current vs Junction Temperature
0.780
0.775
0.770
0.765
0.760
0.755
0.750
60
50
40
30
20
10
0
œ10
-50
0
50
100
150
0
3
6
9
12
15
18
Junction Temperature (°C)
EN Input Voltage (V)
C021
C022
图 11. VFB Voltage vs Junction Temperature
图 12. EN Current vs EN Voltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Vout = 5V
Vout = 3.3V
Vout = 1.8V
Vout = 3.3V
Vout = 1.8V
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
C023
C024
图 13. Efficiency vs Output Current
图 14. Efficiency vs Output Current (VI = 5V)
8
版权 © 2016, Texas Instruments Incorporated
TPS562219A, TPS563219A
www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
TPS563219A Characteristics (接下页)
800
800
750
700
650
600
550
500
450
400
Vo = 0.76V
Vo = 0.76V
Vo = 1.05V
Vo = 6.5V
Vo = 1.05V
Vo = 6.5V
750
700
650
600
550
500
450
400
4
6
8
10
12
14
16
18
0
0.5
1
1.5
2
2.5
3
Input Voltage (V)
Output Current (A)
C025
C026
图 15. Switching Frequency vs Input Voltage
图 16. Switching Frequency vs Output Current
版权 © 2016, Texas Instruments Incorporated
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TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS562219A and TPS563219A are 2-A, 3-A synchronous step-down converters. The proprietary D-CAP2™
mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic
capacitors without complex external compensation circuits. The fast transient response of D-CAP2™ mode
control can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
7
3
VIN
V
V
+
UVP
Hiccup
VREG5
UVP
Control Logic
Regulator
UVLO
+
OVP
OVP
VFB
SS
6
5
VBST
8
PWM
Voltage
Reference
Ref
SS
+
+
HS
Soft Start
2
SW
Ton
One - Shot
XCON
VREG5
LS
TSD
OCL
threshold
PG
4
OCL
+
1
GND
+
V
THPG
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 The Adaptive On-Time Control and PWM Operation
The main control loop of the TPS562219A and TPS563219A are adaptive on-time pulse width modulation (PWM)
controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive
on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component
count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at
the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.
10
版权 © 2016, Texas Instruments Incorporated
TPS562219A, TPS563219A
www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
Feature Description (接下页)
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS562219A and TPS563219A have adjustable soft-start. When the EN pin becomes high, the SS charge
current (ISS) begins charging the capacitor which is connected from the SS pin to GND (CSS). Smooth control of
the output voltage is maintained during start up. The equation for the soft start time, TSS is shown in 公式 1.
Css´ VFBTH ´ 0.86
Tss(ms) =
Iss
(1)
where VFBTH is 0.765 V and Iss is 6 µA.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.3 Power Good
The power good output, PG is an open drain output. The power good function becomes active after 1.7 times
soft-start time. When the output voltage becomes within –10% of the target value, internal comparators detect
power good state and the power good signal becomes high. If the feedback voltage goes under 15% of the target
value, the power good signal becomes low.
7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over
current condition exists consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing
the available output current. When a switching cycle occurs where the switch current is not above the lower OCL
threshold, the counter is reset and the OCL threshold is returned to the higher value.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time
(typically 14 µs) and re-start after the hiccup time.
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.5 Over Voltage Protection
TPS562219A and TPS563219A detect over voltage condition by monitoring the feedback voltage (VFB). When
the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high
and the high-side MOSFET turns off. This function is non-latch operation.
7.3.6 UVLO Protection
Under voltage lock out protection (UVLO) monitors the internal regulator voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 155°C),
the device is shut off. This is a non-latch protection.
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11
TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS562219A and TPS563219A can operate in their normal switching modes. Normal continuous conduction
mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS562219A and
TPS563219A operate at a quasi-fixed frequency of 650 kHz.
7.4.2 Forced CCM Operation
When the TPS562209 and TPS563209 are in the normal CCM operating mode and the switch current falls below
0 A, the TPS562219A and TPS563219A begin operating in forced CCM.
7.4.3 Standby Operation
When the TPS562219A and TPS563219A are operating in either normal CCM or forced CCM, they may be
placed in standby by asserting the EN pin low.
12
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www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS562219A and TPS563219A are typically used as step down converters, which convert a voltage from
4.5 V - 17 V to a lower voltage. Webench software is available to aid in the design and analysis of circuits.
8.2 Typical Application
8.2.1 Typical Application, TPS562219A
U1
TPS562219A
L1 2.2uH
VIN = 4.5 - 17 V
C5
VOUT = 1.05 V, 2 A
3
7
8
VIN
VIN
EN
VBST
VOUT
0.1µF
R4
100k
R3 10.0k
C1
0.1µF
C2
10µF
C3
10µF
C6
22µF
C7
22µF
C8
22µF
2
4
6
1
EN
SW
PG
R1
3.74k
PG
5
SS
VFB
GND
C4
8200pF
R2
10.0k
Copyright © 2016, Texas Instruments Incorporated
图 17. TPS562219A 1.05V/2A Reference Design
8.2.1.1 Design Requirements
For this design example, use the parameters shown in 表 1.
表 1. Design Parameters
PARAMETER
Input voltage range
VALUES
4.5 V to 17 V
1.05 V
Output voltage
Output current
2 A
Output voltage ripple
20 mVpp
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using 公式 2 to calculate VOUT
.
To improve efficiency at light loads consider using larger value resistors, too high of resistance are more
susceptible to noise and voltage errors from the VFB input current are more noticeable.
R1
æ
ö
VOUT = 0.765´ 1+
ç
÷
R2
è
ø
(2)
8.2.1.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
F =
P
2p LOUT ´ COUT
(3)
13
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ZHCSFR7 –NOVEMBER 2016
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of 公式 3
is located below the high frequency zero but close enough that the phase boost provided be the high frequency
zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended
in 表 2.
表 2. TPS562219A Recommended Component Values
L1(uH)
MIN
1.5
C6 + C7 +
C8(µF)
Output Voltage (V)
R2 (kΩ)
R3 (kΩ)
TYP
2.2
MAX
4.7
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
1.5
2.2
2.2
2.2
2.2
3.3
3.3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
1.5
1.5
1.5
2.2
2.2
3.3
6.5
3.3
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using 公式 4, 公式 5 and
公式 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or
heating current rating must be greater than the calculated RMS current.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of 公式 5 and the RMS current
of 公式 6.
V
- VOUT
VOUT
´
IN(MAX)
IlP-P
=
V
LO ´ ƒSW
IN(MAX)
(4)
(5)
IlP-P
IlPEAK = IO +
2
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(6)
For this design example, the calculated peak current is 2.34 A and the calculated RMS current is 2.01 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562219A and
TPS563219A are intended for use with ceramic or other low ESR capacitors. Recommended values range from
20 µF to 68 µF. Use 公式 7 to determine the required RMS current rating for the output capacitor.
VOUT ´ VIN - VOUT
(
12 ´ V ´LO ´ ƒSW
)
ICO(RMS)
=
IN
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286A and each output capacitor is rated for 4A.
8.2.1.2.3 Input Capacitor Selection
The TPS562219A and TPS563219A require an input decoupling capacitor and a bulk capacitor is needed
depending on the application. A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An
additional 0.1 µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage.
14
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8.2.1.2.4 Bootstrap capacitor Selection
A 0.1µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.1.3 Application Curves
The following application curves were generated using the application circuit of 图 17.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0
0
4
0.5
1
1.5
2
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
Output Current (A)
D006
D007
图 18. TPS562219A Efficiency
图 19. TPS562219A Light Load Efficiency
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0.5
1
1.5
2
0
0.5
1
1.5
2
Output Current (A)
Output Current (A)
D008
D009
图 20. TPS562219A Load Regulation, VI = 5 V
图 21. TPS562219A Load Regulation, VI = 12 V
0.5
0.4
0.3
0.2
0.1
0
IO = 2 A
VI = 50 mV / div (ac coupled)
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
6
8
10
12
14
16
18
Time = 1 µsec / div
图 23. TPS562219A Input Voltage Ripple
Input Voltage (V)
D010
图 22. TPS562219A Line Regulation
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www.ti.com.cn
IO = 2 A
VO = 20 mV / div (ac coupled)
VO = 50 mV / div (ac coupled)
IO = 500 mA / div
SW = 5 V / div
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
Time = 200 µsec / div
Time = 1 µsec / div
图 25. TPS562219A Transient Response
图 24. TPS562219A Output Voltage Ripple
VI = 10V/ div
EN = 10V/ div
SS = 5V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 1 msec / div
Time = 1 msec / div
图 26. TPS562219A Start Up Relative To VI
VI = 10V/ div
图 27. TPS562219A Start Up Relative To EN
EN = 10V/ div
SS = 5V/ div
SS = 5V/ div
VO = 500mV/ div
VO = 500mV/ div
PG = 1V/ div
PG = 1V/ div
Time = 5 msec / div
Time = 5 msec / div
图 28. TPS562219A Shut Down Relative To VI
图 29. TPS562219A Shut Down Relative To EN
16
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TPS562219A, TPS563219A
www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
8.2.2 Typical Application, TPS563219A
U1
TPS563219A
L1 1.5 µH
VIN = 4.5 - 17 V
C5
VOUT = 1.05 V, 3 A
VOUT
3
7
8
VIN
VIN
EN
VBST
R3
10.0 kΩ
0.1 µF
C3
C1
C2
R4
100 kΩ
C6
C7
C8
2
4
6
1
SW
PG
EN
0.1 µF
10 µF
10 µF
22 µF
22 µF
22 µF
R1
3.74 kΩ
PG
5
SS
VFB
GND
C4
8200 pF
R2
10.0 kΩ
Copyright © 2016, Texas Instruments Incorporated
图 30. TPS563219A 1.05V/3A Reference Design
8.2.2.1 Design Requirements
For this design example, use the parameters shown in 表 3.
表 3. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
4.5 V to 17V
1.05V
Output current
3A
Output voltage ripple
20mVpp
8.2.2.2 Detailed Design Procedures
The detailed design procedure for TPS563219A is the same as for TPS562200 except for inductor selection.
8.2.2.2.1 Output Filter Selection
表 4. TPS563219A Recommended Component Values
L1 (µH)
MIN
1.0
C6 + C7 + C8
(µF)
Output Voltage (V)
R2 (kΩ)
R3 (kΩ)
TYP
1.5
MAX
4.7
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
20 - 68
1.0
1.5
1.5
1.5
2.2
2.2
2.2
3.3
3.3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
1.0
1.0
1.5
1.5
1.5
2.2
6.5
2.2
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using 公式 8, 公式 9 and
公式 10. The inductor saturation current rating must be greater than the calculated peak current and the RMS or
heating current rating must be greater than the calculated RMS current. Use 650 kHz for ƒSW
.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of 公式 9 and the RMS current
of 公式 10.
V
- VOUT
VOUT
´
IN(MAX)
IlP-P
=
V
LO ´ ƒSW
IN(MAX)
(8)
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ZHCSFR7 –NOVEMBER 2016
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IlP-P
IlPEAK = IO +
2
(9)
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(10)
For this design example, the calculated peak current is 3.505 A and the calculated RMS current is 3.014 A. The
inductor used is a TDK CLF7045T-1R5N with a peak current rating of 7.3-A and an RMS current rating of 4.9-A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563209 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 μF to 68 μF. Use 公式 6 to
determine the required RMS current rating for the output capacitor. For this design, three TDK
C3216X5R0J226M 22 μF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS
current is 0.292 A and each output capacitor is rated for 4 A.
8.2.2.3 Application Curves
The following application curves were generated using the application circuit of 图 30.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0
0.5
1
1.5
2
2.5
3
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3 45
Output Current (A)
D001
D002
图 31. TPS563219A Efficiency
图 32. TPS563219A Light Load Efficiency
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
D004
D003
图 34. TPS563219A Load Regulation, VI = 12 V
图 33. TPS563219A Load Regulation, VI = 5 V
18
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ZHCSFR7 –NOVEMBER 2016
0.5
0.4
0.3
0.2
0.1
0
IO = 3 A
VI = 50 mV / div (ac coupled)
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10
12
14
16
18
Time = 1 µsec / div
Input Voltage (V)
D005
图 36. TPS563219A Input Voltage Ripple
图 35. TPS563219A Line Regulation
IO = 3 A
VO = 20 mV / div (ac coupled)
VO = 50 mV / div (ac coupled)
SW = 5 V / div
IO = 1 A / div
Load step = 0.75 A - 2.25 A
Slew rate = 500 mA / µsec
Time = 200 µsec / div
Time = 1 µsec / div
图 37. TPS563219A Output Voltage Ripple
图 38. TPS563219A Transient Response
VI = 10V/ div
EN = 10V/ div
SS = 5V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 1 msec / div
图 39. TPS563219A Start Up Relative To VI
Time = 1 msec / div
图 40. TPS563219A Start Up Relative To EN
版权 © 2016, Texas Instruments Incorporated
19
TPS562219A, TPS563219A
ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
VI = 10V/ div
SS = 5V/ div
EN = 10V/ div
SS = 5V/ div
VO = 500mV/ div
VO = 500mV/ div
PG = 1V/ div
PG = 1V/ div
Time = 5 msec / div
图 41. TPS563219A Shut Down Relative To VI
Time = 5 msec / div
图 42. TPS563219A Shut Down Relative To EN
20
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TPS562219A, TPS563219A
www.ti.com.cn
ZHCSFR7 –NOVEMBER 2016
9 Power Supply Recommendations
The TPS562209 and TPS563209 are designed to operate from input supply voltage in the range of 4.5V to 17V.
Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO / 0.65.
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
GND
VOUT
Additional
Vias to the
GND plane
OUTPUT
CAPACITOR
Vias to the
internal SW
node copper
BOOST
CAPACITOR
OUTPUT
INDUCTOR
FEEDBACK
RESISTORS
GND
SW
VIN
SS
VBST
EN
TO ENABLE
CONTROL
TPS56x219A
VFB
PG
VIN
Vias to the
internal SW
node copper
HIGH FREQUENCY
INPUT BYPASS
CAPACITOR
POWER GOOD
SW node copper
pour area on internal
or bottom layer
INPUT BYPASS
CAPACITOR
PG PULL UP
RESISTOR
SLOW START
CAPACITOR
VIA TO INTERNAL
GROUND PLANE
TO PG PULL
UP VOLTAGE
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ZHCSFR7 –NOVEMBER 2016
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.2 文档支持
11.3 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持和社区资源、工具和软件，以及样片或购买的快速访
问。
表 5. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS562219A
TPS563219A
11.4 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 商标
D-CAP2, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS562219ADDFR
TPS562219ADDFT
TPS563219ADDFR
TPS563219ADDFT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDF
DDF
DDF
DDF
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2219A
SN
SN
SN
2219A
3219A
3219A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Addendum-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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