TPS563212DRLR [TI]
具有 Eco-Mode 和可选 FCCM 的 4.2V 至 18V、3A、1.2MHz 同步降压转换器 | DRL | 8 | -40 to 150;
| 型号： | TPS563212DRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 Eco-Mode 和可选 FCCM 的 4.2V 至 18V、3A、1.2MHz 同步降压转换器 | DRL | 8 | -40 to 150 转换器 |
| 文件： | 总33页 (文件大小：3476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS563212
ZHCSNA2 –OCTOBER 2021
TPS563212 采用SOT-5X3 封装的4.2V 至18V 输入、3A 同步
降压转换器
1 特性
3 说明
• 4.2V 至18V 输入电压
• 0.6V 至7V 输出电压
TPS563212 是一款具有成本效益且高度灵活的同步降
压转化器，可在可选的 Eco-mode 或强制连续导通模
式 (FCCM) 下工作。另外还可以通过 MODE 引脚配置
可选的电源正常状态指示器或外部软启动。通过正确配
置使能引脚、电源正常状态指示器或外部软启动可以实
现电源时序控制。4.2V 至 18V 的宽输入电压范围支持
12V 和 15V 等各种常见的输入电压轨。该器件的输出
电压为0.6V 至7V，支持高达3A 的持续输出电流。
– 高达3A 的持续输出电流
– 最短打开时间：45ns
– 98% 最大占空比
• 高效率
– 集成式66mΩ和33mΩMOSFET
– 120µA 静态电流（典型值）
• 高度灵活且易于使用
该器件采用高级仿真电流模式 (AECM) 控制拓扑，能
够提供快速瞬态响应和真正的固定开关频率。借助内部
智能环路带宽控制，该器件无需外部补偿，即可在宽输
出电压范围内实现快速瞬态响应。
– 可选Eco-mode 或FCCM 操作
– 可选的电源正常状态指示器或外部软启动
– 精密使能输入
• 高精度
高侧峰值电流的逐周期电流限制可在过载情况下保护器
件，并通过低侧谷值电流限制防止电流失控，增强限制
效果。在过压保护 (OVP)、欠压保护 (UVP)、UVLO
保护和热关断保护情况下将触发断续模式。
– ±1% (25°C) 基准电压精度
– ±8.5% 开关频率容差
• 小解决方案尺寸
– 内置补偿功能，便于使用
– SOT-5X3 封装
– 最小外部元件数量
该器件采用1.6mm x 2.1mm SOT-5X3 封装。
器件信息
封装(1)
• 用于高侧和低侧MOSFET 的逐周期电流限制
• 非锁存OVP、UVP、UVLO 和TSD 保护
• 使用TPS563212 并借助WEBENCH® Power
Designer 创建定制设计方案
器件型号
封装尺寸（标称值）
TPS563212
SOT-5X3 (8)
1.6 mm × 2.1 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 机顶盒(STB)、数字电视
• 智能扬声器
• 有线网络、宽带
• 监控
VIN
VIN
BOOT
TPS563212
C2
C1
L
VOUT
SW
PG/SS
FB
MODE
R1
R2
R3
EN
EN
C3
GND
简化版原理图
效率与输出电流间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEH9
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................25
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 接收文档更新通知................................................... 27
11.3 支持资源..................................................................27
11.4 Trademarks............................................................. 27
11.5 Electrostatic Discharge Caution..............................27
11.6 术语表..................................................................... 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................15
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
October 2021
*
Advance Information
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
5 Pin Configuration and Functions
PG/SS
VIN
1
2
3
4
8
7
6
5
FB
MODE
EN
SW
GND
BOOT
8-Pin SOT-5X3 DRL Package (Top View)
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
This pin can be selected as a power-good function or soft-start function depending on device
MODE pin configuration.
•
•
If the power-good function is selected, this is an open-drain power-good indicator.
If the soft-start function is selected, an external capacitor connected from this pin to GND
defines the rise time for the internal reference voltage.
PG/SS
1
I/O
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors
between VIN and GND.
VIN
2
SW
3
4
P
Switch node terminal. Connect the output inductor to this pin.
GND terminal for the controller circuit and the internal circuitry
GND
G
Supply input for the high-side MOSFET gate drive circuit. Connect a 0.1-µF capacitor between
the BOOT and SW pins.
BOOT
EN
5
6
P
Enable input control. Driving EN high or leaving this pin floating enables the converter. An
external resistor divider can be used to imply an adjustable VIN UVLO function.
I/O
Device operation mode in light load (Eco-mode operation or FCCM operation) and pin 1 function
(PG/SS) selection pin. Connect a resistor from MODE to GND to configure the device according
to 表7-1.
MODE
FB
7
8
I/O
I
Converter feedback input. Connect this pin to the output voltage with a feedback resistor divider.
(1) I = Input, I/O = Input or Output, G = Ground, P = Power
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)(1)
MIN
MAX UNIT
VIN
20
20
22
–0.3
–0.3
–3
SW, DC
SW, transient < 10 ns
VIN –SW, DC
20
V
22
–0.3
–3
Pin voltage(2)
VIN –SW, transient < 10 ns
BOOT
25
6
–0.3
–0.3
–0.3
–40
–65
BOOT –SW
EN, FB, PG/SS, MODE
Operating junction temperature(3)
Storage temperature
6
TJ
150
150
°C
°C
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal.
(3) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/
ESDA/JEDEC JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)(1)
MIN
MAX UNIT
VIN
Input supply voltage range
Output voltage range
4.2
0.6
18
7
V
V
VOUT
SW, DC
18
–0.1
–3
SW, transient < 10 ns
VIN - SW, DC
20
18
–0.1
–3
Pin voltage
VIN - SW, transient < 10 ns
BOOT
20
V
23.5
5.5
5.5
3
–0.1
–0.1
–0.1
0
BOOT - SW
EN, FB, PG/SS, MODE
IOUT
TJ
Output current range
A
Operating junction temperature
125
°C
–40
(1) Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific
performance limits. For specified specifications, see the Electrical Characteristics.
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
6.4 Thermal Information
TPS563212
THERMAL METRIC(1)
DRL (SOT-5X3)
UNIT
8 PINS
116.7
41.7
20.9
1.0
(2)
RθJA
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-ambient thermal resistance on TPS563212EVM
ΨJT
20.8
70
ΨJB
(3)
RθJA(EVM)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953
(2) The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These
values were simulated on a standard JEDEC board. They do not represent the performance obtained in an actual application.
(3) The real RθJA on the TPS563212EVM is about 70℃/W, test condition: VIN = 12 V, VOUT = 5 V, IOUT = 3 A, TA = 25℃.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4.2 V to 18 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VIN
Operation input voltage
4.2
18
V
VIN quiescent current at power save
mode
Nonswitching, VEN = 1.2 V, VFB = 0.65 V,
IOUT = 0 mA
120
µA
IQ(VIN)
Nonswitching, VEN = 1.2 V, VFB = 0.65 V,
IOUT = 0 mA
VIN quiescent current at FCCM
VIN shutdown supply current
450
3
µA
µA
ISD(VIN)
UVLO
VIN = 12 V, VEN = 0 V
10
VUVLO(R)
VUVLO(F)
ENABLE
VEN(R)
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN rising
VIN falling
3.8
3.4
4
4.2
3.8
V
V
3.6
EN voltage rising threshold
EN voltage falling threshold
EN rising, enable switching
EN falling, disable switching
1.05
0.91
1.15
1.01
1.25
1.10
V
V
VEN(F)
EN pin sourcing current pre-EN rising
threshold
IEN(P1)
IEN(H)
VEN = 1.0 V
0.93
2.4
1.2
3.1
1.5
µA
µA
EN pin sourcing current hysteresis
3.81
REFERENCE VOLTAGE
TJ = 25°C
0.594
0.591
–0.1
0.6
0.6
0
0.606
0.609
0.1
V
V
VFB
FB voltage
TJ = –40°C to 125°C, VIN = 12 V
VFB = 0.65 V, TJ = 25°C
IFB(LKG)
START-UP
ISS
FB input leakage current
µA
Soft-start charge current
VSS = 0 V
4.5
1.5
6.6
2
8.3
2.6
µA
ms
From first switching pulse until target
VOUT
tSS
Internal fixed soft-start time
SWITCHING FREQUENCY
fSW(FCCM)
Switching frequency, FCCM operation
1100
1200
66
1300
kHz
POWER STAGE
RDSON(HS)
High-side MOSFET on-resistance
TJ = 25°C, VIN = 12 V, VBOOT-SW = 5 V
mΩ
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
6.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4.2 V to 18 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RDSON(LS)
Low-side MOSFET on-resistance
Minimum ON pulse width
Maximum ON pulse width
Minimum OFF pulse width
TJ = 25°C, VIN = 12 V
33
mΩ
ns
(1)
tON(min)
45
tON(max)
tOFF(min)
6
µs
105
ns
OVERCURRENT PROTECTION
IHS(OC) High-side peak current limit
Peak current limit on HS MOSFET
4.25
3.0
5
4
5.75
4.9
A
A
Valley current limit on LS MOSFET, VIN
12 V
=
ILS(OC)
Low-side valley current limit
Sinking current limit on LS MOSFET, VIN
= 12 V
ILS(NOC)
Low-side negative current limit for FCCM
1.1
1.5
2.2
A
tHIC(WAIT)
tHIC(RE)
Wait time before entering Hiccup
Hiccup time before re-start
108
6
µs
Cycles
OUTPUT OVP AND UVP
VFB falling
62.5%
5%
Undervoltage-protection (UVP) threshold
voltage
VUVP
UVP hysteresis
VFB rising
107%
112%
5%
114%
Overvoltage-protection (OVP) threshold
voltage
VOVP
OVP hysteresis
POWER GOOD
FB falling, PG from high to low
FB rising, PG from low to high
FB falling, PG from low to high
FB rising, PG from high to low
IPG = 0.6 mA
82%
87%
87%
92%
92%
97%
112%
114%
0.3
VPGTH
Power-good threshold
101%
107%
107%
112%
VPG(OL)
IPG(LKG)
PG pin output low-level voltage
V
PG pin leakage current when open drain
output is high
VPG = 5.5 V
1
µA
–1
tPG(R)
tPG(F)
PG delay going from low to high
PG delay going from high to low
Minimum VIN for valid output(1)
112
48
2
µs
µs
V
2.5
VPG/SS < 0.5 V at 100 μA
THERMAL SHUTDOWN
(1)
TJ(SD)
Thermal shutdown threshold
Thermal shutdown hysteresis
150
20
°C
°C
(1)
TJ(HYS)
(1) Not production tested
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
6.6 Typical Characteristics
VIN = 12 V, TA = 25°C, unless otherwise noted
132
130
128
126
124
122
120
118
116
114
500
490
480
470
460
450
440
430
420
410
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
图6-1. Quiescent Current (Eco-mode) vs Junction Temperature
图6-2. Quiescent Current (FCCM) vs Junction Temperature
5
0.606
4.5
4
0.604
0.602
0.6
3.5
3
0.598
0.596
0.594
2.5
2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
图6-3. Shutdown Current vs Junction Temperature
图6-4. Reference Voltage vs Junction Temperature
95
90
85
80
75
70
65
60
55
50
46
44
42
40
38
36
34
32
30
28
26
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
图6-5. High-Side MOSFET On-Resistance vs Junction
图6-6. Low-Side MOSFET On-Resistance vs Junction
Temperature
Temperature
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
6.6 Typical Characteristics (continued)
VIN = 12 V, TA = 25°C, unless otherwise noted
4.4
1.28
1.2
L--> H
H--> L
L ç H
H ç L
4.2
4
1.12
1.04
0.96
0.88
3.8
3.6
3.4
3.2
-40
-20
0
20
40
60
80
100 120 140
-60
-30
0
30
60
90
120
150
TJ - Junction Temperature (°C)
TJ - Junction Temperature (èC)
图6-8. EN Threshold vs Junction Temperature
图6-7. VIN UVLO Threshold vs Junction Temperature
5.2
4.4
5.15
5.1
5.05
5
4.2
4
3.8
3.6
3.4
3.2
4.95
4.9
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
图6-9. High-Side Current Limit Threshold vs Junction
图6-10. Low-Side Current Limit Threshold vs Junction
Temperature
Temperature
1220
1210
1200
1190
1180
1170
1160
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (°C)
图6-12. Switching Frequency vs Output Current, VOUT = 3.3 V, L
= 2.2 µH
图6-11. Switching Frequency vs Junction Temperature
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
6.6 Typical Characteristics (continued)
VIN = 12 V, TA = 25°C, unless otherwise noted
图6-13. VOUT = 1.05-V Efficiency, L = 0.68 µH
图6-14. VOUT = 3.3-V Efficiency, L = 2.2 µH
图6-15. VOUT = 5-V Efficiency, L = 3.3 µH
图6-16. VOUT = 7-V Efficiency, L = 3.3 µH
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
7 Detailed Description
7.1 Overview
The device is a 3-A synchronous buck converter that operates from 4.2-V to 18-V input voltage and 0.6-V to 7-V
output voltage. The device employs AECM control, an emulated current control topology that combines the
advantages of peak current mode control and D-CAP2 control, providing fast transient response with true fixed
switching frequency.
With the proper MODE configurations, the device supports selectable Eco-mode operation or FCCM operation
and a selectable power-good indicator or external soft start.
With an on-time extension function, the device supports a maximum duty cycle of 98%.
7.2 Functional Block Diagram
VIN
EN
Bias & Voltage
Reference
Bootstrap
Regulator
VCC Regulator
UVLO
VUVP
+
-
BOOT
UVP
+
VOVP
-
OVP
Ripple Injection Generator
SW
R3
R1
R2
SW
Mode
Detection
Eco-mode or FCCM
Crj
VCC
Control Logic
Vripple
PFM
Ton
Timer
-
-
Vfb
Vref_int
FB
+
+
-
PWM
+
Vslp
R
Q
S
GND
gm
+
+
Comparator
Error Amp
Oscillator &
Slope Comp
Generator
HS & LS
Current Sense
Vref
Soft-Start
PG/SS
+
-
FB
VPGTH
TSD
PG or SS ?
Mode Selection
& PG or SS
Selection
Eco-mode or FCCM
MODE
7.3 Feature Description
7.3.1 Advanced Emulated Current Mode Control
The device employs AECM control, an emulated current control-based topology that combines the advantages
of peak current mode control and D-CAP2 control, providing fast transient response with true fixed switching
frequency. The AECM control topology supports two basic regulation modes: PFM regulation mode and PWM
regulation mode. During PWM, the device operates at its nominal switching frequency in CCM or DCM. The
frequency is typically approximately 1.2 MHz with a controlled frequency variation. If the load current decreases,
the device enters PFM to sustain high efficiency down to very light loads. In PFM, the switching frequency
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
decreases with the load current. With the internal adaptive loop adjustment, the device eliminates the need for
external compensation to provide a fast transient response over a wide output voltage range.
7.3.2 Mode Selection and PG/SS Pin Function Configuration
The device requires a mode resistor to select the operations mode under light load and configure the function of
pin 1. 表7-1 shows the MODE pin settings.
表7-1. MODE Pin Settings
RECOMMENDED
MODE RESISTOR
VALUE
MODE RESISTOR
RANGE
OPERATION MODE IN FUNCTION OF PG/SS
LIGHT LOAD
PIN
0
Eco-mode
Eco-mode
FCCM
Power Good
Soft Start
[0, 12] kΩ
[30, 50] kΩ
[83, 120] kΩ
[180, ∞] kΩ
47 kΩ
100 kΩ
Float
Soft Start
FCCM
Power Good
图 7-1 shows the typical start-up sequence of the device once the enable signal triggers the EN turn-on
threshold. After the voltage of VIN crosses the UVLO rising threshold, it takes approximately 110 μs to finish
reading and setting of the MODE pin. After this process, the MODE status is latched and does not change until
VIN or EN toggles to restart this device. Then, the soft-start function begins to ramp up the reference voltage to
the PWM comparator.
EN threshold
1.18V
EN
VIN
UVLO
4V
Mode
detection
VIN
MODE
110µs 100µs
Tss
110µs
VOUT
PGOOD
t
图7-1. Power-Up Sequence
7.3.3 Power Good (PG)
This is an optional function configured by the MODE pin.
The device has a built-in power-good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG/SS pin
works as an open-drain output that requires a pullup resistor (to any voltage below 5.5 V). A pullup resistor of 10
kΩ is recommended to pull the device up to a 5-V voltage. It can sink 0.8 mA of current and maintain its
specified logic low level. Once the FB pin voltage is between 92% and 112% of the internal reference voltage
(VREF) and after a deglitch time of 112 μs, the PG/SS is high impedance. The PG/SS pin is pulled low after a
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
deglitch time of 48 μs when the FB pin voltage is lower than UVP or greater than OVP threshold, or in events of
thermal shutdown, EN shutdown, or UVLO conditions. VIN must remain present for the PG/SS pin to stay low.
If the power-good output is not used when the PG function is selected, tie to GND to get better thermal
performance.
表7-2. Power Good Indicator Logic Table
LOGIC SIGNALS
PG LOGIC
STATUS
VIN
EN
TSD
VOUT
VOUT on target
High
Low
Not triggered
VOUT > Target
High
VIN > UVLO
VOUT < Target
Low
Triggered
Low
✕
✕
✕
✕
Low
✕
Low
✕
✕
✕
2.5 V < VIN < UVLO
VIN < 2.5 V
Low
Undefined
✕
7.3.4 Soft Start and Pre-Biased Soft Start
This is an optional function configured by MODE pin.
If the PG function is selected, the device works with an internal soft-start time of 2 ms. If the SS function is
selected, the device has the adjustable soft-start function. When the EN pin becomes high, the soft-start charge
current, ISS, begins charging the capacitor, which is connected from the PG/SS pin to GND (CSS). Smooth
control of the output voltage is maintained during start-up. Use 方程式1 to calculate the soft-start time.
3.5 × C nF × V
ss REF
V
t
ms =
(1)
ss
I
uA
ss
where
• VREF = 0.6 V
• ISS = 6.6 µA
The value of the external soft-start capacitor must not be lower than 4 nF typical to ensure good start-up
behavior.
If the output capacitor is pre-biased at start-up, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage. This scheme makes sure the converters
ramp up smoothly into the regulation point.
7.3.5 Output Discharge Through PG/SS Pin
If the PG function is selected, the device pulls the PG/SS pin low when the device is shut down by one of the
following:
• EN
• OVP
• UVP
• UVLO
• Thermal shutdown
In those cases, the user can connect PG/SS to VOUT through a resistor to discharge VOUT (see 图 7-2). The
discharge rate can be adjusted by R3, which is also used to pull up the PG/SS pin in normal operation. The
minimum supply voltage required for the discharge function to remain active is typically 2.5 V. For reliability, keep
the maximum current into the PG/SS pin less than 1.8 mA. Given an output voltage, the minimum resistance of
R3 can be calculated in 方程式2.
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
VOUT(V)
1.8
R3_MIN(kW) =
- 0.4
(2)
VIN
VIN
BOOT
TPS563212
C2
C1
L
VOUT
SW
PG/SS
FB
MODE
R1
R2
R3
EN
EN
C3
GND
图7-2. Discharge VOUT Through PG/SS Pin with the TPS563212
7.3.6 Precise Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control for the device. When the EN pin voltage exceeds the threshold
voltage, the device begins operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters shutdown mode.
The EN pin has an internal pullup source current, allowing the user to float the EN pin to enable the device. If an
application requires control of the EN pin, use external control logic interface to the EN pin like the open-drain or
open-collector output logic.
The device implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled
when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a
hysteresis of 400 mV.
If an application requires a higher UVLO threshold on the VIN pin, the EN pin can be configured as shown in 图
7-3. When using the external UVLO function, setting the hysteresis at a value greater than 400 mV is
recommended.
The EN pin has a small pullup current, Ip, which sets the default state of the EN pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the external
UVLO function because it increases by Ih when the EN pin crosses the enable threshold. Use 方程式 3 and 方程
式 4 to calculate the values of R1 and R2 for a specified UVLO threshold. Once R1 and R2 have settled down,
the EN voltage can be calculated by 方程式5, which must be lower than 5.5 V with the maximum VIN.
VIN
Device
R1
R2
Ip
Ih
EN
图7-3. Adjustable VIN Undervoltage Lockout
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
V
EN_FALL
V
∙
− V
START
STOP
V
EN_RISE
R =
(3)
1
V
EN_FALL
I
1 −
+ I
p
h
V
EN_RISE
R
∙ V
1
EN_FALL
R =
(4)
(5)
2
V
− V
+ R ∙ I + I
1 p h
STOP
EN_FALL
R
∙ V + R R
I
+ I
h
2
IN
1 2
+ R
p
V
=
EN
R
1
2
where
• Ip = 1.2 µA
• Ih = 3.1 µA
• VEN_FALL = 1.01 V
• VEN_RISE = 1.15 V
• VSTART = Expected input voltage enabling the device
• VSTOP = Expected input voltage disabling the device
7.3.7 Overcurrent Limit and Undervoltage Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the peak and
valley of the inductor current.
During the on time of the high-side MOSFET switch, the inductor current flows through high-side MOSFET and
increases at a linear rate determined by the following:
• VIN
• VOUT
• On time
• Output inductor value
The high-side switch current is sensed when the high-side MOSFET is turned on after a set of blanking time and
then compared with the high-side MOSFET current limit threshold in every switching cycle. If the cross-limit
event is detected after the minimum on time, the high-side MOSFET is turned off immediately. The high-side
MOSFET current is limited by a clamped maximum peak current threshold IHS_LIMIT, which is constant.
The current going through low-side MOSFET is also sensed and monitored. When the low-side MOSFET is
turned on, the inductor current begins ramping down. The low-side MOSFET is not turned off at the end of a
switching cycle if its current is above the low-side current limit, ILS_LIMIT. The low-side MOSFET is kept on for the
next cycle so that inductor current keeps ramping down, until the inductor current ramps below the low-side
current limit, ILS_LIMIT, and the subsequent switching cycle comes, the low-side MOSFET is turned off, and the
high-side MOSFET is turned on after a dead time.
There are some important considerations for this type of overcurrent protection. The load current is higher than
the overcurrent threshold by one-half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current can be higher than the current available
from the converter. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it.
The device shuts down after the UVP delay time (typically 108 μs) and re-starts after the hiccup time (six times
of soft start time). The hiccup behavior helps reduce the device power dissipation under severe overcurrent
conditions.
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.8 Overvoltage Protection
The device detects overvoltage condition by monitoring the feedback voltage. When the feedback voltage
becomes higher than 112% of the target voltage, the OVP comparator output goes high and both the high-side
MOSFET and low-side MOSFET turn off. This function is a non-latch operation.
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
7.3.9 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
150°C typically. The device re-initiates the power-up sequence when the junction temperature drops below
130°C typically.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical on and off control for the device. When VEN is below 1.01 V (typical), the device is
in shutdown mode with a shutdown current of 3 μA (typical). The device also employs VIN UVLO protection. If
VIN voltage is below their respective UVLO level, the regulator is turned off.
7.4.2 Active Mode
The device is in active mode when VEN is above the precision enable threshold voltage and VIN is above its
respective UVLO level. The simplest way to enable the device is to float the EN pin, which allows self-start–up
when the input voltage is between 4.2 V to 18 V.
Active mode depends on the load current and the configuration of the MODE pin.
When the MODE pin is connected with a 100-kΩresistor (typical) or floated (typical) to GND, FCCM operation is
selected. No matter what the load current is, the device works with PWM regulation with fixed switching
frequency.
When the MODE pin is connected with a 0-Ω resistor (typical) or 47-kΩ resistor (typical) to GND, Eco-mode
operation is selected. The device is in one of the following modes with different loading:
1. Continuous conduction mode (CCM) operation with fixed switching frequency when load current is above
half of the peak-to-peak inductor current ripple. The device works with PWM regulation.
2. Discontinuous conduction mode (DCM) operation with fixed switching frequency. When load current is lower
than half of the peak-to-peak inductor current ripple in CCM operation, the device works with PWM
regulation.
3. During Eco-mode operation with switching frequency decreased at very light load, the device works with
PFM regulation.
7.4.3 FCCM Operation
If FCCM operation is selected by the MODE pin, the device is set to operate in FCCM operation in light-load
conditions and allows the inductor current to become negative. In FCCM, the device switches with a fixed
frequency over the entire load range, which is suitable for applications requiring tight control of the switching
frequency and output voltage ripple.
7.4.4 CCM Operation
CCM operation is employed in the device when the load current is higher than half of the peak-to-peak inductor
current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in this mode,
and the maximum continuous output current of 3 A can be supplied by the device.
7.4.5 DCM Operation and Eco-mode Operation
The light load running includes DCM operation and Eco-mode operation.
As the output current decreases from heavy load condition, the inductor current reduces as well and eventually
comes to a point that its rippled valley touches zero level, which is the boundary between CCM and DCM. The
low-side MOSFET is turned off when the zero inductor current is detected. As the load current further decreases,
the converter runs into DCM.
At even lighter current loads, Eco-mode is activated to maintain high efficiency operation. The on time is kept
almost the same as it was in CCM so that it takes longer time to discharge the output capacitor with smaller load
current to the level of the reference voltage. This makes the switching frequency lower, proportional to the load
current, and keeps the light load efficiency high. The transition point to the light-load operation, IOUT(LL), current
can be calculated in 方程式6.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
0.852
(VIN - VOUT )∂ VOUT
IOUT(LL)
=
∂
2 ∂L1 ∂ fsw
V
IN
(6)
7.4.6 On-Time Extension for Large Duty Cycle Operation
The minimum on time, TON_MIN, is the smallest duration of time that the high-side MOSFET can be on. TON_MIN
is typically 45 ns in the device. The minimum off time, TOFF_MIN, is the smallest duration that the high-side
MOSFET can be off. TOFF_MIN is typically 105 ns in the device. In CCM operation, TON_MIN and TOFF_MIN limit the
voltage conversion range given a fixed switching frequency.
The minimum duty cycle allowed is:
DMIN = TON_MIN ì fSW
(7)
The maximum duty cycle allowed is:
DMAX = 1- TOFF _MIN ì fSW
(8)
In the device, a frequency foldback scheme is employed to extend the maximum duty cycle when TOFF_MIN is
reached. The switching frequency decreases once longer duty cycle is needed under low VIN conditions. With
the duty increased, the on time is extended up to the maximum on time of 6 μs. A wide range of frequency
foldback allows the device output voltage to stay in regulation with a much lower supply voltage VIN. This leads
to a lower effective dropout voltage.
Given an output voltage, the maximum operation supply voltage can be found by:
VOUT
V
=
IN_MAX
fSW ∂ TON_MIN
(9)
At lower supply voltage, the switching frequency decreases once TOFF_MIN is triggered. The minimum VIN without
frequency foldback can be approximated by:
VOUT
V
=
IN_MIN
(1-fSW ∂TOFF _MIN
)
(10)
Taking considerations of power losses in the system with heavy load operation, VIN_MAX is higher than the result
calculated in 方程式9. With frequency foldback, VIN_VIN is lowered by decreased fSW, as shown in 图7-4.
1400
1200
1000
800
600
400
Iout=0.5A
Iout=1.5A
200
Iout=3A
0
4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
Input Voltage (V)
6
6.2 6.4 6.6
图7-4. Frequency Foldback at Dropout (VOUT = 5 V)
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The device is a highly integrated, synchronous buck converter. This device is used to convert a higher DC input
voltage to a lower DC output voltage, with a maximum output current of 3 A. Alternately, the WEBENCH®
software may be used to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
8.2 Typical Application
The application schematic of 图 8-1 was developed to meet the requirements of the device. This circuit is
available as the TPS563212EVM evaluation module. The design procedure is given in this section.
图8-1. TPS563212 3.3-V, 3-A Reference Design
8.2.1 Design Requirements
表8-1 shows the design parameters for this application.
表8-1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
4.2 to 18 V
Output voltage
3.3 V
Output current rating
Transient response, 1.5-A load step
Output ripple voltage
Operating frequency
3 A
ΔVOUT/VOUT ≤±3%
≤10 mV at CCM
1.2 MHz
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS563212 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost.
3. Open the advanced tab to optimize for output voltage ripple.
4. Once in a TPS563212 design, you can enable the second stage L-C filter and change other settings from the
drop-down on the left.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using 1%
tolerance or better divider resistors. Referring to the application schematic of 图 8-1, start with 10 kΩ or 20 kΩ
for R9 and use 方程式 11 to calculate R8. To improve efficiency at light loads, consider using larger value
resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the FB
input current are noticeable.
VOUT - VREF
VREF
R8 =
∂R9
(11)
表8-2 shows the recommended components value for common output voltages.
8.2.2.3 Output Inductor Selection
To calculate the minimum value of the output inductor, use 方程式 12. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by
the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output
capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor
ripple current. In general, the inductor ripple value is at the discretion of the designer. For this part, TI
recommends the range of KIND from 25% to 55%.
V
- VOUT
VOUT
IN_MAX
LMIN
=
∂
V
KIND ∂IOUT ∂ fSW
IN_MAX
(12)
where
• IOUT = 3 A
For this design example, use KIND = 40%. The inductor value is calculated to be 1.87 μH. For this design, a
nearest standard value of 2.2 μH was chosen. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The inductor peak-to-peak ripple current, peak current, and RMS
current are calculated using 方程式13, 方程式14, and 方程式15.
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
V
- VOUT
VOUT
IN_MAX
IRIPPLE
=
∂
V
L1 ∂ fSW
IN_MAX
(13)
(14)
IRIPPLE
ILPEAK = IOUT
+
2
1
2
2
ILRMS
=
IOUT
+
IRIPPLE
12
(15)
For this design example, the calculated peak current is 3.5 A and the calculated RMS current is 3.01 A. The
chosen inductor is a Wurth Elektronik 74439344022 2.2-μH. It has a saturation current rating of 16 A and a
RMS current rating of 8 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
8.2.2.4 Output Capacitor Selection
After selecting the inductor, the output capacitor needs to be optimized. The LC filter used as the output filter has
double pole at:
1
fP =
2p L1 ∂COUT _E
(16)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –
40 dB per decade rate and the phase drops rapidly. A high frequency zero introduced by internal circuit that
reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero
frequency. The inductor and capacitor for the output filter must be selected so that the double pole of fP is
located below the high frequency zero but close enough. The phase boost provided by the high frequency zero
provides adequate phase margin for a stable circuit. To meet this requirement, make the L1 × COUT_E value meet
the range of L1 × COUT_E value recommended in 表8-2.
表8-2. Recommended Component Values
RANGE OF L1 ×
R8(2)
(kΩ)
R9
(kΩ)
(4)
OUTPUT
L1(3)
(µH)
COUT
(µF)
C7(6)
(pF)
(5)
COUT_E
VOLTAGE (V)(1)
(μH × μF)
17–130
17–130
15–160
15–160
15–160
15–160
0.76
1.05
1.8
2.5
3.3
5
5.36
15.0
40.0
31.6
45.3
73.2
20.0
20.0
20.0
10.0
10.0
10.0
0.56
0.68
1.0
2×22
2×22
1×22
1×22
1×22
1×22
—
10–100
10–100
10–100
10–100
10–100
1.5
2.2
3.3
(1) Use the recommended L1 and COUT combination of the higher and closest output rail for the
unlisted output rails.
(2) R8 = 10 kΩand R9 = Float for VOUT = 0.6 V
(3) Inductance values are calculated based on VIN=18 V, but they can also be used for other input
voltages. Users can calculate their preferred inductance value per 方程式12.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
(4) COUT is the sum of nominal output capacitance. 22-μF, 0805, 10-V or higher specifications
capacitors are recommended.
(5) COUT_E is the effective value after derating. The value of L1 × COUT_E is recommended to be within
the range.
(6) R6 and C7 can be used to improve the load transient response and improve the loop-phase margin.
The capacitor value and ESR determine the amount of output voltage ripple. The device is intended for use with
ceramic or other low-ESR capacitors. Use 方程式 17 to determine the required RMS current rating for the output
capacitor.
VOUT ∂(V
- VOUT )
IN_MAX
ICORMS
=
12 ∂ VIN_MAX ∂L1 ∂ fSW
(17)
Two Murata GRM21BR61C226ME44L 22-μF, 0805, 16-V output capacitors are used for this design. From the
data sheet, the estimated DC derating rate is 66.8% at room temperature with an AC voltage of 0.2 V. The total
output effective capacitance is approximately 14.7 μF. The value of L1 × COUT_E is 33 μH × μF, which is within
the recommended range.
8.2.2.5 Input Capacitor Selection
The device requires an input decoupling capacitor. A bulk capacitor is needed depending on the application. TI
recommends a ceramic capacitor over 10 μF for the decoupling capacitor. An additional 0.1-μF capacitor (C3)
from the VIN pin to ground is recommended to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage. The capacitor must also have a ripple current rating
greater than the maximum input current ripple of the device. The input ripple current can be calculated using 方
程式18.
V
IN_MIN - VOUT
VOUT
ICIRMS = IOUT
∂
∂
V
V
IN_MIN
IN_MIN
(18)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at
least a 25-V voltage rating is required to support the maximum input voltage. For this design, one Murata
GRM21BR61E226ME44L (10-μF, 25-V, 0805, X5R) capacitor has been selected. The effective capacitance
under input voltage of 12 V is 0.18 × 22 = 4 μF. The input capacitance value determines the input ripple voltage
of the regulator. The input voltage ripple can be calculated using 方程式 19. Using the design example values,
IOUT_MAX = 3 A, CIN_E = 4 μF, and fSW = 1.2 MHz, yields an input voltage ripple of 187.5 mV and a RMS input
ripple current of 0.7 A.
IOUT _MAX ∂ 0.25
DV
=
+ (IOUT _MAX ∂RESR _MAX )
IN
CIN ∂ fSW
(19)
where
• RESR_MAX = Maximum series resistance of the input capacitor
8.2.2.6 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. TI
recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V or
higher voltage rating.
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
8.2.2.7 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1
is connected between VIN and the EN pin of the TPS563212 and R2 is connected between EN and GND. The
UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply should turn on and start
switching when the input voltage increases above 6.6 V (UVLO start or enable). After the regulator starts
switching, it must continue to do so until the input voltage falls below 5.7 V (UVLO stop or disable). 方程式 3 and
方程式 4 can be used to calculate the values for the upper and lower resistor values. For the specified stop
voltages, the nearest standard resistor value for R1 is 174 kΩand for R2 is 36.5 kΩ.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
8.2.3 Application Curves
VIN = 12 V, L1= 2.2 μH, COUT = 22 μF, TA = 25°C (unless otherwise noted)
图8-3. Load Regulation
图8-2. Efficiency
3.4
3.368
3.336
3.304
3.272
3.24
150
130
110
90
Iout=0.03A
Iout=3A
70
50
Vin=6.5V
Vin=12V
Vin=18V
30
10
4
6
8
10
12
14
16
18
0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
Input Voltage (V)
Output Current (A)
图8-4. Line Regulation
图8-5. Case Temperature Rise vs Load Current
图8-6. Steady State Waveforms, IOUT = 0 A
图8-7. Steady State Waveforms, IOUT = 0.1 A
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
图8-8. Steady State Waveforms, IOUT = 1.0 A
图8-9. Steady State Waveforms, IOUT = 3 A
图8-10. Transient Response 0.3 to 2.7 A with Slew
Rate of 2.5 A/μs
图8-11. Transient Response 0.5 to 2 A with Slew
Rate of 2.5 A/μs
图8-12. Transient Response 1 to 2 A with Slew
Rate of 2.5 A/μs
图8-13. Transient Response 1.5 to 3 A with Slew
Rate of 2.5 A/μs
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
图8-14. Start-Up Relative to VIN
图8-15. Shutdown Relative to VIN
图8-16. Enable Relative to EN
图8-17. Disable Relative to EN (ECO)
图8-18. Output Short Protection (ECO)
图8-19. Output Short Recovery (ECO)
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.2 V and 18 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the device or converter,
additional bulk capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 47 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the FB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
图10-1. Top Layout Example
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
图10-2. Bottom Layout Example
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS563212 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost.
3. Open the advanced tab to optimize for output voltage ripple.
4. Once in a TPS563212 design, you can enable the second stage L-C filter and change other settings from the
drop-down on the left.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® are registered trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPS563212
TPS563212
ZHCSNA2 –OCTOBER 2021
www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TPS563212
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS563212DRLR
ACTIVE
SOT-5X3
DRL
8
4000 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 150
3212
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS563219DDFT
17 V Input, 3A Synchronous Step-Down Regulator in SOT-23 with Power-good and Soft-start 8-SOT-23-THIN -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明