TPS563240DDCT [TI]
17V、3A、1.4MHz 同步降压稳压器 | DDC | 6 | -40 to 125;
| 型号： | TPS563240DDCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 17V、3A、1.4MHz 同步降压稳压器 | DDC | 6 | -40 to 125 开关 光电二极管 输出元件 稳压器 |
| 文件： | 总26页 (文件大小：1224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS563240
ZHCSJ66 –DECEMBER 2018
TPS563240 17V、3A、1.4MHz 同步降压稳压器
1 特性
3 说明
1
•
集成 70mΩ 和 30mΩ FET 且支持 3.5A 瞬态电流的
TPS563240 是一款采用 SOT-23 封装的简单易用型
3A 转换器
3A 同步降压稳压器。峰值瞬态输出电流可达 3.5A。
•
•
•
•
D-CAP3™模式控制，用于快速瞬态响应
输入电压范围：4.5V 至 17V
输出电压范围：0.6V 至 7V
这些器件经过优化，最大限度减少了运行所需的外部组
件数量并且可以实现低待机电流。
此开关稳压器采用 D-CAP3 模式控制，能够提供快速
瞬态响应，并且在无需外部补偿组件的情况下支持诸如
专用聚合物等低等效串联电阻 (ESR) 输出电容以及超
低 ESR 陶瓷电容器。
脉冲跳跃模式，采用 无声 ™(OOA) 模式运行，轻
负载运行时 Fs 在 25kHz 以上
•
•
•
•
•
•
•
•
1.4MHz 开关频率
低关断电流（低于 10µA）
1% 反馈电压精度 (25°C)
从预偏置输出电压中启动
逐周期过流限制
TPS563240 在脉冲跳跃模式下运行，从而在轻载运行
期间保持高效率。通过采用 无声 ™(OOA) 模式运
行，TPS563240 在轻负载条件下可将 Fsw 保持在
25kHz 以上。TPS563240 采用 6 引脚 1.6mm ×
2.9mm SOT (DDC) 封装，额定结温范围为 –40°C 至
125°C。
断续模式过流保护
非锁存欠压保护 (UVP) 和热关断 (TSD) 保护
固定软启动时间：1.7ms
器件信息(1)
2 应用
•
•
•
•
•
电视、机顶盒
器件号
TPS563240
封装
DDC (6)
封装尺寸（标称值）
1.60mm x 2.90mm
宽带调制解调器
接入点网络
无线路由器
安全监控
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
空白
空白
简化电路原理图
TPS563240 效率
Efficiency at 12V input
TPS563240
100%
1
2
3
6
5
4
VBST
EN
GND
SW
90%
80%
70%
60%
EN
VOUT
COUT
VIN
VIN
VOUT
VFB
CIN
Vout = 0.9V
Vout = 1.05V
50%
Vout = 1.2V
Vout = 1.5V
Vout = 1.8V
Vout = 2.5V
40%
30%
Vout = 3.3V
Vout = 5V
20%
10%
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
D001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSE74
TPS563240
ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 接收文档更新通知 ................................................. 20
11.2 社区资源................................................................ 20
11.3 商标....................................................................... 20
11.4 静电放电警告......................................................... 20
11.5 术语表 ................................................................... 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
日期
修订版本
说明
2018 年 12 月
*
初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
2
3
6
5
4
VBST
EN
SW
VIN
VFB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive VFB to this GND at a single point.
GND
1
—
SW
VIN
VFB
EN
2
3
4
5
O
I
Switch node connection between high-side NFET and low-side NFET.
Input voltage supply pin. The drain terminal of high-side power NFET.
Converter feedback input. Connect to output voltage with feedback resistor divider.
Enable input control. Active high and must be pulled up to enable the device.
I
I
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST and SW pins.
VBST
6
O
Copyright © 2018, Texas Instruments Incorporated
3
TPS563240
ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
19
UNIT
V
VIN
VBST
24.5
26.5
5.5
V
VBST (10 ns transient)
V
VBST (vs SW)
V
Input voltage
VFB
5.5
V
SW
SW (10 ns transient)
19
V
–3.5
-0.3
–40
–55
21
V
EN
VIN + 0.3
150
V
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
17
UNIT
V
VIN
EN
TJ
Supply input voltage range
EN Input voltage range
–0.1
–40
VIN
V
Operating junction temperature
125
°C
6.4 Thermal Information
TPS563240
DDC (SOT)
6 PINS
117.1
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
57.3
31.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
11.2
ψJB
31.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
Operating – non-switching
supply current
IVIN
VIN current, EN = 5 V, VFB = 0.7 V, TJ = 25°C
VIN current, EN = 0 V, TJ = 25°C
235
2.5
300
10
µA
µA
IVIN(SDN)
Shutdown supply current
LOGIC THRESHOLD
VENH
VENL
REN
Enable threshold
Rising
1.27
1.15
1000
1.34
V
V
Enable threshold
Falling
1.08
800
EN pin resistance to GND
VEN = 1 V
1200
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
Continuous mode operation, TJ = 25°C
Continuous mode operation
VFB = 0.7 V
594
588
600
600
0
606
612
±50
mV
mV
nA
VFB
FB voltage
IFB
FB input current
MOSFET
RDS(on)h
RDS(on)l
High-side switch resistance
Low-side switch resistance
TJ = 25°C
TJ = 25°C
70
30
mΩ
mΩ
CURRENT LIMIT
High side FET source
Current limit
Iocl_h_source
Iocl_l_source
Iocl_l_sink
5.5
3.1
6.3
3.9
0
7.1
4.7
A
A
A
Low side FET source
Current limit
Low side FET sink Current
limit
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
160
25
Thermal shutdown
TSDN
°C
threshold(1)
ON-TIME TIMER CONTROL
tON(MIN)
Minimum on time(1)
VIN = 12 V, load = 3 A
Internal soft-start time
50
ns
ns
tOFF(MIN)
SOFT START
tss
Minimum off time
250
Soft-start time
1.7
ms
FREQUENCY
Fsw
Switching frequency
1400
kHz
OUTPUT UNDERVOLTAGE PROTECTION
VUVP
Output UVP threshold
UVP propagation delay
Hiccup detect (H > L)
65%
0.36
tUVPDLY
ms
ms
UVP protection Hiccup Time
before restart
tHIC
25
UVLO
Wake up VIN voltage
Shutdown VIN voltage
Hysteresis VIN voltage
4.2
3.8
0.4
4.4
UVLO
UVLO threshold
3.6
V
(1) Not production tested.
版权 © 2018, Texas Instruments Incorporated
5
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ZHCSJ66 –DECEMBER 2018
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6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
2.96
2.94
2.92
2.9
252
248
244
240
236
232
228
224
220
2.88
2.86
2.84
2.82
2.8
2.78
2.76
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (°C)
Junction Temperature (°C)
D001
D001
图 1. Shutdown Current vs Junction Temperature
图 2. Supply Current vs Junction Temperature
610
608
606
604
602
600
598
596
594
592
590
1.3
1.29
1.28
1.27
1.26
1.25
1.24
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (°C)
Junction Temperature (°C)
D001
D001
图 3. VFB Voltage vs Junction Temperature
图 4. EN Rising threshold vs Junction Temperature
110
100
90
1.18
1.17
1.16
1.15
1.14
1.13
1.12
1.11
1.1
80
70
60
50
40
30
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (°C)
Junction Temperature (°C)
D001
D001
图 5. EN Falling threshold vs Junction Temperature
图 6. High-Side Rds-On vs Junction Temperature
6
版权 © 2018, Texas Instruments Incorporated
TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
Typical Characteristics (接下页)
VIN = 12 V (unless otherwise noted)
60
3.4
3.3
3.2
3.1
3
50
40
30
20
10
2.9
2.8
2.7
2.6
Iout = 3A
Iout = 1.5A
-40
-20
0
20
40
60
80
100 120 140
5
5.2
5.4
5.6
5.8
6
6.2
Junction Temperature (°C)
Input Voltage (V)
D001
D001
图 7. Low-Side Rds-On vs Junction Temperature
图 8. Dropout for 3.3 V Output Voltage
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
5.2
5
4.8
4.6
4.4
4.2
4
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
Iout = 3A
Iout = 1.5A
7
7.5
8
8.5
9
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
Input Voltage (V)
D001
D001
0.9 V Efficiency
L = 0.56 μH
(Wurth:7443835600
56)
图 9. Dropout for 5 V Output Voltage
图 10. Efficiency vs Output Current, VOUT = 0.9 V
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
D001
D001
1.05 V Efficiency
L = 0.56 μH
(Wurth:7443835600
56)
1.2 V Efficiency
L = 0.68 μH
(Wurth:7443835600
68)
图 11. Efficiency vs Output Current, VOUT = 1.05 V
图 12. Efficiency vs Output Current, VOUT = 1.2 V
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ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
VIN = 12 V (unless otherwise noted)
90%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
D001
D001
1.5 V Efficiency
L = 0.68 μH
(Wurth:7443835600
68)
1.8 V Efficiency
L = 1 μH
(Wurth:744311100)
图 14. Efficiency vs Output Current, VOUT = 1.8 V
图 13. Efficiency vs Output Current, VOUT = 1.5 V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
Vin = 6.5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
D001
D001
2.5 V Efficiency
L = 1 μH
(Wurth:744311100)
3.3 V Efficiency
L = 1.5 μH
(Wurth:744311150)
图 15. Efficiency vs Output Current, VOUT = 2.5 V
图 16. Efficiency vs Output Current, VOUT = 3.3 V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
D001
5 V Efficiency
L = 1.5 μH
图 17. Efficiency vs Output Current, VOUT = 5 V
(Wurth:744311150)
8
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TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
7 Detailed Description
7.1 Overview
The TPS563240 is a 3-A synchronous step-down converter. The proprietary D-CAP3 mode control supports low
ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex
external compensation circuits. The fast transient response of D-CAP3 mode control can reduce the output
capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
3
VIN
VUVP
+
UVP
Hiccup
VREG5
Control Logic
Regulator
UVLO
4
FB
BST
SW
6
2
PWM
Voltage
Reference
+
+
+
+
SS
Soft Start
HS
Ripple Injection
One-Shot
TSD
XCON
VREG5
LS
On-time
Reduction
OCL
threshold
OCL
+
1
GND
+
ZC
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS563240 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP3 mode control.
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ZHCSJ66 –DECEMBER 2018
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Feature Description (接下页)
7.3.2 Pulse Skip Control
The TPS563240 is designed with advanced Eco-mode to maintain high light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The transition point to the light load
operation IOUT(LL) current can be calculated in 公式 1.
(V - VOUT ) ì VOUT
1
IN
IOUT(LL)
=
ì
2 ì L ì fSW
V
IN
(1)
7.3.3 Out-of-Audio™ (OOA) Operation
As the load current continues to decrease, the switching frequency can decrease into the acoustic audible
frequency range. To prevent this from happening, Out-of-Audio™ (OOA) operation under light-load condition is
implemented. The OOA control circuit monitors the states of both the high-side and low-side FETs. When both
high-side and low-side FETs are off for a period longer than 30 μs, the on time generated by one shot timer is
decreased by a little step, thus the off time of both FETs will be reduced to a length lower than 30us. If the load
current decreases further, and cause the off time of both FETs longer than 30us again, the above described on
time reduction process will repeat. By this means, the switching frequency is maintained higher than ~33kHz as
load decrease. When the on time reduces to ~30% of that in CCM operation, the on time will keep at this
minimum length. If load current decreases further, the switching frequency can't be maintained at ~33kHz
anymore, instead, it will decrease linearly towards zero.
When the load current increases from zero, the on time is kept at minimum length, which is~30% of that in CCM
operation, and the switching frequency increases linearly as load increases. When the off time of both FETs
decreases to a length lower than 20us, the on time generated by one shot timer will increase by a step, thus the
off time of both FETs will be increased above 20us. If the load current increases further, and cause the off time
of both FETs shorter than 20us again, the above described on time increase process will repeat. By this means,
the switching frequency is maintained lower than ~50kHz as load increases. When the on time increases to the
length of that in CCM operation, the on time can't be increased anymore. If load current continue increases, the
switching frequency will increase linearly towards 1.4MHz nominal frequency. Below figure shows the frequency
VS load curve at 12Vin/5Vout condition with 1.5uH inductor used.
12Vin, 5Vout, 1.5uH inductor
60
55
50
45
40
35
30
25
20
Full load to no load
No load to full load
0
5
10
15
20
25
30
Load (mA)
D001
图 18. Frequency VS load current at 12Vin/5Vout condition with 1.5uH inductor used
10
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TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
Feature Description (接下页)
7.3.4 Soft Start and Pre-Biased Soft Start
The TPS563240 has an internal 1.7-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.5 Current Protection
There are two kinds of current protection in TPS563240: High-side FET source current limit and low-side FET
source current limit.
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the low-side FET switch, the inductor current flow through low-side FET and decreases
linearly. The average value of the inductor current is the load current IOUT. If the monitored current is above the
low-side FET source current limit level, the converter maintains low-side FET on and delays the creation of a
new set pulse, even the voltage feedback loop requires one, until the current cross the low-side FET source
current limit level. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored
in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time
(typically 0.36 ms) and re-start after the hiccup time (typically 25 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
During the on time of the high-side FET switch, the inductor current flow through high-side FET and increases at
a linear rate determined by VIN, VOUT, the on-time and the output inductor value. The switch current is compared
with high-side FET source current limit after a short blanking time. If the cross-limit event detected before the one
shot timer expires, the high-side FET will be turn off immediately, and will not be allowed on in the following 1uS
period.
7.3.6 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS563240 can operate in normal switching modes. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS563240 operates at a quasi-fixed frequency of
1.4MHz.
版权 © 2018, Texas Instruments Incorporated
11
TPS563240
ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
Device Functional Modes (接下页)
7.4.2 Eco-mode Operation
When the TPS563240 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS563240
begins operating in pulse skipping Eco-mode. Each switching cycle is followed by a period of energy saving
sleep time. The sleep time ends when the VFB voltage falls below reference voltage. As the output current
decreases, the sleep time between switching pulses increases.
7.4.3 Standby Operation
When the TPS563240 is operating in either normal CCM or Eco-mode, it may be placed in standby by asserting
the EN pin low.
12
版权 © 2018, Texas Instruments Incorporated
TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a typical step-down DC-DC converter. It's typically used to convert a higher dc voltage to a lower
dc voltage with a maximum available output current of 3 A. The following design procedure can be used to select
component values for the TPS563240. Alternately, the WEBENCH® software may be used to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
The application schematic in 图 19 was developed to meet the previous requirements. This circuit is available as
the evaluation module (EVM). The sections provide the design procedure.
图 19 shows the TPS563240 6.5-V to 17-V input, 3.3-V output converter schematics.
R4 0 ꢀ
C7 0.1 ꢁF
1
2
6
5
GND
SW
VBST
EN
L1
VOUT = 3.3V/3A
R3 10 kꢀ
EN
VOUT
1.5 ꢁH
C9
22 ꢁF
C8
NC
3
4
VIN
VFB
VOUT
R1 45.3 kꢀ
R2
10 kꢀ
C4
1
C1
C2
C3
10 ꢁF
NC
0.1 ꢁF
1
Not Installed
VIN
1
图 19. 3.3-V/3-A Reference Design
版权 © 2018, Texas Instruments Incorporated
13
TPS563240
ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
Typical Application (接下页)
8.2.1 Design Requirements
表 1 shows the design parameters for this application.
表 1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
6.5 to 17 V
3.3 V
Output voltage
Transient response, 1.5-A load step
Input ripple voltage
ΔVout = ±5%
400 mV
Output ripple voltage
Output current rating
Operating frequency
100 mV
3 A
1.4 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using 公式 2 to calculate VOUT
.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1
VOUT = 0.6 ì(1+
)
(2)
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP =
2p LOUT ì COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of 公式 3 is located below the high
frequency zero but close enough that the phase boost provided by the high frequency zero provides adequate
phase margin for a stable circuit. To meet this requirement use the values recommended in 表 2.
表 2. Recommended Component Values
L1 (µH)
TYP
0.56
0.56
0.68
0.82
1
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
C8 + C9 (µF)
MIN
0.33
0.33
0.47
0.47
0.56
0.68
0.82
1
MAX
1
1
1.05
1.2
1.5
1.8
2.5
3.3
5
6.65
7.5
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10 to 44
10 to 44
10 to 44
10 to 44
10 to 44
10 to 44
10 to 44
10 to 44
10 to 44
1
10
1.5
1.5
2.2
2.2
3.3
3.3
3.3
15
20
31.6
45.3
73.2
97.6
1
1.5
1.5
6.5
1
1.5
14
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TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using 公式 4, 公式 5, and
公式 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or
heating current rating must be greater than the calculated RMS current.
V
- VOUT
VOUT
IN(MAX)
IlP-P
IlPEAK = IO
ILO(RMS)
=
ì
V
LO ì fSW
IN(MAX)
(4)
(5)
IlP-P
+
1
2
2
=
IO
+
IlP-P
12
(6)
For this design example, the calculated peak current is 3.63 A and the calculated RMS current is 3.02 A. The
inductor used is a WE 744311150 with a rated current of 11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563240 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 10 µF to 44 µF. Use 公式 7 to
determine the required RMS current rating for the output capacitor.
VOUT ì V - VOUT
(
)
IN
ICO(RMS)
=
12 ì V ì LO ì fSW
IN
(7)
For this design one Murata GRM31CR61A226KE19 22-µF output capacitor is used. The typical ESR is 2 mΩ.
The calculated RMS current is 0.365 A and output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS563240 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
8.2.2.5 Dropout
With a constant 1.4-MHz switching frequency, there is a minimum input voltage limit for a given output voltage to
be regulated. This is due to the minimum off time limit. If the input voltage less than the minimum input voltage
limit, the output voltage drops accordingly, which is called dropout condition. 图 8 and 图 9 show the typical
dropout curve for 3.3 V and 5 V output voltage with 3 A and 1.5 A load respectively. 公式 8 can be used to
estimate this minimum input voltage limit.
8176
59
:
;
+ 4@OH + 4. × +1 × kPKBB (IEJ ) F P@1 F P@2o + (8 + 4. × +1) × (P@1 + P@2
)
@
(
8
=
+ (4@OD + 4.) × +1
+0(/+0)
1
59
F PKBB (IEJ )
(
where
•
•
•
•
•
•
•
•
•
•
VOUT = target output voltage
FSW = maximum switching frequency including tolerance
toff(min) = minimum off time including tolerance
Rdsl = low side FET on resistance
Rdsh = high side FET on resistance
RL = inductor DC resistance
IO = maximum load current
td1 = dead time between high side FET off and low side FET on, 15nS typical
td2 = dead time between low side FET off and high side FET on, 10nS typical
Vd = forward voltage of low side FET body diode
(8)
15
版权 © 2018, Texas Instruments Incorporated
TPS563240
ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
8.2.3 Application Curves
TA = 25°C, VIN = 12 V (unless otherwise noted)
3.33
3.32
3.31
3.3
3.31
3.305
3.3
3.295
3.29
3.29
3.28
3.27
3.26
3.25
3.24
3.285
3.28
3.275
3.27
3.265
3.26
Vin = 6.5V
Vin = 12V
Vin = 17V
0A Load
1.5A Load
3A Load
3.255
0
0.5
1
1.5
2
2.5
3
6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.517
Input Voltage (V)
Output Current (A)
D001
D001
图 20. Load Regulation
图 21. Line Regulation
图 23. Input Voltage Ripple
图 25. Output Voltage Ripple
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Vin = 6.5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2
3
D001
IOUT = 3 A
图 22. Efficiency
IOUT = 0 A
IOUT = 5 mA
图 24. Output Voltage Ripple
16
版权 © 2018, Texas Instruments Incorporated
TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
IOUT = 10 mA
IOUT = 0.25 A
图 26. Output Voltage Ripple
图 27. Output Voltage Ripple
IOUT = 3 A
Slew rate is 1.6A/µs
图 29. Transient Response, 0.6 to 2.4A
图 28. Output Voltage Ripple
Slew rate is 1.6A/µs
图 30. Transient Response, 0 to 3 A
IOUT = 0 A
图 31. Start Up Relative to VIN
版权 © 2018, Texas Instruments Incorporated
17
TPS563240
ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
IOUT = 3 A
IOUT = 0 A
图 33. Shutdown Relative to VIN
图 32. Start-Up Relative to EN
IOUT = 3 A
图 34. Shutdown Relative to EN
9 Power Supply Recommendations
TPS563240 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation.
18
版权 © 2018, Texas Instruments Incorporated
TPS563240
www.ti.com.cn
ZHCSJ66 –DECEMBER 2018
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not suggest routing SW copper under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
Trace on the
GND
bottom layer
VOUT
Additional
Vias to the
GND plane
OUTPUT
CAPACITOR
BOOST
CAPACITOR
GND
SW
BST
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
EN
FB
OUTPUT
INDUCTOR
VIN
VIN
GND trace under IC
On top layer
INPUT BYPASS
CAPACITOR
GND
图 35. Example Layout
版权 © 2018, Texas Instruments Incorporated
19
TPS563240
ZHCSJ66 –DECEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
D-CAP3, 无声, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Out-of-Audio is a trademark of #IMPLIED.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS563240DDCR
TPS563240DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
3240
3240
Samples
Samples
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
Addendum-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS563252DRLR
3-V to 17-V input voltage, 3-A, 1.2-Mhz synchronous buck converter in SOT563 | DRL | 6 | -40 to 125
TI
TPS563257DRLR
3-V to 17-V input voltage, 3-A, 1.2-Mhz synchronous buck converter in SOT563 | DRL | 6 | -40 to 125
TI
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