TPS61372YKBT [TI]

具有负载断开功能的 16V/3.6A 同步升压 | YKB | 16 | -40 to 125;


型号：	TPS61372YKBT
厂家：	TEXAS INSTRUMENTS
描述：	具有负载断开功能的 16V/3.6A 同步升压 \| YKB \| 16 \| -40 to 125
文件：	总31页 (文件大小：2058K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS61372

ZHCSID4B –JUNE 2018 –REVISED JANUARY 2021

具有负载断开功能的TPS61372 16V、3.8A 同步升压转换器

1 特性

3 说明

• 输入电压范围：2.5V 至5.5V

• 输出电压范围：高达16V

• 导通电阻：

TPS61372 是内置了负载断开功能的完全集成型同步升

压转换器。该器件可支持高达 16V 的输出电压（电流

限制为 3.8A）。输入电压的范围为 2.5V 至 5.5V，可

支持通过单节锂离子电池或5V 总线供电的应用。

– 低侧FET - 33mΩ

– 高侧FET - 104mΩ

TPS61372 以自适应关断时间控制拓扑为基础采用了峰

值电流模式。在中等到重负载条件下，该器件会在

1.5MHz PWM 模式下工作。在轻负载条件下，该器件

可通过MODE 引脚连接配置为自动 PFM 或强制PWM

模式。自动 PFM 模式的优势是可在轻负载条件下实现

高效率，而强制PWM 模式则可以在整个负载范围内保

持恒定开关频率。TPS61372 具有软启动功能，可最大

限度地减小启动期间的浪涌电流。TPS61372 可在关断

时断开负载，并提供断续模式输出短路保护。此外，该

器件还实施了输出过压和热关断保护。TPS61372 可通

过 16 引脚 WCSP 1.57mm × 1.52mm × 0.5mm 封装

实现紧凑的解决方案尺寸。

• 开关峰值电流限制：3.8A

• 来自V_IN的静态电流：74μA

• 来自V_OUT的静态电流：10μA

• 来自V_IN的关断电流：1μA

• 开关频率：1.5MHz

• 软启动时间：0.9ms

• 断续输出短路保护

• 可选自动PFM 和强制PWM

• 关断期间负载断开

• 外部环路补偿

• 输出过压保护

• 1.57mm × 1.52mm × 0.5mm 16 引脚WCSP

• 使用TPS61372 并借助WEBENCH^®Power

Designer 创建定制设计方案

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS61372

DSBGA (16)

1.57mm × 1.52mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• RF PA 驱动器

• NAND 闪存

• 备用电源

• 电机驱动器

• 光学传感器驱动器

C_BST

C_IN

VOUT

BST

VIN

C_OUT

Forced

PWM

Auto

PFM

VOUT

MODE

R_UP

OFF

R_DOWN

COMP

GND

R_C

典型应用电路

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSEE7

TPS61372

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ZHCSID4B –JUNE 2018 –REVISED JANUARY 2021

Table of Contents

8 Application and Implementation..................................12

8.1 Application Information............................................. 12

8.2 Typical Application.................................................... 12

9 Power Supply Recommendations................................21

10 Layout...........................................................................23

10.1 Layout Guidelines................................................... 23

10.2 Layout Example...................................................... 23

11 Device and Documentation Support..........................25

11.1 Device Support........................................................25

11.2 接收文档更新通知................................................... 25

11.3 支持资源..................................................................25

11.4 Trademarks............................................................. 25

11.5 静电放电警告...........................................................25

11.6 术语表..................................................................... 25

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................7

7 Detailed Description........................................................9

7.1 Overview.....................................................................9

7.2 Functional Block Diagram...........................................9

7.3 Feature Description...................................................10

7.4 Device Functional Modes..........................................11

Information.................................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (October 2018) to Revision B (January 2021)

Page

• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1

• Changed 2 to S in 方程式11 ............................................................................................................................17

• Updated 节8.2.2.7 ...........................................................................................................................................19

Changes from Revision * (June 2018) to Revision A (October 2018)

Page

• 首次发布量产数据数据表.................................................................................................................................... 1

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5 Pin Configuration and Functions

GND

COMP

GND

MODE

BST

VIN

VOUT

图5-1. YKB Package 16-Pin DSBGA (Top View)

表5-1. Pin Functions

I/O

DESCRIPTION

NUMBER

NAME

Output voltage feedback. A resistor divider connecting to this pin sets the output voltage.

COMP

Output of the internal error amplifier. The loop compensation network must be connected

between this pin and GND.

No connection. Tie directly to VIN pin. Do not connect with GND or leave it floating.

MODE

Operation mode selection pin. MODE = low, the device works in auto PFM mode with good

light load efficiency. MODE = high, the device is in forced PWM mode and keeps the switching

frequency constant across the whole load range.

B1, B2, B3

GND

Ground

Enable logic input. Logic high level enables the device. Logic low level disables the device and

turns it into shutdown mode.

C1, C2, C3

PWR The switching node pin of the converter. It is connected to the drain of the internal low-side

FET and the source of the internal high-side FET.

BST

Power supply for the high-side FET gate driver. A capacitor must be connected between this

pin and the SW pin.

D1, D2, D3

VOUT

VIN

PWR Boost converter output

IC power supply input

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

-0.3

MAX

SW+6

UNIT

Voltage range at terminals⁽²⁾

Operating junction temperature, T_J

Storage temperature, T_stg

BST

SW, VOUT

VIN, EN, COMP, FB, MODE, NC

–0.3

–40

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽²⁾

±1500

(1)

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽³⁾

±500

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

in to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows

safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary

precautions.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary

precautions.

6.3 Recommended Operating Conditions

Over operating free-air temperature range unless otherwise noted.

MIN

2.5

NOM

MAX

5.5

UNIT

V_IN

V_OUT

T_J

Input voltage

Output voltage

Operating junction temperature

125

°C

–40

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6.4 Thermal Information

TPS61372

THERMAL METRIC⁽¹⁾

YKB

16 PINS

87.1

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

0.7

24.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.4

24.3

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

V_IN= 2.5 V to 5.5 V and V_OUT= 5 V to 16 V, T_J= - 40°C to 125°C , Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

POWER SUPPLY

Input voltage under voltage lockout

(UVLO) threshold, rising

2.32

2.1

V_{IN_UVLO}

V_OUT= 12 V, T_J= - 40°C to 125°C

Input voltage under voltage lockout

(UVLO) threshold, falling

IC enabled, no switching

T_J= –40°C to 85°C

I_Q

Quiescent current into VIN pin

Quiescent current into VOUT pin

110

µA

IC enabled, no switching, V_IN= 2.5 V,

V_OUT= 5 V to 16 V,

T_J= –40°C to 85°C

I_Q

µA

V_IN= 2.5 V to 5.5 V, V_OUT= SW = 0 V,

Shutdown current from VIN to GND EN = 0,

I_SD

0.03

T_J= - 40°C to 85°C

OUTPUT VOLTAGE

Reference voltage on FB pin

0.585

0.594

1.016

0.603

V_REF

AUTO PFM mode

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C

V_REF

I_{FB_LKG}

Leakage current into FB pin

POWER SWITCHES

Low-side FET on resistance

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C

mΩ

R_DS(on)

High-side + Dis connect FET on

resistance

104

CURRENT LIMIT

Current Limit (Auto PFM)

Current Limit (Forced PWM)

EN, MODE LOGICS

V_IN= 3 V to 4.5 V, V_OUT= 5 V to 16 V,

T_J= - 40°C to 125°C

3.4

3.8

3.6

4.3

4.0

I_LIM

V_IN= 3 V to 4.5 V, V_OUT= 5 V to 16 V,

T_J= - 40°C to 125°C

3.28

EN, MODE pin high level input

voltage

V_IH

1.2

EN, MODE pin low level input

voltage

V_IL

0.4

V_HYS

T_DEGLITCH

R_PD

EN, MODE pin Hysteresis

100

µS

kΩ

EN, MODE deglitch time

rising / falling

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C

EN, MODE pull down resistor

800

SWITCHING CHARACTER

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V_IN= 2.5 V to 5.5 V and V_OUT= 5 V to 16 V, T_J= - 40°C to 125°C , Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

MHz

kHz

V_IN

V_IN= 3 V to 4.5 V, V_OUT= 5 V to 12 V,

T_J= - 40°C to 125°C

f_SW

Switch frequency

1.2

1.7

f_{SW_FOLD}

V_{FSW_LOW}

Switch frequency foldback

V_IN= 4 V, T_J= - 40°C to 125°C

470

15%

535

600

25%

Threshold for fsw foldback (1.5 MHz

normal)

20%

V_{FSW_LOW_}

Hysteresis for fsw foldback

V_IN= 4 V, T_J= 25°C

150

HSY

TIMING

t_{ON_MIN}

t_SS

Minimum on time

V_IN= 4 V, T_J=- 40°C to 125°C

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C

0.9

Soft-start time

t_{HIC_ON}

t_{HIC_OFF}

Off time of hiccup cycle

On time of hiccup cycle

1.9

ERROR AMPLIFIER

COMP output high voltage Auto

PFM

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C, V_FB

= V_REF- 200mV

1.4

1.5

0.8

V_COMPH

COMP output high voltage Forced V_IN= 4 V, V_OUT= 12 V, T_J= 25°C, V_FB

PWM

= V_REF- 200mV

V_IN= 4 V, V_°OUT= 12 V, T_J= 25°C,

V_FB= V_REF+ 200mV

COMP output low voltage Auto PFM

V_COMPL

COMP output low voltage Forced

PWM

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C, V_FB

= V_REF+ 200mV

0.6

175

Error amplifier trans conductance

Sink current of COMP

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C

µS

µA

V_IN= 4 V, T_J= 25°C, V_FB= V_REF

200mV

I_{SINK_EA}

V_IN= 4 V, T_J= 25°C, V_FB= V_REF

200mV

I_{SOURCE_EA}Source current of COMP

µA

PROTECTION

Output over-voltage protection

threshold

V_IN= 2.5 V to 5.5 V, T_J=- 40°C to

125°C

V_OVP

16.5

17.3

500

Output over-voltage protection

V_{OVP_HYS}

hysteresis

V_IN= 4 V, V_OUT= 12 V, T_J= 25°C

THERMAL

T_SD

Thermal shutdown threshold

Thermal shutdown hysteresis

V_IN= 4 V, V_OUT= 12 V

140

°C

T_{SD_HYS}

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6.6 Typical Characteristics

100

V_IN= 3 V

V_IN= 4 V

V_IN= 5 V

V_IN= 3 V

V_IN= 4 V

V_IN= 5 V

0.0001

0.001

0.01

Load (A)

0.1

0.5

0.0001

0.001

0.01

Load (A)

0.1

0.5

D001

D002

V_OUT= 12 V

L = 2.2 µH

Auto PFM

V_OUT= 12 V

L = 2.2 µH

Forced PWM

图6-1. Efficiency vs Load

图6-2. Efficiency vs Load

12.5

12.4

12.3

12.2

12.1

0.61

0.608

0.606

0.604

0.602

0.6

11.9

11.8

11.7

11.6

0.598

0.596

0.594

0.592

V_IN= 3 V

V_IN= 4 V

V_IN= 5 V

11.5

0.0001

0.59

-40

0.001

0.01 0.02 0.05 0.1 0.2

Load (A)

0.5

-20

100

120

Temperature (èC)

D003

D004

V_OUT= 12 V

L = 2.2 µH

Auto PFM

V_IN= 4 V

图6-3. Load Regulation

图6-4. Reference Voltage vs Temperature

100

T_J= -40èC

T_J= 25èC

T_J= 125èC

2.5

3.5

4.5

-40

-20

100

120

V_IN(V)

Temperature (èC)

D005

D006

V_IN= 2.5 V to 5.5 V

V_OUT= 12 V

No Switching

V_IN= 4 V

V_OUT= 12 V

图6-5. I_qvs V_IN

图6-6. Low-Side RDS_ONvs Temperature

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150

140

130

120

110

100

2.7

2.6

2.5

2.4

2.3

2.2

2.1

Rising

Falling

1.9

1.8

-40

-20

100

120

-40

-20

100

120

Temperature (èC)

D007

D008

V_IN= 4 V

V_OUT= 12 V

图6-7. High-side RDS_ONvs Temperature

图6-8. UVLO Threshold vs Temperature

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7 Detailed Description

7.1 Overview

The TPS61372 is a highly-integrated synchronous boost converter to support 16-V output with load disconnect

and short protection built-in. The TPS61372 supports input voltage ranging from 2.5 V to 5.5 V. The TPS61372

uses the peak current mode with adaptive off-time control topology to regulate the output voltage. The

TPS61372 operates at a quasi-constant frequency pulse-width modulation (PWM) at moderate to heavy load

current. At the beginning of each cycle, the low-side FET turns on and the inductor current ramps up to reach a

peak current determined by the output of the error amplifier (EA). When the peak current pre-set value

determined by the output trips of the EA, the low-side FET turns off. As long as the low-side FET turns off, the

high-side FET turns on after a short delay time to avoid the shoot through. The duration of low-side FET off state

is determined by the V_IN/ V_OUTratio.

High efficiency is achieved at light load as the TPS61372 operates in PFM operation. The device can be also

configured at forced PWM mode to keep the frequency constant across the whole load range and to have more

immunity against noise sensitive applications.

7.2 Functional Block Diagram

VIN

C_BST

C_IN

BST

VIN

VOUT

V_OUT

BOOT

REG

VCC

C_OUT

UVLO,

OVP,

Thermal

HS Driver

Fault

Proteciton

LS Driver

Forced

PWM

VOUT

MODE

Auto

PFM

R_UP

V_OUT

V_IN

V_REF

Hiccup

Control

REF

OFF

R_DOWN

Soft

start

Current limit

trigger

COMP

VOUT

VIN

PWM

Comparator

TOFF

R_C

GND

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7.3 Feature Description

7.3.1 Undervoltage Lockout

The undervoltage lockout (UVLO) circuit prevents the device from malfunctioning at the low input voltage of the

battery from the excessive discharge. The device starts operation once the rising V_INtrips the UVLO threshold

and it disables the output stage of the converter once V_INis below the UVLO falling threshold.

7.3.2 Enable and Disable

When the input voltage is above the UVLO threshold and the EN pin is pulled above the high threshold (1.2 V

minimum), the TPS61372 is enabled. When the EN pin is pulled below the low threshold (0.4 V maximum), the

TPS61372 goes into shutdown mode.

7.3.3 Error Amplifier

The TPS61372 has a transconductance amplifier and compares the feedback voltage with the internal voltage

reference (or the internal soft-start voltage during start-up phase). The transconductance of the error amplifier is

175 µA / V typically. The loop compensation components are placed between the COMP terminal and ground to

optimize the loop stability and response speed.

7.3.4 Bootstrap Voltage (BST)

The TPS61372 has an integrated bootstrap regulator and requires a small ceramic capacitor between the BST

and SW pin to provide the gate drive voltage for the high-side FET. The recommended value for this ceramic

capacitor is between 20 nF to 200 nF.

7.3.5 Load Disconnect

The TPS61372 device provides a load disconnect function, which completely disconnects the output from the

input during shutdown or fault conditions.

7.3.6 Overvoltage Protection

If the output voltage is detected above the overvoltage protection threshold (typically 17.3 V), the TPS61372

stops switching immediately until the voltage at the V_OUTpin drops below the output overvoltage protection

recovery threshold (with 500-mV hysteresis). This function prevents the devices against the overvoltage and

secures the circuits connected with the output of excessive overvoltage.

7.3.7 Thermal Shutdown

A thermal shutdown is implemented to prevent the damage due to the excessive heat and power dissipation.

Typically, the thermal shutdown occurs at the junction temperature exceeding 140°C (typical). When the thermal

shutdown is triggered, the device stops switching and recovers when the junction temperature falls below 120°C

(typical).

7.3.8 Start-Up

The TPS61372 implements the soft start function to reduce the inrush current during start-up. The TPS61372

begins soft start when the EN pin is pulled high. There are two phases for the start-up procedure:

• When V_OUTis below 120% V_IN, the output votlage ramps up with the switching frequency of 535 kHz (typical).

• When V_OUTexceeds 120% V_IN, the switching frequency changes to 1.5 MHz typically and ramps up the

output voltage to the setpoint.

7.3.9 Short Protection

The TPS61372 provides a hiccup protection mode when output short protection occurs. In hiccup mode, the

TPS61372 shuts down after the 1.9-ms duration of current limit is triggered and the V_OUTis pulled below 105%

V_IN. In hiccup steady state, the device shuts down itself and restarts after a 74-ms (typical) waiting time, which

helps to reduce the overall thermal dissipation at continuous short condition. After the short condition releases,

the device can recover automatically and restart the start-up phase.

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7.4 Device Functional Modes

7.4.1 Operation

In light load condition, the TPS61372 can be configured at Auto PFM or Forced PWM. At Auto PFM operation,

the switching frequency is lowered at light load and features higher efficiency, while for Forced PWM operation,

the frequency keeps constant across the whole load range.

7.4.2 Auto PFM Mode

The TPS61372 integrates a power-save mode with pulse frequency modulation (PFM) at light load (set the mode

pin low logic or floating). The device skips the switching cycles and regulates the output voltage at a higher

threshold (typically 101.6% × V_{OUT_NORM}). 图 7-1 shows the working principle of the PFM operation. The auto

PFM mode reduces the switching losses and improves efficiency at light load condition by reducing the average

switching frequency.

V_{OUT_PFM}

V_{OUT_NORM}

V_OUT

Load

I_{CLAMP_LOW}

TOFF longer with

lower current

TON = (L * I _{CLAMP_LOW}) / V_IN

PFM

PWM

图7-1. Auto PFM Operation Behavior

7.4.3 Forced PWM Mode

In forced PWM mode, the TPS61372 keeps the switching frequency constant across the whole load range.

When the load current decreases, the output of the internal error amplifier decreases as well to lower the

inductor peak current and delivers less power. The high-side FET is not turned off even if the current through the

FET goes negative to keep the switching frequency be the same as that of the heavy load.

7.4.4 Mode Selectable

There is a mode pin to configure the TPS61372 into two different operation modes. The device works in auto

PFM mode when pulling the mode pin to low or floating and in forced PWM mode when mode pin is high.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS61372 is a synchronous boost converter. The following design procedure can be used to select

component values for the TPS61372. This section presents a simplified discussion of the design process.

Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software

uses an interactive design procedure and accesses a comprehensive database of components when generating

a design. This section presents a simplified discussion of the design process.

8.2 Typical Application

2.2uH

C_BST

C_IN

0.1uF

10 uF

BST

VOUT

VIN

R_MODE

100k

C_OUT1

10uF

C_OUT2

10uF

C_OUT3

10uF

Forced

PWM

Auto

PFM

MODE

R_UP1

909k

GND

R_EN

100k

R_UP2

1000k

OFF

R_DOWN

100k

COMP

GND

680pF

R_C

61.9k

图8-1. TPS61372 12-V Output With Load Disconnect Schematic

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8.2.1 Design Requirements

For this design example, use 表8-1 as the design parameters.

表8-1. Design Parameters

PARAMETER

Input voltage range

Output voltage

VALUE

3 V to 5 V

12 V

Output ripple voltage

Output current

± 3%

0.4 A

Operating frequency

1.5 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS61372 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

• Input voltage range

• Output voltage

• Output ripple voltage

• Output current rating

• Operating frequency

8.2.2.2 Setting the Output Voltage

The output voltage of the TPS61372 is externally adjustable using a resistor divider network. The relationship

between the output voltage and the resistor divider is given by 方程式1.

R_UP

V_OUT= V_FB´ (1+

)

R_DOWN

(1)

where

• V_OUTis the output voltage

• R_UPis the top divider resistor

• R_DOWNis the bottom divider resistor

Choose R_DOWNto be approximately 100 kΩ. Slightly increasing or decreasing R_DOWNcan result in closer output

voltage matching when using standard value resistors. In this design, R_DOWN= 100 kΩ and R_UP= 1.909 MΩ (1

MΩ+ 909 kΩ) , resulting in an output voltage of 12 V.

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For the best accuracy, TI recommends R_DOWNto be around 100 kΩ to ensure that the current following through

R_DOWNis at least 100 times larger than FB pin leakage current. Changing R_DOWNtowards the lower value

increases the robustness against noise injection. Changing R_DOWNtowards the higher values reduces the

quiescent current for achieving higher efficiency at the light load currents.

8.2.2.3 Selecting the Inductor

A boost converter normally requires two main passive components for storing the energy during power

conversion: an inductor and an output capacitor. The inductor affects the steady state efficiency (including the

ripple and efficiency) as well as the transient behavior and loop stability, which makes the inductor to be the most

critical component in application.

When selecting the inductor, as well as the inductance, the other parameters of importance are:

• The maximum current rating (RMS and peak current should be considered)

• The series resistance

• Operating temperature

Choosing the inductor ripple current with the low ripple percentage of the average inductor current results in a

larger inductance value, maximizes the potential output current of the converter, and minimizes EMI. The larger

ripple results in a smaller inductance value and a physically smaller inductor, which improves transient response,

but results in potentially higher EMI.

The rule of thumb in choosing the inductor is to make sure the inductor ripple current (ΔI_L) is a certain

percentage of the average current. The inductance can be calculated by 方程式2, 方程式3, and 方程式4:

_IN´ D

DI_L=

L ´ f_SW

(2)

(3)

(4)

V_OUT´ I_OUT

DI_{L _R}= Ripple% ´

h ´ V

Ripple % V_OUT´ I_OUT

V ´ D

L =

ƒ_SW

where

• Δ_ILis the peak-peak inductor current ripple

• V_INis the input voltage

• D is the duty cycle

• L is the inductor

• ƒ_SWis the switching frequency

• Ripple% is the ripple ration versus the DC current

• V_OUTis the output voltage

• I_OUTis the output current

• ηis the efficiency

The current flowing through the inductor is the inductor ripple current plus the average input current. During

power up, load faults, or transient load conditions, the inductor current can increase above the peak inductor

current calculated.

Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current

approaches the saturation level, its inductance can decrease 20% to 35% from the value at 0-A bias current

depending on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated

current, especially the saturation current, is larger than its peak current during the operation.

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The inductor peak current varies as a function of the load, the switching frequency, and the input and output

voltages and it can be calculated by 方程式5 and 方程式6.

I_PEAK= I

´ DI_L

(5)

where

• I_PEAKis the peak current of the inductor

• I_INis the input average current

• ΔI_Lis the ripple current of the inductor

The input DC current is determined by the output voltage, the output current, and efficiency can be calculated by:

V_OUT´ I_OUT

V_IN´ h

(6)

where

• I_INis the input current of the inductor

• V_OUTis the output voltage

• V_INis the input voltage

• ηis the efficiency

While the inductor ripple current depends on the inductance, the frequency, the input voltage, and duty cycle

calculated by 方程式2, replace 方程式2, 方程式6 into 方程式5 to calculate the inductor peak current:

I_OUT

V_IN´ D

I_PEAK

(1- D) ´ h

L ´ f_SW

(7)

where

• I_PEAKis the peak current of the inductor

• I_OUTis the output current

• D is the duty cycle

• ηis the efficiency

• V_INis the input voltage

• L is the inductor

• ƒ_SWis the switching frequency

The heat rating current (RMS) is calculated by 方程式8:

(DI_L)²

I_{L _RMS}= I

(8)

where

• I_{L_RMS}is the RMS current of the inductor

• I_INis the input current of the inductor

• ΔI_Lis the ripple current of the inductor

It is important that the peak current does not exceed the inductor saturation current and the RMS current is not

over the temperature related rating current of the inductors.

For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation

current. The total losses of the coil consists of the DC resistance ( DCR ) loss and the following frequency

dependent loss:

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• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)

• Additional losses in the conductor from the skin effect (current displacement at high frequencies)

• Magnetic field losses of the neighboring windings (proximity effect)

For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and frequency-

dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However, it is

usually a tradeoff between the loss and footprint.

The following inductor series in 表8-2 from the different suppliers are recommended.

表8-2. Recommended Inductors for TPS61372

SATURATION

CURRENT /

TYP.

DCR Typ (mΩ)

PART NUMBER

SIZE (L × W × H mm)

VENDOR⁽¹⁾

L (μH)

TYP.

XAL4020-222ME

DFE322512F-2R2M=P2

DFE322520FD-4R7M#

2.2

4.7

5.6

2.6

3.4

4 x 4 x 2

Coilcraft

Murata

3.2 x 2.5 x 1.2

3.2 x 2.5 x 2.0

(1) See the Third-party Products Disclaimer.

8.2.2.4 Selecting the Output Capacitors

The output capacitor is mainly selected to meet the requirements at load transient or steady state. Then the loop

is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series

resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum

capacitance needed for a given ripple can be calculated by 方程式9:

I_OUT´ (V_OUT- V )

C_OUT

f_SW´ DV ´ V_OUT

(9)

where

• C_OUTis the output capacitor

• I_OUTis the output current

• V_OUTis the output voltage

• V_INis the input voltage

• Δ_Vis the output voltage ripple required

• ƒ_SWis the switching frequency

The additional output ripple component caused by ESR is calculated by 方程式10:

DV_ESR= I_OUT´ R_ESR

(10)

where

• ΔV_ESRis the output voltage ripple caused by ESR

• R_ESRis the resistor in series with the output capacitor

For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors,

it must be considered if used.

Care must be taken when evaluating the rating of a ceramic capacitor under the DC bias. Ceramic capacitors

can derate by as much as 70% of its capacitance at its rated voltage. Therefore, enough margins on the voltage

rating should be considered to ensure adequate capacitance at the required output voltage.

表8-3. Recommended Output Capacitor for TPS61372

PART NUMBER

PIECES

DESCRIPTION

SIZE

VENDOR⁽¹⁾

C (μF)

GRM188R61E106MA73D

X5R, 0603, 5 V, ±20% tolerance

0603

Murata

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8.2.2.5 Selecting the Input Capacitors

Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter as they

have extremely low ESR and are available in small footprints. Input capacitors should be located as close as

possible to the device.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the

power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce

ringing at the V_INpin. This ringing can couple to the output and be mistaken as loop instability or can even

damage the part. Place additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, between C_IN

and the power source lead, to reduce ringing that can occur between the inductance of the power source leads

and C_IN.

8.2.2.6 Loop Stability and Compensation

8.2.2.6.1 Small Signal Model

The TPS61372 uses the peak current with adaptive off-time control topology. With the inductor current

information sensed, the small-signal model of the power stage reduces from a two-pole system, created by L

and C_OUT, to a single-pole system, created by R_OUTand C_OUT. An external loop compensation network

connecting to the COMP pin of TPS61372 is added to optimize the loop stability and the response time, a

resistor R_C, capacitor C_C, and C_Pshown in 图8-2 comprises the loop compensation network.

VIN

VOUT

C_IN

R_ESR

C_OUT

R_OUT

R_SENSE

R_UP

TOFF

G_EA

R_DOWN

V_REF

R_C

R_EA

图8-2. TPS61372 Control Equivalent Circuitry Model

The small signal of power stage including the slope compensation is:

≈

∆

’≈

÷∆

◊«

’

◊

1 +

1 -

2p ì f_ESR

2p ì f_RHP

R_OUTì (1-D)

2 ì R_SENSE

G_PS(S) =

1 +

2p ì f_P

(11)

where

• D is the duty cycle

• R_OUTis the output load resistor

• R_SENSEis the equivalent internal current sense resistor, which is typically 0.2 Ωof TPS61372

The single pole of the power stage is:

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f_P=

2p ´ R_OUT´ C_OUT

(12)

where

• C_OUTis the output capacitance, for a boost converter having multiple, identical output capacitors in parallel,

simply combine the capacitors with the equivalent capacitance

The zero created by the ESR of the output capacitor is:

f_ESR

2p ´ R_ESR´ C_OUT

(13)

where

• R_ESRis the equivalent resistance in series of the output capacitor

The right-hand plane zero is:

R_OUT´ (1- D)²

2p ´ L

f_RHP

(14)

where

• D is the duty cycle

• R_OUTis the output load resistor

• L is the inductance

The TPS61372 COMP pin is the output of the internal trans-conductance amplifier.

方程式15 shows the equation for feedback resistor network and the error amplifier.

R_DOWN

2´ p ´ f_Z

H_EA(S) = G_EA´R_EA

_UP+ R_DOWN

(1+

)´(1+

)

2´ p ´ f_P1

2´ p ´ f_P2

(15)

where

• R_EAis the output impedance of the error amplifier R_EA= 500 MΩ. G_EAis the transconuctance of the error

amplifier, G_EA= 175 μS.

• ƒ_P1, ƒ_P2is the pole's frequency of the compensation

• f_Zis the zero’s frequency of the compensation network

f_P1

2p ´ R_EA´ C_c

(16)

where

• C_Cis the zero capacitor compensation

f_P2

2p ´ R_C´ C_P

(17)

where

• C_Pis the pole capacitor compensation

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• R_Cis the resistor of the compensation network

f_Z=

2p ´R_C´C_C

(18)

8.2.2.7 Loop Compensation Design Steps

With the small signal models coming out, the next step is to calculate the compensation network parameters with

the given inductor and output capacitance.

1. Set the Crossover Frequency, ƒ_C.

• The first step is to set the loop crossover frequency, ƒ_C. The higher crossover frequency, the faster the

loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either

1/10 of the switching frequency, ƒ_SW, or 1/5 of the RHPZ frequency, ƒ_RHPZ. Then calculate the loop

compensation network values of R_c, C_c, and C_pin following sections.

2. Set the Compensation Resistor, R_C.

• By placing ƒ_Zbelow ƒ_C, for frequencies above ƒ_C, R_C| | R_EAapproximately = R_C, so R_C× G_EAsets the

compensation gain. Setting the compensation gain, K_COMP-dB, at ƒ_Z, results in the total loop gain, T_(s)

G_PS(s)× H_EA(s)× He(s) being zero at ƒ_C.

• Therefore, to approximate a single-pole rolloff up to f_P2, rearrange 方程式19 to solve for RC so that the

compensation gain, K_EA, at f_Cis the negative of the gain, K_PS, read at frequency f_Cfor the power stage

bode plot or more simply:

R_DOWN

K_EA(f_C) = 20 ´ log(G_EA´ R_C´

) = - K_PS(f_C)

R_UP+ R_DOWN

(19)

where

– K_EAis gain of the error amplifier network

– K_PSis the gain of the power stage

– G_EAis the transconductance of the amplifier, the typical value of G_EA= 175 µA / V

3. Set the compensation zero capacitor, C_C.

• Place the compensation zero at the power stage pole position of R_OUT, C_OUTto get:

f_Z=

2p ´ R_C´ C_C

(20)

(21)

• Set ƒ_Z= ƒ_P, and get:

_OUT´C_OUT

C_C

2R_C

4. Set the compensation pole capacitor, C_P.

• Place the compensation pole at the zero produced by the R_ESRand the C_OUT. It is useful for canceling

unhelpful effects of the ESR zero.

f_P2

2p ´ R_C´ C_P

(22)

(23)

f_ESR

2p ´ R_ESR´ C_OUT

• Set ƒ_P2= ƒ_ESR, and get:

R_ESR´ C_OUT

C_P=

R_C

(24)

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• If the calculated value of C_Pis less than 10 pF, it can be neglected.

Designing the loop for greater than 45° of phase margin and greater than 6-dB gain margin eliminates output

voltage ringing during the line and load transient. The R_C= 61.9 kΩ, C_C= 680 pF for this design example.

8.2.2.8 Selecting the Bootstrap Capacitor

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side FET

device gate during the turnon of each cycle and also supplies charge for the bootstrap capacitor. The

recommended value of the bootstrap capacitor is 20 nF to 200 nF. C_BSTshould be a good quality, low-ESR

ceramic capacitor located at the pins of the device to minimize potentially damaging voltage transients caused

by trace inductance. A value of 100 nF is selected for this design example.

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8.2.3 Application Curves

Typical condition V_IN= 3 V to 5 V, V_OUT= 12 V, temperature = 25°C, unless otherwise noted

V_IN= 4 V

V_OUT= 12 V

Mode = Auto PFM

V_IN= 4 V

V_OUT= 12 V

Mode = Auto PFM

L = 2.2 µH

C_OUT= 3 × 10 µF

L = 2.2 µH

C_OUT= 3 × 10 µF

图8-3. Steady-State at 200-mA Load

图8-4. Steady-State at 10-mA Load

V_IN= 4 V

V_OUT= 12 V

Mode = Auto PFM

V_IN= 4 V

V_OUT= 12 V

Mode = Auto PFM

L = 2.2 µH

C_OUT= 3 × 10 µF

L = 2.2 µH

C_OUT= 3 × 10 µF

图8-5. Start-Up by EN, Load = 12.5 Ω

图8-6. Shutdown by EN, Load = 12.5 Ω

V_IN= 4 V

V_OUT= 12 V

Mode = Auto PFM

V_IN= 4 V

V_OUT= 12 V

Mode = Auto PFM

L = 2.2 µH

C_OUT= 3 × 10 µF

L = 2.2 µH

C_OUT= 3 × 10 µF

图8-7. Load Transient, 200 mA to 400 mA, 100 mA /

图8-8. Shorted Output

µs

9 Power Supply Recommendations

The devices are designed to operate from an input voltage supply ranging from 2.5 V to 5.5 V. This input supply

must be well regulated. If the input supply is located more than a few inches from the TPS61372, the bulk

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capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value

of 47 µF is a typical choice.

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10 Layout

10.1 Layout Guidelines

The basic PCB board layout requires a separation of sensitive signal and power paths. If the layout is not

carefully done, the regulator can suffer from the instability or noise problems.

The following checklist is suggested that be followed to get good performance for a well-designed board:

1. Minimize the high current path from output of chip, the output capacitor to the GND of chip. This loop

contains high di / dt switching currents (nano seconds per ampere) and easy to transduce the high frequency

noise.

2. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under

the switching regulator to minimize inter plane coupling.

3. Use a combination of bulk capacitors and smaller ceramic capacitors with low series resistance for the input

and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for

decoupling the noise.

4. The ground area near the IC must provide adequate heat dissipating area. Connect the wide power bus (for

example, V_OUT, SW, GND ) to the large area of copper, or to the bottom or internal layer ground plane, using

vias for enhanced thermal dissipation.

5. Place the input capacitor being close to the V_INpin and the PGND pin in order to reduce the input supply

ripple.

6. Place the noise sensitive network like the feedback and compensation being far away from the SW trace.

7. Use a separate ground trace to connect the feedback and the loop compensation circuitry. Connect this

ground trace to the main power ground at a single point to minimize circulating currents.

10.2 Layout Example

VIN

VOUT

VIN

BST

VOUT

GND

COMP

GND

MODE

GND

Mode

Top Layer

Bottom Layer

GND

图10-1. Recommended Layout

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10.2.1 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power

dissipation limits of a given component.

Two basic approaches for enhancing thermal performance are listed below:

•Improving the power dissipation capability of the PCB design

•Improving the thermal coupling of the component to the PCB

As power demand in portable designs is more and more important, designers must figure the best trade-off

between efficiency, power dissipation and solution size. Due to integration and miniaturization, junction

temperature can increase significantly which could lead to bad application behaviors (that is, premature thermal

shutdown or worst case reduce device reliability). Junction-to-ambient thermal resistance is highly application

and board-layout dependent. In applications where high maximum power dissipation exists, special care must be

paid to thermal dissipation issues in board design. Keep the device operating junction temperature (T_J) below

125°C.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Development Support

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS61372 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS61372YKBR

TPS61372YKBT

ACTIVE

DSBGA

YKB

3000 RoHS & Green

250 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 125

TPS

61372

ACTIVE

YKB

SNAGCU

TPS

61372

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS61372YKBR

TPS61372YKBT

DSBGA

YKB

3000

250

180.0

8.4

1.68

1.72

0.62

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Dec-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS61372YKBR

TPS61372YKBT

DSBGA

YKB

3000

250

182.0

20.0

Pack Materials-Page 2

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TPS61372YKBT [TI]

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