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TPS650830

ZHCSDM1 –DECEMBER 2014

TPS650830 面向移动计算机的简单而灵活的宽输入电压电源管理单元

(PMU)

1

1 特性

•

5 个可重新配置的稳压器：

•

用于实时时钟 (RTC) 域的备用电池/3.1V LDO 选择

器输出

–

可在宽输入电压和宽输出电流范围内保持高效

可更改电压、电流和序列以优化系统

•

电源检测和监视：适配器、电池 1 和电池 2

过温保护比较器，用于堆叠式正温度系数 (PTC) 热

敏电阻或单个负温度系数 (NTC) 热敏电阻

4 个采用外部功率金属氧化物半导体场效应晶体

管 (MOSFET) 的可变输出电压降压控制器：

•

1Hz 嵌入式控制器 (EC) 唤醒时钟输出

–

VR1 = 1V；VR3 = 3.3V，VR4 =

1.2V/1.35V/1.1V（对于 DDRx

VDDQ），VR5 = 5V

先进的系统复位控制

I²C 接口：标准模式 (100kHz)，快速模式

(400kHz)，快速模式+ (1000kHz)

–

V_IN范围：5.4V 至 24V

采用外部功率 MOSFET，连续输出电流范围

为 <1A 至 >10A

2 应用

•

NVDC 或非 NVDC 电源系统架构

–

1 个带有内部功率 MOSFET 的可变输出电压降

压转换器：

2 节、3 节或 4 节串联锂电池供电类产品

平板电脑、超极本、二合一电脑和笔记本电脑

移动 PC、一体化计算机、移动因特网设备

–

VR2 = 1.8V

V_IN范围：3V 至 3.6V

高达 2A 的持续输出电流

现场可编程逻辑门阵列 (FPGA)，工业计量设备，

个人医疗产品

–

输出电压直流精度 ±1%；直流 + 交流精度

±5%，支持差分输出电压感测

3 说明

在超低静态电流模式下，每个控制器或转换器的

静态电流典型值为 30μA

TPS650830 是一款单芯片解决方案电源管理集成电路

(IC)，专为最新的 Intel 处理器而设计，主要应用于由

2 节、3 节或 4 节串联锂离子电池组供电且采用

NVDC 或非 NVDC 电源架构的平板电脑、超极本和笔

记本电脑。

•

3 个固定输出电压低压降线性稳压器 (LDO)：

–

LDO1：1/2 VR4 固定输出电压 LDO（对于

DDRx VTT）(Vout = VDDQ/2)

–

连续输出电流高达 1A，直流 + 交流精度

±5%，峰值电流为 2A

器件信息⁽¹⁾

–

LDO3：3.3V 固定输出电压 LDO，直流精度

±1%，电流 < 40mA

器件型号

TPS650830

封装

NFBGA (168)

NFBGA (159)

封装尺寸（标称值）

7.00mm x 7.00mm

9.00mm x 9.00mm

–

用于外部模数转换器 (ADC) 的高精度参考电

源

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

–

用于 EC_VCC 电源轨的 3.3V 负载开关

–

LDO5：5V 固定输出电压 LDO，直流精度

±1%，电流 < 100mA

简化系统图

TPS650830 PMIC

Non-NVDC

–

用于控制器和转换器栅极驱动的电源

FET FET

ADAPTOR

VBATA

FET

CHARGER

FET

VR5, 5V

NVDC

FET

LOAD

SWITCH

可自动切换至 5V 稳压器以实现高效率

FET

VR3, 3.3V

VR2, 1.8V

+

-

LOAD

SWITCH

BAT1

•

8 个用于外部稳压器、负载开关或 LDO 的电源正

常状态比较器和序列逻辑

FET

LOAD

SWITCH

+

-

SKYLAKE

PLATFORM

LOAD

SWITCH

BAT2

•

支持电源按钮逻辑且可编程响应时间

LOAD

SWITCH

FET

VR1, 1V

LOAD

SWITCH

2 个通用电平转换器

FET

VR4, 1.2V

LDO1, 0.6V

RTC, 3.1V

I/O

+

-

I2C

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLVSCF4

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

8.5 Register Map........................................................... 48

Application and Implementation ........................ 90

9.1 Application Information............................................ 90

9.2 Typical Applications ................................................ 90

9.3 System Examples ................................................ 103

9.4 Do's and Don'ts .................................................... 103

1

2

3

4

5

6

7

特性.......................................................................... 1

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）............................................................... 3

Pin Configuration and Functions......................... 4

Specifications....................................................... 11

7.1 Absolute Maximum Ratings .................................... 11

7.2 ESD Ratings .......................................................... 12

7.3 Recommended Operating Conditions..................... 13

7.4 Thermal Information................................................ 14

7.5 Electrical Characteristics......................................... 15

7.6 Timing Requirements.............................................. 32

7.7 Typical Characteristics............................................ 34

Detailed Description ............................................ 38

8.1 Overview ................................................................. 38

8.2 Functional Block Diagram ....................................... 39

8.3 Feature Description................................................. 40

8.4 Device Functional Modes........................................ 46

10 Power Supply Recommendations ................... 104

11 Layout................................................................. 105

11.1 Layout Guidelines ............................................... 105

11.2 Layout Example .................................................. 107

11.3 Thermal Considerations...................................... 108

12 器件和文档支持 ................................................... 109

12.1 器件支持 ............................................................. 109

12.2 文档支持 ............................................................. 109

12.3 商标..................................................................... 109

12.4 静电放电警告....................................................... 109

12.5 术语表 ................................................................. 109

13 机械、封装和可订购信息..................................... 110

8

4 修订历史记录

日期

修订版本

注释

2014年12月

*

最初发布。

2

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

5 说明（续）

TPS650830 应用于 Volume 系统，该系统采用合并式低电压轨，可实现体积最小且成本最低的系统电源解决方

案。

TPS650830 可基于 Intel 参考设计提供完整的电源解决方案。该器件具有 5 个高效降压稳压器 (VR) 和 1 个灌/拉

LDO，可与上电序列逻辑器件搭配使用以管理外部负载开关，从而提供正确的电源轨、排序和保护，其中包括

DDR3 和 DDR4 存储器电源。该稳压器支持动态电压调节 (DVS)，可最大限度地提高效率（包括联网待机功

能）。高频稳压器采用小型电感和电容，以减小解决方案体积。可通过 4 个 VR 控制器调节输出功率。凭借 I²C

接口，可以通过嵌入式控制器 (EC) 轻松加以控制。每个器件版本均提供 7x7 NFBGA 和 9x9 NFBGA 两种封装。

7x7 NFBGA 封装适用于类型 4 印刷电路板 (PCB)，可实现最小电路板面积。 9x9 NFBGA 封装适用于类型 3

和类型 4 PCB 板，可最大限度地降低成本并缩小电路板面积。

3

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

6 Pin Configuration and Functions

168-Pin NFBGA

7x7 ZAJ Package

(Top View)

4

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

159-Pin NFBGA

9x9 ZCG Package

(Top View)

Pin Functions

I/O

DESCRIPTION

ZAJ PACKAGE

NUMBER

ZCG PACKAGE

NUMBER

NAME

VBSTVR1

DRVHVR1

SWVR1

M11

N12

N11

N9

R14

T14

T13

T11

T12

J10

I

O

I

VR1 Bootstrap pin

VR1 High side gate drive output (external power FET)

VR1 Switch node connection

DRVLVR1

PGNDVR1

FBVR1P

O

-

VR1 Low side gate drive output (external power FET)

VR1 Power GND

N10

K10

I

VR1 Remote positive feedback sense (Connect to vout of

VR1 at output load capacitor)

5

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

ZAJ PACKAGE

NUMBER

ZCG PACKAGE

NUMBER

NAME

FBVR1N

J9

M10

L9

K11

R12

M11

I

VR1 Remote negative feedback sense (Connect to GND of

VR1 at output load capacitor)

VREGVR1

ILIMVR1

VR1 5V drive supply input (shorted on board with LDO5V),

shared with VR5

VR1 Current limit setting, low-side FET valley current

sense

ENVR1

PGVR1

VINVR2

M12

M9

R15

P11

I

O

I

VR1 Enable

VR1 power good comparator output

F12, F13

H15, H16

VR2 Power Input voltage. Connect to a 3.3V voltage

regulator, such as V3.3A_DSW

SWVR2

PGNDVR2

FBVR2P

H12, H13

G12, G13

G10

K15, K16

J15, J16

G10

I

-

I

VR2 Switch node connection

VR2 Power GND

VR2 Remote positive feedback sense (Connect to vout of

VR2 at output load capacitor)

FBVR2N

E10

G12

I

VR2 Remote negative feedback sense (Connect to GND of

VR2 at output load capacitor)

VREGVR2

ENVR2

E13

F11

E12

B11

A12

A11

A9

G16

J14

H13

B13

A14

A13

A11

A12

F11

I

VR2 5V drive supply input (shorted on board with LDO5V)

VR2 Enable

PGVR2

O

I

VR2 Power good comparator output

VR3 Bootstrap pin

VBSTVR3

DRVHVR3

SWVR3

O

I

VR3 High side gate drive output (external power FET)

VR3 Switch node connection

DRVLVR3

PGNDVR3

FBVR3P

O

-

VR3 Low side gate drive output (external power FET)

VR3 Power GND

A10

C10

I

VR3 Remote positive feedback sense (Connect to vout of

VR3 at output load capacitor)

FBVR3N

ILIMVR3HS

ILIMVR3LS

VINVR3

D7

D10

C9

E8

I

VR3 Remote negative feedback sense (Connect to GND of

VR3 at output load capacitor)

E12

E10

H11

VR3 Current limit setting, high-side FET peak current

sense

VR3 Current limit setting, low-side FET valley current

sense

G9

VR3 Input voltage sense and high-side current-sense

kelvin (Connect to drain of high-side FET)

ENVR3

PGVR3

NVDCZ

E9

B9

H9

D11

B11

K9

I

O

I

VR3 Enable

VR3 Power good comparator output

NVDC select [two-level: Low = NVDC, High = non-NVDC].

Connect NVDCZ to GND for NVDC, Connect NVDCZ to

LDO3 for non-NVDC

VBSTVR4

DRVHVR4

SWVR4

B3

A2

A3

A5

A4

C3

C4

A3

A4

A6

A5

F5

I

O

I

VR4 Bootstrap pin

VR4 High side gate drive output (external power FET)

VR4 Switch node connection

DRVLVR4

PGNDVR4

FBVR4P

O

-

VR4 Low side gate drive output (external power FET)

VR4 Power GND

I

VR4 Remote positive feedback sense (Connect to vout of

VR4 at output load capacitor)

FBVR4N

D5

B4

E6

B5

I

VR4 Remote negative feedback sense (Connect to GND of

VR4 at output load capacitor)

VREGVR4

VR4 5V drive supply input (shorted on board with LDO5V),

shared with VR3

6

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Pin Functions (continued)

I/O

DESCRIPTION

ZAJ PACKAGE

NUMBER

ZCG PACKAGE

NUMBER

NAME

ILIMVR4

D2

F3

I

VR4 Current limit setting, low-side FET valley current

sense

ENVR4

DDRID

C2

D4

B2

C2

I

VR4 Enable

VR4 Output voltage selection . Low = 1.2V, High = 1.35V,

Float = 1.1V

PGVR4

VBSTVR5

DRVHVR5

SWVR5

B5

M3

M1

N2

N4

N3

L7

C6

R4

T3

T4

T6

T5

N8

O

I

VR4 Power good comparator output

VR5 Bootstrap pin

O

I

VR5 High side gate drive output (external power FET)

VR5 Switch node connection

DRVLVR5

PGNDVR5

VINVR5

O

-

VR5 Low side gate drive output (external power FET)

VR5 Power GND

I

VR5 Input voltage sense and high-side current-sense

kelvin (Connect to drain of high-side FET)

FBVR5P

FBVR5N

G4

L4

K5

L5

J6

H5

M7

N6

I

VR5 Remote positive feedback sense (Connect to vout of

VR5 at output load capacitor)

VR5 Remote negative feedback sense (Connect to GND of

VR5 at output load capacitor)

ILIMVR5HS

ILIMVR5LS

VR5 Current limit setting, high-side FET peak current

sense

VR5 Current limit setting, low-side FET valley current

sense

ENVR5

PGVR5

M2

M4

R2

B6

I

O

I

VR5 Enable

VR5 Power good comparator output

LDO1 Enable

DDR_VTT_CTRL

VINLDO1

E3

E4

A6, B6

F9

A7, B7

H9

I

LDO1 Input supply

VINLDO1S

I

LDO1 Input voltage reference kelvin sense (Connect to

vout of VR4 at output load capacitor)

VOUTLDO1

FBLDO1

A8, B8

D8

A9, B9

F9

O

I

LDO1 Output voltage, VOUTLDO1 = (1/2 * VINLDO1SNS)

LDO1 Feedback voltage kelvin sense, (Connect to vout of

LDO1 at output load capacitor)

PGNDLDO1

SCLK

A7, B7

J1

A8, B8

M1

-

I

LDO1 Power GND

I2C Clock

SDA

H1

K1

I/O

I

I2C Data

SLAVEADDR

L3

N4

I2C Slave Address select (low = GND = 0x30, high = 3.3V

= 0x32, open = float = 0x34) Keep same connection during

operation

VDDPG

VSA

D1

E7

G2

F7

I

PGx supply, sets output level for PG pins

Power good comparator input and discharge path for

external rail

ENA

PGA

B12

D6

B15

C12

I

Enable for VSA power good comparator

O

Power good comparator output, OD or level shifted to

VDDLV

VSB

K9

M9

I

Power good comparator input and discharge path for

external rail

ENB

PGB

C11

C5

D13

A10

I

Enable for VSB power good comparator

O

Power good comparator output, OD or level shifted to

VDDLV

VSC

ENC

K8

L8

I

Power good comparator input and discharge path for

external rail

C12

D15

Enable for VSC power good comparator

7

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

ZAJ PACKAGE

NUMBER

ZCG PACKAGE

NUMBER

NAME

PGC

C6

D7

O

I

Power good comparator output, OD or level shifted to

VDDLV

VSD

E6

L10

Power good comparator input and discharge path for

external rail

END

PGD

J13

H3

L16

J4

I

Enable for VSD power good comparator

O

Power good comparator output, OD or level shifted to

VDDLV

VSE

F4

G6

I

Power good comparator input and discharge path for

external rail

ENE

PGE

F10

C4

J12

D5

I

Enable for VSE power good comparator

O

Power good comparator output, OD or level shifted to

VDDLV

VSF

E8

J8

I

Power good comparator input and discharge path for

external rail

ENF

PGF

J12

H4

L14

K5

I

Enable for VSF power good comparator

O

Power good comparator output, OD or level shifted to

VDDLV

VSG

J10

K7

I

Power good comparator input and discharge path for

external rail

ENG

PGG

B10

F3

C14

G4

I

Enable for VSG power good comparator

O

Power good comparator output, OD or level shifted to

VDDLV

VSH

F5

N5

G8

T7

I

Power good comparator input and discharge path for

external rail

VIN5VSW

Internal load switch from 5V switching regulator to LDO5

output. Connect VIN5VSW to 5V switching regulator

output.

PGH

M6

R8

O

Power good comparator output, OD or level shifted to

VDDLV

ENLVA

L8

L6

N10

P5

I

LVx buffer supply, sets output level for PG pins

Enable level shifter A Pin not connected electrically.

Connect to Ground. (Level Shifter A input is ACOK pin)

LVA

LVB

L12

L10

M5

N14

N12

P7

O

I

Level shifter A open-drain output, used for BC_ACOK

output level shifted to EC_VCC. Input is from ACOK pin

Level shifter B push-pull output, level shifted to VDDLV.

Input is from ENH pin

EN5VSW

Enable Internal load switch from 5V switching regulator to

LDO5 output through VIN5VSW. Connect to powergood of

5V switching regulator.

ENH

L11

H2

K2

P13

L2

I

Input to LS B general purpose level shifter.

PWRBTNIN

Power button input (internal pull-up to LDO3) (logic low)

PCH_PWRBTNZ

N2

O

Power button signal to PCH (level-shifted DSW domain)

(logic low)

EC_ONOFFZ

1HZ

K4

K11

H10

J4

M5

M13

L12

L6

O

I

Debounced version of PWRBTNIN (logic low)

1Hz clock output for waking up embedded controller, EC.

VCOMP comparator push-pull output

TRIPZ

VCOMP

VCOMP comparator input (Also used for TMODE - > 5.5V)

Resume Reset Power Good

RSMRSTZ_PWR

GD

J11

F16

O

ALL_SYS_PWRG

D

G11

E11

F15

G14

O

Non-core rails power good

PCH_PWROK

Core and Non Core Power Good

8

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Pin Functions (continued)

I/O

DESCRIPTION

ZAJ PACKAGE

NUMBER

ZCG PACKAGE

NUMBER

NAME

SYS_PWROK

DPWROK

DS3_VREN

VCCST_PWRGD

EC_RSTZ

ACOK

H11

K12

K13

E4

K13

M15

M16

C1

O

I

Delayed ALL_SYS_PWRGD

Delayed version of V3.3A_DSW_PG

DS3 VR enable (enables external power switch)

VCCST Power Good

J3

L4

EC reset (logic low)

D11

L1

F13

P1

ACOK input

ECVCC

I

EC VCC supply

BAT1

F1

H1

I

Battery 1 voltage sense input

BAT1SWONZ

F2

J2

O

Battery 1 low voltage status (OD) or Battery 1 switch ON

(PP, VIN level) (logic low)

BAT2

G1

G2

J1

I

Battery 2 voltage sense input

BAT2SWONZ

K3

O

Battery 2 low voltage status (OD) or Battery 2 switch ON

(PP, VIN level) (logic low)

ACIN

E2

J2

H3

M3

I

AC Adaptor voltage sense

ACSWONZ

O

AC adapter low voltage status (OD) or AC adapter switch

ON (PP, VIN level) (logic low)

VINPP

E5

H7

I

VIN for Power Path Domain. Connect to external diode OR

from: AC, BAT1, BAT2

VDCSNS

PMIC_INTZ

VBATTBKUP

V3P3A_RTC

VIN

G3

D12

B13

C13

N6

G1

E14

C16

D16

T8

I

O

I

VDC voltage monitor

PMIC to EC interrupt (logic low)

RTC backup battery supply connection

PCH RTC power supply

O

I

IC input voltage

VINLDO3

AGND1

M8

C1

R10

E1

I

LDO3 Iiput supply

-

Analog GND1 - tie directly to the ground plane

Analog GND2 - tie directly to the ground plane

Analog GND3 - tie directly to the ground plane

Analog GND4 - tie directly to the ground plane

5V internal supply used primarily for the gate drives

AGND2

K1

N1

-

AGND3

L13

D13

N7

N16

E16

T9

-

AGND4

-

LDO5V

O

LDO3V

N8

T10

3.3V LDO used as a reference voltage, and as a pull-up

supply.

EN3V3SW

K3

L1

P9

I

Enable for load switch from LDO3V pin to VOUT3V3SW

output pin

VOUT3V3SW

M7

O

EC domain load switch output and discharge path from

LDO3V

STANDBYZ

SHUTDOWNZ

RESETZ

D9

C7

C8

C10

C8

I

Set rails in standby (low power mode)

Set shutdown mode (all supplies off) (logic low)

D9

O

Global disable output for external converters/power tree

(logic low)

VDDIO

E1, M13

F1, P16

I

Voltage supply input for I/O buffers. VDDIO should be tied

to LDO3 (3.3V)

VREF1V25

B1

L2

D1

P3

O

decoupling cap connection for internal voltage reference

TEMP_ALERTZ

Open-drain output of silicon temperature sensor. Input to

Power Monitor Unit (connect to PROCHOT# of system).

Active low, pull-up to V1.00S with 50ohm

VDD5

VPROGOTP

D3

I

Always connect to LDO5. supply voltage for OTP

programming (must be connected to LDO5V in normal

operation)

9

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

ZAJ PACKAGE

NUMBER

ZCG PACKAGE

NUMBER

NAME

DEPOPULATED

BALL - PICK-N-

PLACE

B2

C3 (also used for

via - see below)

DEPOPULATED PICK-N-PLACE INDICATOR

BALL

INDICATOR

NC POPULATED A1, A13, N1, N13 A1, A2, B1, A15,

POPULATED

BALL

CORNERS - solder to PCB for mechanical strength

BALL -

A16, B16, R16,

T16, T15, R1, T1,

T2

CORNERS

DEPOPULATED No Depopulated B3, B4, B6, B10,

DEPOPULATED VIA PLACEMENT FOR INTERNAL BALL ROUTES - For

BALL - FOR VIAS Balls for Vias in

7x7. Type 4 PC

put micro-vias

B12, B14, C3,

C5, C7, C9, C11,

C13, C15, D2,

D4, D6, D8, D10,

D12, D14, E2,

E3, E5, E7, E9,

E11, E13, E15,

F2, F4, F6, F8,

F10, F12, F14,

G3, G5, G7, G9,

G11, G13, G15,

H2, H4, H6, H8,

H10, H12, H14,

J3, J5, J7, J9,

J11, J13, K2, K4,

K6, K8, K10, K12,

K14, L3, L5, L7,

L9, L11, L13,

BALL

Type3 PCBs, put a plated through-hole (PTH) via at each

depopulated ball, to connect to the internal row balls.

under each ball

pad

L15, M2, M4, M6,

M8, M10, M12,

M14, N3, N5, N7,

N9, N11, N13,

N15, P2, P4, P6,

P8, P10, P12,

P14, P15, R3,

R5, R7, R9, R11,

R13,

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TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX UNIT

CHIP

Power input pins

VIN, VINLDO3

-0.3

28

V

Analog ground pins

AGND1, AGND2, AGND3, AGND4

0.3

SWITCHING REGULATORS

Input pins - controllers

Switch pins - controllers

High drive pins - controllers

Low drive pins - controllers

Bootstrap pins - controllers

Input pin - converter

VINVR3, VINVR5

-0.3

-1

28

V

SWVR1 , SWVR3 , SWVR4 , SWVR5

DRVHVR1, DRVHVR3, DRVHVR4, DRVHVR5

DRVLVR1, DRVLVR3, DRVLVR4, DRVLVR5

VBSTVR1, VBSTVR3, VBSTVR4, VBSTVR5

Differential voltage between VBSTVRx and SWVRx

VINVR2

-0.3

32

7

32

7

3.6

0.3

3.6

5.7

0.3

5.7

3.6

Switch pins - converter

Power ground pins

SWVR2

PGNDVR1, PGNDVR2, PGNDVR3, PGNDVR4, PGNDVR5

ENVR1, ENVR2, ENVR3, ENVR4, ENVR5

NVDCZ

Enable pins

NVDC select pin

Positive remote feedback pins

Positive remote feedback pin

Negative remote feedback pins

Gate drive regulator input power pins

Low-side current limit

High-side current limit

LDO REGULATOR

FBVR1P, FBVR2P, FBVR3P, FBVR4P

FBVR5P

FBVR1N, FBVR2N, FBVR3N, FBVR4N, FBVR5N

VREGVR1 (1_5), VREGVR2, VREGVR4 (3_4)

ILIMVR1, ILIMVR3LS, ILIMVR4, ILMVR5LS

ILMVR3HS, ILMVR5HS

Input pin

VINLDO1

-0.3

3.6

0.3

3.6

V

Output pin

VOUTLDO1

PGNDLDO1

VINLDO1S

FBLDO1

Power ground pin

Input feedback pin

Output feedback pin

I2C

SCLK, SDAT, SLAVEADDR

POWERGOOD COMPARATOR LOGIC

-0.3

3.6

V

Powergood (push/pull) supply for input

pins

VDDPG

Powergood input voltage sense pins

Powergood enable pins

VSA, VSB, VSC, VSD, VDE, VSF, VSG, VSH

ENA, ENB, ENC, END, ENE, ENF, ENG, ENH

-0.3

5.7

3.6

V

Powergood output pins

PGA, PGB, PGC, PGD, PGE, PGF, PGG, PGH, PGVR1, PGVR2,

PGVR3, PGVR4, PGVR5

POWERGOOD TREE LOGIC

Open-drain outputs

DPWROK, RSMRSTZ_PWRGD, VCCST_PGOOD,

SYS_PWROK, ALL_SYS_PWRGD, PCH_PWROK

-0.3

3.6

V

DDR CONTROL

Input pins

DDR_VTT_CTRL, DDRID

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

MAX UNIT

Absolute Maximum Ratings (continued)

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

LEVEL SHIFTERS

Level shifter (push/pull) supply input pin

Level shifter enable input pins

Level shifter output pins

VDDLV

ENLVA

-0.3

3.6

V

LVA, LVB

POWER PATH LOGIC

Power path comparator input voltage

sense pins

VCOMP, BAT1, BAT2, ACIN

-0.3

7

V

Power path comparator open-drain output BAT1SWONZ, BAT2SWONZ, ACSWONZ

pins

28

3.6

28

PTC over-temperature comparator open-

drain output pin

TRIPZ

Power path domain diode OR input pin

VINPP

POWER BUTTON

PWRBNTIN, PCH_PWRBTNZ, EC_ONOFFZ

RESETS

-0.3

3.6

V

ECVCC, RESETZ, EC_RSTZ

CLOCKS

EC wake clock: 1HZ

POWER MONITOR

VDCSNS

-0.3

28

3.6

12

V

TEMP_ALERTZ

ACOK

REFERENCE

LDO output pins

LDO5V

-0.3

7

V

LDO output pins

VREF1V25, LDO3V

EN3V3SW

3.6

7

3.3V load switch enable pin

3.3V load switch output pin

5V load switch enable pin

5V load switch input pin

BACKUP BATTERY RTC SELECTOR

VBATTBKUP, V3P3A_RTC

MISC

VOUT3V3SW

EN5VSW

VIN5VSW

-0.3

3.6

V

Input control pins

STANDBYZ, SHUTDOWNZ

PMIC_INTZ

-0.3

3.6

7

V

Output alert pin

Output DS3 VR enable pin

Buffers supply input pin

VPROGOTP

DS3_VREN

VDDIO

GENERAL

Operating junction temperature, T_J

Storage temperature, T_stg

–40

–65

150

°C

7.2 ESD Ratings

VALUE

1000

500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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TPS650830

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ZHCSDM1 –DECEMBER 2014

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

CHIP

Power input pins: VIN, VINLDO3

-0.3

21

V

Analog ground pins: AGND1, AGND2, AGND3, AGND4

SWITCHING REGULATORS

0.3

Input pins - controllers: VINVR3, VINVR5

-0.3

-1

21

26

5

V

Switch pins - controllers: SWVR1 , SWVR3 , SWVR4 , SWVR5

High drive pins - controllers: DRVHVR1, DRVHVR3, DRVHVR4, DRVHVR5

Low drive pins - controllers: DRVLVR1, DRVLVR3, DRVLVR4, DRVLVR5

Bootstrap pins - controllers: VBSTVR1, VBSTVR3, VBSTVR4, VBSTVR5

Bootstrap pins - controllers: (differential voltage between VBSTVRx and SWVRx):

Input pin - converter: VINVR2

-0.3

26

5

3.3

0.3

3.3

5

Switch pins - Converter: SWVR2

Power ground pins: PGNDVR1, PGNDVR2, PGNDVR3, PGNDVR4, PGNDVR5

Enable pins: ENVR1, ENVR2, ENVR3, ENVR4, ENVR5

NVDC select pin: NVDCZ

Positive remote feedback pins: FBVR1P, FBVR2P, FBVR3P, FBVR4P

Positive remote feedback pin: FBVR5P

3.3

0.3

5

Negative remote feedback pins: FBVR1N, FBVR2N, FBVR3N, FBVR4N, FBVR5N

Gate drive regulator input power pins: VREGVR1 (1_5), VREGVR2, VREGVR4 (3_4 )

Low-side current limit: ILIMVR1, ILIMVR3LS, ILIMVR4, ILMVR5LS

High-side current limit: ILMVR3HS, ILMVR5HS

LDO REGULATOR

3.3

Input pin: VINLDO1

-0.3

3.3

1.65

0.3

V

Output pin: VOUTLDO1

Power ground pin: PGNDLDO1

Input feedback pin: VINLDO1S

3.3

Output feedback pin: FBLDO1

1.65

I2C

SCLK, SDAT, SLAVEADDR

-0.3

3.3

V

POWERGOOD COMPARATOR LOGIC

Powergood (push/pull) supply for input pins: VDDPG

Powergood input voltage sense pins: VSA, VSB, VSC, VSD, VDE, VSF, VSG, VSH

Powergood enable pins: ENA, ENB, ENC, END, ENE, ENF, ENG, ENH

-0.3

3.3

5

V

3.3

Powergood output pins: PGA, PGB, PGC, PGD, PGE, PGF, PGG, PGH, PGVR1, PGVR2, PGVR3, PGVR4,

PGVR5

POWERGOOD TREE LOGIC

Open-drain outputs: DPWROK, RSMRSTZ_PWRGD, VCCST_PGOOD, SYS_PWROK, ALL_SYS_PWRGD,

PCH_PWROK

-0.3

3.3

V

DDR CONTROL

Input pins: DDR_VTT_CTRL, DDRID

LEVEL SHIFTERS

Level shifter (push/pull) supply input pin: VDDLV

Level shifter enable input pins: ENLVA

Level shifter output pins: LVA, LVB

-0.3

3.3

V

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TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

MAX UNIT

Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)

MIN

POWER PATH LOGIC

Power path comparator input voltage sense pins: VCOMP, BAT1, BAT2, ACIN

Power path comparator open-drain output pins: BAT1SWONZ, BAT2SWONZ, ACSWONZ

PTC over-temperature comparator open-drain output pin: TRIPZ

Power path domain diode or input pin: VINPP

POWER BUTTON

-0.3

5

V

21

3.3

21

PWRBNTIN, PCH_PWRBTNZ, EC_ONOFFZ

RESETS

-0.3

3.3

V

ECVCC, RESETZ, EC_RSTZ

CLOCKS

EC Wake Clock: 1HZ

POWER MONITOR

VDCSNS

-0.3

21

3.3

V

TEMP_ALERTZ

ACOK

REFERENCE

LDO output pins: LDO5V

-0.3

5

V

LDO output pins: VREF1V25, LDO3V

3.3V load switch enable pin: EN3V3SW

3.3V load switch output pin: VOUT3V3SW

5V load switch enable pin: EN5VSW

5V load switch input pin: VIN5VSW

BACKUP BATTERY RTC SELECTOR

VBATTBKUP, V3P3A_RTC

3.3

5

-0.3

3.3

V

MISC

Input control pins: STANDBYZ, SHUTDOWNZ

Output alert pin: PMIC_INTZ

Output DS3 VR enable pin: DS3_VREN

Buffers supply input pin: VDDIO

VPROGOTP

-0.3

3.3

5

V

GENERAL

Operating free air temperature, T_A

Operating junction temperature, T_J

–40

85

°C

125

7.4 Thermal Information

TPS650830

ZAJ (168 PINS) ZCG (159 PINS)

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

37.7

15.1

11.8

0.3

34.7

15.1

13.7

0.3

R_θJC(top)

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

11.7

N/A

13.8

N/A

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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TPS650830

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ZHCSDM1 –DECEMBER 2014

7.5 Electrical Characteristics

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONTROL

CONTROL - SYSTEM

V_VDCParametric System input voltage

V_VDCFunctional System input voltage

Parametric and functional

5.4

7.4

21

24

V

Functional

System quiescent current (includes

IDDQ for LDO5V, LDO3V, and

VREF1.25V, all registers are

default setting)

I_Q

Measured at VIN = 7.4V

95

150

μA

System under voltage lockout

threshold - All IC functionality

including 5VLDO, except LDO3

and internal refsys

V_{UVLO_5V_Main}

V_VDCvoltage decreasing (falling edge)

V_VDCvoltage increasing

4.95

4.9

5.1

200

5.0

5.25

V

mV

V

System under voltage lockout

threshold hysteresis

V_{Hys_5V_Main}

CONTROL - INTERNAL REFERENCES

V_O(VLDO5)

VLDO5 output

VIN = 5.4V - 21V, 10mA load

5.1

VIN = 5.4V to 21V, Measured as

Line regulation

V_O(LDO5V)

Line regulation for regulator over

operating voltage range

(ΔV_O(LDO5V)/V_O(LDO5V)) over this operating

range with 40mA load current. measured

at VLDO5V pin with respect to AGND pin

0.5%

VIN = 5.4V - 21V Measured as

(ΔV_O(LDO5V)/V_O(LDO5V)) over this operating

range with 10mA to 100mA load current.

measured at VLDO5V pin with respect to

AGND pin

Load regulation Load regulation for regulator over

2%

V_O(LDO5V)

I_{SC (LDO5V)}

C_{O (LDO5V)}

operating current range

Over current protection

External output capacitance

Measured at 0.9x the regulation voltage

115

2.7

mA

Actual capacitance after derating. ex: 2uF

capacitance, then use a 4.7uF capacitor

with 60% derating. Recommended Part

number:

4.7

1.25

0.22

10

1.256

0.47

μF

See below for output capacitance.

measured at VREF1V25 pin with respect

to AGND pin

VREF1V25 output - Internal

buffered bandgap output

V_O(VREF1V25)

1.244

0.2

V

Actual capacitance after derating. ex:

0.2uF capacitance, then use a 0.47uF

capacitor with 60% derating.

C_{O (VREF1V25)}

External output capacitance

μF

Recommended part number:

V_I(LDO3V)

V_O(LDO3V)

LDO3V input

LDO3V output

Parametric and functional

Functional

5.4

3.45

7.4

3.3

21

24

V

VIN = 7.4V, 1mA load

3.267

3.333

Maximum current for external user is

limited 40mA

I_{O (LDO3V)}

Output current

40

0.5%

mA

I_{SC (LDO3V)}

Output circuit current limit

Measured at 0.9x VOREG

75

VIN = 5.4V to 21V, Measured as

Line regulation

V_O(LDO3V)

Line regulation for regulator over

operating voltage range

(ΔV_O(LDO3V)/V_O(LDO3V)) over the operating

range with 20mA load current. measured

at VLDO3V pin with respect to AGND pin

VIN = 7.4 Measured as

(ΔV_O(LDO3V)/V_O(LDO3V)) over this operating

range with 0mA to 50mA load current.

measured at VLDO3V pin with respect to

AGND pin

Load regulation Load regulation for regulator over

V_O(LDO3V)

operating current range

C_{O (LDO3V)}

T_{R (LDO3V)}

External output capacitance

Rise time

2.2

4.7

10

μF

μs

Measured from 5% to 95% of the output

with 2.2μF

300

450

15

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONTROL - INPUT/ OUTPUT BUFFERS

CONTROL - DDR_VTT_CTRL (Intel external connection DDR_VTT_CTRL) - 1V logic, tolerates 3V

V_{IL_DDR_VTT_CTR}

L

DDR_VTT_CTRL input low voltage Input low voltage threshold

0.49

V

V_{IH_DDR_VTT_CTR}DDR_VTT_CTRLL input high

Input high voltage threshold

0.61

voltage

L

V_{HYST_DDR_VTT_}DDR_VTT_CTRLL hysteresis

Hysteresis voltage

70

mV

μA

voltage

CTRL

I_{leakage_DDR_VTT_}

DDR_VTT_CTRL input current

Input current, Clamped to 1.0V

0.01

0.2

CTRL

CONTROL - INPUT TTL BUFFERS (ALL INPUT PINS), (DEFAULT: SHUTDOWNZ, STANDBYZ, ENLVA, EN3V3SW, EN5VSW, ENVR1,

ENVR2, ENVR3, ENVR4, ENVR5, ENA. ENB, ENC, END, ENE, ENF, ENG, ENH), (OPTIONAL: VSA, VSB, VSC, VSD, VSE, VSF, VSG,

VSH, ENLVA, ENLVB)

V_{IL_INPUTS}

Input low voltage

0.4

V

V_{IH_INPUTS}

Input high voltage

Hysteresis voltage

Input current

1.2

V_{HYST_INPUTS}

I_{leakage_INPUTS}

V_{IL_PWRBTNZ}

300

mV

μA

V

Clamped on 3.3V

0.01

0.3

0.4

Input low voltage for PWRBTNZ

Internal 5kohm pull-up resistor between

PWRBTNZ pin and VDDIO

V_{IH_PWRBTNZ}

Input high voltage for PWRBTNZ

1.6

V

V_{HYST_PWRBTNZ}Hysteresis voltage for PWRBTNZ

Output current for PWRBTNZ

580

660

mV

PWRBTNZ = GND, Internal 5kohm pull-

up resistor between PWRBTNZ pin and

VDDIO

when power button is pressed to

close and pulling PWRBTNZ to

I_{Output_PWRBTNZ}

790

μA

GND.

Time set to 0 ms, Measured from 0.5%

PWBTNZ rising to 5% of the

EC_ONOFFZ output

T_{EC_ONOFFZ_Debo}EC_ONOFFZ_Debounce time, 0

0

ms

setting

uinc_0e

Time set to 30 ms, Measured from 0.5%

PWBTNZ rising to 5% of the

EC_ONOFFZ output

T_{EC_ONOFFZ_Debo}EC_ONOFFZ_Debounce time, 30

30

ms setting

uinc_30e

CONTROL - PUSH-PULL OUTPUTS (ALL OUTPUT PINS), (DEFAULT: RESETZ, 1HZ, DS3_VREN), (OPTIONAL: PGVR1, PGVR2,

PGVR3, PGVR4, PGVR5, PGA, PGB, PGC, PGD, PGE, PGF, PGG, PGH) Pull-Up Rail = VDDIO connect to LDO3 = 3.3V

Pulled-Up to VDDIO pin which should by

tied to LDO3 pin = 3.3V

V_PP

Pull-up output voltage supply

Low level output voltage

High level output voltage

VDDIO

V

V_{OL_PP}

V_{OH_PP}

I_OL= 3 mA

0.6

VDDIO

- 0.6

I_OH= 3 mA

CONTROL - PUSH-PULL OUTPUTS (DEFAULT: LVA, LVB) Pull-Up Rail = VDDLV

Pulled up to VDDLV pin which could by

tied to 3.3V or lower

V_{PP_VDDLV}

V_{OL_PP_LV}

V_{OH_PP_LV}

LV pull-up output voltage supply

LV low level output voltage

LV high level output voltage

VDDLV

V

I_OL= 3 mA

0.6

VDDLV

- 0.6

I_OH= 3 mA

CONTROL - OPEN-DRAIN OUTPUT(ALL OUTPUT PINS), (DEFAULT: ACSWONZ, BAT1SWONZ, BAT2SWONZ, PGVR1, PGVR2,

PGVR3, PGVR4, PGVR5, PGA, PGB, PGC, PGD, PGE, PGF, PGG, PGH, VCCST_PWRGD, SYS_PWROK, PCH_PWROK,

RSMRSTZ_PWRGD, ALL_SYS_PWRGD, PMIV_INTZ, EC_RSTZ, PCH_PWRBTNZ, EC_ONOFFZ, DPWROK), (OPTIONAL: LVA, LVB)

V_{OL_OD1}

I_{LK_OD1}

OD- output voltage

OD leakage current

I_OL= 2 mA

0.4

V

V_(PIN)= 3.3V

0.45

μA

16

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONTROL - OPEN-DRAIN OUTPUTS (TEMP_ALERT) External pull-up resistor can be 75 ohm to 1V when connected to PROCHOTz

of Intel System

Open-drain low level output

voltage

V_{OL_OD}

I_OL= 15 mA

0.165

0.35

V

I_{LK_OD}

Open-drain leakage current

V_(PIN)= 3.3V

μA

CONTROL - TRISTATE INPUT BUFFER (SLAVEADDR, DDRID)

V_{IL_TRISTATE}

V_{IH_TRISTATE}

I_TRISTATE

Low level input voltage

High level input voltage

I_TRISTATEcurrent

I_OL= 6 μA

0.33

V

I_OH= 6 μA

1.8

Allowable current when floating

-0.650

0.675

μA

CONTROL - VSA, VSB, VSC, VSD, VSE, VSF, VSG, VSH (ALL LOADSWITCH POWERGOOD COMPARATORS)

When VSx configured as voltage sense

input

VSx input voltage range

0.7

106%

90%

1.8

5

9

V

When VSx configured as voltage sense

input, VSx = 5.7V

VSx input leakage current

Power good threshold high VSx

μA

When VSx configured as voltage sense

input and powergood window comparator.

108%

-3%

92%

3%

110%

Power good threshold high VSx

hysteresis

When VSx configured as voltage sense

input and powergood window comparator.

When VSx configured as voltage sense

input and powergood window comparator.

Power good threshold low VSx

94%

Power good threshold low VSx

hystersis

When VSx configured as voltage sense

input and powergood window comparator.

EMBEDDED CONTROLLER RESET

V_{OL_OD}

EC_RSTZ output low voltage

I_OL= 2mA, V_{EC_RST}= 3.3V

0.4

0.2

V

Output buffer in open-drain mode,

V_{EC_RST}= 3.3V

I_{LKG_OD}

EC_RSTZ leakage current

0.01

µA

EC_RST time duration (Trst)

Reset Timer register value: 00

Reset Timer register value: 01

Reset Timer register value: 10

20

40

80

ms

EC_RST time duration (Trst) -

Default setting

Reset Timer register value: 11

200

ms

µA

V

I_LK

ECVCC input queiscent current

3

Reset Voltage Threshold register value:

000

ECVCC voltage threshold (Vth)

1.344

1.44

1.4

1.5

1.6

1.7

2.4

2.6

2.8

3.0

1.456

Reset Voltage Threshold register value:

001

ECVCC voltage threshold (Vth)

1.56

1.664

1.768

2.496

2.704

2.912

3.12

V

Reset Voltage Threshold register value:

010

1.536

1.632

2.304

2.496

2.688

2.88

Reset Voltage Threshold register value:

011

Reset Voltage Threshold register value:

100

Reset Voltage Threshold register value:

101

Reset Voltage Threshold register value:

110

Reset Voltage Threshold register value:

111

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TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER PATH COMPARATORS (ACIN, BAT1, BAT2)

Output low saturation voltage for

open-drain logic output pin

(TRIPZ)

Comparator input voltage > internal

reference voltage. Output pulling low,

Sink current = 5mA

0.5

V

IOUT VCOMP- internal current

source

Current out of the VCOMP pin when

IOUT VCOMP enabled

9.5

10

1.223

61

10.6

μA

V

VREF_VCOMP_rising, internal

reference voltage

Rising voltage at VCOMP pin, changes

TRIPZ to logic low

1.211

1.235

VHYST VCOMP_falling, internal

hysteresis voltage

Falling voltage at VCOMP pin, changes

TRIPZ to logic high

mV

Output low saturation voltage for

open-drain logic output pin

(acswONZ, BAT1SWONZ,

BAT2SWONZ)

Comparator input voltage > internal

reference voltage. Output pulling low,

Sink current = 5mA

0.5

0.1

V

Current into the ACIN, BAT1, or BAT2

ILKG_ACIN_BAT1_BAT2 - Current pins from 5.4V-24V (when pin is below,

leakage

μA

at, or above 6V internal protection

switch.)

VREF_ACIN_rising - Internal

reference voltage

Rising voltage at ACIN pin, makes

ACSWONZ trigger low

1.2365

1.25 1.2645

125

V

mV

V

Falling voltage with respect to

VREF_ACIN at ACIN pin, makes

ACSWONZ trigger high

VHYST_ACIN_falling - Internal

hysteresis voltage

VREF_BAT1_rising - Internal

reference voltage

Rising voltage at BAT1 pin, makes

BAT1SWONZ trigger low

1.25 1.2645

125

Falling voltage with respect to

VREF_BAT1 at BAT1 pin, makes

BAT1SWONZ trigger high

VHYST_BAT1_falling - Internal

hysteresis voltage

mV

V

VREF_BAT2_rising - Internal

reference voltage

Rising voltage at BAT2 pin, makes

BAT2SWONZ trigger low

1.25 1.2645

125

Falling voltage with respect to

VREF_BAT2 at BAT1 pin, makes

BAT2SWONZ trigger high

VHYST_BAT2_falling - Internal

hysteresis voltage

mV

Supply voltage (VDCSNS) monitor Supply voltage monitor register value

debounce VDLMTCRT[5:4]: 00

10

60

μs

Supply voltage(VDCSNS) monitor Supply voltage monitor register value

debounce

VDLMTCRT[5:4]: 11

Critical supply voltage threshold register

value VDLMTCRT[3:0]: 0001, Supply

Critical supply voltage (VDCSNS) voltage decreasing. With 2S resistor

1.18

1.2

20

1.22

V

falling threshold

divider from VDC to VDCSNS with 4R

top, R bottom. VDC = 6V when VDCSNS

pin = 1.2V.

Critical supply voltage hysteresis, Supply

voltage increasing. With 2S resistor

divider from VDC to VDCSNS with 4R

top, R bottom. VDC_hyst = 100mV when

VDCSNS_hyst pin = 20mV.

Critical supply voltage (VDCSNS)

rising threshold hysteresis

mV

18

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

AC-ADAPTER DETECTION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IL

V_IH

ACOK input low voltage

0.4

V

ACOK input high voltage

1.2

V

ACOK input current

ACOK = 3.3 V

0.01

61

0.1

95

13

25

36

μA

μs

ms

Adapter detection debounce time

ACOKDB register value: 00

ACOKDB register value: 01

ACOKDB register value: 10

ACOKDB register value: 11 default

50

7

10

15

24

20

30

CONVERTERS

VR1 POWER

Input voltage

Parametric and functional

Functional

5.4

7.4

21

24

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V100ACNT[7:6] =

2'b00, V100ACNT[5:4] = 2'b00 (default)

Output voltage - Default

Output voltage

1.05

1.00

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V100ACNT[7:6] =

2'b00, V100ACNT[5:4] = 2'b01

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V100ACNT[7:6] =

2'b00, V100ACNT[5:4] = 2'b10

Output voltage

0.975

0.950

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V100ACNT[7:6] =

2'b00, V100ACNT[5:4] = 2'b11

Output voltage

Power save mode enabled, SLP_S0Z =

L , V100ACNT[7:4] = 4'b01XX

Output voltage

0.850

0.900

0.950

V

Power save mode enabled, SLP_S0Z =

L , V100ACNT[7:4] = 4'b10XX

Power save mode enabled, SLP_S0Z =

L , V100ACNT[7:4] = 4'b11XX

R_TRIP= 10.56kΩ (programmable based

on external resistor), RDSON LS FET

7mΩ

Low-side output valley current limit

(programmed by external resistor)

7300

9400

12000

mA

current limit (Vsw - PGND)

V_TRIP= 0.8V

-110

45

-100

50

-90

55

mV

µA

I_LIM- Current limit pin source

current

T_A25℃

TC_ILIM- External FET Rdson

current limit temperature

coefficient

With respect to 25℃

4780

ppm/℃

V_ILIM- Current limit pin setting

voltage range

V_ILIM= R_TRIP*I_LIM

0.2

2

V

ULQ/Auto Mode, V_VIN= 5.4V to 21V, I_OUT

= I_MAX= 6.810A, Measured at the

regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

Maximum line regulation

Maximum load regulation

-0.5%

0.5%

feedback pins (FBVR1P - FBVR1N).

ULQ/Auto Mode, V_VIN= 7.4V, I_OUT= 0A

to I_MAX= 6.810A, Measured at the

regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

-0.5%

0.61%

feedback pins (FBVR1P - FBVR1N).

19

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC and AC, ULQ/Auto Mode, V_VIN= 5.4V

to 21V, I_OUT= 0A to 70% max load, 70%

max load to 0mA and I_OUT= 30% max

load to max load, max load to 30% max

load, di/dt = 2.5A/us

Maximum total output voltage load

transient variation

-5%

5%

PWM Mode (NVDCZ= 3.3V =

programmed to low switching frequency)

379

715

500

800

550

865

150

kHz

μs

VR1_Controller switching

frequency (7.4V)

PWM Mode (NVDCZ= GND =

programmed to high switching frequency)

Delay time from enable to first switching

pulse.

Start-up time

From first switching pulse to 95% of

VO(Min), Continuous slope (no slope

reversal).Ssee Cout spec

Output ramp-up tIme

1000

μs

VR1 MOSFET Drivers

DRVH resistance

DRVL resistance

Dead time

Source, IDRVH = -50mA

Sink, IDRVH = 50mA

3.0

2.0

3.0

0.8

10

4.5

3.5

4.5

2.0

Ω

Source, IDRVL = -50mA

Sink, IDRVL = 50mA

Ω

DRVH - off to DRVL - on

DRVL - off to DRVH - on

ns

Dead time

20

High-side driver minimum on-time DRVH - on

High-side driver minimum off-time DRVH - off

80

260

VR1 OUTPUT DISCHARGE

Output auto discharge resistance

Discharge register value: 00, Default

Discharge register value: 01

Discharge register value: 10

Discharge register value: 11

1000

90

kΩ

Ω

125

225

550

160

315

690

170

450

Ω

VR1_Controller Feedback input

resistance

Controller enabled

1

2.25

25

MΩ

VR1_Bootstrap switch ON

resistance (Rdson)

-40 ≤ T_A≤ 125°C

15

Ω

VR1 CONTROL

VR1_Power good threshold high

Fail when Vout increasing

105.5%

89.5%

130

108% 110.5%

-3%

VR1_Power good threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

VR1_Power good threshold low

Fail when Vout decreasing

92%

3%

94.5%

160

VR1_Power good threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

Overtemperature protection

Overtemperature hysteresis

145

10

°C

VR2 POWER

V_VINVR2power input voltage -

Parametric and functional

V_VINVR2voltage range, V_VIN= 5.4V to 21V

V_VINVR2voltage range, V_VIN= 5.4V to 24V

3.135

2.97

3.3

3.465

3.63

V

V_VINVR2power input voltage -

Functional

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V18ACNT[7:6] =

2'b00, V18ACNT[5:4] = 2'b00

Output voltage

1.854

V

20

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V18ACNT[7:6] =

2'b00, V18ACNT[5:4] = 2'b01

Output voltage

1.836

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V18ACNT[7:6] =

2'b00, V18ACNT[5:4] = 2'b10 (DEFAULT)

Output voltage - Default

Output voltage

1.8

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V18ACNT[7:6] =

2'b00, V18ACNT[5:4] = 2'b11

1.764

Power save mode enabled, SLP_S0Z =

L , V18ACNT[7:4] = 4'b01XX

Output voltage

1.728

1.746

1.764

V

Power save mode enabled, SLP_S0Z =

L , V18ACNT[7:4] = 4'b10XX

V

Power save mode enabled, SLP_S0Z =

L , V18ACNT[7:4] = 4'b11XX

V

Maximum average output current

range

V_VINVR2= 2.97V to 3.63V

2500

325

mA

Ripple current valley positive

current limit

1110

2450

1875

Low side valley cycle by cycle

positive current limit

2000

1400

Low side valley cycle by cycle

negative current limit

PFM valley current threshold

High side switch on resistance

Low side switch on resistance

V_VINVR2= 2.97V to 3.63V

90

30

125

105

95

mA

mΩ

V_VINVR2= 3.3V, 100% duty cycle

V_VINVR2= 3.3V, 0% duty cycle

ULQ/Auto Mode, V_VINVR2= 2.97V to

3.63V, I_OUT= Imax, ALL VOUTS,

Measured at the regulation point output

capacitor with Kelvin connections made

directly from the regulation point to the

differential feedback pins (FBVR2P -

FBVR2N).

Maximum line regulation

-0.5%

0.5%

1.0%

ULQ/Auto Mode, V_VINVR2= 2.97V to

3.63V, I_OUT= 0A to Imax, ALL VOUTS,

Measured at the regulation point output

capacitor with Kelvin connections made

directly from the regulation point to the

differential feedback pins (FBVR2P -

FBVR2N).

Maximum load regulation - PWM

Mode

ULQ/Auto Mode, V_VINVR2=2.97V to

3.63V, I_OUT= 0A to Imax, ALL VOUTS,

Measured at the regulation point output

capacitor with Kelvin connections made

directly from the regulation point to the

differential feedback pins (FBVR2P -

FBVR2N).

Maximum load regulation - AUTO

Mode

-0.65%

21

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC and AC, ULQ/Auto Mode, V_VINVR2

=

V2.97V to 3.63V, I_OUT= 0A to 70% max

load, 70% max load to 0mA, di/dt = 2.5

A/us, Measured at the regulation point

output capacitor with Kelvin connections

made directly from the regulation point to

the differential feedback pins (FBVR2P -

FBVR2N).

-5%

5%

Maximum total output voltage load

transient variation

DC and AC, ULQ/Auto Mode, V_VINVR2

=

2.97V to 3.63V, I_OUT= 30% max load to

max load, max load to 30% max load ,

di/dt = 2.5 A/us, Measured at the

regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

-5%

5%

feedback pins (FBVR2P - FBVR2N).

PWM Mode, I_OUT= 67% of max output

current

Switching frequency

1700

250

80

2000

860

100

200

500

2300

1450

120

KHz

kΩ

Ω

Discharge register value

DISCHGCNT3[7:6]: 00, Default

Output auto discharge resistance

Discharge register value

DISCHGCNT3[7:6]: 01

Discharge register value

DISCHGCNT3[7:6]: 10

160

400

240

Ω

Discharge register value

DISCHGCNT3[7:6]: 11

Output auto discharge resistance

Feedback input resistance

600

Ω

Enabled

3

MΩ

μA

Quiescent current associated with I_Vout= 0mA, enabled, at T_A=25°C Not

30

55

converter when enabled

switching, Measured at LDO3V,

VREGVR2

VR2 CONTROL

Power good threshold high

Fail when Vout increasing

106%

90%

120

108%

-3%

110%

94%

140

Power good threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

Power good threshold low

Fail when Vout decreasing

92%

3%

Power good threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

Over temperature protection THOT

°C

Over temperature hysteresis

THOT

10

Over temperature

protectionTSHUT

130

160

°C

Over temperature hysteresis

TSHUT

VR3 POWER

Input voltage

Parametric and functional

Functional

5.4

7.4

21

24

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V33ADSWCNT[7:6] =

2'b00, V33ADSWCNT[5:4] = 2'b00

Output voltage

3.399

3.366

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V33ADSWCNT[7:6] =

2'b00, V33ADSWCNT[5:4] = 2'b01

22

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V33ADSWCNT[7:6] =

2'b00, V33ADSWCNT[5:4] = 2'b10

(DEFAULT)

Output voltage - Default

3.3

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V33ADSWCNT[7:6] =

2'b00, V33ADSWCNT[5:4] = 2'b11

Output voltage

3.234

V

Power save mode enabled, SLP_S0Z =

L , V33ADSWCNT[7:4] = 4'b01XX

Output voltage

3.168

3.201

3.234

12645

V

Power save mode enabled, SLP_S0Z =

L , V33ADSWCNT[7:4] = 4'b10XX

Power save mode enabled, SLP_S0Z =

L , V33ADSWCNT[7:4] = 4'b11XX

V

High-side output peak current limit R_TRIP= 25kΩ (programmable based on

(programmed by external resistor) external resistor), RDSON HS FET 18mΩ

11500

13750

mA

High-side I_LIM- current limit pin

T_A= 25℃

44

50

-100

3300

56

µA

mV

source current

Current Limit (Vsw - PGND)

V_TRIP= 0.8V

-110

-90

High-side TC_ILIM- current limit

temperature coefficient

With respect to 25℃

ppm/℃

High-side V_ILIM- current limit pin

setting voltage range

V_ILIM= R_TRIP*I_LIM

0.2

6400

45

2

10500

55

V

RTRIP = 9.43kΩ (programmable based

on external resistor), RDSON LS FET

7mΩ

Low-side output valley current limit

(programmed by external resistor)

8420

mA

I_LIM- current limit pin source

current

T_A= 25℃

50

µA

ppm/℃

V

Low-side TC_ILIM- current limit

temperature coefficient

With respect to 25℃

V_ILIM= R_TRIP*I_LIM

4780

V_ILIM- current limit pin setting

voltage range

0.2

-10

2

Maximum range low side zero

crossing threshold

10

mV

ULQ/Auto Mode, V_VIN= 5.4V to 21V, I_OUT

= I_MAX, Measured at the regulation point

output capacitor with Kelvin connections

made directly from the regulation point to

the differential feedback pins (FBVR3P -

FBVR3N).

Maximum line regulation

Maximum load regulation

-0.5%

0.65%

0.55%

ULQ/Auto Mode, V_VIN= 7.4V, I_OUT= 0A

to I_MAX, Measured at the regulation point

output capacitor with Kelvin connections

made directly from the regulation point to

the differential feedback pins (FBVR3P -

FBVR3N).

DC and AC, ULQ/Auto Mode, V_VIN= 5.4V

to 21V, I_OUT= 0A to 70% max load, 70%

max load to 0mA and I_OUT= 30% max

load to max load, max load to 30% max

load, di/dt = 2.5A/us , Measured at the

regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

Maximum total output voltage load

transient variation

-5%

5%

feedback pins (FBVR3P - FBVR3N).

23

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM Mode (NVDCZ= 3.3V =

programmed to low switching frequency)

430

500

550

kHz

VR3_Controller switching

frequency

PWM Mode (NVDCZ= GND =

programmed to high switching frequency)

715

800

865

kHz

Time to start switching from enable to

95% of VO(Min), Continuous slope (no

slope reversal). see Cout spec

Total turn-on time (start-up time +

output ramp-up time)

1200

μs

VR3 MOSFET Drivers

DRVH resistance

DRVL resistance

Dead time

Source, IDRVH = -50mA

Sink, IDRVH = 50mA

3.0

2.0

3.0

0.8

10

4.5

3.5

4.5

2.0

Ω

Source, IDRVL = -50mA

Sink, IDRVL = 50mA

Ω

DRVH - off to DRVL - on

DRVL - off to DRVH - on

ns

Dead time

20

High-side driver minimum on-time DRVH - on

High-side driver minimum off-time DRVH - off

80

260

VR3 OUTPUT DISCHARGE

Output auto discharge resistance

Discharge register value: 00, Default

Discharge register value: 01

Discharge register value: 10

Discharge register value: 11

1000

90

kΩ

Ω

125

225

550

160

315

690

170

450

Ω

VR3_Controller feedback input

resistance

Controller enabled

1

2.25

MΩ

VR3_Bootstrap switch ON

resistance (Rdson)

T_A= 25°C

20

Ω

VR3_Controller HSD leakage

V_IN= 7.4 V, Controller disabled

1.55

μA

VR3 CONTROL

VR3_Power good threshold high

Fail when Vout increasing

105.5%

89.5%

130

108% 110.5%

-3%

VR3_Power good threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

VR3_Power good threshold low

Fail when Vout decreasing

92%

3%

94.5%

160

VR3_Power good threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

Overtemperature protection

Overtemperature hysteresis

145

10

°C

VR4 POWER

Input voltage

Parametric and functional

Functional

5.4

7.4

21

24

V

Power save mode disabled, Output

voltage select register value: 000

DDRID = 0V

Output voltage

1.236

1.224

1.212

1.200

V

Power save mode disabled, Output

voltage select register value: 001

DDRID = 0V

Power save mode disabled, Output

voltage select register value: 010

DDRID = 0V

Power save mode disabled, Output

voltage select register value: 011, default

DDRID = 0V

24

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power save mode disabled, Output

voltage select register value: 100

DDRID = 0V

Output voltage

1.188

V

Power save mode disabled, Output

voltage select register value: 101

DDRID = 0V

Output voltage

1.176

1.164

1.152

1.391

1.377

1.364

1.35

V

Power save mode disabled, Output

voltage select register value: 110

DDRID = 0V

Power save mode disabled, Output

voltage select register value: 111

DDRID = 0V

Power save mode disabled, Output

voltage select register value: 000

DDRID = 3.3V

Power save mode disabled, Output

voltage select register value: 001

DDRID = 3.3V

Power save mode disabled, Output

voltage select register value: 010

DDRID = 3.3V

Power save mode disabled, Output

voltage select register value: 011

DDRID = 3.3V

Power save mode disabled, Output

voltage select register value: 100, default

DDRID = 3.3V

1.337

1.323

1.310

1.296

1.082

1.133

1.111

1.1

Power save mode disabled, Output

voltage select register value: 101, default

DDRID = 3.3V

Power save mode disabled, Output

voltage select register value: 110

DDRID = 3.3V

Power save mode disabled, Output

voltage select register value: 111

DDRID = 3.3V

Power save mode disabled, Output

voltage select register value: 000

DDRID = Open

Power save mode disabled, Output

voltage select register value: 001

DDRID = Open

Power save mode disabled, Output

voltage select register value: 010

DDRID = Open

Power save mode disabled, Output

voltage select register value: 011

DDRID = Open

Power save mode disabled, Output

voltage select register value: 100, default

DDRID = Open

1.089

1.078

Power save mode disabled, Output

voltage select register value: 101, default

DDRID = Open

25

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power save mode disabled, Output

voltage select register value: 110

DDRID = Open

Output voltage

1.067

V

Power save mode disabled, Output

voltage select register value: 111

DDRID = Open

Output voltage

1.056

V

Low-side output valley current limit R_TRIP= 10.7kΩ (Programmable based on

(programmed by external resistor) external resistor), RDSON LS FET 7mΩ

7300

-110

45

9550

-100

50

12000

-90

mA

mV

µA

Current limit (Vsw - PGND)

V_TRIP= 0.8V

I_LIM- current limit pin source

current

T_A= 25℃

55

Low-side TC_LIM- current limit

temperature coefficient

With respect to 25℃

4780

ppm/℃

V_ILIM- current limit pin setting

voltage range

V_ILIM= R_TRIP*I_LIM

0.2

2

V

ULQ/Auto Mode, V_VIN= 5.4V to 21V, I_OUT

= I_MAX=7.5A, Measured at the regulation

point output capacitor with Kelvin

connections made directly from the

regulation point to the differential

Maximum line regulation

Maximum load regulation

-0.5%

0.5%

feedback pins (FBVR4P - FBVR4N).

ULQ/Auto Mode, V_VIN= 7.4V, I_OUT= 0A

to I_MAX=7.5A, Measured at the regulation

point output capacitor with Kelvin

connections made directly from the

regulation point to the differential

-0.5%

0.65%

feedback pins (FBVR4P - FBVR4N).

DC and AC, ULQ/Auto Mode, V_VIN= 5.4V

to 21V, I_OUT= 0A to 70% max load, 70%

max load to 0mA and I_OUT= 30% max

load to max load, max load to 30% max

load, di/dt = 2.5A/us , Measured at the

regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

Maximum total output voltage load

transient variation

-5%

5%

feedback pins (FBVR4P - FBVR4N).

PWM Mode (NVDCZ= 3.3V =

programmed to low switching frequency)

430

715

500

800

550

865

200

kHz

μs

VR4_Controller switching

frequency

PWM Mode (NVDCZ= GND =

programmed to high switching frequency)

Time to start switching from enable. See

Cout spec

Start-up time

Time to start switching from enable to

95% of VO(Min), Continuous slope (no

slope reversal). see Cout spec

Total turn-on time (start-up time +

output ramp-up time)

300

1025

μs

26

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

VR4 MOSFET DRIVERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DRVH resistance

DRVL resistance

Dead time

Source, IDRVH = -50mA

3.0

2.0

3.0

0.8

10

4.5

3.5

4.5

2.0

Ω

Sink, IDRVH = 50mA

Source, IDRVL = -50mA

Sink, IDRVL = 50mA

Ω

DRVH - off to DRVL - on

DRVL - off to DRVH - on

ns

Dead time

20

High-side driver minimum on-time DRVH - on

High-side driver minimum off-time DRVH - off

80

260

VR4 OUTPUT DISCHARGE

Output auto discharge resistance

Discharge register value: 00, Default

Discharge register value: 01

Discharge register value: 10

Discharge register value: 11

1000

90

kΩ

Ω

100

225

550

160

315

690

170

450

Ω

VR4_Controller feedback input

resistance

V10 controller enabled

T_A= 25°C

1

2.25

20

MΩ

VR4_Bootstrap switch ON

resistance (Rdson)

Ω

VR4 CONTROL

VR4_Power good threshold high

Fail when Vout increasing

105.5%

89.5%

130

108% 110.5%

-3%

VR4_Power good threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

VR4_Power good threshold low

Fail when Vout decreasing

92%

3%

94.5%

160

VR4_Power good threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

Overtemperature protection

Overtemperature hysteresis

145

10

°C

LDO1 POWER

Input voltage

Output voltage

Input voltage

Output voltage

Input voltage

Output voltage

DDRID = 0V

1.2

0.6

V

DDRID = 0V, VOUTLDO1 = (VINLDO1S)

/ 2

DDRID = 3.3V

1.35

0.675

1.1

DDRID = 3.3V, VOUTLDO1 =

(VINLDO1S) / 2

DDRID = Open

DDRID = Open, VOUTLDO1 =

(VINLDO1S)/ 2

0.55

I_OUT≤ 10 mA, 1.1V ≤ VINLDO1 ≤ 1.35V,

Output voltage relative to VINLDO1S / 2,

where VINLDO1S = FBVR4 = FBV10,

Load transient from 0mA to 70%*10mA,

dI/dt = 2.5 A/us

-20

-30

20

30

mV

Output voltage tolerance - AC and

DC transient load

I_OUT≤ 1 A, 1.1V ≤ VINLDO1 ≤ 1.35V,

VOUTLDO1 = Output voltage relative to

VINLDO1S / 2, where VINDO1S = FBVR4

= FBV10, Load transient from 0mA to

70%*1A, dI/dt = 2.5 A/us

Leakage current

T_A= 25°C, VIN13 = 1.2V, Disabled

5

µA

T_A= 25°C Bias current measured when

VINLDO13 is at 1.2V

Bias current at VIN13_SENSE

40

27

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Max current from LDO without exceeding

load regulation

LDO1 source current limit

1000

mA

Max current sinked into LDO without

exceeding load regulation (raise output

voltage above programmed value to sink

current into LDO)

Sink current limit

1000

mA

Measured with VOUT at 0.9*Programmed

voltage

Source short circuit current limit

Sink short circuit current limit

2000

mA

V_VIN= 1.1V, 1.2V and 1.35V, I_OUT= 0A to

1.0A, Measured at the regulation point

output capacitor with Kelvin connections

made directly from the regulation point to

the differential feedback pins (FBLDO1 -

FBVR4N).

Maximum load regulation

4.5%

DC and AC, V_VIN= 1.0V to 1.42V, I_OUT

0A to 1.0A, Measured at the regulation

point output capacitor with Kelvin

connections made directly from the

regulation point to the differential

feedback pins (FBLDO1 - FBVR4N).

=

Maximum total output voltage

variation

5%

35

Measure from LDO enable to V_OUTstable.

Time to ramp from 0.3V to V_O(min)

.

Total turn-on time (enable + ramp) Continuous slope (no slope reversal).

Assumes V_VINis present, with a 4x10µF

µs

output capacitor bank

External output capacitor (Cout)

External input capacitor (Cin)

40

10

µF

kΩ

Ω

Output auto discharge resistance

FBLDO1 input impedance

Discharge register value: 0, Default

Discharge register value: 1

Enabled

1000

60

80

25

100

20

MΩ

μA

Quiescent current into V_VINLDO1

V_VINLDO1= 1.35V, I_LDO1= 0 mA, Enabled

V_VINLDO1= 1.35V, Enabled

3.5

5

Quiescent current from 3.3V

reference LDO when LDO1 is

enabled

250

LDO1 CONTROL

LDO1_Power good threshold high Fail when V_OUTincreasing

108%

88%

130

110%

-5%

112%

92%

160

LDO1_Power good threshold high Good when V_OUTdecreases (after a

hysteresis

PGOOD fail event)

LDO1_Power good threshold low

Fail when V_OUTdecreasing

90%

5%

LDO1_Power good threshold low

hysteresis

Good when V_OUTincreases (after a

PGOOD fail event)

Overtemperature protection

Overtemperature hysteresis

145

10

°C

VR5 POWER

Input voltage

Parametric and functional

Functional

5.4

7.4

21

24

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V5ADS3CNT[7:6] =

2'b00, V5ADS3CNT[5:4] = 2'b00

Output voltage

5.15

5.1

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V5ADS3CNT[7:6] =

2'b00, V5ADS3CNT[5:4] = 2'b01

28

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V5ADS3CNT[7:6] =

2'b00, V5ADS3CNT[5:4] = 2'b10

(DEFAULT)

Output voltage- Default

5.0

V

Power save mode disabled (SLPS0Z = H,

or SLPS0Z = L & , V5ADS3CNT[7:6] =

2'b00, V5ADS3CNT[5:4] = 2'b11

Output voltage

4.9

V

Power save mode enabled, SLP_S0Z =

L , V5ADS3CNT[7:4] = 4'b01XX

Output voltage

4.8

4.85

4.9

V

Power save mode enabled, SLP_S0Z =

L , V5ADS3CNT[7:4] = 4'b10XX

Power save mode enabled, SLP_S0Z =

L , V5ADS3CNT[7:4] = 4'b11XX

High-side output peak current limit R_TRIP= 13.1kΩ (programmable based on

(programmed by external resistor) external resistor), RDSON HS FET 18mΩ

6600

-110

44

7245

-100

50

7900

-90

mA

mV

µA

current limit (Vsw - PGND)

V_TRIP= 0.8V

High-side I_LIM- current limit pin

source current

T_A= 25℃

56

High-side TC_ILIM- current limit

temperature coefficient

With respect to 25℃

3300

ppm/℃

V

High-side V_ILIM- current limit pin

setting voltage range

V_ILIM= R_TRIP*I_LIM

0.2

3350

45

2

5600

55

Low-side output valley current limit R_TRIP= 5kΩ (programmable based on

(programmed by external resistor) external resistor), RDSON LS FET 7mΩ

4465

50

mA

I_LIM- current limit pin source

T_A= 25℃

µA

current

Low-side TC_ILIM- current limit

With respect to 25℃

4780

ppm/℃

V

temperature coefficient

V_ILIM- current limit pin setting

V_ILIM= R_TRIP*I_LIM

0.2

-10

2

voltage range

Maximum range low side zero

crossing threshold

10

mV

ULQ/Auto Mode, V_VIN= 5.4V to 21V, I_OUT

= I_MAX, Measured at the regulation point

output capacitor with Kelvin connections

made directly from the regulation point to

the differential feedback pins (FBVR5P -

FBVR5N).

Maximum line regulation

-0.5%

1.05%

0.75%

ULQ/Auto Mode, V_VIN= 7.4V, I_OUT= 0A

to I_MAX, Measured at the regulation point

output capacitor with Kelvin connections

Maximum load regulation

made directly from the regulation point to

the differential feedback pins (FBVR5P -

FBVR5N).

DC and AC, ULQ/Auto Mode, V_VIN= 5.7V

to 21V (when Vout=5V), V_VIN= 5.4V to

21V (when Vout=1.8V), I_OUT= 0A to 70%

max load, 70% max load to 0mA and I_OUT

Maximum total output voltage load = 30% max load to max load, max load to

-5%

5%

transient variation

30% max load, di/dt = 2.5A/us , Measured

at the regulation point output capacitor

with Kelvin connections made directly

from the regulation point to the differential

feedback pins (FBVR5P - FBVR5N).

29

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM Mode (NVDCZ= 3.3V =

programmed to low switching frequency)

430

500

550

VR5_Controller switching

frequency

PWM Mode (NVDCZ= GND =

kHz

programmed to high switching

frequency)Frequency drops at Vin < 6V

close to Vout = 5V to extend Ton

25

875

925

Time to start switching from enable to

95% of VO(Min), Continuous slope (no

slope reversal). See Cout spec

Total turn-on time (start-up time +

output ramp-up time)

1200

μs

VR5 MOSFET Drivers

DRVH resistance

DRVL resistance

Dead time

Source, IDRVH = -50mA

Sink, IDRVH = 50mA

3.0

2.0

3.0

0.8

10

4.5

3.5

4.5

2.0

Ω

Source, IDRVL = -50mA

Sink, IDRVL = 50mA

Ω

DRVH - off to DRVL - on

DRVL - off to DRVH - on

ns

Dead time

20

High-side driver minimum on-time DRVH - on

High-side driver minimum off-time DRVH - off

80

260

VR5 OUTPUT DISCHARGE

Output auto discharge resistance

Discharge register value: 00, Default

Discharge register value: 01

Discharge register value: 10

Discharge register value: 11

1000

90

kΩ

Ω

150

250

575

190

315

690

170

450

Ω

VR5_Controller Feedback input

resistance

Controller enabled

2.5

4.25

MΩ

VR5_Bootstrap switch ON

resistance (Rdson)

T_A= 25°C

20

Ω

VR5_Controller HSD leakage

V_IN= 7.4 V, Controller disabled

1.55

μA

VR5 CONTROL

VR5_Power good threshold high

Fail when Vout increasing

105.5%

89.5%

130

108% 110.5%

-3%

VR5_Power good threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

VR5_Power good threshold low

Fail when Vout decreasing

92%

3%

94.5%

160

VR5_Power good threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

Overtemperature protection

Overtemperature hysteresis

145

10

°C

INPUT POWER SOURCE DETECTION

AC-ADAPTER DETECTION

V_IL

V_IH

ACOK input low voltage

0.4

V

ACOK input high voltage

1.2

V

ACOK input current

ACOK = 3.3 V

0.01

61

0.1

95

13

25

36

μA

μs

ms

Adapter detection debounce time

ACOKDB register value: 00

ACOKDB register value: 01

ACOKDB register value: 10

ACOKDB register value: 11 Default

50

7

10

15

24

20

30

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARACTER

POWER MONITORING

1 Hz CLOCK

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1Hz EC CLOCK - pulled-0-up to EC_VCC Internal Pull-up Rail = EC_VCC = 1.8V or 3.3V

Clock frequency

0.8

1

1.2

Hz

V

Duty cycle

50%

Pulled-Up to EC_VCC pin which should

be tied to 3.3v LDO3 pin, can also have

EC_VCC pull-up to 1.8V, instead of 3.3V

EC_

VCC

V_PP

Pull-up output voltage supply

V_{OL_PP}

V_{OH_PP}

Low level output voltage

High level output voltage

I_OL= 3 mA

0.66

V

EC_VC

C - 0.66

I_OH= 3 mA

COINCELL SELECTOR

VDCIN > UVLO, 3.3V and 5V LDOs up ,

Measured at the V3P3A_RTC pin with

respect to AGND.. Place a 1µF capacitor

at V3P3A_RTC. (Do not exceed 2uF

capacitance).

V_3v1LDO

3V1 LDO regulation voltage

3.0

3.1

3.2

1

V

I_3v1LDO

Maximum 3V1 LDO output current Maximum output current out of 3V3RTC.

mA

VBATTBKUP quiescent current,

when no adapter and no main

battery connected to system,

automatically VBATTBKUP

internally selected. internal 3.1V

LDO automatically off

V_VDC< UVLO, V_BBC= 2.0V to 3.0V, V_VDC

= 0V

I_{Q_bkup_no_Vsys}

0.03

0.45

0.85

μA

VBATTBKUP quiescent current,

when adapter or main battery

connected to system, automatically V_VDC> UVLO, V_BBC= 2.0V to 3.0V, V_VDC

VBATTBKUP internally not

selected, internal 3.1V LDO

automatically on and selected.

I_{Q_bkup_with_Vsys}

0.15

1

μA

kΩ

= 7.4V

Place between backup battery and

VBATTBKUP pin, for limiting current out

of backup battery

External resistor in series with

backup battery

R_{ext_bkup}

I2C INTERFACE⁽¹⁾

V_IL

V_IH

SDA, SCL input low voltage

SDA, SCL input high voltage

SDA, SCL input current

0.4

V

1.2

Clamped on 3.3V

0.01

0.04

0.3

0.4

μA

I_SDA= 5mA (using a 354Ω or larger

external pull-up resistor)

SDA output low voltage

V

C_b

Capacitive load for SDA and SCL

400

pF

(1) All values referred to V_IHmin and V_IHmax levels.

31

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

7.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

μs

I2C INTERFACE

Standard-mode

100

400

f_(SCL)

SCL clock frequency

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode

1000

4.7

1.3

0.5

4

Bus free time between a STOP and

START condition

t_BUF

Fast-mode Plus

Standard-mode

Fast-mode

μs

ns

μs

ns

Hold time (repeated) START

condition

t_{HD; STA}

600

260

4.7

600

260

250

100

50

Fast-mode Plus

Standard-mode

Fast-mode

Setup time for a repeated START

condition

t_{SU; STA}

Fast-mode Plus

Standard-mode

Fast-mode

t_{SU; DAT}Data setup time

t_{HD; DAT}Data hold time

ns

Fast-mode Plus

Standard-mode

Fast-mode

0

3.45

0.9

μs

ns

0

Fast-mode Plus

Standard-mode

Fast-mode

0

1000

300

t_rCL

Rise time of SCL signal

20

ns

Fast-mode Plus

120

Standard-mode (using a 2.95KΩ or smaller

external pull-up resistor)

1000

Fast-mode (using an 885Ω or smaller external

pull-up resistor)

300

120

t_rDA

Rise time of SDA signal

Fall time of SDA signal

ns

Fast-mode Plus (using a 354Ω or smaller

external pull-up resistor)

Standard-mode

300

20 x (V_DD

/

Fast-mode

t_fDA

5.5 V)

ns

20 x (V_DD

/

120

Fast-mode Plus

5.5 V)

Standard-mode

Fast-mode

4

µs

ns

t_{SU; STO}Setup time for STOP condition

600

260

Fast-mode Plus

32

TPS650830

www.ti.com.cn

ZHCSDM1 –DECEMBER 2014

VOLUME #1 Application Block Diagram:

VR1 = V1.00A (V11), & V085A (V12), VR2 = V1.8A (V8), VR3 = V33ADSW (V6),

VR4 = V1.2U (V10), VR5 = V5ADS3 (V5)

TPS650830 ± VOLUME

COMPA = V3.3A_PCH (V7), COMPB = V1.8U_2.5U (V9), COMPC = Generic Comparator,

COMPD = VCCIO (V4), COMPE = V3.3S, COMPF = V1.8S, COMPG = V1.00S

S5/S4

G3 ÆS5/S4

S5/S4 Æ S0

G3

VOL#1

VDC

(BAT/ADP

Insertion)

VREF1V25

UVLO3Z

[UVLO2Z_LDO3EN]

LDO3

LDO3_PG

UVLO5Z

[UVLO1Z_LDO5EN]

(Power On Dig Reset)

LDO5

LDO5_PGD

OTP_LOAD

1ms from UVLO5/Dig Reset to OTP Loaded

I2C Ready

PMIC I2C

3.2V

3.1V LDO

Vcoin_cell_battery

V3P3A_RTC

[V3P3A_RTC]

2.0V

V3.3A_DSW_EN (V6)

[ENVR3] (Tie to LDO3 or to GND)

VERY IMPORTANT: This pin is ignored. The ENVR3 is driven internally for Volume

V33ADSW (V6)

[FBVR3P]

PG

V3.3A_DSW_PG (V6)

[PGVR3]

>10ms delay from PG

V3.3A_DSW to DPWROK

DPWROK

[DPWROK]

ext

V1.8A_EN (V8)

[ENVR2]

Assumes V1.8A enabled by DPWROK.

Could also be enabled by SLP_SUSZ later.

V1.8A (V8)

[FBVR2P]

PG

V1.8A_PG

[PGVR2]

DPWROK to SLP_SUSZ takes 95ms from PCH

95ms

SLP_SUSZ

[ENE]

ext

V5ADS3_EN

[ENVR5]

V5ADS3_EN is copy of SLP_SUSZ

DS3_VREN

[DS3_VREN]

DS3VREN is gated by

V5ADS3_EN

~ 1us delay

V5ADS3 (V5)

[FBVR5P]

PG

V5ADS3_PG

[PGVR5]

V5A_DS3_PG to V1.00A_PG

<20mSec

ext

V33APCH_EN_control

[ENA]

int

V33APCH_EN_qualified

[PGE]

± to Load Switch

V3.3APCH (7)

[VSA]

PG

V3.3APCH_PG

[PGA]

ext

V085A_EN

[ENVR1]

/ V100A_EN

1.00V

PG

V085A (V12)

[FBVR1P]

/ V100A (V11)

V085A_PG

[PGVR1]

/ V100A_PG

int

RSMRSTZ

[RSMRSTZ]

internal

>10mSec

RSMRSTZ_PWRGD

[RSMRSTZ_PWRGD]

external

SLP_S4Z

[ENB]

V1.8U_2.5U_EN

[PGB]

SLP_S4Z to V1.8U_2.5U ramp

0.5ms tdelay +tramp-up 2ms

[Load Sw turn-on time]

=

V1.8U_2.5U (V9)

[VSB]

ext

PG

V1.8U_2.5U_PG

[PMIC internal]

V1.2U_EN

[ENVR4]

SLP_S4Z to V1.2U ramp

>2.5ms

[4ms]

V1.2U (V10)

[FBVR4P]

PG

V1.2U_PG

[PGVR4]

SLP_S3Z

[ENF] for powergood tree only

ext

V100S_EN

[ENG]

± to Load Switch

V1.00S

[VSG]

ext

PG

V1.00S_PG

[PGG]

V3.3S_EN

[ENG]

± to Load Switch

V3.3S

[VSE]

PG

V3.3S_PG

[PMIC internal]

ext

V1.8S_EN

[ENG]

± to Load Switch

V1.8S

[VSF]

ext

PG

SLP_S3Z

[V1.2U_PG

outputs drive same ENVR3 pin, with single

pull-up resistor]

&

V1.2U_PG

& V1.00S_PG

V1.8S_PG

[PGF]

&

V1.00S_PG open-drain

ext

VCCIO_EN

No direct SLP_S3Z connection

[PGD]

± to Load Switch

VCCIO (V4)

[VSD]

PG

VCCIO_PG

[PMIC internal]

2ms (from the last PG)

ALL_SYS_PWRGD

[ALL_SYS_PWRGD]

1.00V

VCCST_PWRGD

[VCCST_PWRGD]

Prog

PCH_PWROK

[PCH_PWROK]

SYS_PWROK

[SYS_PWROK]

Figure 1. TPS650830 Volume Timing Diagram

33

TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

7.7 Typical Characteristics

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

0.95

1.89

1.87

1.85

1.84

1.82

1.80

1.78

1.76

1.75

1.73

1.71

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

Vin=2.97

Vin=3.30

Vin=3.63

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

0

0.5

1

1.5

2

2.5

Iout (A)

D001

Figure 2. VR1 Output Voltage Load Regulation, NVDC

Figure 3. VR2 Output Voltage Load Regulation, NVDC

3.465

1.272

Vin=5.40

Vin=8.10

Vin=8.70

Vin=13.50

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

1.260

1.248

1.236

1.224

1.212

1.200

1.188

1.176

1.164

1.152

1.140

3.432

3.399

3.366

3.333

3.300

3.267

3.234

3.201

3.168

3.135

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

Iout (A)

D001

Figure 4. VR3 Output Voltage Load Regulation, NVDC

Figure 5. VR4 Output Voltage Load Regulation, NVDC

5.25

100

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

0

0.5

1

1.5

2

2.5

3

3.5

4

0

1

2

3

4

5

6

7

Iout (A)

D001

Figure 6. VR5 Output Voltage Load Regulation, NVDC

Figure 7. VR1 Efficiency vs Load, NVDC

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ZHCSDM1 –DECEMBER 2014

Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

Vin=2.97V

Vin=3.30V

Vin=3.63V

0.0

0.5

1.0

1.5

2.0

2.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Iout (A)

D001

Figure 8. VR2 Efficiency vs Load, NVDC

Figure 9. VR3 Efficiency vs Load, NVDC

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

0

1

2

3

4

5

6

7

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

Iout (A)

D001

Figure 10. VR4 Efficiency vs Load, NVDC

Figure 11. VR5 Efficiency vs Load, NVDC

900000

800000

700000

600000

500000

400000

300000

200000

100000

0

800000

700000

600000

500000

400000

300000

200000

100000

0

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

0

1

2

3

4

5

6

7

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5 6.5

6

Iout (A)

D001

Figure 12. VR1 Switching Frequency vs Load, NVDC

Figure 13. VR3 Switching Frequency vs Load, NVDC

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ZHCSDM1 –DECEMBER 2014

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Typical Characteristics (continued)

800000

700000

600000

500000

400000

300000

200000

100000

0

900000

800000

700000

600000

500000

400000

300000

200000

100000

0

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

0

1

2

3

4

5

6

7

0

0.5

1

1.5

2

2.5

3

3.5

Iout (A)

D001

Figure 14. VR4 Switching Frequency vs Load, NVDC

Figure 15. VR5 Switching Frequency vs Load, NVDC

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

3.5

2.00

8

7

6

5

4

3

2

1

0

Vout (Vin=2.97V)

Vout (Vin=3.30V)

Vout (Vin=3.63V)

Iout (Vin=2.97V)

Iout (Vin=3.30V)

Iout (Vin=3.63V)

Vout (Vin=5.4V)

Vout (Vin=8.7V)

Vout (Vin=15V)

Vout (Vin=24V)

Iout (Vin=5.4V)

Iout (Vin=8.7V)

Iout (Vin=15V)

Iout (Vin=24V)

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0

1

2

3

4

5

6

7

8

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Iout (VR1) Programmed (A)

Iout(VR2) Programmed (A)

D001

Figure 16. VR1 Current Limit: Vout and Iout vs Load, Non-

NVDC

Figure 17. VR2 Current Limit: Vout and Iout vs Load, Non-

NVDC

5.4

4.8

4.2

3.6

3

9

8

7

6

5

4

3

2

1

0

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

9

8

7

6

5

4

3

2

1

0

Vout (Vin=5.40V)

Vout (Vin=8.70V)

Vout (Vin=15.00V)

Vout (Vin=24.00V)

Iout (Vin=5.40V)

Iout (Vin=8.70V)

Iout (Vin=15.00V)

Iout (Vin=24.00V)

Vout (Vin=5.40V)

Vout (Vin=8.70V)

Vout (Vin=13.50V)

Vout (Vin=24.00V)

Iout (Vin=5.40V)

Iout (Vin=8.70V)

Iout (Vin=13.50V)

Iout (Vin=24.00V)

2.4

1.8

1.2

0.6

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

Iout (VR4) Programmed (A)

D001

Figure 18. VR3 Current Limit: Vout and Iout vs Load, Non-

NVDC

Figure 19. VR4 Current Limit: Vout and Iout vs Load, Non-

NVDC

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ZHCSDM1 –DECEMBER 2014

Typical Characteristics (continued)

10

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Vout (Vin=5.40V)

Vout (Vin=8.70V)

Vout (Vin=13.50V)

Vout (Vin=24.00V)

Iout (Vin=5.40V)

Iout (Vin=8.70V)

Iout (Vin=13.50V)

Iout (Vin=24.00V)

9

8

7

6

5

4

3

2

1

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Iout (VR5) Programmed (A)

D001

Figure 20. VR5 Current Limit: Vout and Iout vs Load, Non-NVDC

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TPS650830

ZHCSDM1 –DECEMBER 2014

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPS650830 is a single-chip solution Power Management IC designed specifically for the latest Intel

Processors targeted for Tablets, Ultrabooks, and Notebooks with NVDC or non-NVDC power architectures, using

2S, 3S, or 4S Lithium-Ion battery packs.

The TPS650830 is used for Volume systems with the low voltage rails merged for the smallest footprint and

lowest cost system power solution.

The TPS650830 can provide the complete power solution based on the Intel Reference Designs. Five highly

efficient step-down voltage regulators (VRs) and a sink/source LDO, are used along with power-up sequence

logic managing external load switches to provide the proper power rails, sequencing, and protection - including

DDR3 and DDR4 memory power. The regulators support dynamic voltage scaling (DVS) for maximum efficiency

including Connected Standby. The high frequency voltage regulators use small inductors and capacitors to

achieve a small solution size. Output power is adjustable on four VR controllers. An I²C interface allows simple

control by the embedded controller (EC). Each version is available in a 7x7 NFBGA package and a 9x9 NFBGA

package. The 7x7 NFBGA package can be used in Type 4 PCB boards for the smallest area implementation.

The 9x9 NFBGA package can be used in Type 3 and Type 4 PCB boards allowing to minimize cost and area.

The Powergood Comparator Logic allows controlling and monitoring four external load switches within the

sequence. All the VR and Load Switch Powergood signals are used in the Power Good Tree of which the outputs

are shown with open-drain outputs. Enable inputs allow connecting externally to set the sequence, and it also

allows using various Sleep Mode State signals. The STANDBYZ allows entering a Deep Sleep Mode, in which

the out put voltages of the voltage regulators can be reduced to save power by DVS.

The Power Monitoring comparators are used to detect and monitor up to three input power sources (adapter,

battery1, battery2, or any other combination). Over temperature of the PMIC self-protects, and outputs a Status

output, TEMPALERTZ; plus there is a dedicated comparator that can monitor system over temperature with

multiple stacked PTC thermistors, or an NTC thermistor. The PMIC automatically swtiches between an internal

3.1V LDO when a powersource is connected; or to a Backup Battery (Coin Cell) when all power sources are

removed. This output RTC rail is used to maintain the always-on RTC rails for critical register data.

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8.2 Functional Block Diagram

SHUTDOWNZ

STANDBYZ

TTL

POWER MONITOR

VDDIO

PGVR4

OD/PP

VREGVR4

ILIMVR4

FBVR4N

VDDIO

PP

FBVR4P

VBSTVR4

DRVHVR4

VR4

PPATH

LOGIC

Controller

V12U/135U/

1.05U

VDDIO

RESETZ

SWVR4

DRVLVR4

PGNDVR4

Vout=1.05V-

1.2V

10A max

PP

PG

EN

VSET

VSA

VSB

VSC

VSD

VSE

REF

EN/

PGOOD

LOGIC

VDDIO

DCH

VDDIO

VSF

VSG

DDRID

ENVR4

TTL

3 L

VSH

VDDIO

TTL

ENA

ENB

ENC

END

ENE

ENF

ENG

ENH

DDR_VTT_CTRL

SEQ

+

INTEL

AND

OEM

LOGIC

VDDIO

TTL

VINDLO1S

VINLDO1[2X]

LDO1

SINK/SRC LDO

V0.6DX/0.675DX

/0.525DX

VOUTLDO1[2X]

EN

LOGIC

FBLDO1

PGA

PGB

PGC

PGD

PGE

PGF

Vout= (VR1)/2

1A max

VDDPG

PGNDLDO1[2X]

VINVR2 [2X]

SWVR2 [2X]

OD/PP

PGG

PGH

VDDPG

VR2

PG

VDDIO

Converter

Out range:

0.85v-3.3v

Vout INTEL

FBVR2P

ENLVA

EN

VSET

TTL

VREGVR2

LVA

LVB

VDDLVS

FBVR2N

OD/PP

PGNDVR2 [2X]

EN/

PGOOD

LOGIC

VDDLV

VDDIO

VREGVR1

PGVR2

ENVR2

DIGCORE

OD/PP

ILIMVR1

FBVR1N

VDDIO

FBVR1P

TTL

VR1

Controller

Vout range

0.85v-5v

Vout INTEL

VBSTVR1

VBATTBKUP

BACKUP

BATTERY

SELECTOR

V33ARTC

DRVHVR1

SWVR1

RTC

DIG

EN/

PGOOD

LOGIC

PG

V3P3A_RTC

TRIPZ

EN

VSET

DRVLVR1

OD/PP

OEM

VCOMP

PGVR3

PGNDVR1

PGVR1

VDDIO

OD/PP

VDDIO

NVDCZ

OD/PP

TTL

VDDIO

VREGVR4

ENVR1

PGVR5

TTL

VINVR3

ILIMVR3HS

ILIMVR3LS

FBVR3N

EN/

PGOOD

LOGIC

VDDIO

EN/

PGOOD

LOGIC

OD/PP

PG

VR3

VINVR5

FBVR3P

EN

VSET

Controller

Out range:

0.85v-5v

EN

VSET

VBSTVR3

ILIMVR5HS

FBVR5N

I2C AND

REGFILE

Vout INTEL

FBVR5P

DRVHVR3

SWVR3

VR5

VBSTVR5

Controller

Out range:

0.85v-5v

DRVLVR3

DRVHVR5

SWVR5

Vout INTEL

VDDIO

PGNDVR3

ENVR3

TTL

DRVLVR5

OTP

VREGVR1

PGNDVR5

VIN

UVLO

VINLDO3

VDDIO

ILIMVR5LS

DFT AND

AMUX

TTL

LDO5V

REFSYS

ENVR5

VREF1V25

LDO3V

VIN5VSW

EN5VSW

TEMP_ALERTZ

VDDIO [2X]

DIETEMP

OD

PGA

PGB

PGC

PGD

SW

TTL

SW

EN3V3SW

AGND [4]

TTL

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ZHCSDM1 –DECEMBER 2014

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8.3 Feature Description

8.3.1 Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage

Regulator or Load Switch) for SkyLake Platform

For the SkyLake Power Map implementation, the five PMIC voltage regulators and LDO1 are assigned with the

low -voltage rails merged or split according to the configuration. For the Volume (merged low voltage rails)

configuration six external load switches are controlled and monitored by using six powergood comparator logic

blocs.

Table 1. Voltage Regulator and Powergood Comparator Logic Assignment for Intel SkyLake Platform

I_out

SkyLake PLATFORM POWER SYSTEM VOLTAGE RAIL

VOLUME (Merged Low Voltage Rails)

OUTPUT

VOLTAGE, V_outACTIVE MODE

I_out

CONNECTED

STANDBY

MODE

TPS650830

VR1

VR2

VR3

VR4

VR5

V1.00A / 0.85A

V1.8A

1.00V

1.8V

6.47A

1.44A

6.29A

7.24A

3.75A

0mA

4mA

6mA

8mA

1mA

V3.3A_DSW

V1.2U

3.3V

1.2V,1.35V,1.1V

5V

V5A_DS3

0.6V, 0.675V,

0.55V

LDO1

V0.6Dx

0.6A

0mA (off)

External VR_a

External VR_b

none

-

Powergood

Comparator

Logic a

V3.3A_PCH Enable/Sense External Load Switch

V1.8U_2.5U Enable/Sense External Load Switch

Generic Comparator

3.3V

1.8V

-

–

Powergood

Comparator

Logic b

Powergood

Comparator

Logic c

Powergood

Comparator

Logic d

VCCIO Enable/Sense External Load Switch

V3.3S Sense External Load Switch

V1.8S Sense External Load Switch

V1.0S Sense External Load Switch

1.00V

3.3V

1.8V

1.00V

Powergood

Comparator

Logic e

Powergood

Comparator

Logic f

Powergood

Comparator

Logic g

8.3.2 Converters

Table 2. Converters

Enable in Control section

Power good handling in Control section

All converters have same input voltage

All converters have same power good scheme

All converters have same auto discharge scheme

*

All converters have UVLO with same shutdown voltage and hysteresis

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The PMIC has 5 built in DCDC converters. The voltage regulators are highly configurable both in terms of

voltage and current. Of the five voltage regulators, four voltage regulators have an external power stage, with

programmable current limit (programmed by an external resistor), which allows optimal selection of external

passive components based on desired system load. VR2 has a completely integrated power stage, except for the

required passive components. To maintain high efficiency, the converters are implemented as synchronous step

down converters.

One additional voltage regulators in the form of Low Drop Out (LDO) linear regulators are integrated as part of

the PMIC. One of the LDOs, V6, is capable of sinking and sourcing current that regulates from the step down

controller (for DDR memory). This LDO is designed to specifically provide the VTT power to DDR memory. Its

output voltage tracks the output voltage of the step down controller and is set to regulate to half of the step down

controller voltage.

8.3.2.1 Power Save Mode

At medium and heavy loads, the converter and the controllers operate in a PWM mode. As soon as the inductor

current gets discontinuous, which means that the output current gets lower than half of the inductor ripple

current, the converters enter Power Save Mode. In Power Save Mode the switching frequency decreases linearly

with the load current and maintains a high efficiency. By default, the converters and controller operate in the

AutoPFM mode such that the transition into and out of Power Save Mode happens within the entire regulation

scheme and is seamless in both directions.

PFM Mode at Light Load

PFM Ripple

Nominal DC Output Voltage

PWM Mode at Heavy Load

Figure 21. PFM and PWM Mode Operation

The figure above shows the converter/ controller operation in PFM and PWM mode. In PFM mode the minimum

voltage that the output falls to is the programmed regulation voltage. The output voltage ripple in PFM mode is

determined based on the external passive components (L and C). The regulator ensures that the minimum

voltage during PFM mode is the same as the programmed regulation voltage (within the AC and DC tolerance).

8.3.2.2 Voltage Regulator Startup

All the voltage regulators including the VTT LDO1 can be enabled using either pin enables or I2C commands.

The default setting uses the pin enable. The VTT LDO1 can only be enabled using the DDR_VTT_CTRL discrete

input. VTT LDO1 can be enabled by pin (DDR_VTT_CTRL) or by register (0xE9, MSB bit 7 masks the

DDR_VTT_CTRL pin, and bit 6 enables the VTT LDO1). Each other Voltage Regulator (VR) can be enabled by

the enable pin (ENAVRx) or by I2C Register (xCNT). The voltage should not be changed by register at the exact

same time the voltage regulator is enabled. If a different voltage than the default is needed at power-up, then the

register (xCNT) should program the voltage first, and then a separate command should enable the register

separately. Dynamic voltage change (DVS) can be done any time after power-up.

Each of the voltage regulators except for the VTT LDO1 are controlled by an internal softstart to make sure the

output voltage ramps up gently and does not cause huge inrush current during startup to prevent droop on the

input. The VTT LDO1 startup time is driven by the DDR memory requirements for the VTT voltage rail - which

requires that the ramp up on voltage be faster than 35µs.

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ZHCSDM1 –DECEMBER 2014

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8.3.2.3 Power Good

During operation, when the voltage regulators are enabled, the output voltage for each rail is monitored in order

to assess if the output voltage is within a specified voltage range. A power good status bit is generated and

stored in the PWRSTAT1 register. If the output voltage is within the specified voltage range, the respective power

good status bit is set to a logic low. If the output voltage falls below or goes above the specified voltage range,

the power good status bit will be set to a logic high. By default, if any of the output voltage rails experience a

power good fault condition, the PMIC will automatically shutdown in order to protect the system unless and until

the power fault is masked. The voltage thresholds for each of the power good comparators is a percentage

relative to the nominal voltage setting of the output voltage - please see the parametric table for each voltage

regulator power good for the USL and LSL limits of the power good comparators.

If a particular voltage rail is not critical to the performance of the overall system, the respective power good

output can be masked using the PGMASK1 and PGMASK2 registers. The masking of a power good fault will

inhibit an automatic PMIC shutdown. This can be also very helpful for debug purposes incase of system failure to

isolate the voltage regulator with the sensitive output voltage.

In order to avoid an erroneous power good fault during the turn-on of the voltage regulators, the power good

output is masked for a fixed 30µs relative to the enable whether it be from the discrete signal or from an I2C

command. Power Good is also masked when coming out of sleep (S3 state) for a period of 100µs to ensure that

there is no false triggering of the power good comparator.

8.3.2.4 Current Limit

All voltage regulators are current limited, the current limit can be set based on the application load current using

an external resistor for all VRs except for VR2 which has an internally set current limit as it has an integrated

power stage. The current limit controls the maximum output current. If the maximum current is reached, the

output voltage will start to droop since the load can no longer be supplied with sufficient power. If the voltage

drops below the power good threshold, the power fault status will be set to a logic high and if the power fault is

not masked, the PMIC will automatically shutdown in a controlled manner to protect the system.

For voltage regulators with an externally programmable current limit, please use the following equation to

calculate the desired resistor value to prevent inductor saturation under nominal operation. I_REFis typically in the

order of 50µA. R_DSONis the resistance of the low side FET under nominal operating conditions. A scaling factor

of 1.5 is used to take into account for the inductor variation (±20%) and temperature coefficient differences

between the reference current and the FET R_DSON. Note that the inductor should be sized appropriately

(dimension, saturation current, heat rating) based on the intended application load.

R_EXT=R_DSON*(I_LOAD+I_ripple/2)*1.5/I_REF

(1)

8.3.2.5 Output Discharge Feature

All the voltage regulators have a built in output discharge feature. The output discharge feature consists of being

able to configure register bits to enable a discharge resistor which is only active whenever the voltage regulator

is disabled. The discharge resistors for each of the voltage regulators can be configured using the DISCHCNT1,

DISCHCNT2, DISCHCNT3 and DISCHCNT4 registers. The discharge resistors are disconnected when the

voltage regulators are enabled in order to minimize any losses within the PMIC.

8.3.2.6 Output Voltage Control

All voltage regulators are designed to regulate a fixed output voltage. To achieve high accuracy the output

voltage for the converters and controller is sensed using a separate feedback pin. For each of the voltage rails,

except for the VTT LDO, the output voltage can be changed to slightly higher or lower values by changing the

default setting in the voltage regulator control registers (see section on the Voltage Regulator Voltage Options).

This function can be used to save power when supplying the connected load at its minimum possible supply

voltage or to compensate for voltage drops during load transients by programming it slightly higher. In addition

the range of the output voltage for the regulators is highly programmable. If you need a different output voltage

configuration from the specified default, please contact TI to generate you a custom part.

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ZHCSDM1 –DECEMBER 2014

8.3.2.7 Converter Low Power Mode Operation

For optimizing low power operation, the output voltage of the converters can be set to a specific value. The low

power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options

tables. Entering the low power mode is accomplished by asserting the SLP_S0# signal to a logic low. In this low

power mode, the power good function remains active and is not affected by the transition from normal operation

mode to the low power mode and vice versa.

8.3.2.8 Controller Low Power Mode Operation

For optimizing low power operation, the output voltage of the V10 controller can be set to a specific value. The

low power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options

tables. Entering the low power mode is accomplished by asserting the DDR_VTT_CTRL signal to a logic low. In

this low power mode, the power good function remains active and is not affected by the transition from normal

operation mode to the low power mode and vice versa.

In situations where the output current demand from the controller is very small, the controller can be placed in an

Ultra Low Quiescent (ULQ) mode to reduce power consumption and increase the efficiency.

8.3.2.9 Undervoltage Lockout

An undervoltage lockout function prevents converter start-up if the supply voltage on the VIN pin of the PMIC is

lower than the undervoltage lockout threshold (see electrical characteristics table). When in operation, the

converter triggers a shut down of the system if the supply voltage on the VIN pin drops below the undervoltage

lockout threshold and the system will not automatically restart.

8.3.3 Coincell Selector

8.3.3.1 Functional Description of RTC Powerpath and LDO

In case where the main system battery is removed and there is no alternate power source, the RTC data,

configuration and status registers, oscillator and timekeeping path of the RTC block are backed up by either a

super capacitor or a coin cell battery. If the coincell/ super capacitor battery voltage falls below the minimum

operational voltage and there is no input voltage (AC/ DC above the PMIC UVLO), the RTC data registers will be

invalid. As the Intel RTC cannot handle a max voltage higher than 3.2V, when AC/ DC is present and is higher

than the UVLO threshold, the RTC is supplied by the AC/DC rather than from the coincell - thus maximizing the

stored charge in the coincell battery. When AC/DC is present, the internal coincell selector selects the higher of

the coincell voltage and the AC/DC voltage. When AC/DC is chosen as a source, there is a coincell LDO which

is driven from the 5V PMIC LDO to regulate The output voltage is programmable to 2.975V, 3.0V, 3.025V, 3.05V,

3.075V, 3.1V, 3.13V, 3.16V.

The main power source for the RTC LDO is the 5V PMIC internal LDO, when the main system battery (VDC) is

greater than 5.4V. The RTC LDO will be bypassed and the RTC supply will be powered by the coincell when

VDC falls below this threshold - to maximize the coincell battery life. The coincell is used as a last resort. All

power routing of the source selection for the RTC power is done internally and no external connections other

than the coin cell or super cap is required.

8.3.4 I²C - Interface

I²C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I²C-Bus Specification

and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a clock line (SCL) with

pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices

connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or

a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device

addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A

slave device receives and/or transmits data on the bus under control of the master device.

The TPS650830 works as a slave and supports the following data transfer modes, as defined in the I²C-Bus

Specification: standard mode (100 kbps), fast mode (400 kbps). The interface adds flexibility to the power supply

solution, enabling most functions to be programmed to new values depending on the instantaneous application

requirements. Register contents are loaded when voltage is applied to TPS650830 higher than the undervoltage

lockout threshold. The I²C interface is running from an internal oscillator that is automatically enabled when there

is an access to the interface.

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The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as

F/S-mode in this document.

The TPS650830 supports 7-bit addressing; 10-bit addressing and general call address are not supported. The

default device address is defined by the status of the SLAVEADDR pin. 3 different slave addresses are possible,

0x30 (SLAVEADDR 0 V), 0x32 (SLAVEADDR 3.3 V) and 0x34 (SLAVEADDR floating).

All registers are set to their default value when the supply voltage is below the UVLO threshold.

8.3.4.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, see Figure 22. All I²C-compatible devices should recognize a

start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse, see Figure 23. All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge, see Figure 24, by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link

with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data from

the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to

high while the SCL line is high, see Figure 22. This releases the bus and stops the communication link with the

addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop

condition, all devices know that the bus is released, and they wait for a start condition followed by a matching

address

Attempting to read data from register addresses not listed in this section results in FFh being read out. FS I²C

operation does not support repeated start

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SDA

SCL

S

P

Start

Stop

Condition

Figure 22. START and STOP Conditions

SDA

SCL

data line

change of data allowed

stable;

data valid

Figure 23. Bit Transfer on the I²C-bus

Data Output

by Transmitter

Not Acknowledge

Data Output

by Receiver

Acknowledge

SCL From

Master

1

2

8

9

S

Clock Pulse for

START

Acknowledgement

Condition

Figure 24. Acknowledge on the I²C-Bus

recognize START or

REPEATED START

condition

recognize STOP or

REPEATED START

condition

generate ACKNOWLEDGE

signal

P

SDA

MSB

acknowledgement

signal from slave

Sr

Address

R/W

SCL

1

2

7

8

9

1

2

3 − 8

9

S

or

Sr

or

P

ACK

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

START or

repeated START

condition

STOP or

repeated START

condition

Figure 25. Bus Protocol

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SCL

SDA

...

A6

A5 A4

A0 R/W ACK

R7

R6 R5

R0 ACK

0

D7

D6 D5

D0 ACK

0

Start

Slave Address

Register Address

Data

Stop

NOTE: SLAVE=This Device

Figure 26. I²C Interface WRITE to TPS650830 in F/S Mode

SCL

SDA

...

..

...

..

...

..

A6

A0 R/W ACK

R7

R0 ACK

0

A6

A0 R/W ACK D7

D0 ACK

0

1

0

Start

Slave

Drives

the Data

Stop

Register

Address

Master

Drives

ACK and Stop

Slave Address

NOTE: SLAVE=This Device

Slave Address

Repeated

Start

Figure 27. I²C Interface READ from TPS650830 in F/S Mode

8.4 Device Functional Modes

The TPS650830 PMIC has been designed to provide the overall power solution for use with the latest Intel

Processors. This section describes the internal state machine of the TPS650830 PMIC.

NO POWER State: If the VIN pin of the PMIC is below the VUVLO voltage threshold and the voltage on the

VBATTBKUP pin is below 2.3V, the PMIC will be in the NO POWER state. Naturally, in this state, all voltage

regulators are off.

RTC DOMAIN State: If a coincell or supercap is connected to the VBATTBKUP pin of the PMIC and its voltage

is greater than 2.3V, the state machine will be in the RTC DOMAIN state. When entering this state, all I2C

registers that reside in the RTC Domain will reset to their default settings.

POWER UP State: If the voltage on the VIN pin is greater than the VUVLO voltage threshold, the PMIC will enter

the POWER UP state. In this state, I2C control of all the registers is possible. If this is the first time entering the

POWER UP state, it will remain in this state until a high level is detected on the SHUTDOWNZ pin which could

be controlled by an external source. (Typically SHUTDOWNZ is connected to LDO3 to always keep it high).

Once a high level is detected on the SHUTDOWNZ pin, the PMIC will assert the VR3 internal enable high (This

internal signal is AND'ed with the VR3EN pin to turn on VR3). This enables the VR3 (V3.3A_DSW) regulator.

The PMIC will generate the V3.3A_DSW power good signal, PGVR3. The PMIC will then generate the DPWROK

signal which is a delayed version of the PGVR3 signal and sends it to the Platform Controller Hub (PCH) of the

system.

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Device Functional Modes (continued)

POWER SEQUENCE State: The PMIC enters this state once a low to high transition is detected on the

SLP_SUS# pin. This pin is driven by the PCH. In this state, the PMIC asserts the ENVR5 pin high to enable the

V5A_DS3 regulator, VR5. The SLP_SUS# signal also enables an external load switch which provides 3.3V to the

EC. The output of this load switch is monitored by the main PMIC on the ECVCC pin. Once the voltage on this

pin is detected, the PMIC will assert the PGVR3 pin , which should be connected externally to the ENVR2 pin.

The ENVR2 pin enables the V1.8V voltage regulator, VR2.

NORMAL MODE State: Entering this state occurs after the RSMRST#_PWRGD is asserted high. This power

good output is the AND of the V3.3A_DSW_PG (PGVR3), V5A_DSW_PG (PGVR3), V3.3A_PCH_PG (PGA),

V1.8A_PG (PGVR2), V1.00A_PG (PGVR1), and the V0.85A_PG (PGVR1). The PMIC will remain in this state

during normal operation. Only certain events will send the PMIC to other states as described in this section.

COLD OFF State: The PMIC will enter this state if the PCH detects that the PWRBTN# has been asserted for at

least 5 seconds. In this state, all the voltage regulators except for the V3.3A_DSW (VR3) regulator are turned off.

The 1Hz clock is turned off. Exiting this state occurs if the PWRBTNIN pin is asserted low and the SLP_SUS#

transitions from a logic low to a logic high. These events will send the State Machine to the POWER SEQUENCE

state.

EMERGENCY SHUTDOWN State: The EMERGENCY SHUTDOWN state occurs through various avenues. In

this state, all voltage regulators and 1 Hz clock are turned off. Exiting this state requires that the PWRBTNIN pin

detect a high to low transition or that the ACOK pin detect a low to high transition. Either of these events will

send the State Machine to the POWER UP state.

VOLTAGE REGULATOR FAULT: Every voltage regulator has a power good fault associated with it. If at any

point, any power good fault is detected, the state machine will enter the EMERGENCY SHUTDOWN state. TI

recommends that the power good faults not be masked during normal operation.

FORCE SHUTDOWN: If the Force Shutdown command is issued via the SHDWNCTRL register, the state

machine will enter the EMERGENCY SHUTDOWN state.

POWER BUTTON INTERRUPT: If the PWRBTNIN pin is held low for longer than the time defined by the

FLT[3:0] bits in the PBCONFIG register, the state machine will enter the EMERGENCY SHUTDOWN state.

CRITICAL TEMP: If at any point the PMIC die temperature exceeds the Overtempeture Protection parameter,

the state machine will enter the EMERGENCY SHUTDOWN state. In order to avoid the PMIC die temperature

from reaching the Critical Temperature range, all the voltage rail power good faults default to being enabled. TI

recommends that the power good faults not be masked during normal operation.

DVS: When Dynamic Voltage Scaling (DVS) is programmed, include an Active State when STANDBYZ pin is Hi;

and a Low Power Mode State when the STANDBYZ pin is low. The output voltages will typically be at a higher

voltage setting in the Active Mode to allow a high performance operation from the system. The output voltages

will typically be at a lower voltage setting in the Sleep Mode to allow a low-power operation from the system and

increase battery run-time. If DVS is not programmed, then the output voltage will always be at the same value,

regardless what the logic value is of the STANDBYZ pin.

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8.5 Register Map

8.5.1 OTP_SPARE2 Register (address = 0xF0) [reset = 00000000]

Figure 28. OTP_SPARE2 Register Format

B7

SPARE2[7]

0

B6

SPARE2[6]

0

B5

SPARE2[5]

0

B4

SPARE2[4]

0

B3

SPARE2[3]

0

B2

SPARE2[2]

0

B1

SPARE2[1]

0

B0

SPARE2[0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3. OTP_SPARE2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

SPARE2[7:0]

RW

00000000 OTP SPARE BYTE for Future use

8.5.2 OTP_SPARE1 Register (address = 0xEF) [reset = 00000000]

Figure 29. OTP_SPARE1 Register Format

B7

SPARE1[7]

0

B6

SPARE1[6]

0

B5

SPARE1[5]

0

B4

SPARE1[4]

0

B3

SPARE1[3]

0

B2

SPARE1[2]

0

B1

SPARE1[1]

0

B0

SPARE1[0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. OTP_SPARE1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

SPARE1[7:0]

RW

00000000 OTP SPARE BYTE for future use

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8.5.3 VREN_PIN_OVR Register (address = 0xEE) [reset = 00000000]

Figure 30. VREN_PIN_OVR Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V12_PIN_OVR V11_PIN_OVR V10_PIN_OVR V9_PIN_OVR

V8_PIN_OVR

V7_PIN_OVR

V5_PIN_OVR

V4_PIN_OVR

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. VREN_PIN_OVR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

V12_PIN_OVR

RW

0

V12 ENABLE PIN Over Ride

0: V12 Pin controls V12 (Default)

1: V12 is ON if VREN PIN MASK = '0'

6

5

4

3

2

1

0

V11_PIN_OVR

V10_PIN_OVR

V9_PIN_OVR

V8_PIN_OVR

V7_PIN_OVR

V5_PIN_OVR

V4_PIN_OVR

RW

0

V11 ENABLE PIN Over Ride

0: V11 Pin controls V11 (Default)

1: V11 is ON if VREN PIN MASK = '0'

V10 ENABLE PIN Over Ride

0: V10 Pin controls V10 (Default)

1: V10 is ON if VREN PIN MASK = '0'

V9 ENABLE PIN Over Ride

0: V9 Pin controls V9 (Default)

1: V9 is ON if VREN PIN MASK = '0'

V8 ENABLE PIN Over Ride

0: V8 Pin controls V8 (Default)

1: V8 is ON if VREN PIN MASK = '0'

V7 ENABLE PIN Over Ride

0: V7 Pin controls V7 (Default)

1: V7 is ON if VREN PIN MASK = '0'

V5 ENABLE PIN Over Ride

0: V5 Pin controls V5 (Default)

1: V5 is ON if VREN PIN MASK = '0'

V4 ENABLE PIN Over Ride

0: V4 Pin controls V4 (Default)

1: V4 is ON if VREN PIN MASK = '0'

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8.5.4 TEMPHOT Register (address = 0xEC) [reset = 00000000]

Figure 31. TEMPHOT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_T RESERVED_T

LDO1_HOT

VR5_HOT

VR4_HOT

VR3_HOT

VR2_HOT

VR1_HOT

EMPHOT[1]

EMPHOT[0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. TEMPHOT Register Field Descriptions

Bit

7:6

5

Field

Type

R

Reset

00

Description

RESERVED_TEMPHOT[1:0]

LDO1_HOT

Read Always Returns '1'

RW

0

LDO1 HOT TEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

4

3

2

1

0

VR5_HOT

VR4_HOT

VR3_HOT

VR2_HOT

VR1_HOT

RW

0

VR5 HOT TEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR4 HOT TEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR3 HOT TEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR2 HOT TEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR1 HOT TEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

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8.5.5 TEMPCRIT Register (address = 0xEB) [reset = 00000000]

Figure 32. TEMPCRIT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_T RESERVED_T

LDO1_CRIT

VR5_CRIT

VR4_CRIT

VR3_CRIT

VR2_CRIT

VR1_CRIT

EMPCRIT[1]

EMPCRIT[0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. TEMPCRIT Register Field Descriptions

Bit

7:6

5

Field

Type

R

Reset

00

Description

RESERVED_TEMPCRIT[1:0]

LDO1_CRIT

Read Always Returns '1'

RW

0

LDO1 CRITTEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

4

3

2

1

0

VR5_CRIT

VR4_CRIT

VR3_CRIT

VR2_CRIT

VR1_CRIT

RW

0

VR5 CRITTEMPs

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR4 CRITTEMPs

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR3 CRITTEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR2 CRITTEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

VR1 CRITTEMP

0: Not asserted (Default)

1: Asserted, write '1' to clear

8.5.6 STDBY_CTRL Register (address = 0xEA) [reset = 11111110]

Figure 33. STDBY_CTRL Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_S RESERVED_S RESERVED_S RESERVED_S RESERVED_S EN_VCOMP_1

VCOMP_EN

QLSLPS0_ACT

IVE

TDBY_CTRL[4] TDBY_CTRL[3] TDBY_CTRL[2] TDBY_CTRL[1] TDBY_CTRL[0]

0U

1

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. STDBY_CTRL Register Field Descriptions

Bit

7:3

2

Field

Type

R

Reset

11111

1

Description

RESERVED_STDBY_CTRL[4:0]

EN_VCOMP_10U

Read Always Returns '1'

RW

VCOMP Current Source Control bit:

0: Disable

1: Enable (Default)

1

0

VCOMP_EN

RW

1

0

VCOMP Enable Control bit:

0: Disable

1: Enable (Default)

QLSLPS0_ACTIVE

SLP_S0 & DDR_VTT_CTRL Detect logic Control

0: Normal Operation DELAY_ALL_SYS_PG is used in

QSLPS0Z (Default)

1: DELAY_ALL_SYS_PG is ignored for QSLPS0Z

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8.5.7 MISC_BITS Register (address = 0xE9) [reset = 00010000]

Figure 34. MISC_BITS Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V13_PIN_OVR

MV13EN

V6_PIN_OVR

MV6EN

msLP_S3ZPG msLP_SUSZP

G

SPARE

V13DISCHG

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. MISC_BITS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

V13_PIN_OVR

RW

0

V13 ENABLE PIN Over Ride

0: V13 is OFF if MV13EN is '1' (Default)

1: V13 is ON if MV13EN is '1'

6

5

4

3

MV13EN

RW

0

1

0

V13 Enable Pin Mask

0: DDR_VT_CTRL Pin controls V13 (Default)

1: V13_EN_PIN Bit [Bit(3)] controls V13

V6_PIN_OVR

MV6EN

V6 ENABLE PIN Over Ride

0: V6 Pin controls V6 (Default)

1: V6 is ON if VREN PIN MASK = '0'

V6 Enable Pin Mask

0: VR Enable Pin controls VR enable

1: VR Enable Pin masked V*CTLV controls VR enable (Default)

msLP_S3ZPG

SLP_S3Z is part of the power good tree

0: SLP_S3Z is part of Power Good Tree (Default)

1: SLP_S3Z is masked and set to 1 (not part of the Power Good

tree)

2

1

msLP_SUSZPG

BC_ACOK_EN

RW

0

1

SLP_SUSZ is part of the power good tree

0: SLP_SUSZ is part of Power Good Tree (Default)

1: SLP_SUSZ is masked and set to 1 (not part of the Power

Good tree)

Enables BC_ACOK output out of LVA pin. The in put is ACOK

pin, instead of ENLVA pin.

0: LVA pin is not BC_ACOK, and ENLVA is the input for LVA

output, behaving as a general purpose level-shifter.

1: LVA pin is BC_ACOK, and ACOK is the input, and ENLVA is

not functional. BC_ACOK is a level-shifted version of ACOK.

(Default)

0

V13DISCHG

RW

0

V0.6DX discharge resistance (V13)

0: no discharge (Default)

1: 100 Ω

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8.5.8 PGOOD_STAT2 Register (address = 0xE8) [reset = 00000000]

Figure 35. PGOOD_STAT2 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_P RESERVED_P RESERVED_P V12_PGOOD

GOOD_STAT2[ GOOD_STAT2[ GOOD_STAT2[

V11_PGOOD

V11_SPGD

V8_SPGD

V6_SPGD

2]

1]

0]

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. PGOOD_STAT2 Register Field Descriptions

Bit

7:5

4

Field

Type

R

Reset

000

0

Description

RESERVED_PGOOD_STAT2[2:0]

V12_PGOOD

Read Always Returns '1'

R

V12 PGOOD STATUS

0: Fail (Default)

1: Pass

3

2

1

0

V11_PGOOD

V11_SPGD

V8_SPGD

R

0

V11 PGOOD STATUS

0: Fail (Default)

1: Pass

V11S PGOOD STATUS

0: Fail (Default)

1: Pass

V8S PGOOD STATUS

0: Fail (Default)

1: Pass

V6_SPGD

V6S PGOOD STATUS

0: Fail (Default)

1: Pass

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8.5.9 PGOOD_STAT1 Register (address = 0xE7) [reset = 00000000]

Figure 36. PGOOD_STAT1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V13_PGOOD

V10_PGOOD

V9_PGOOD

V8_PGOOD

V7_PGOOD

V6_PGOOD

V5_PGOOD

V4_PGOOD

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. PGOOD_STAT1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

V13_PGOOD

R

0

V13 PGOOD STATUS

0: Fail (Default)

1: Pass

6

5

4

3

2

1

0

V10_PGOOD

V9_PGOOD

V8_PGOOD

V7_PGOOD

V6_PGOOD

V5_PGOOD

V4_PGOOD

R

0

V10 PGOOD STATUS

0: Fail (Default)

1: Pass

V9 PGOOD STATUS

0: Fail (Default)

1: Pass

V8 PGOOD STATUS

0: Fail (Default)

1: Pass

V7 PGOOD STATUS

0: Fail (Default)

1: Pass

V6 PGOOD STATUS

0: Fail (Default)

1: Pass

V5 PGOOD STATUS

0: Fail (Default)

1: Pass

V4 PGOOD STATUS

0: Fail (Default)

1: Pass

8.5.10 PWFAULT_MASK2 Register (address = 0xE6) [reset = 00000000]

Figure 37. PWFAULT_MASK2 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_P RESERVED_P RESERVED_P RESERVED_P RESERVED_P RESERVED_P V11_FLTmsK

WFAULT_MAS WFAULT_MAS WFAULT_MAS WFAULT_MAS WFAULT_MAS WFAULT_MAS

V12_FLTmsK

K2[5]

K2[4]

K2[3]

K2[2]

K2[1]

K2[0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. PWFAULT_MASK2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:2

RESERVED_PWFAULT_MASK2[5:

0]

000000

Read Always Returns '1'

1

0

V11_FLTmsK

0

V11 Power Fault Masked

0: Not Masked (Default)

1: Masked

V12_FLTmsK

V12 Power Fault Masked

0: Not Masked (Default)

1: Masked

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8.5.11 PWFAULT_MASK1 Register (address = 0xE5) [reset = 00000000]

Figure 38. PWFAULT_MASK1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V4_FLTmsK

V5_FLTmsK

V6_FLTmsK

V7_FLTmsK

V8_FLTmsK

V9_FLTmsK

V10_FLTmsK

V13_FLTmsK

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. PWFAULT_MASK1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

V4_FLTmsK

RW

0

V4 Power Fault Masked

0: Not Masked (Default)

1: Masked

6

5

4

3

2

1

0

V5_FLTmsK

V6_FLTmsK

V7_FLTmsK

V8_FLTmsK

V9_FLTmsK

V10_FLTmsK

V13_FLTmsK

RW

0

V5 Power Fault Masked

0: Not Masked (Default)

1: Masked

V6 Power Fault Masked

0: Not Masked (Default)

1: Masked

V7 Power Fault Masked

0: Not Masked

1: Masked

V8 Power Fault Masked

0: Not Masked (Default)

1: Masked

V9 Power Fault Masked

0: Not Masked (Default)

1: Masked

V10 Power Fault Masked

0: Not Masked (Default)

1: Masked

V13 Power Fault Masked

0: Not Masked (Default)

1: Masked

8.5.12 COMPH_REF Register (address = 0xE4) [reset = 00000000]

Figure 39. COMPH_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

COMP_H_DIS COMP_H_REF[ COMP_H_REF[ COMP_H_REF[ COMP_H_REF[ COMP_H_REF[ COMP_H_REF[ COMP_H_REF[

CHG

6]

5]

4]

3]

2]

1]

0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. COMPH_REF Register Field Descriptions

Bit

Field

Type

Reset

Description

7

COMP_H_DISCHG

RW

0

Comparator H Discharge value

0: No discharge

1: 100 Ω

6:0

COMP_H_REF[6:0]

RW

0000000

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

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8.5.13 COMPG_REF Register (address = 0xE3) [reset = 00011110]

Figure 40. COMPG_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C COMP_G_REF COMP_G_REF COMP_G_REF COMP_G_REF COMP_G_REF COMP_G_REF COMP_G_REF

OMPG_REF

[6]

0

[5]

0

[4]

1

[3]

1

[2]

1

[1]

1

[0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. COMPG_REF Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Comparator PGOOD Mode[7]

RW

0

Comparator Ref:

0: PGOOD Mode

1: Comparator Mode

6:0

COMP_G_REF[6:0]

RW

R

0011110

0

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

RESERVED_COMPG_REF

8.5.14 COMPF_REF Register (address = 0xE2) [reset = 00011110]

Figure 41. COMPF_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C COMP_F_REF[ COMP_F_REF[ COMP_F_REF[ COMP_F_REF[ COMP_F_REF[ COMP_F_REF[ COMP_F_REF[

OMPF_REF

6]

5]

4]

3]

2]

1]

0]

0

1

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. COMPF_REF Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Comparator PGOOD Mode[7]

RW

0

Comparator Ref:

0: PGOOD Mode

1: Comparator Mode

6:0

7

COMP_F_REF[6:0]

RW

R

0011110

0

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

RESERVED_COMPF_REF

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8.5.15 COMPE_REF Register (address = 0xE1) [reset = 00011110]

Figure 42. COMPE_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C COMP_E_REF[ COMP_E_REF[ COMP_E_REF[ COMP_E_REF[ COMP_E_REF[ COMP_E_REF[ COMP_E_REF[

OMPE_REF

6]

0

5]

0

4]

1

3]

1

2]

1

1]

1

0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. COMPE_REF Register Field Descriptions

Bit

7

Field

Type

R

Reset

0

Description

RESERVED_COMPE_REF

COMP_E_REF[6:0]

6:0

RW

0011110

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

Comparator PGOOD Mode[7]

Comparator Ref:

0: PGOOD Mode

1: Comparator Mode

8.5.16 COMPD_REF Register (address = 0xE0) [reset = 00011110]

Figure 43. COMPD_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C COMP_D_REF[ COMP_D_REF[ COMP_D_REF[ COMP_D_REF[ COMP_D_REF[ COMP_D_REF[ COMP_D_REF[

OMPD_REF

6]

5]

4]

3]

2]

1]

0]

0

1

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. COMPD_REF Register Field Descriptions

Bit

7

Field

Type

R

Reset

0

Description

RESERVED_COMPD_REF

COMP_D_REF[6:0]

6:0

RW

0011110

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

Comparator PGOOD Mode[7]

Comparator Ref:

0: PGOOD Mode

1: Comparator Mode

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8.5.17 COMPC_REF Register (address = 0xDF) [reset = 00011110]

Figure 44. COMPC_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C COMP_C_REF[ COMP_C_REF[ COMP_C_REF[ COMP_C_REF[ COMP_C_REF[ COMP_C_REF[ COMP_C_REF[

OMPC_REF

6]

0

5]

0

4]

1

3]

1

2]

1

1]

1

0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. COMPC_REF Register Field Descriptions

Bit

7

Field

Type

R

Reset

0

Description

RESERVED_COMPC_REF

COMP_C_REF[6:0]

6:0

RW

0011110

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

Comparator PGOOD Mode[7]

Comparator Ref:

0: PGOOD Mode

1: Comparator Mode

8.5.18 COMPB_REF Register (address = 0xDE) [reset = 00011110]

Figure 45. COMPB_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C COMP_B_REF[ COMP_B_REF[ COMP_B_REF[ COMP_B_REF[ COMP_B_REF[ COMP_B_REF[ COMP_B_REF[

OMPB_REF

6]

5]

4]

3]

2]

1]

0]

0

1

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. COMPB_REF Register Field Descriptions

Bit

7

Field

Type

R

Reset

0

Description

RESERVED_COMPB_REF

COMP_B_REF[6:0]

6:0

RW

0011110

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

Comparator PGOOD Mode[7]

Comparator Ref:

0: PGOOD Mode

1: Comparator Mode

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8.5.19 COMPA_REF Register (address = 0xDD) [reset = 00011110]

Figure 46. COMPA_REF Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C COMP_A_REF[ COMP_A_REF[ COMP_A_REF[ COMP_A_REF[ COMP_A_REF[ COMP_A_REF[ COMP_A_REF[

OMPA_REF

6]

0

5]

0

4]

1

3]

1

2]

1

1]

1

0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. COMPA_REF Register Field Descriptions

Bit

7

Field

Type

R

Reset

0

Description

RESERVED_COMPA_REF

COMP_A_REF[6:0]

6:0

RW

0011110

Comparator Ref:

Bits(2:0) => Reference Voltage

Bits(6:3) => Feedback selection

Comparator PGOOD Mode[7]

Comparator Ref:

0: PGOOD Mode

1: Comparator Mode

8.5.20 CLKCTRL1 Register (address = 0xD0) [reset = 00000000]

Figure 47. CLKCTRL1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_C RESERVED_C RESERVED_C RESERVED_C RESERVED_C RESERVED_C RESERVED_C

ECWAKEEN

LKCTRL1[6]

LKCTRL1[5]

LKCTRL1[4]

LKCTRL1[3]

LKCTRL1[2]

LKCTRL1[1]

LKCTRL1[0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. CLKCTRL1 Register Field Descriptions

Bit

7:1

0

Field

Type

RW

Reset

0000000

0

Description

RESERVED_CLKCTRL1[6:0]

ECWAKEEN

RW

1 Hz clock

0: clock OFF (Default)

1: Clock ON

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8.5.21 SPWRSRCINT Register (address = 0x6F) [reset = 00000000]

Figure 48. SPWRSRCINT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED1_

SPWRSRCINT

SLOWBATT2

SLOWBATT1

SACOK

RESERVED_S RESERVED_S RESERVED_S RESERVED_S

PWRSRCINT[3 PWRSRCINT[2 PWRSRCINT[1 PWRSRCINT[0

]

0

R

0

R

0

R

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. SPWRSRCINT Register Field Descriptions

Bit

7

Field

Type

R

Reset

Description

RESERVED1_SPWRSRCINT

SLOWBATT2

0

6

R

LOWBATT2 detection status

0: BATT2 above threshold (Default)

1: BATT2 below threshold

5

4

SLOWBATT1

R

0

LOWBATT1 detection status

0: BATT1 above threshold (Default)

1: BATT1 below threshold

SACOK

0

AC adapter (ACOK) detection status

0:Aadapter removed (Default)

1: Adapter inserted

3:0

RESERVED_SPWRSRCINT[3:0]

0000

8.5.22 LOWBATTDET Register (address = 0x6A) [reset = 11111000]

Figure 49. LOWBATTDET Register Format

B7

B6

B5

B4

B3

B2

B1

B0

LOWBATTDB[1 LOWBATTDB[0 LOWBATT2_E LOWBATT1_E

ACIN_EN

RESERVED_L RESERVED_L RESERVED_L

OWBATTDET[2 OWBATTDET[1 OWBATTDET[0

]

N

]

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. LOWBATTDET Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

LOWBATTDB[1:0]

RW

11

Low battery detection debounce time

00: 4 RTC periods (120 us)

01: 32 RTC periods (960us)

10: 64 RTC periods (1920 us)

11: 128 RTC periods (3840us) (Default)

5

4

LOWBATT2_EN

RW

1

Low battery Two detection Enable

0: Disable

1: Enable (Default)

LOWBATT1_EN

1

Low battery One detection Enable

0: Disable

1: Enable (Default)

3

ACIN_EN

1

AC IN Comparator

0: Disable

1: Enable (Default)

2:0

RESERVED_LOWBATTDET[2:0]

000

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8.5.23 ACOKDBDM Register (address = 0x69) [reset = 00001111]

Figure 50. ACOKDBDM Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_A RESERVED_A RESERVED_A RESERVED_A

ACOKDB[1]

ACOKDB[0]

ACOKDM[1]

ACOKDM[0]

COKDBDM[3]

COKDBDM[2]

COKDBDM[1]

COKDBDM[0]

0

1

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. ACOKDBDM Register Field Descriptions

Bit

7:4

3:2

Field

Type

RW

Reset

0000

11

Description

RESERVED_ACOKDBDM[3:0]

ACOKDB[1:0]

RW

Adapter detection debounce time

00: 81 us

01: 10 ms

10: 20 ms

11: 30 ms (Default)

1:0

ACOKDM[1:0]

RW

11

Adapter detection mode

00: reserved

01: low-to-high

10: high-to-low

11: both, low-to-high and high-to-low (Default)

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8.5.24 VDLMTCRT Register (address = 0x51) [reset = 00000101]

Figure 51. VDLMTCRT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_V VDLMTCOMP TDBNCVDLMT TDBNCVDLMT VDLMTCRTH[3 VDLMTCRTH[2 VDLMTCRTH[1 VDLMTCRTH[0

DLMTCRT

CRT[1]

0

CRT[0]

0

]

0

1

0

1

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. VDLMTCRT Register Field Descriptions

Bit

7

Field

Type

RW

Reset

Description

RESERVED_VDLMTCRT

VDLMTCOMP

0

6

RW

Critical supply voltage comparator for VDCSNS pin input voltage

sense. Connect voltage divider resistors from VIN to detect

when input voltage is low

0: disable (Default)

1: enable

5:4

3:0

TDBNCVDLMTCRT[1:0]

VDLMTCRTH[3:0]

RW

00

Supply voltage monitor debounce of VDCSNS input voltage

sense pin

00: No Deglitch disable (Default)

01: 10 us

10: 1x RTC (30us)

11: 2x RTC (60us)

0101

Critical supply voltage falling threshold on VDCSNS pin.

Connect voltage divider resistors from VIN to detect when input

voltage is low. For 2S should be 4X top resistor, X bottom

resistor. [rising hysteresis = 20mV]

0000: no limit

0001: 1.2 V

0010: 1.18 V

0011: 1.16 V

0100: 1.14 V

0101: 1.12 V (Default)

0110: 1.10 V

0111: 1.08 V

1000: NA

1001: NA

1010: NA

1011: NA

1100: NA

1101: NA

1110: NA

1111: NA

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8.5.25 SDWNCTRL Register (address = 0x49) [reset = 00000000]

Figure 52. SDWNCTRL Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_S RESERVED_S RESERVED_S RESERVED_S RESERVED_S RESERVED_S RESERVED_S

SDWN

DWNCTRL[6]

DWNCTRL[5]

DWNCTRL[4]

DWNCTRL[3]

DWNCTRL[2]

DWNCTRL[1]

DWNCTRL[0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. SDWNCTRL Register Field Descriptions

Bit

7:1

0

Field

Type

R

Reset

0000000

0

Description

RESERVED_SDWNCTRL[6:0]

SDWN

RW

Forced emergency reset, bit is self clearing

0: No action

1: Force emergency reset

8.5.26 RSTCTRL Register (address = 0x48) [reset = 00011100]

Figure 53. RSTCTRL Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_R RESERVED_R RESERVED_R

TRST[1]

TRST[0]

VTHRST[2]

VTHRST[1]

VTHRST[0]

STCTRL[2]

STCTRL[1]

STCTRL[0]

0

1

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. RSTCTRL Register Field Descriptions

Bit

7:5

4:3

Field

Type

R

Reset

000

11

Description

RESERVED_RSTCTRL[2:0]

TRST[1:0]

RW

Reset time duration

00: 20 ms

01: 40 ms

10: 80 ms

11: 200 ms (Default)

2:0

VTHRST[2:0]

RW

100

Reset voltage threshold

000: 1.4 V

001: 1.5 V

010: 1.6 V

011: 1.7 V

100: 2.4 V (Default)

101: 2.6 V

110: 2.8 V

111: 3.0 V

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8.5.27 VRENPINMASK Register (address = 0x43) [reset = 00000000]

Figure 54. VRENPINMASK Register Format

B7

MV12EN

0

B6

MV11EN

0

B5

MV10EN

0

B4

MV9EN

0

B3

MV8EN

0

B2

MV7EN

0

B1

MV5EN

0

B0

MV4EN

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. VRENPINMASK Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MV12EN

RW

0

V12 Enable Pin Mask

0: VR Enable Pin controls VR enable (Default)

1: VR Enable Pin masked V*CTLV controls VR enable

6

5

4

3

2

1

0

MV11EN

MV10EN

MV9EN

MV8EN

MV7EN

MV5EN

MV4EN

RW

0

V11 Enable Pin Mask

0: VR Enable Pin controls VR enable (Default)

1: VR Enable Pin masked V*CTLV controls VR enable

V10 Enable Pin Mask

0: VR Enable Pin controls VR enable (Default)

1: VR Enable Pin masked V*CTLV controls VR enable

V9 Enable Pin Mask

0: VR Enable Pin controls VR enable (Default)

1: VR Enable Pin masked V*CTLV controls VR enable

V8 Enable Pin Mask

0: VR Enable Pin controls VR enable (Default)

1: VR Enable Pin masked V*CTLV controls VR enable

V7 Enable Pin Mask

0: VR Enable Pin controls VR enable (Default)

1: VR Enable Pin masked V*CTLV controls VR enable

V5 Enable Pin Mask

0: VR Enable Pin controls VR enable

1: VR Enable Pin masked V*CTLV controls VR enable

V4 Enable Pin Mask

0: VR Enable Pin controls VR enable (Default)

1: VR Enable Pin masked V*CTLV controls VR enable

8.5.28 REGLOCK Register (address = 0x42) [reset = 00000000]

Figure 55. REGLOCK Register Format

B7

B6

B5

B4

B3

B2

B1

B0

CNTLOCK

0

RESERVED[6] RESERVED[5] RESERVED[4] RESERVED[3] RESERVED[2] RESERVED[1] RESERVED[0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. REGLOCK Register Field Descriptions

Bit

7:1

0

Field

Type

R

Reset

0000000

0

Description

RESERVED[6:0]

CNTLOCK

RW

Locks all V*CNT registers

0: All V*CNT registers are unlocked and can be overwritten

(Default)

1: All V*CNT registers are locked and can't be overwritten

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8.5.29 VREN Register (address = 0x41) [reset = 00000000]

Figure 56. VREN Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_V RESERVED_V RESERVED_V RESERVED_V RESERVED_V RESERVED_V

EC_SLP_S4

EC_DS4

REN[5]

0

REN[4]

0

REN[3]

0

REN[2]

0

REN[1]

0

REN[0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. VREN Register Field Descriptions

Bit

7:2

1

Field

Type

RW

Reset

000000

0

Description

RESERVED_VREN[5:0]

EC_SLP_S4

RW

0: Disable (Default)

1: Enable

0

EC_DS4

RW

0

0: Disable (Default)

1: Enable

8.5.30 PWRGDCNT1 Register (address = 0x40) [reset = 01011111]

Figure 57. PWRGDCNT1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_P RSMRSTN_PW RSMRSTN_PW PCH_PWROK[ PCH_PWROK[ DEL_ALL_SYS DEL_ALL_SYS DEL_ALL_SYS

WRGDCNT1

RGD[1]

RGD[0]

1]

0]

_PWRGD[2]

_PWRGD[1]

_PWRGD[0]

0

1

0

1

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. PWRGDCNT1 Register Field Descriptions

Bit

7

Field

Type

R

Reset

0

Description

RESERVED_PWRGDCNT1

RSMRSTN_PWRGD[1:0]

6:5

RW

10

Delay of RSMRSTN_PWRGD

00: No Delay

01: 164x RTC (about 5 ms)

10: 328x RTC (about 10 ms) (Default)

11: 656x RTC (about 20 ms)

4:3

2:0

PCH_PWROK[1:0]

RW

11

Delay of PCH_PWROK compared to ALL_SYS_PWRGD

00: 82x RTC (about 2.5 ms)

01: 164x RTC (about 5 ms)

10: 328x RTC (about 10 ms)

11: 656x RTC (about 20 ms) (Default)

DEL_ALL_SYS_PWRGD[2:0]

111

Delay of SYS_PWR_OK compared to ALL_SYS_PWRGD

000: 82x RTC (about 2.5 ms)

001: 164x RTC (about 5 ms)

010: 328x RTC (about 10 ms)

011: 492x RTC (about 15 ms)

100: 656x RTC (about 20 ms)

101: 1640x RTC (about 50 ms)

110: 2460x RTC (about 75 ms)

111: 3280x RTC (about 100 ms) (Default)

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8.5.31 DISCHCNT4 Register (address = 0x3F) [reset = 00000000]

Figure 58. DISCHCNT4 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_DI RESERVED_DI V33SDISCHG[ V33SDISCHG[ V18SDISCHG[ V18SDISCHG[ V100SDISCH[1 V100SDISCH[0

SCHCNT4[1]

SCHCNT4[0]

1]

0

0]

0

1]

0

0]

0

]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. DISCHCNT4 Register Field Descriptions

Bit

7:6

5:4

Field

Type

R

Reset

00

Description

RESERVED_DISCHCNT4[1:0]

V33SDISCHG[1:0]

RW

00

V3.3S discharge resistance (V6S)

00:No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

3:2

1:0

V18SDISCHG[1:0]

V100SDISCH[1:0]

RW

00

V18S discharge resistance (V8S)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

V100S discharge resistance (V11S)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

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8.5.32 DISCHCNT3 Register (address = 0x3E) [reset = 00000000]

Figure 59. DISCHCNT3 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V18U25UDISC V18U25UDISC V12UDISCHG[ V12UDISCHG[ V100ADISCHG V100ADISCHG V085ADISCH[1 V085ADISCH[0

HG[1]

0

HG[0]

0

1]

0

0]

0

[1]

0

[0]

0

]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. DISCHCNT3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

V18U25UDISCHG[1:0]

RW

00

V1.8U_2.5U discharge resistance (V9)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

5:4

3:2

1:0

V12UDISCHG[1:0]

V100ADISCHG[1:0]

V085ADISCH[1:0]

RW

00

V1.2U discharge resistance (V10)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

V100A discharge resistance (V11)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

V085A discharge resistance (V12)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

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8.5.33 DISCHCNT2 Register (address = 0x3D) [reset = 00000000]

Figure 60. DISCHCNT2 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V5ADS3DISCH V5ADS3DISCH V33ADSWDIS V33ADSWDIS V33PCHDISCH V33PCHDISCH V18ADISCH[1] V18ADISCH[0]

G[1]

0

G[0]

0

CHG[1]

0

CHG[0]

0

G[1]

0

G[0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. DISCHCNT2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

V5ADS3DISCHG[1:0]

RW

00

V5ADS3 discharge resistance (V5)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

5:4

3:2

1:0

V33ADSWDISCHG[1:0]

V33PCHDISCHG[1:0]

V18ADISCH[1:0]

RW

00

V33A_DSW discharge resistance (V6)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

V33PCH discharge resistance (V7)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

V18A discharge resistance (V8)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

8.5.34 DISCHCNT1 Register (address = 0x3C) [reset = 00000000]

Figure 61. DISCHCNT1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_DI RESERVED_DI RESERVED_DI RESERVED_DI RESERVED_DI RESERVED_DI VCCIODISCHG VCCIODISCHG

SCHCNT1[5]

SCHCNT1[4]

SCHCNT1[3]

SCHCNT1[2]

SCHCNT1[1]

SCHCNT1[0]

[1]

[0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. DISCHCNT1 Register Field Descriptions

Bit

7:2

1:0

Field

Type

R

Reset

000000

00

Description

RESERVED_DISCHCNT1[5:0]

VCCIODISCHG[1:0]

RW

VCCIO discharge resistance (V4)

00: No discharge (Default)

01: 100 Ohm

10: 200 Ohm

11: 500 Ohm

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ZHCSDM1 –DECEMBER 2014

8.5.35 VRMODECTRL Register (address = 0x3B) [reset = 00111111]

Figure 62. VRMODECTRL Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_V RESERVED_V V33ADSW_LP

VCCIO_LPM

V085A_LPM

V12U_LPM

V100A_LPM

V5ADS3_LPM

RMODECTRL[ RMODECTRL[

M

1]

0]

0

1

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. VRMODECTRL Register Field Descriptions

Bit

7:6

5

Field

Type

R

Reset

00

Description

RESERVED_VRMODECTRL[1:0]

V33ADSW_LPM

RW

1

Force low power mode (LPM mode)

0: Force Auto mode when SLP_S0# is asserted (low)

1: LPM & Mode set by CTLV bits, ignore SLP_S0# (Default)

4

3

2

1

0

VCCIO_LPM

V085A_LPM

V12U_LPM

RW

1

Force low power mode (Auto mode)

0: Force Auto mode when SLP_S0# is asserted (low)

1: Mode set by CTLV bits, ignore SLP_S0# (Default)

Force low power mode (Auto mode)

0: Force Auto mode when SLP_S0# is asserted (low)

1: Mode set by CTLV bits, ignore SLP_S0# (Default)

Force low power mode (LPM mode)

0: Force Auto mode when DDR_VTT_CTRL is low

1: LPM & Mode set by CTLV bits, ignore SLP_S0# (Default)

V100A_LPM

V5ADS3_LPM

Force low power mode (Auto mode)

0: Force Auto mode when SLP_S0# is asserted (low)

1: Mode set by CTLV bits, ignore SLP_S0# (Default)

Force low power mode (LPM mode)

0: Force Auto mode when SLP_S0# is asserted (low)

1: LPM & Mode set by CTLV bits, ignore SLP_S0# (Default)

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8.5.36 V085ACNT Register (address = 0x38) [reset = 00101010]

Figure 63. V085ACNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V085ALVSEL[1 V085ALVSEL[0 V085AVSEL[1] V085AVSEL[0] AOACCNTV08 AOACCNTV08

CTLV085A[1]

CTLV085A[0]

]

5A[1]

1

5A[0]

0

1

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. V085ACNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

V085ALVSEL[1:0]

RW

00

V085A low power mode output voltage set point - set at

assertion of SLP_S0#

00: Disabled, voltage stays at value set by V085AVSEL[1:0]

(Default)

01: 0.70V

10: 0.75V

11: 0.80V

5:4

3:2

V085AVSEL[1:0]

RW

00

10

Output voltage select

00: 0.95V (Default)

01: 0.90V

10: 0.85V

11: 0.80V

AOACCNTV085A[1:0]

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01, forced PFM/ Auto

10: Bits D[1:0] set to 10, forced Auto/ Forced PWM (Default)

11: Bits D[1:0] set to 11, forced PWM operation

1:0

CTLV085A[1:0]

RW

10

Mode control (V12)

00: Converter disabled

01: Forced PFM/ Auto

10: Auto/ forced PWM enabled (If auto mode not present)

(Default)

11: Forced PWM operation

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ZHCSDM1 –DECEMBER 2014

8.5.37 V100ACNT Register (address = 0x37) [reset = 00101010]

Figure 64. V100ACNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V100ALVSEL[1 V100ALVSEL[0 V100AVSEL[1] V100AVSEL[0] AOACCNTV10 AOACCNTV10

CTLV100A[1]

CTLV100A[0]

]

0A[1]

1

0A[0]

0

1

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. V100ACNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

V100ALVSEL[1:0]

RW

00

V100A low power mode output voltage set point - set at

assertion of SLP_S0#

00: Disabled, voltage stays at value set by V100AVSEL[1:0]

(Default)

01: Vnom - 4%

10: Vnom - 3%

11: Vnom - 2%

5:4

3:2

V100AVSEL[1:0]

RW

10

Output voltage select

00: Vnom + 5 % (1.05V)

01: Vnom (1 V)

10: Vnom -2.5 % (0.975V) (Default)

11: Vnom - 5 % (0.95V)

AOACCNTV100A[1:0]

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01, forced PFM/ Auto

10: Bits D[1:0] set to 10, forced Auto/ Forced PWM (Default)

11: Bits D[1:0] set to 11, forced PWM operation

1:0

CTLV100A[1:0]

RW

10

Mode control (V11)

00: Converter disabled

01: Forced PFM/ Auto

10: Auto/ forced PWM enabled (If auto mode not present)

(Default)

11: Forced PWM operation

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8.5.38 V1P2UCNT Register (address = 0x36) [reset = 00111010]

Figure 65. V1P2UCNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V1P2ULVSEL V1P2UVSEL[2] V1P2UVSEL[1] V1P2UVSEL[0] AOACCNTV1P AOACCNTV1P CTLV1P2U[1]

CTLV1P2U[0]

2U[1]

1

2U[0]

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. V1P2UCNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

V1P2ULVSEL

RW

0

V1.2U low power mode output voltage set point - set at

assertion of SLP_S0#

0: Disabled, voltage stays at value set by V1P2UVSEL (Default)

1: Vnom - 3%

6:4

V1P2UVSEL[2:0]

RW

011

Output voltage select

000: Vnom + 3%

001: Vnom + 2%

010: Vnom + 1%

011: Vnom +0% (Default)

100: Vnom - 1%

101: Vnom -2%

110: Vnom -3%

111: Vnom -4%

3:2

1:0

AOACCNTV1P2U[1:0]

CTLV1P2U[1:0]

RW

10

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: no change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01, forced PFM/ Auto

10: Bits D[1:0] set to 10, forced Auto/ Forced PWM (Default)

11: Bits D[1:0] set to 11, forced PWM operation

Mode control (V10)

00: Converter disabled

01: Forced PFM/ Auto

10: Auto/ forced PWM enabled (If auto mode not present)

(Default)

11: Forced PWM operation

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8.5.39 V18U25UCNT Register (address = 0x35) [reset = 00001010]

Figure 66. V18U25UCNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_V RESERVED_V RESERVED_V RESERVED_V AOACCNTV18 AOACCNTV18 CTLV18U25U[1 CTLV18U25U[0

18U25UCNT[3] 18U25UCNT[2] 18U25UCNT[1] 18U25UCNT[0]

U25U[1]

U25U[0]

]

0

1

0

1

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. V18U25UCNT Register Field Descriptions

Bit

7:4

3:2

Field

Type

R

Reset

0000

10

Description

RESERVED_V18U25UCNT[3:0]

AOACCNTV18U25U[1:0]

RW

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01

10: Bits D[1:0] set to 10 (Default)

11: Bits D[1:0] set to 11

1:0

CTLV18U25U[1:0]

RW

10

Mode control (V9)

00: Disabled

01: Enabled

10: Enabled (Default)

11: Enabled

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8.5.40 V18ACNT Register (address = 0x34) [reset = 00101010]

Figure 67. V18ACNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V18ALVSEL[1] V18ALVSEL[0] V18AVSEL[1]

V18AVSEL[0] AOACCNTV18 AOACCNTV18

CTLV18A[1]

CTLV18A[0]

A[1]

1

A[0]

0

1

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. V18ACNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

V18ALVSEL[1:0]

RW

00

V18A low power mode output voltage set point - set at assertion

of SLP_S0#

00: Disabled, voltage stays at value set by V18AVSEL[1:0]

(Default)

01: Vnom - 4%

10: Vnom - 3%

11: Vnom - 2%

5:4

3:2

V18AVSEL[1:0]

RW

10

Output voltage select

00: Vnom + 3 %

01: Vnom + 2 %

10: Vnom (Default)

11: Vnom - 2 %

AOACCNTV18A[1:0]

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01, forced PFM/ Auto

10: Bits D[1:0] set to 10, forced Auto/ Forced PWM (Default)

11: Bits D[1:0] set to 11, forced PWM operation

1:0

CTLV18A[1:0]

RW

10

Mode control (V8)

00: Converter disabled

01: Forced PFM/ Auto

10: Auto/ forced PWM enabled (If auto mode not present)

(Default)

11: Forced PWM operation

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8.5.41 V33APCHCNT Register (address = 0x33) [reset = 00001010]

Figure 68. V33APCHCNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_V RESERVED_V RESERVED_V RESERVED_V AOACCNTV33 AOACCNTV33 CTLV33APCH[ CTLV33APCH[

33APCHCNT[3] 33APCHCNT[2] 33APCHCNT[1] 33APCHCNT[0]

APCH[1]

APCH[0]

1]

1

0]

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 43. V33APCHCNT Register Field Descriptions

Bit

7:4

3:2

Field

Type

RW

Reset

0000

10

Description

RESERVED_V33APCHCNT[3:0]

AOACCNTV33APCH[1:0]

RW

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01

10: Bits D[1:0] set to 10 (Default)

11: Bits D[1:0] set to 11

1:0

CTLV33APCH[1:0]

RW

10

Mode control (V7)

00: Disabled

01: Enabled

10: Enabled (Default)

11: Enabled

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8.5.42 V33ADSWCNT Register (address = 0x32) [reset = 00101010]

Figure 69. V33ADSWCNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V33ADSWLVS V33ADSWLVS V33ADSWVSE V33ADSWVSE AOACCNTV33 AOACCNTV33 CTLV33ADSW[ CTLV33ADSW[

EL[1]

0

EL[0]

0

L[1]

1

L[0]

0

ADSW[1]

ADSW[0]

1]

1

0]

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 44. V33ADSWCNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

V33ADSWLVSEL[1:0]

RW

00

V33A_DSW low power mode output voltage set point - set at

assertion of SLP_S0#

00: Disabled, voltage stays at value set by V33ADSWVSEL[1:0]

(Default)

01: Vnom - 4%

10: Vnom - 3%

11: Vnom - 2%

5:4

3:2

V33ADSWVSEL[1:0]

RW

10

Output voltage select

00: Vnom + 3 %

01: Vnom + 2 %

10: Vnom (Default)

11: Vnom - 2 %

AOACCNTV33ADSW[1:0]

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01, forced PFM/ Auto

10: Bits D[1:0] set to 10, forced Auto/ Forced PWM (Default)

11: Bits D[1:0] set to 11, forced PWM operation

1:0

CTLV33ADSW[1:0]

RW

10

Mode control (V6)

00: Converter disabled

01: Forced PFM/ Auto

10: Auto/ forced PWM enabled (If auto mode not present)

(Default)

11: Forced PWM operation

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8.5.43 V5ADS3CNT Register (address = 0x31) [reset = 00101010]

Figure 70. V5ADS3CNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

V5ADS3LVSEL V5ADS3LVSEL V5ADS3VSEL[ V5ADS3VSEL[ AOACCNTV5A AOACCNTV5A CTLV5ADS3[1] CTLV5ADS3[0]

[1]

0

[0]

0

1]

1

0]

0

DS3[1]

1

DS3[0]

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 45. V5ADS3CNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

V5ADS3LVSEL[1:0]

RW

00

V5ADS3 low power mode output voltage set point - set at

assertion of SLP_S0#

00: Disabled, voltage stays at value set by V5ADS3VSEL[1:0]

(Default)

01: Vnom - 4%

10: Vnom - 3%

11: Vnom - 2%

5:4

3:2

V5ADS3VSEL[1:0]

RW

10

Output voltage select

00: Vnom + 3 %

01: Vnom + 2 %

10: Vnom (Default)

11: Vnom - 2 %

AOACCNTV5ADS3[1:0]

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01, forced PFM/ Auto

10: Bits D[1:0] set to 10, forced Auto/ Forced PWM (Default)

11: Bits D[1:0] set to 11, forced PWM operation

1:0

CTLV5ADS3[1:0]

RW

10

Mode control (V5)

00: Converter disabled

01: Forced PFM/ Auto

10: Auto/ forced PWM enabled (If auto mode not present)

(Default)

11: Forced PWM operation

77

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8.5.44 VCCIOCNT Register (address = 0x30) [reset = 00001010]

Figure 71. VCCIOCNT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_V CSDECAYEN VCCIOVSEL[1] VCCIOVSEL[0] AOACCNTVCC AOACCNTVCC CTLVVCCIO[1] CTLVVCCIO[0]

CCIOCNT

IO[1]

1

IO[0]

0

1

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 46. VCCIOCNT Register Field Descriptions

Bit

7

Field

Type

R

Reset

Description

RESERVED_VCCIOCNT

CSDECAYEN

0

6

RW

Enables VCCIO decay when SLP_S0# is asserted. [wait 2us

after removing FPWM, before entering DECAY mode. Direct

FPWM to DECAY by SLP0Z may cause ringing. Decay exit time

within 100us not guaranteed for Vout > 1V.]

0: VCCIO stays at voltage set by VCCIOVSEL independent of

state of SLP_S0# (Default)

1: VCCIO decays to 0V, PGOOD is maintained when SLP_S0#

is asserted (low)

5:4

3:2

VCCIOVSEL[1:0]

RW

00

10

Output voltage select

00: 0.975V (Default)

01: 0.950V

10: 0.875V

11: 0.850V

AOACCNTVCCIO[1:0]

Mode control for exit standby (rising edge of SLP_S0#) -

changes bits D[1:0] on exit

00: No change in bits D[1:0] - fast change mode disabled

01: Bits D[1:0] set to 01, forced PFM/ Auto

10: Bits D[1:0] set to 10, forced Auto/ Forced PWM (Default)

11: Bits D[1:0] set to 11, forced PWM operation

1:0

CTLVVCCIO[1:0]

RW

10

Mode control (V4)

00: Converter disabled

01: Forced PFM/ Auto

10: Auto/ forced PWM enabled (If auto mode not present)

(Default)

11: Forced PWM operation

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8.5.45 PGMASK2 Register (address = 0x19) [reset = 00000000]

Figure 72. PGMASK2 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_P RESERVED_P RESERVED_P RESERVED_P

V18U25UPG

MV12UPG

MV33SPG

MV18SPG

GMASK2[3]

GMASK2[2]

GMASK2[1]

GMASK2[0]

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 47. PGMASK2 Register Field Descriptions

Bit

7:4

3

Field

Type

R

Reset

0000

0

Description

RESERVED_PGMASK2[3:0]

V18U25UPG

RW

V1.8_2.5U PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

2

1

0

MV12UPG

MV33SPG

MV18SPG

RW

0

V1.2U PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

V3.3S PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

V1.8S PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

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8.5.46 PGMASK1 Register (address = 0x18) [reset = 00000000]

Figure 73. PGMASK1 Register Format

B7

B6

B5

B4

MV18APG

0

B3

B2

B1

B0

MVCCIOPG

MV085APG

MV100APG

MV33APCHPG MV5ADS3PG MV33ADSWPG

MV100SPG

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 48. PGMASK1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MVCCIOPG

RW

0

VCCIO PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

6

5

4

3

2

1

0

MV085APG

MV100APG

MV18APG

RW

0

V0.85A PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

V100A PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

V1.8A PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

MV33APCHPG

MV5ADS3PG

MV33ADSWPG

MV100SPG

V3.3A PCH PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

V5A DS3 PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

V3.3A DSW PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

V100S PG is part of the power good tree

0: Power Good function is enabled (Default)

1: Power Good function is masked and set to 1 (not part of the

Power Good tree)

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8.5.47 PWRSTAT2 Register (address = 0x17) [reset = 00000000]

Figure 74. PWRSTAT2 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED[5] RESERVED[4] RESERVED[3] RESERVED[2] RESERVED[1] RESERVED[0] V100A_FAULT V085A_FAULT

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 49. PWRSTAT2 Register Field Descriptions

Bit

7:2

1

Field

Type

R

Reset

000000

0

Description

RESERVED[5:0]

V100A_FAULT

RW

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

0

V085A_FAULT

RW

0

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

8.5.48 PWRSTAT1 Register (address = 0x16) [reset = 00000000]

Figure 75. PWRSTAT1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

VCCIO_FAULT V5A_DS3_FAU V33A_DSW_F V33A_PCH_FA V18A_FAULT V18U_25U_FA V12U_FAULT V06DX_FAULT

LT

AULT

ULT

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 50. PWRSTAT1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

VCCIO_FAULT

RW

0

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

6

5

4

3

2

1

0

V5A_DS3_FAULT

V33A_DSW_FAULT

V33A_PCH_FAULT

V18A_FAULT

RW

0

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

V18U_25U_FAULT

V12U_FAULT

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

These bits indicate that the VR has lost regulation

0: Clears register

1: Indicates power fault

V06DX_FAULT

These bits indicate that the VR has lost regulation

0: Clears register (Default)

1: Indicates power fault

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8.5.49 PBSTATUS Register (address = 0x15) [reset = 00000000]

Figure 76. PBSTATUS Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED_P

BSTATUS

LVL

HT[5]

HT[4]

HT[3]

HT[2]

HT[1]

HT[0]

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 51. PBSTATUS Register Field Descriptions

Bit

7

Field

Type

R

Reset

Description

RESERVED_PBSTATUS

LVL

0

6

R

Power button present level

0: Power button held (Default)

1: Power button released

5:0

HT[5:0]

R

000000

Time that the button has been held

00000: Disabled (Default)

00001: Disabled

000010: 2 s

000011: 3 s

000100: 4 s

000101: 5 s

000110: 6 s

000111: 7 s

001000: 8 s

001001: 9 s

001010: 10 s

..

...

111100: 60 s

111101: 61 s

111110: 62 s

111111: 63 s

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8.5.50 PBCONFIG Register (address = 0x14) [reset = 00011111]

Figure 77. PBCONFIG Register Format

B7

B6

CLRHT

0

B5

FLT[5]

0

B4

FLT[4]

1

B3

FLT[3]

1

B2

FLT[2]

1

B1

FLT[1]

1

B0

FLT[0]

1

PWRBTNDBN

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 52. PBCONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PWRBTNDBN

RW

0

Power button debounce

0: 30 ms (Default)

1: 0 ms (no debounce)

6

CLRHT

RW

0

Reset of power button timer logic

0: No action (Default)

1: Reset of HT, bit is self clearing

5:0

FLT[5:0]

011111

Time that the button must be held to force an emergency reset

000000: 0 s

000001: 1 s

000010: 2 s

000011: 3 s

000100: 4 s

000101: 5 s

000110: 6 s

000111: 7 s

001000: 8 s

001001: 9 s

001010: 10 s

..

011111: 31 s (Default)

...

111100: 60 s

111101: 61 s

111110: 62 s

111111: 63 s

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8.5.51 IRQLVL1msK Register (address = 0x13) [reset = 10100101]

Figure 78. IRQLVL1msK Register Format

B7

B6

B5

B4

B3

B2

B1

B0

MRESET

RESERVED2_I

RQLVL1msK

MPMU

RESERVED1_I RESERVED1_I

RQLVL1msK[1] RQLVL1msK[0]

MPWRSRC

RESERVED_IR

QLVL1msK

MPWRBTN

1

0

1

0

1

0

1

RW

R

RW

R

RW

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 53. IRQLVL1msK Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MRESET

RW

1

RESET mask interrupt

0: Not masked

1: Masked (Default)

6

5

RESERVED2_IRQLVL1msK

MPMU

R

0

1

RW

Power monitor mask interrupt

0: Not masked

1: Masked (Default)

4:3

2

RESERVED1_IRQLVL1msK[1:0]

MPWRSRC

R

00

1

RW

Power source mask interrupt

0: Not masked

1: Masked (Default)

1

0

RESERVED_IRQLVL1msK

MPWRBTN

R

0

1

RW

Power button mask interrupt

0: Not masked

1: Masked (Default)

8.5.52 RESETIRQ2MASK Register (address = 0x12) [reset = 00000010]

Figure 79. RESETIRQ2MASK Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED1_ RESERVED1_ RESERVED1_ RESERVED1_ RESERVED1_ RESERVED1_

RESETIRQ2M RESETIRQ2M RESETIRQ2M RESETIRQ2M RESETIRQ2M RESETIRQ2M

MCRITTEMP

RESERVED_R

ESETIRQ2MAS

K

ASK[5]

ASK[4]

ASK[3]

ASK[2]

ASK[1]

ASK[0]

0

1

0

R

RW

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 54. RESETIRQ2MASK Register Field Descriptions

Bit

Field

Type

Reset

Description

7:2

RESERVED1_RESETIRQ2MASK[5:

0]

R

000000

1

0

MCRITTEMP

RW

R

1

0

Temperature triggered reset mask interrupt

0: Not masked

1: Masked (Default)

RESERVED_RESETIRQ2 MASK

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8.5.53 RESETIRQ1MASK Register (address = 0x11) [reset = 00110000]

Figure 80. RESETIRQ1MASK Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED1_ RESERVED1_

RESETIRQ1M RESETIRQ1M

MFCO

MVRFAULT

RESERVED_R RESERVED_R RESERVED_R RESERVED_R

ESETIRQ1MAS ESETIRQ1MAS ESETIRQ1MAS ESETIRQ1MAS

ASK[1]

ASK[0]

K[3]

K[2]

K[1]

K[0]

0

1

0

R

RW

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 55. RESETIRQ1MASK Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

RESERVED1_RESETIRQ1MASK[1:

0]

R

00

5

4

MFCO

RW

R

1

Power button triggered reset mask interrupt

0: Not masked

1: Masked (Default)

MVRFAULT

1

Voltage regulator triggered reset mask interrupt

0: Not masked

1: Masked (Default)

3:0

RESERVED_RESETIRQ1MASK[3:0

]

0000

8.5.54 MPWRSRCINT Register (address = 0x0C) [reset = 01111000]

Figure 81. MPWRSRCINT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED1_

MPWRSRCINT

MLOWBAT2

MLOWBAT1

MACOK

MPMICHOT

RESERVED_M RESERVED_M RESERVED_M

PWRSRCINT[2 PWRSRCINT[1 PWRSRCINT[0

]

0

1

0

R

0

R

0

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 56. MPWRSRCINT Register Field Descriptions

Bit

7

Field

Type

R

Reset

Description

RESERVED1_MPWRSRCINT

MLOWBAT2

0

1

6

RW

Low battery voltage mask interrupt

0: Not masked

1: Masked (Default)

5

4

MLOWBAT1

RW

R

1

Low battery voltage mask interrupt

0: Not masked

1: Masked (Default)

MACOK

1

AC/DC adapter detection mask interrupt

0: Not masked

1: Masked (Default)

3

MPMICHOT

1

PMIC internal temperature mask interrupt

0: Not masked

1: Masked (Default)

2:0

RESERVED_MPWRSRCINT[2:0]

000

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8.5.55 MPMUINT Register (address = 0x0B) [reset = 00010100]

Figure 82. MPMUINT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED2_ RESERVED2_ RESERVED2_

MPMUACOK

RESERVED1_

MPMUINT

MPMUVDC

RESERVED_M RESERVED_M

MPMUINT[2]

MPMUINT[1]

MPMUINT[0]

PMUINT[1]

PMUINT[0]

0

1

0

1

0

R

RW

R

RW

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 57. MPMUINT Register Field Descriptions

Bit

7:5

4

Field

Type

R

Reset

000

1

Description

RESERVED2_MPMUINT[2:0]

MPMUACOK

RW

Power monitor critical supply voltage (adapter) mask interrupt

0: Not masked

1: Masked (Default)

3

2

RESERVED1_MPMUINT

MPMUVDC

R

0

1

RW

Power monitor critical supply voltage mask interrupt

0: Not masked

1: Masked (Default)

1:0

RESERVED_MPMUINT[1:0]

R

00

8.5.56 RESETIRQ2 Register (address = 0x09) [reset = 00000000]

Figure 83. RESETIRQ2 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED1[5 RESERVED1[4 RESERVED1[3 RESERVED1[2 RESERVED1[1 RESERVED1[0

CRITTEMP

RESERVED_R

ESETIRQ2

]

0

R

0

R

0

R

0

R

0

R

0

R

0

RW

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 58. RESETIRQ2 Register Field Descriptions

Bit

7:2

1

Field

Type

R

Reset

000000

0

Description

RESERVED1[5:0]

CRITTEMP

RW

Temperature triggered reset interrupt

0: Critical temperature not reached (Default)

1: Critical temperature reached, forcing emergency shutdown

0

RESERVED_RESETIRQ2

R

0

86

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8.5.57 RESETIRQ1 Register (address = 0x08) [reset = 00000000]

Figure 84. RESETIRQ1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED1_ RESERVED1_

RESETIRQ1[1] RESETIRQ1[0]

FCO

VRFAULT

RESERVED[3] RESERVED[2] RESERVED[1] RESERVED[0]

0

R

RW

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 59. RESETIRQ1 Register Field Descriptions

Bit

7:6

5

Field

Type

R

Reset

00

Description

RESERVED1_RESETIRQ1[1:0]

FCO

RW

0

Power button triggered reset interrupt

0: Power button counter has not forced an emergency reset

(Default)

1: Power button counter has forced an emergency reset

4

VRFAULT

RW

0

Voltage regulator triggered reset interrupt

0: Voltage regulator fault has not triggered an emergency reset

(Default)

1: Voltage regulator fault has triggered an emergency reset

3:0

RESERVED[3:0]

R

0000

8.5.58 PMUINT Register (address = 0x05) [reset = 00000000]

Figure 85. PMUINT Register Format

B7

B6

B5

B4

PMUACOK

B3

RESERVED1_

B2

B1

B0

RESERVED2[2 RESERVED2[1 RESERVED2[0

PMUVDC

RESERVED_P RESERVED_P

]

PMUINT

MUINT[1]

MUINT[0]

0

R

0

R

0

R

0

RW

R

RW

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. PMUINT Register Field Descriptions

Bit

7:5

4

Field

Type

R

Reset

000

0

Description

RESERVED2[2:0]

PMUACOK

RW

Adapter detection interrupt

0: No Interrupt Pending (Default)

1: AC Adapter removed (SACOK H -> L)

3

2

RESERVED1_PMUINT

PMUVDC

R

0

RW

Power monitor critical supply voltage interrupt

0: Critical supply voltage over threshold limit (Default)

1: Critical supply voltage below threshold limit

1:0

RESERVED_PMUINT[1:0]

R

00

87

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8.5.59 PWRSRCINT Register (address = 0x04) [reset = 00000000]

Figure 86. PWRSRCINT Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESERVED1_

PWRSRCINT

LOWBATT2

LOWBATT1

ACOK

PMICHOT

RESERVED[2] RESERVED[1] RESERVED[0]

0

R

RW

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. PWRSRCINT Register Field Descriptions

Bit

7

Field

Type

R

Reset

Description

RESERVED1_PWRSRCINT

LOWBATT2

0

6

RW

Low battery2 interrupt [rising-edge detect threshold =1.25V;

falling-edge hysteresis = 125mV]

0: No battery2 detected (Default)

1: Battery2 detected

5

4

LOWBATT1

ACOK

RW

0

Low battery1 interrupt [rising-edge detect threshold =1.25V;

falling-edge hysteresis = 125mV]

0: No battery1 detected (Default)

1: Battery1 detected

AC/DC adapter detection interrupt. [rising-edge detect threshold

=1.25V; falling-edge hysteresis = 125mV]

0: No adapter detected (Default)

1: Adapter detected

3

PMICHOT

RW

R

0

PMIC internal temperature interrupt

0: PMIC temperature normal (Default)

1: PMIC temperature hot

2:0

RESERVED[2:0]

000

8.5.60 IRQLVL1 Register (address = 0x02) [reset = 00000000]

Figure 87. IRQLVL1 Register Format

B7

B6

B5

B4

B3

B2

B1

B0

RESET

RESERVED2

PMU

RESERVED1[1 RESERVED1[0

PWRSRC

RESERVED

PWRBTN

]

0

R

0

R

0

RW

R

RW

R

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. IRQLVL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESET

R

0

RESET interrupt

0: Not asserted

1: Asserted

6

5

RESERVED2

PMU

R

0

Power monitor interrupt

0: Not asserted

1: Asserted

4:3

2

RESERVED1[1:0]

PWRSRC

R

00

0

Power source interrupt

0: Not asserted

1: Asserted

1

0

RESERVED

PWRBTN

R

0

RW

Power button interrupt

0: Not asserted

1: Asserted, write '1' to clear

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8.5.61 REVID Register (address = 0x01) [reset = 00000000]

Figure 88. REVID Register Format

B7

MINREV[3]

0

B6

MINREV[2]

0

B5

MINREV[1]

0

B4

MINREV[0]

0

B3

B2

B1

B0

MAJREV[3]

MAJREV[2]

MAJREV[1]

MAJREV[0]

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. REVID Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

MINREV[3:0]

RW

0000

Major revision ID

1010: A

1011: B

1100: C

1101: D

1110: E

1111: F

3:0

MAJREV[3:0]

RW

0000

Minor revision ID

0000: 0

0001: 1

0010: 2

0011: 3

0100: 4

0101: 5

0110: 6

0111: 7

8.5.62 VENDORID Register (address = 0x00) [reset = 00100010]

Figure 89. VENDORID Register Format

B7

B6

B5

B4

B3

B2

B1

B0

VENDORID[7] VENDORID[6] VENDORID[5] VENDORID[4] VENDORID[3] VENDORID[2] VENDORID[1] VENDORID[0]

0

1

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. VENDORID Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

VENDORID[7:0]

RW

00100010 Vendor ID: 0x22

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS65083x can be used in several different applications from computing, industrial interfacing and much

more. This section describes the general application information and provides more detailed description on the

TPS65083x powering the Intel SkyLake system.

9.2 Typical Applications

9.2.1 General Application

The TPS65083x can be used in any system that needs multiple voltage rails. A DC supply voltage in between

5.4V and 21V is required. If the supply voltage is less than this range then a small boost can be added to supply

the VIN and VINLDO3.

Along with the 5 DCDCs and 1 LDO, the TPS65083x has 8 general purpose comparators, 2 level shifters, board

temperature monitoring system and 3 power path comparators. latter 2 can be used as simple comparators if

desired increasing the total comparators available for use to 12 on the TPS65083x.

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Typical Applications (continued)

Cin

VIN

TPS65083x

DRVHVR1

VBSTVR1

System Level Power Goods

Comparator Block

Vout

0.1 PF

SWVR1

VSx [A-H]

8

VR1

Controller

Cout

DRVLVR1

PGNDVR1

ENx [A-H]

8

FBVR1P

FBVR1N

PGx [A-H]

8

Cin

VIN

ILIMVR1

Rcs

DRVHVR3

VBSTVR3

2

Level Shifters

2

Vout

0.1 PF

SWVR3

Cout

VR3

Controller

DRVLVR3

PGNDVR3

VIN5VSW

EN5VSW

FBVR3P

FBVR3N

Load Switches

ILIMVR3LS

ILIMVR3HS

Rcs

EN3V3SW

Cin

VIN

Digital & Control

Block

Rcs (HS)

VOUT3V3SW

VIN

VINLDO3

DRVHVR5

VBSTVR5

VIN

1 PF

0.1 PF

Vout

SWVR5

LDO3V

Internal LDOs &

4.7 PF

Supplies

Cout

LDO5V

VR5

Controller

DRVLVR5

PGNDVR5

10 PF

VREF1V25

FBVR5P

FBVR5N

0.47 PF

ILIMVR5LS

ILIMVR5HS

Rcs

Cin

VIN

Rcs (HS)

3.3V

I2C Block

VINVR2

DRVHVR4

VBSTVR4

Cin

PGNDVR2

VR2

Converter

Vout

0.1 PF

100 Q

SWVR4

FBVR2N

FBVR2P

Cout

VR4

Controller

Cout

DRVLVR4

PGNDVR4

SWVR2

Lout

Vout

LDO1

FBVR4N

FBVR4P

FBVR4N

ILIMVR4

Rcs

Cout

Cin

Figure 90. Simplifed General Block Diagram

9.2.1.1 Design Requirements

The TPS65083x requires decoupling caps on the supply pins. Follow the Electrical Characteristics for

recommended capacitance on these supplies.

The controllers, converter, LDO, and some other features can be adujusted to meet the application needs. The

following describes how to design and adjust the external components to achieve desired performances.

91

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Typical Applications (continued)

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Controller Design Procedure

Designing the controller breaks down into several steps: designing the output filter, selecting the FETs, bootstrap

capacitor, and input capacitors and setting the current limits.

Controllers VR1 and VR4 require VREG supply and capacitors. VREG should be connected to the 5V LDO and a

1uF, X5R, 20%, 10V or similar capacitor should be used for decoupling.

Cin

VIN

DRVHVRx

VBSTVRx

Lout

LDO5V

Vout

VREGVRx

0.1 PF

SWVRx

1 PF

Cout

Controller

DRVLVRx

PGNDVRx

ENVRx

FBVRxP

FBVRxN

ILIMVRx

PGVRx

Rcs

Figure 91. Controller Diagram

9.2.1.2.1.1 Selecting the Inductor

An inductor is required to be placed between the external FETs and the output capacitors. The inductor and

output capacitors together make the double-pole which contributes towards stability. In addition, the inductor is

directly responsible for the output ripple, efficiency, and transient performance. With an increase in inductance

used the ripple current decreases which, typically increases efficiency. However, with an increase in inductance

used, the transient performance decreases. Finally, the inductor selected has to be rated for appropriate

saturation current, core losses and DC resistance (DCR).

Use the equation below to calculate the recommended inductance for the controller. Let K_INDbe the ratio of I_Lripple

to the Iout_MAX. It is recommended that K_INDis set to a value between 0.2 and 0.4.

:

;

8₁₇₆× 8 F 8₁₇₆

+0

. =

8 × B × +KQP_/#:× -_+0&

+0

59

(2)

With the chosen inductance value, the peak current for the inductor in steady state operation, I_Lmax, can be

calculated using the equation below. The rated saturation current of the inductor must be higher than the I_Lmax

current.

:

;

8 F 8₁₇₆× 8₁₇₆

+0

+

= +KQP_I=T+ J

K

.I=T

2 × 8 × B × .

+0

59

(3)

Following these equations the preferred inductor selected for the controllers are listed below in the Table 65.

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Typical Applications (continued)

Table 65. Recommended Inductors

MANUFACTURER

Cyntec

PART NUMBER

PIME031B

VALUE

SIZE

HEIGHT

0.47 µH - 1 µH

0.33 µH - 2.2 µH

1 µH - 3.3 µH

3.3 mm x 3.7 mm

1.2 mm

Cyntec

PIMB041B

PIMB051B

PIME051E

PIMB051H

PIME061B

PIME061E

PIMB061H

4.45 mm x 4.75 mm

5.4 mm x 5.75 mm

6.8 mm x 7.3 mm

1.2 mm

1.5 mm

1.8 mm

1.2 mm

1.5 mm

1.8 mm

Cyntec

0.33 µH - 4.7 µH

0.47 µH - 4.7 µH

0.56 µH - 3.3 µH

0.33 µH - 4.7 µH

0.1 µH - 4.7 µH

Cyntec

9.2.1.2.1.2 Selecting the Output Capacitors

Ceramic capacitors with low ESR values provide the lowest output voltage ripple and are recommended. The

output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their

wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on

the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the

voltage ripple in PFM Mode. In order to achieve specified regulation performance and low output voltage ripple,

the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic

capacitors drops with increasing DC bias voltage.

For the output capacitors of the DCDC controller the use of a small ceramic capacitors placed as close as

possible to the inductor and the respective PGND pins of the IC is recommended. This solution typically,

provides the smallest and lowest cost solution available for DCAP2 controllers.

When selecting different output capacitance for the DCAP2 controller, use the equation below to determine the

minimum Cout required for stability of the controller.

8₁₇₆× 9

%

176

>

× 10^F6

8 × B × .

+0

59

(4)

Following this criteria, it is recommended to use listed capacitors in or similar capacitors.

9.2.1.2.1.3 Selecting the FETs

This controller is designed to drive NMOS FETs. Typically, the lower R_DSonfor the high and low side FETs the

better but, be sure to size the FETs, inductor and output capacitors appropriately as the R_DSonfor the low side

FET decreases, the minimum current limit increases. The Texas Instruments CSD87381P is recommended for

the controllers.

9.2.1.2.1.4 Bootstrap Capacitor

To make sure that the internal high side gate drivers are supplied with a stable low noise supply voltage, a

capacitor must be connected between the VBSTVRx pins and the respective SWVRx pins. Using ceramic

capacitors with the value of 0.1 µF are recommended for the converters and the controllers, respectfully. For

testing, a 0.1 µF, size 0402, 10 V capacitor was used for the controllers.

It is recommended to reserve a small resistor in series with the bootstrap capacitor in case the turn on / off of the

FETs need to be slowed in order to reduce voltage ringing on the switch node. This is common practice for

controller design.

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9.2.1.2.1.5 Setting the Current Limits

The controller has a Valley Current Limit topology, also known as a Low Side Current Limit. This type of current

limit works by limiting the current only when the low side FET is on. If the current being sourced by the low side

FET is greater than the set low side current limit, I_LS, the controller will hold the low side FET on and the high

side off until the current through the low side FET decreases below the set I_LS. Only if the current through the low

side FET is less than the I_LSwill the low side FET be allowed to turn off and the high side FET to turn on.

A fast current increase is limited by the maximum on time for the high side FET. This forces the low side FET to

turn on every period. Once the low side FET turns on, the Low Side Current Limit can control the FETs until the

current decreases below the I_LS. The maximum on time for the high side FET limits the current increase to

maximum on time multiplied by the di/dt of the inductor until the low side FET is switched on.

I_OCLis the average current when the valley current is consistently the I_LS.

I

OCL

ILS

Figure 92. I_OCLDepiction

The low side current limit for the controllers is set by a resistor, R_CS, at the I_LIMxpin. A current, I_TRIP, is sourced

across the R_CSto set the voltage for the current limit comparator. Use the equation below to determine the R_CS

resistor. It is recommended to set I_OCLto 130% of I_OUTmaxand use a resistor with ±1% or less tolerance for best

results. Since the current limit is when the inductor current is near its maximum it is recommended to use the

saturation derating of the inductor when calculating the R_CS

.

:

;

× 8

OS

8 F 8

KQP

2^EJ× . × B × 8

8 × 4_&5× (+_1%.

F

)

KJ

EJ

4_%5=

+

64+2

(5)

There is a minimum and a maximum I_OCLthat can be achieved for the given parameters used in the equation

above. To ensure that the R_CShas been sized correctly, the following equation must be true across the

application temperature range.

8

%5IEJ

< +₆₄₊₂× 4_%5< 8

%5I=T

(6)

If the controller has high side current limit then, use Equation 7 to calculate the high side R_CSresistor. The high

side current limit must be set higher than the low side current limit. Again, since the current limit is when the

inductor current is near its maximum it is recommended to use the saturation derating of the inductor when

calculating the R_CS

.

:

;

8 F 8₁₇₆× 8

+0

l4_&5KJ× l+_1%.

+

¹⁷⁶p p

2 × . × B × 8

59

+0

n

F 8µ#r × 20GÀ

3200À

4_{%5 (*5)}

=

+

64+2

(7)

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ZHCSDM1 –DECEMBER 2014

9.2.1.2.1.6 Selecting the Input Capacitors

Because of the nature of the switching converter and controller with a pulsating input current, a low ESR input

capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by

high input voltage spikes. For the controller, 12µF of input capacitance is recommended for most applications. To

achieve the low ESR requirement, a ceramic capacitor is recommended. However, the voltage rating and DC

bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without

any limit for better input voltage filtering. Be sure to size the ceramic capacitor to achieve the recommended input

capacitance. A ceramic capacitor placed as close as possible to the respective VINx and PGNDx pins of the

FETs is recommended.

The preferred capacitors for the controllers are two muRata GRM21BR61E106MA73: 10 μF, 0805, 25 V, +/-20%

or similar.

9.2.1.2.2 Converter Design Procedure

Designing the converter has only 2 steps: designing the output filter and selecting the input capacitors. The

converter must be supplied by a 3.3V source which can be provided by one of the TPS65083x controllers.

The converter requires VREG supply and capacitors. VREG should be connected to the 5V LDO and a 1uF,

X5R, 20%, 10V or similar capacitor should be used for decoupling.

Lout

VINVR2

SWVR2

Vout

3.3V

LDO5V

VREGVRx

Cin

Cout

FBVR2P

FBVR2N

Converter

1 PF

100

PGVRx

ENVRx

图 93. Converter Diagram

9.2.1.2.2.1 Selecting the Inductor

An inductor is required to be placed between the SWVRx and the output capacitors. The inductor and output

capacitors together make the double-pole which contributes towards stability. In addition, the inductor is directly

responsible for the output ripple, efficiency, and transient performance. With an increase in inductance used the

ripple current decreases which, typically increases efficiency. However, with an increase in inductance used, the

transient performance decreases. Finally, the inductor selected has to be rated for appropriate saturation current,

core losses and DC resistance (DCR).

Use the equation below to calculate the recommended inductance for the controller. Let K

_Lrippleto the Iout _MAX. It is recommended that K _INDis set to a value between 0.2 and 0.4.

be the ratio of I

IND

:

;

8₁₇₆× 8 F 8₁₇₆

+0

. =

8 × B × +KQP_/#:× -_+0&

+0

59

(8)

With the chosen inductance value, the peak current for the inductor in steady state operation, I -

, can be

Lmax

calculated using the equation below. The rated saturation current of the inductor must be higher than the I

current.

Lmax

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ZHCSDM1 –DECEMBER 2014

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:

;

8 F 8₁₇₆× 8₁₇₆

+0

+

= +KQP_I=T+ J

K

.I=T

2 × 8 × B × .

+0

59

(9)

Following these equations the preferred inductors selected for the converter are listed below in the Table 66.

Table 66. Recommended Inductors

MANUFACTURER

Cyntec

PART NUMBER

PIFE32251B-R68MS

744383230068

VALUE

0.68 µH

SIZE

HEIGHT

1.2 mm

1.0 mm

3.2 mm x 2.5 mm

2.5 mm x 2 mm

Würth

9.2.1.2.2.2 Selecting the Output Capacitors

Ceramic capacitors with low ESR values provide the lowest output voltage ripple and are recommended. The

output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their

wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on

the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the

voltage ripple in PFM Mode. In order to achieve specified regulation performance and low output voltage ripple,

the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic

capacitors drops with increasing DC bias voltage.

For the output capacitors of the DCDC converters the use of a small ceramic capacitors placed as close as

possible to the inductor and the respective PGND pins of the IC is recommended. If, for any reason, the

application requires the use of large capacitors which can not be placed close to the IC, use a smaller ceramic

capacitor in parallel to the large capacitor. The small capacitor should be placed as close as possible to the

inductor and the respective PGND pins of the IC.

At the DCDC converters the recommended capacitor for use is the muRata GRM188R60J226MEAO: 22 µF,

0603, 6.3 V, ±20% or similar. This capacitor was selected to achieve the highest derated capacitance in a small

0603 package. If the selected output voltage is greater than 3.3V then the muRata GRM21BR61A226ME44:

22µF, 0805, 10V, ± 20%, or similar is recommended for use. This capacitor is recommended to maintain the

actual capacitance as DC bias increases.

9.2.1.2.2.3 Selecting the Input Capacitors

Because of the nature of the switching converter and controller with a pulsating input current, a low ESR input

capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by

high input voltage spikes. For the controller, 12µF of input capacitance is recommended for most applications. To

achieve the low ESR requirement, a ceramic capacitor is recommended. However, the voltage rating and DC

bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without

any limit for better input voltage filtering. Be sure to size the ceramic capacitor to achieve the recommended input

capacitance. A ceramic capacitor placed as close as possible to the respective VINx and PGNDx pins of the IC is

recommended.

The preferred capacitors for the controllers are two muRata GRM21BR61E106MA73: 10 μF, 0805, 25 V, +/-20%

or similar.

9.2.1.2.3 LDO Design Procedure

The LDO must handle the fast load transients from the DDR memory for termination. Therefore, it is important to

maintain a high amount of capacitance with low ESR on the LDO outputs and inputs. Ceramic capacitors are

ideal for this. Below is the recommended capacitors.

The preferred output capacitor for the LDO is muRata GRM188R60J476M: 47 μF, 0603, 6.3 V, +/-20% or similar.

The preferred input capacitor for the LDO is muRata GRM155R60J106ME44: 10 μF, 0402, 6.3 V, +/-20% or

similar.

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9.2.1.2.4 Board Temperature Monitoring Design Procedure

Board temperature monitoring requires only 1 thermistor if only 1 sense point is desired. It can be scaled by

adding as many thermistors as sense points desired. Simply connect a PTC thermistor that has an exponential

coefficient curve from the VCOMP pin to GND and a pull up to desired voltage source on the TRIPZ pin. Place

thermistor where desired. If multiple sense points are desired string the thermistors together in a series

connection while placing the thermistors where desired.

10µA

100k

VCOMP Pin

TRIPZ Pin

RT1

+

VREF = 1.25V

±

RT2

RT3

RT4

图 94. Board Temperature Monitoring Circuit Example

The thermistors should have low room and mid temperature resistances in the range of 1kΩ to 10kΩ. The hot

point resistance should be roughly 10x mid temperature resistance in the range of 100kΩ to 200kΩ. There is an

internal 10µA current source that provides a voltage across the thermistors. Once this voltage exceeds the

comparator thershold of 1.25V the TRIPZ pin switches to LOW indicating a HOT board temperature. Therefore,

the resistance required for HOT board temperature is 125kΩ. Select thermistors that align this resistance with the

desired HOT temperature setpoint.

The recommended thermistors for this feature is the muRata PRF15BG102RB6RC.

9.2.1.2.5 Sequencing the Voltage Rails

To sequence the voltage rails of the PMIC, the power goods of the VRs and PG comparators can be feed back

into the enables for the VRs and comparators. RC delays can be added externally the PMIC can be programmed

to have delays set internally.

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9.2.1.2.6 Power Path Design Procedure

The TPS65083x has power path comparators and outputs to control the power path switches. Simiply connect a

voltage divider to the adaptor and batteries to set the threshold to the desired value. The outputs of the

comparators require a pull up since they are open-drain outputs. In-order for the power path comparators to work

without VIN supplied connect the VINPP to the power rails that are being monitored by using a diode to select

the highest voltage among the sources.

Adaptor

Battery 1

Battery 2

VINPP

Pull Up

R1a

R1b

R1c

TPS65083x

ACIN

ACOUT

BAT1OUT

BAT2OUT

BAT1IN

BAT2IN

R2a

R2b

R2c

图 95. Power Path Comparators and VINPP Supply

Example:

Desired is to measure a battery and an adaptor to decide when to switch over from battery to adaptor. The

votlages desired for thresholds are 9V and 6V respectively. Using 公式 10 the resistors required to set the 9V

threshold are R1a = and R2a = . The resistors required to set the 6V threshold are R1b = and R2b = .

8

+0

4₁= 4₂× l

F 1p

8_6DNAODKH@

(10)

9.2.1.3 Application Performance Curves

表 67. Application Curves Overview

TYPE

DESCRIPTION AND ASSUMPTIONS

FIGURE NUMBER

Using CSD87381P FET Block, PIME051H-1R0MS,

3 x GRM31CR60G227ME11 + 1 x GRM21BR60J107M, NDVCZ = HIGH, Vout = 1V

Efficiency VR1

图 96

Using PIFE32251B-R68MS,

4 x ZRB18AR60G476ME01, NDVCZ = HIGH, Vout = 1.8V

Efficiency VR2

Efficiency VR3

Efficiency VR4

Efficiency VR5

图 97

图 98

图 99

图 100

Using CSD87381P FET Block, PIMB061H-1R5MS,

3 x GRM21BR60J107M , NDVCZ = HIGH, Vout = 3.3V

Using CSD87381P FET Block, PIME051H-1R0MS,

2 x GRM31CR60G227ME11 + 1 x GRM21BR60J107M, NDVCZ = HIGH, Vout = 1.2V

Using CSD87381P FET Block, PIMB051H-3R3MS,

11 x GRM21BR61A476ME15, NDVCZ = HIGH, Vout = 5V

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ZHCSDM1 –DECEMBER 2014

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.70V

Vin=15.00V

Vin=24.00V

Vin=2.97V

Vin=3.30V

Vin=3.63V

0

1

2

3

4

5

6

7

0.0

0.5

1.0

1.5

2.0

2.5

Iout (A)

D001

图 96. Typical Efficiency for VR1

图 97. Typical Efficiency for VR2

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.70V

Vin=13.50V

Vin=24.00V

Vin=8.70V

Vin=15.00V

Vin=24.00V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Iout (A)

0

1

2

3

4

5

6

7

Iout (A)

D001

图 98. Typical Efficiency for VR3

图 99. Typical Efficiency for VR4

100

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.70V

Vin=13.50V

Vin=24.00V

0

0.5

1

1.5

2

2.5

3

3.5

Iout (A)

D001

图 100. Typical Efficiency for VR5

9.2.2 Specific Application - TPS650830 Powering the Intel SkyLake Platform Volume Configuration

Volume configuration is the lowest cost and smallest solution for SkyLake power. It combines multiple same

voltage rails into one rail reducing cost and size. Load switches are utilized to separate the rails and power the

system with correct sequencing. The PMIC controls these load switches with the power good comparators. The

TPS65083x also supports Premium configurations, see TPS650831 and TPS650832 or literature numbers:

SLVSCS5 and SLVSCS6.

99

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ZHCSDM1 –DECEMBER 2014

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All Pullup Resistors 100kohm, unless noted

V33A_DSW

V3.3S

TPS650830

V33A_DSW

(EC_VCC)

V100S

VOLUME #1 Application

Block Diagram:

V12(V085A) = No Load Sw,

V11 (V1.00A) = No Load Sw

SHUTDOWNZ

STANDBYZ

LDO3

SLP_S0Z

TTL

POWER MONITOR

Rpull-up Shared with

V100S_PG

VDDIO

OD/PP

PGVR4

V12U_PG

V33A_DSW

VREGVR4

VLDO5

ILIMVR4

FBVR4N

VDDIO

VR4

Controller

PP

AGND

FBVR4P

VBSTVR4

DRVHVR4

Volume #1

PPATH

LOGIC

V12U

VDC

Comp_PG_mod

e

CCOOMMPP

COMP

CO

Comp_Mode

Enable Logic

Pgood_logic

Vout Range

1.056V-

VDDIO

RESETZ

A

1

-

ENA & V33APCHCNT

ENB & V18U25UCNT

PGOOD A

SWVR4

DRVLVR4

PGNDVR4

1.391V

PP

B

MP

0

-

ENB & V18U25UCNT

PGOOD C

PG

EN

VSET

VSA

VSB

VSC

VSD

VSE

Vout 1.2V/

1.35V/1.1V

COC

-

ENC

V33APCH

REF

DCH

V18U25U

VCCIO(V0975)

V18S

EN/

PGOOD

LOGIC

CO

D

MP

1

0

-

END & VCCIOCNT

ENA & V33APCHCNT

PGOOD F

COMPIN_C

V33S

PGNDVR4

VDDIO

CO

E

MP

ENE

ENF

ENG

VDDIO

VSF

VSG

CO

F

MP

DDRID

ENVR4

TTL

DDRID

3 L

V100S

CO

G

MP

PGOOD G

VSH

VDDIO

LS_INC

SLP_S4Z

TTL

ENA

ENB

ENC

END

ENE

ENF

ENG

ENH

V5ADS3_PG

DDR_VTT_CTRL

SEQ

+

INTEL

AND

OEM

VDDIO

DDR_VTT_CTRL

SLP_S4Z

TTL

COMPEN_C

& V100S_PG

VINDLO1S

V12U_PG

VINLDO1[2X]

V100S_PG

SLP_SUSZ

SLP_S3Z

LDO1

SINK/SRC LDO

V0.6DX/0.675DX

/0.55DX

Vout= (VR4)/2

1A max

VOUTLDO1[2X]

EN

LOGIC

LS_INB

FBLDO1

PGA

PGB

V33APCH_PG

V18U25ULSW

COMPOUT_C

VCCIOLSW

PGC

PGD

VDDPG

PGNDLDO1[2X]

VINVR2 [2X]

SWVR2 [2X]

OD/PP

PGE

PGF

PGG

PGH

PGNDLDO1

V33A_DSW

V33APCHLSW

Rpull-up Shared

with V12U_PG

V33A_DSW

V1.8S_PG

V100S_PG

LS_OUTC

VR2

Converter

V33A_DSW

VDDPG

PG

EN

V33A_DSW

VDDIO

FBVR2P

Vout range

VSET 1.76v-1.85v

ENLVA

TTL

V18A

VREGVR2

VLDO5

V33A_DSW

(EC_VCC)

LVA

LVB

BCACOK

LS_OUTB

VDDLVS

FBVR2N

Vout 1.8V

2A max

OD/PP

c

PGNDVR2 [2X]

EN/

PGOOD

LOGIC

VDDLV

PGNDVR2

V33A_DSW

VLDO5

VDDIO

OD/PP

VREGVR1

PGVR2

ENVR2

DIGCORE

V9,V4,V33S PGOOD

DO NOT HAVE PINS!

V18A_PG

ILIMVR1

FBVR1N

V18U25ULSW

SLP_S3Z

VDDIO

V18A_EN/

DPWROK

FBVR1P

VR1

Controller

V18S

V18U25U

TTL

VDC

VBSTVR1

VBATTBKUP

Vout range

0.95v-1.05v

BACKUP

BATTERY

SELECTOR

V33ARTC

DRVHVR1

SWVR1

V100A

RTC

DIG

EN/

PGOOD

LOGIC

PG

V3P3A_RTC

TRIPZ

Vout 1.00V

EN

VSET

DRVLVR1

TH_HOTZ

THERMs

OD/PP

OEM

VCOMP

PGVR3

PGNDVR1

PGVR1

VDDIO

PGNDVR1

V33ADSW_PG

OD/PP

VDDIO

VR1_PG

NVDCZ

OD/PP

TTL

SLP_S3Z

V100S

VDDIO

VREGVR4

V33APCHLSW

V33APCH

SLP_S3Z

ENVR1

PGVR5

TTL

VINVR3

ILIMVR3HS

ILIMVR3LS

FBVR3N

V33APCH_PG

V5ADS3_PG

VDC

EN/

PGOOD

LOGIC

V33S

VDDIO

VCCIOLSW

VCCIO(V0975)

EN/

PGOOD

LOGIC

OD/PP

VR3

Controller

PG

V085A

VINVR5

FBVR3P

EN

VSET

EN

VSET

Vout range

3.23v-3.34v

VBSTVR3

ILIMVR5HS

FBVR5N

VDC

AGND

I2C AND

REGFILE

VR5

Controller

FBVR5P

DRVHVR3

SWVR3

V33A_DSW

Vout 3.3V

VDC

VBSTVR5

Vout range

4.9v-5.1v

DRVLVR3

DRVHVR5

SWVR5

V5ADS3

VDDIO

TTL

PGNDVR3

ENVR3

Vout 5V

DRVLVR5

VLDO3

PGNDVR3

OTP

VREGVR1

PGNDVR5

VIN

VDC

VLDO5

VLDO3

UVLO

VINLDO3

VDDIO

ILIMVR5LS

DFT AND

AMUX

TTL

LDO5V

REFSYS

PGNDVR5

ENVR5

SLP_SUSZ

VREF1V25

LDO3V

VIN5VSW

EN5VSW

50ohm

V100S

TEMP_ALERTZ

VDDIO [2X]

DIETEMP

OD

PGA

PGB

PGC

PGD

SW

TTL

VLDO3

SW

EN3V3SW

AGND [4]

TTL

EC

V5ADS3_PG

AGND

FROM EC

V5A_DS3

VLDO5

LEGEND

TTL = TTL LEVEL INPUT BUFFER

3L = 3 LEVEL (HI/LO/HI-Z) INPUT BUFFER

PP = PUSH-PULL OUTPUT BUFFER

PPB = PUSH PULL OUTPUT BUFFER WITH

HI-Z MODE (TEST ONLY)

OD = OPEN DRAIN OUTPUT BUFFER

TR = PUSH-PULL WITH CONTROLLED Tr

OD/PP = OPEN-DRAIN OR PUSH PULL

AGND

GROUND PLANE

AGND

PGNDVR2

PGNDVR1

PGNDVR4

PGNDLDO1

PGNDVR5

PGNDVR3

图 101. TPS650830 Volume Application Diagram

9.2.2.1 Design Requirements

The deisgn requirements are set by the Intel SkyLake Platform. Below are the requirements of the power supply

system. This procedure assumes the system is a 2S NVDC system but, the TPS65083x supports 3S NVDC, as

well as non-NVDC systems. 2S NVDC system has an input voltage range of 5.4V to 8.7V.

•

There must be 9 separate voltage rails:

–

V5A_DS3 - 5V, I_MAX= 3.5A

V3.3A_DSW - 3.3V, I_MAX= 3.5A

V3.3A_PCH - 3.3V, I_MAX= 3A

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–

V1.00A - 1.0V, I_MAX= 4.9A

VCCIO - 1.0V, I_MAX= 2.9A

V1.8A - 1.8V, I_MAX= 1A

V1.8U - 1.8V, I_MAX= 1A

VDDQ - 1.2V, I_MAX= 7.5A

VTT - 0.6V, I_MAX= ±1A

•

All rails must have maximum tolerance of ±5% of the nominal voltage at all times with load transients.

–

Load Transients are defined as 0% to 70%, 70% to 0%, 30% to 100% and 100% to 30% load current

steps relative of the I_MAXcurrent defined for each rail.

•

Maximum height of components = 1.8 mm.

Sequence in the order below:

–

V3.3A_DSW with VIN supplied

V1.8A with VIN supplied

V5A_DS3 with SLP_SUS# transition to HIGH

V3.3A_PCH with SLP_SUS# transition to HIGH

V1.00A with SLP_SUS# transition to HIGH

VDDQ with SLP_S4# transition to HIGH

V1.8U with SLP_S4# transition to HIGH

VCCIO with SLP_S3# transition to HIGH

VTT with DDR_VTT_CTRL / SLP_S0# transition to HIGH

9.2.2.2 Detailed Design Procedure

The TPS650830 supplies 6 voltage rails and controls 3 load switches to meet the sequence order for the

V3.3A_PCH, V1.8U, and VCCIO rails.

•

VR1 supplies the V1.00A rail and the VCCIO rail with a load switch.

VR2 supplies the V1.8A rail and the V1.8U rail with a load switch.

VR3 supplies the V3.3A_DSW rail and the V3.3A_PCH rail with a load switch.

VR4 supplies the VDDQ rail and the VINLDO1 for termination.

VR5 supplies the V5A_DS3 rail.

VLDO1 supplies the VTT rail.

To meet the sequencing requirement the power goods of the VRs and PG comparators are feed back into the

enables for the VRs and comparators. The 5 external control signals SLP_SUS#, _S4#, _S3#, _S0#, and

DDR_VTT_CTRL are responsible for transitioning the system from sleep state to sleep state and the reverse

sequencing.

Since, the requirements are for a 2S NVDC system the NVDCZ pin should be tied LOW.

9.2.2.2.1 Output Inductance and Capacitance

Following the recommend design procedure in Detailed Design Procedure will yield output inductance and

capacitance similar to 表 68.

表 68. SkyLake Volume Configuration Output L and C

OUTPUT

INDUCTANCE

MINIMUM OUTPUT

CAPACITANCE

CAPACITOR

MANUFACTURER

VRx

RECOMMENDED OUTPUT CAPACITORS

1 x GRM31CR60G227ME11 and

1 x ZRB18AR60G476ME01

VR1

0.56 µH

160 µF

muRata

VR2

VR3

VR4

VR5

0.68 µH

1 µH

47 µF

87 µF

117 µF

76 µF

4 x ZRB18AR60G476ME01

2 x GRM31CR60G227ME11

1 x GRM31CR60G227ME11

8 x GRM21BR61A476ME15

muRata

0.56 µH

2.2 µH

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9.2.2.3 Application Performance Curves

表 69. Application Curves Overview

TYPE

DESCRIPTION AND ASSUMPTIONS

FIGURE NUMBER

Using CSD87381P FET Block, PIMB051H-0R56M,

1 x GRM31CR60G227ME11 + 1 x ZRB18AR60G476ME01, NDVCZ = LOW, Vout = 1V

Efficiency VR1

图 102

Using PIFE32251B-R68MS,

4 x ZRB18AR60G476ME01, NDVCZ = LOW, Vout = 1.8V

Efficiency VR2

Efficiency VR3

Efficiency VR4

Efficiency VR5

图 103

图 104

图 105

图 106

Using CSD87381P FET Block, PIME051H-1R0MS,

2 x GRM31CR60G227ME11, NDVCZ = LOW, Vout = 3.3V

Using CSD87381P FET Block, PIMB051H-0R56M,

1 x GRM31CR60G227ME11, NDVCZ = LOW, Vout = 1.2V

Using CSD87381P FET Block, PIME051B-2R2MS,

8 x GRM21BR61A476ME15, NDVCZ = LOW, Vout = 5V

space

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

30

Vin=2.97V

Vin=3.30V

Vin=3.63V

20

10

0

1

2

3

4

5

6

7

0.0

0.5

1.0

1.5

2.0

2.5

Iout (A)

D001

图 102. Typical Efficiency for VR1

图 103. Typical Efficiency for VR2

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Iout (A)

0

1

2

3

4

5

6

7

Iout (A)

D001

图 104. Typical Efficiency for VR3

图 105. Typical Efficiency for VR4

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ZHCSDM1 –DECEMBER 2014

100

90

80

70

60

50

40

30

20

10

0

Vin=5.40V

Vin=8.10V

Vin=8.70V

Vin=13.50V

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

Iout (A)

D001

图 106. Typical Efficiency for VR5

9.3 System Examples

Below is a diagram of the SkyLake Platform System Power Delivery. The PMIC is flexible and adjusts well

across SkyLake platforms.

TPS650830

VOLUME

6V t 8.4V

VCORE

VCCGT

FET

2S Battery Pack

FET FET

Driver

SKYLAKE

PLATFORM

AC/DC

Adaptor

NVDC

Charger

FET

Vcore

VCCSA

SVID

FET

ALERT#

TPS650830 ± PMIC

FET

V5ADS3

FET FET

5V, 3.55A

SMBus

V3.3A_PCH

LOAD

SWITCH

V3.3A_DSW

FET FET

3.3V, 6.6A

V3.3S

LOAD

SWITCH

Protection

LOAD V1.8U_V2.5U

SWITCH

V1.8A

1.00V

1.8V, 1.8A

SMBus

EC

Embedded

Controller

LOAD

SWITCH

Gas

Gauge

V1.8S

FET FET

1.00V, 6.81A

V0.85A

V1.00A

Legend:

V1.2U

1.2V, 7.47A

Power bus

Signal Wire

LOAD

SWITCH

VCCIO

V0.6DX

0.6V, 1.2A

I2C

LOAD

SWITCH

V1.0S

Integrated FET

regulator

External FET

regulator

图 107. TPS650830 Volume Simplified System Power Configuration Diagram

9.4 Do's and Don'ts

•

Always either float or connect the VINPP to the same voltage as VIN. Never ground VINPP.

If not using a voltage regulator connect the enable to ground and float the output.

103

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10 Power Supply Recommendations

Any power supply capable of delivering the required input power is acceptable provided that there is a source

within the recommended operating conditions for VIN and VINLDO3. The input voltage for the VR2 converter

must be 3.3V always. The input voltage of the controllers may vary from the VIN and VINLDO3 voltage. Ensure

that VINPP is connected to the VIN or floated but not grounded.

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11 Layout

11.1 Layout Guidelines

For all switching power supplies, the layout is an important step in the design, especially at high peak currents

and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as

well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground

tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.

Use a common ground node for power ground and a different one for control ground to minimize the effects of

ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.

There are 2 packages availible for the TPS65083x, the ZAJ and ZCG. The ZAJ is a 7 mm x 7 mm BGA with 0.5

mm ball pitch. The ZCG is a 9 mm x 9 mm BGA with 0.5 mm ball pitch but, some of the inner balls have been

removed for easier routing. Both packages preform relatively the same and the decision between which package

is best for the application depends on the space constraints and routing technology used.

11.1.1 Fanout for ZAJ using Type 4 Routing

This small 7 mm x 7 mm package utilizes the Type 4 routing technique to decrease system board area as much

as possible. This Type 4 rounting has vias in pad, blind and buried vias, and minimum trace width / spacing of 4

mils.

= Ball Pad

4 mil

= Via, with 10 mil pad

and 6 mil drill

= Top Layer Trace

10 mil

6 mil

= Inner 1 / Bottom

Layer Trace

= Inner 2 / Bottom

Layer Trace

10 mil

Inner Balls

图 108. Fanout for ZAJ Package Using Type 4 Routing

105

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Layout Guidelines (接下页)

11.1.2 Fanout for ZCG using Type 3 Routing

The ZCG has some of the inner balls removed to essentially create a 0.1 mm ball pitch for the inner balls of the

package. This feature allows for Type 3 routing of the board. This Type 3 routing has no vias in pad, no blind and

buried vias, and minimum trace width / spacing of 4 mils.

= Ball Pad

= Via, with 20 mil pad

and 10 mil drill

= Top Layer Trace

10 mil

4 mil

= Inner 1 / Bottom

Layer Trace

= Inner 2 / Bottom

Layer Trace

20 mil

Inner Balls

图 109. Fanout for ZCG Package using Type 3 Routing

11.1.3 Layout Checklist

•

All inductors, input/output caps and FETs for the converters and controller should be on the same board layer

as the IC.

•

Place feedback connection points near the output capacitors and minimize the control feedback loop as much

as possible to achieve the best regulation performance.

•

Bootstrap capacitors must be place close to the IC from the SWVRx to VBSTVRx pins.

DRVLVRx signals must be routed on the same layer as the IC and the FETs and minimize the length and

parasitic inductance of the trace as much as possible.

•

Each converter and controller should have their own separate ground and each ground should connect to the

common ground separately. The input capacitors, output capacitors, and FET grounds for each VRx

converter and controller must be connected to the ground plane for the respective VRx rail. Since, the PGNDs

for each rail are not connect to each other or AGND, it is required to use the PGNDVRx pins for the input and

ouput capacitors for each VRx rail. This ground plane should connect in one place to the common ground

close to the input and output capacitor ground pads. See the figure below for a visual representation of the

converter layout scheme.

•

The internal reference regulators must have their input and output caps close to the IC pins.

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Layout Guidelines (接下页)

•

Route the FBVRxP and FBVRxN signals as a differential pair.

11.2 Layout Example

11.2.1 ZAJ Package

图 110. Top Layer ZAJ Layout

图 111. Bottom Layer ZAJ Layout

11.2.2 ZCG Package

图 112. Top Layer ZCG Layout

图 113. Bottom Layer ZCG Layout

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11.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-

dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

•

Improving the power dissipation capability of the PCB design

Improving the thermal coupling of the component to the PCB by soldering the PowerPAD™

Introducing airflow in the system

For more details on how to use the thermal parameters in the dissipation ratings table please check the Thermal

Characteristics Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).

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12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

如需获得器件支持，请在此将问题提交至 E2E 论坛：e2e.ti.com

12.1.2 开发支持

关于

TPS65083x

的常见问题解答

(FAQ)，请参见此处的

FAQ：http://e2e.ti.com/support/power_management/pmu/w/design_notes/2898.tps65083x-faqs

12.2 文档支持

12.2.1 相关文档

应用报告《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》（文件编号：SZZA017）

应用报告《半导体和 IC 封装热指标》（文件编号：SPRA953）

12.3 商标

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

109

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13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

110

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型号：	TPS650830ZCGR
厂家：	TEXAS INSTRUMENTS
描述：	用于 Skylake 处理器的可编程中等输入电压范围电源管理 IC (PMIC) \| ZCG \| 159 \| -40 to 85 集成电源管理电路
文件：	总116页 (文件大小：1853K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS650830ZCGR [TI]

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