TPS65142RTGR [TI]
LCD Bias Power Integrated with WLED Backlight Drivers;
| 型号： | TPS65142RTGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LCD Bias Power Integrated with WLED Backlight Drivers CD |
| 文件： | 总32页 (文件大小：2934K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65142
www.ti.com
SLVSAX5 –JULY 2011
LCD Bias Power Integrated with WLED Backlight Drivers
Check for Samples: TPS65142
•
•
•
•
Overvoltage Protection
Thermal Shutdown
Undervoltage Lockout
32-Pin 6 x 3 mm2 QFN Package
1
FEATURES
•
•
Integrated Bias and Backlight Power
2.3 V to 6 V Input Voltage Range for Bias
–
Up to 16.5 V Boost Converter with 1.8 A
Switch Current
APPLICATIONS
•
•
–
1.2 MHz/650 kHz Selectable Switching
Frequency
Note-PC TFT-LCD Panels
Tablet TFT-LCD Panels
–
–
–
–
–
–
–
Internal Compensation
Internal Soft-start at Power on
Reset Function (XAO Signal)
Regulated VGH
Regulated VGL
Gate Voltage Shaping
LCD Discharge Function
DESCRIPTION
The TPS65142 provides a compact solution to the
bias power and the WLED backlight in note-pc
TFT-LCD panels. The device features
converter, a positive charge pump regulator, and a
negative charge pump regulator to power the source
drivers and the gate drivers. A 150mA unity-gain
high-speed buffer is offered to drive the VCOM plane.
Gate voltage shaping and the LCD discharge function
are offered to improve the image quality. A reset
function allows a proper reset of the TCON at the
power on. The TPS65142 also offers the complete
solution to driver up to 6 chains of WLEDs with
1000:1 ratio PWM dimming.
a boost
•
•
150 mA Unity Gain VCOM Buffer
4.5 V to 24 V WLED Backlight Input Range
–
–
–
–
–
–
–
Integrated 1.5 A/40 V MOSFET
Boost Output Tracks WLED Voltage
Internal Compensation
External Current Setting Input
6 Current-Sink Channels of 25 mA
Better than 3% Current Matching
Up to 1000:1 PWM Dimming Range
All features are integrated in a compact 6 x 3 mm2
Thin QFN package.
SPACER
V
AVDD
9 V/300 mA
IN
3.3 V
AVDD Boost Converter
Positive Charge Pump Regulator,
Gate Voltage Shaping
LCD Discharge Function
V
GHM
24 V/20 mA
V
GL
-6 V/20 mA
Negative Charge Pump Regulator
Reset Function
XAO
V
COM
(±±50 mAꢀ
Unity Gain VCOM Buffer
BL_PWR
4.5 V to 24 V
6
IFB
n
25 mA
WLED Boost Converter
With Current Sinks
PWM_DIM
BL_EN
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65142
SLVSAX5 –JULY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)(2)
TA
ORDERING
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65142RTGR
32-Pin 6×3 TQFN
TS65142
(1) The device is supplied taped and reeled, with 3000 devices per reel.
(2) All voltage values are with respect to ground terminal.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
6.5
6.5
20
Input voltage range
–0.3
V
V
FB, FREQ, COMP, VDPM, VFLK, VDET, FBN, XAO
SW, OPI, OPO, SUP, DRVP, DRVN, EN, DCTRL, IFB1 to IFB6
–0.3
–0.3
V
Voltage
REF, FBP and ISET
VGH, VGHM, RE
VBAT
–0.3
3.6
35
V
–0.3
V
–0.3
24
V
BL_SW and VO
Human Body Model
Machine Model
Charged Device Model
–0.3
40
V
2
kV
V
ESD rating
200
500
V
Continuous power dissipation
Storage temperature range
See the Thermal Information Table
–65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS65142
THERMAL METRIC(1)
UNITS
QFN (32 PINS)
θJA
Junction-to-ambient thermal resistance
35.4
19.9
5.6
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.4
θJCbot
1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SLVSAX5 –JULY 2011
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX UNIT
VIN
VS
Input voltage range
2.3
6
16.5
32
V
V
AVDD Boost output voltage range(1)
Positive charge pump output voltage range
Battery voltage range
VGH
VBAT
VO
V
4.5
24
V
WLED boost converter output voltage
Negative charge pump output voltage range
Inductor for the AVDD boost converter(2)
Inductor for the WLED boost converter
Input decoupling capacitor
38
V
VGL
L1
–14
4.7
4.7
1
V
10
10
µH
µH
µF
µF
µF
°C
°C
L2
CIN
CO1
CO2
TA
Output decoupling capacitor of the AVDD boost converter
Output decoupling capacitor of the WLED boost converter
Operating ambient temperature
20
2.2
–40
–40
10
85
TJ
Operating junction temperature
125
(1) Maximum output voltage is limited by the overvoltage protection and not the maximum power switch rating
(2) Refer to application section for further information.
ELECTRICAL CHARACTERISTICS
VIN = 3.3 V, VS = 9V, VGH = 20 V, VBAT = 10.8V, IISET = 15µA, VIFBx = 0.5V, EN = VIN, TA = –40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
IQ(IN)
Operating quiescent current into VIN
Operating quiescent current into VGH
Device not switching
0.17
22
0.5
40
mA
IQ(VGH)
VGH = 20 V, VFLK not oscillating
Device not switching. VS = 9 V, EN = high
Device not switching. VS = 9 V, EN = GND
VIN = 1.8 V, VS = GND
VIN = 1.8 V, VGH = 32 V
VIN = 1.8 V, VS = 16.5 V
WLED boost regulator switching, no load
EN = GND
µA
2.8
2.5
20
IQ(SUP)
Operating quiescent current into SUP
mA
ISD(VIN)
ISD(VGH)
ISD(SUP)
IQ(BAT)
ISD(BAT)
IQ(VO)
Shutdown current into VIN
Shutdown current into VGH
Shutdown current into SUP
VBAT pin quiescent current
VBAT pin shutdown current
VO pin quiescent current
33
50
µA
µA
µA
mA
µA
µA
30
3
5
0.2
18
VO = 35 V
75
VIN falling
1.9
3.9
2.1
2.2
4.45
VIN under voltage lockout threshold
V
VIN rising
UVLO
VBAT rising
VBAT under voltage lockout threshold
UVLO voltage of WLED control circuit
V
V
VBAT falling
2.2
2.5
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, VS = 9V, VGH = 20 V, VBAT = 10.8V, IISET = 15µA, VIFBx = 0.5V, EN = VIN, TA = –40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LOGIC SIGNALS FREQ, VFLK, EN, DCTRL
VIH
VIL
Logic high input voltage
VIN = 2.5 V to 6 V
2.0
V
Logic low input voltage
VIN = 2.5 V to 6 V
0.5
0.1
V
ILKG
Input leakage current of VFLK pin
VFLK = 6 V, FREQ = GND
µA
Pull-down resistance for EN and DCTRL
pins
RPD
EN = DCTRL = 3.3 V
400
800
18
1600
kΩ
AVDD BOOST CONVERTER
VS
Output voltage boost(1)
7
16.9
16.5
19
V
V
VOVP
Overvoltage protection
VS rising
TA = –40°C to 85°C
TA = 25°C
1.226
1.230
1.240 1.254
1.240 1.250
0.1
VFB
Feedback regulation voltage
Feedback input bias current
N-channel MOSFET on-resistance
V
µA
Ω
IFB
VFB = 1.240 V
VIN = VGS = 5 V, ISW = current limit
VIN = VGS = 3.3 V, ISW = current limit
0.13
0.15
0.38
0.44
rDS(ON)
AVDD Boost converter SW leakage
current
ILkg(SW)
ILIM
VIN = 1.8 V, VSW = 17 V, Device not switching
30
µA
VIN = 2.5 V to 6 V
VIN = 2.3 V to 2.5 V
FREQ = high
1.8
1.5
2.5
3.2
A
A
N-Channel MOSFET current limit
0.9
1.2
1.5
MHz
kHz
fBOOST
TSS
Switching frequency
Softstart time
FREQ = low
470
625
780
FREQ = high, L1 = 6.8 µH, CO1 = 2 0µF
and 10 mA load current
2
ms
Line regulation
Load regulation
VIN = 2.5 V … 6 V, IOUT = 10 mA
IOUT = 0 A …500 mA
0.008
0.15
%/V
%/A
VGH REGULATOR
fSWP Switching frequency
0.5 x fBOOST
MHz
V
TA = –40°C to 85°C
TA = 25°C
1.210
1.221
1.240 1.270
1.240 1.259
0.1
VFBP
Reference voltage of feedback
IFBP
Feedback input bias current
DRVP RDS(ON) (PMOS)
DRVP RDS(ON) (NMOS)
VFBP = 1.240 V
µA
Ω
rDS(ON)P1
rDS(ON)N1
VGL REGULATOR
VS = 9 V, I(DRVP) = 40 mA
VS = 9 V, I(DRVP) = –40 mA
8
3
20
10
Ω
fSWN
Switching frequency
0.5 x fBOOST
MHz
V
VREF
Reference voltage
3.05
3.12
0
3.18
48
VFBN
Reference voltage of feedback
Feedback input bias current
DRVN RDS(ON) (PMOS)
DRVN RDS(ON) (NMOS)
–48
mV
µA
Ω
IFBN
VFBN = 0 V
0.1
20
rDS(ON)P2
rDS(ON)N2
VS = 9 V, I(DRVN) = 40 mA
VS = 9 V, I(DRVN) = –40 mA
8
3
10
Ω
GATE VOLTAGE SHAPING VGHM
I(DPM)
Capacitor charge current VDPM pin
17
20
13
13
23
25
25
µA
Ω
rDS(ON)M1
rDS(ON)M2
VGH to VGHM rDS(ON) (M1 PMOS)
VGHM to RE rDS(ON) (M2 PMOS)
VFLK = low, I(VGHM) = 20 mA
VFLK = high, I(VGHM) = 20 mA, VGHM = 7.5 V
Ω
(1) Maximum output voltage limited by the overvoltage protection and not the maximum power switch rating
4
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SLVSAX5 –JULY 2011
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, VS = 9V, VGH = 20 V, VBAT = 10.8V, IISET = 15µA, VIFBx = 0.5V, EN = VIN, TA = –40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RESET
VIN(DET)
V(DET)
VIN voltage range for reset detection
Reset IC threshold
1.6
6
V
Falling
1.074
1.1 1.126
V
V(DET_HYS)
I(DET_B)
IXAO
Reset IC threshold hysteresis
Reset IC input bias current
Reset sink current capability(2)
Reset leakage current
65
mV
µA
mA
µA
V(DET) = 1.1 V
0.1
V(XAO_ON) = 0.5 V
V(XAO) = VIN = 3.3 V
1
ILKG(XAO)
2
VCOM BUFFER
VSUP
SUP input supply range(3)
IB
7
–1
2
16.5
1
V
µA
V
Input bias current
VCM = V(OPI) = VSUP/2 = 4.5 V
VOFFSET = 10 mV, I(OPO) = 10 mA
VCM = V(OPI) = V(SUP)/2 = 4.5 V, 1 MHz
VCM = V(OPI) = V(SUP)/2 = 4.5 V, no load
I(OPO) = 10 mA
VCM
CMRR
AVOL
VOL
Common Mode Input Voltage Range
Common Mode Rejection Ratio(4)
Open Loop Gain(4)
V
S – 2
66
90
dB
dB
V
Output Voltage Swing Low
0.10
0.25
VS
–
VS –
0.65
VOH
ISC
Output Voltage Swing High
Short Circuit Current
I(OPO) = 10 mA
V
0.8
150
150
Source (V(OPI) = 4.5V, V(OPO) = GND)
Sink (V(OPI) = 4.5 V, V(OPO) = 9 V)
mA
Source (V(OPI) = 4.5 V, V(OFFSET) = 15 mV)
Sink (V(OPI) = 4.5 V, V(OFFSET) = 15 mV)
150
140
40
IO
Output Current
mA
PSRR
SR
Power Supply Rejection Ratio(4)
Slew Rate(4)
–3 db Bandwidth(4)
dB
AV = 1, V(OPI) = 2 VPP
40
V/µs
MHz
BW
AV = 1, V(OPI) = 60 mVPP
50
(2) External pull-up resistor to be chosen so that the current flowing into XAO Pin (/XAO = 0 V) when active is below I(XAO) MIN = 1 mA.
(3) Maximum output voltage limited by the Overvoltage Protection and not the maximum Power Switch rating.
(4) Typical values are for reference only
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, VS = 9V, VGH = 20 V, VBAT = 10.8V, IISET = 15µA, VIFBx = 0.5V, EN = VIN, TA = –40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.204
19.4
TYP
MAX UNIT
WLED CURRENT REGULATION
V(ISET)
K(ISET)
IFB
ISET pin voltage
1.229 1.253
1000
V
(5)
Current multiple IOUT/ISET
ISET current = 20 µA
(5)
Current accuracy
ISET current = 20 µA
ISET current = 20 µA
IFB voltage = 20 V on all pins
IFB = 450 mV
20
20.6
mA
Km
(Imax–Imin)/IAVG
1% 2.5%
3
ILKG
IFB pin leakage current
µA
I(IFB_MAX)
Current sink max output current
25
mA
WLED BOOST OUTPUT REGULATION
V(IFB_L)
V(IFB_H)
V(reg_L)
VO(step)
VO dial up threshold
Measured on V(IFB) min
Measured on V(IFB) min
400
700
16
mV
mV
V
VO dial down threshold
Minimum VO regulation voltage
VO stepping voltage
100
150
mV
WLED BOOST REGULATOR POWER SWITCH
R(PWM_SW)
I(LN_NFET)
PWM FET on-resistance
PWM FET leakage current
0.2
0.45
1
Ω
V(BL_SW) = 35 V, TA = 25°C
µA
WLED OSCILLATOR
fS
Oscillator frequency
0.9
1.0
1.2
7%
MHz
Dmax
Dmin
Maximum duty cycle of WLED Boost
Minimum duty cycle of WLED Boost
IFB = 0 V
85%
94%
CURRENT LIMIT, OVER VOLTAGE AND SHORT CIRCUIT PROTECTIONS
ILIM
N-Channel MOSFET current limit
VO overvoltage threshold
D = DMAX
1.5
38
15
3
40
A
V
V
V
VOVP
VOVP(IFB)
VSC
Measured on the VO pin
Measured on the IFBx pin
39
17
IFB overvoltage threshold
20
Short circuit detection threshold
VBAT –VO, VO ramp down
1.7
2.5
Short circuit detection delay during start
up
VSC(dly)
32
ms
THERMAL SHUTDOWN
TSD
Thermal shutdown
Thermal shutdown hysteresis
Temperature rising
150
14
°C
°C
TSDHYS
(5) Tested at TA = 25°C to 85°.
6
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SLVSAX5 –JULY 2011
DEVICE INFORMATION
PIN ASSIGNMENT
TOP VIEW (6×3 32-PIN QFN PACKAGE)
27
26
25
24
23
22
21
20
19
18
17
1
2
DRVP
FBP
SW
VIN
3
AGND
DRVN
FBN
VGH
4
VGHM
RE
5
6
VDET
XAO
REF
VFLK
VDPM
IFB 3
IFB 2
IFB 1
DCTRL
PGND
(ePAD)
7
8
9
IFB 4
IFB 5
EN
10
11
PIN FUNCTIONS
PIN
NAME
SW
I/O
DESCRIPTION
NO.
1
Switch pin of the AVDD boost converter
Input supply pin
VIN
2
I
AGND
DRVN
FBN
3
Analog ground
4
O
I
Voltage driver of the negative charge pump
Negative charge pump feedback pin
Reset IC threshold pin (Voltage divider)
5
VDET
XAO
6
I
7
O
O
I
Reset IC output pulling down XAO pin when active.
Reference voltage for the negative charge pump
Channel 4 of the WLED backlight current sink
Channel 5 of the WLED backlight current sink
Backlight enable input
REF
8
IFB4
9
IFB5
10
11
12
13
14
15
16
17
18
I
EN
I
IFB6
I
Channel 6 of the WLED backlight current sink
The backlight boost converter switching node
Input of the backlight boost converter
BL_SW
VBAT
VO
I
O
I
The output of the backlight boost converter
WLED current sink level programming input
Backlight PWM dimming control input
ISET
DCTRL
IFB1
I
I
Channel 1 of the WLED backlight current sink
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PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
IFB2
NO.
19
20
21
22
23
24
25
26
27
28
I
I
Channel 2 of the WLED backlight current sink
IFB3
Channel 3 of the WLED backlight current sink
Sets the delay to enable VGHM Output. Pin for external capacitor. Floating if no delay needed
Charge/discharge signal for VGHM
VDPM
VFLK
RE
O
I
Sets the slope for the gate shaping function. Pin for external Resistor
Output for gate-high modulation
VGHM
VGH
FBP
O
I
Input for positive Charge Pump
I
Positive charge pump feedback pin
DRVP
SUP
Voltage driver of positive charge pump
I
Supply pin of the gate shaping and operational amplifier blocks. Connected as well to the overvoltage protection
comparator. This pin needs to be connected to the output of the AVDD boost converter.
OPO
OPI
29
30
31
32
O
I
Output voltage of VCOM Buffer
Input voltage of VCOM Buffer
AVDD Boost converter feedback pin
FB
I
FREQ
I
AVDD boost converter switching frequency selection: 1.2MHz when V(FREQ) = VIN and 650 kHz when V(FREQ)
ground
=
PGND
ePAD
Exposed pad that serves as the power ground for both boost converters
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SLVSAX5 –JULY 2011
BLOCK DIAGRAM
VS
VIN
SW
SUP
VIN
FB
FREQ
PGND
AVDD
Boost
Control
OPI
OPO
SW
DRVN
FBN
VGL
DRVP
FBP
Negative
Charge Pump
Regulator
Postive
Charge Pump
Regulator
VGH
VGH
VGHM
RE
REF
Linear
Regulator
VIN
Gate
Voltage
Shaping
XAO
VFLK
Reset
Function
VDET
VDPM
IFB1
IFB2
IFB3
IFB4
DCTRL
AGND
Dimming
Control
PWM
Dimming
Current
Regulator
WLED Boost
Control
IFB5
IFB6
Enable
EN
ISET
VBAT
Battery
Voltage
VO
BL_SW
PGND
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
NAME
CONDITIONS
FIGURE
BOOST CONVERTER (AVDD)
Efficiency vs. Load Current
Load Transient Response
VIN = 3.3 V, VS = 9 V, L = 6.8 µH, f = 1.2 MHz
Figure 1
Figure 2
Figure 3
Figure 4
VIN = 3.3V, VS = 9 V, IS = 50 mA to 250 mA
CCM Operation, VIN = 3.3 V, VS = 9 V, IS = 200 mA, VGH = 24 V, IGH = 10 mA
DCM Operation, VIN = 3.3 V, VS = 9 V, IS = 5 mA, VGH = 24 V, IGH = 1 mA
Switch Node (SW) Wave form
POSITIVE CHARGE PUMP (VGH
)
Output Voltage Ripple
VIN = 3.3V, VGH = 24 V, IGH = 20 mA, VS = 9 V, IS = 100 mA
VIN = 3.3 V, VGH = 21.5 V IGL = 5 mA to 15 mA, VS = 9 V, IS = 100 mA
VIN = 4.2 V, VGH = 24 V, VS = 14 V
Figure 5
Figure 6
Figure 7
Load Transient Response
Output Voltage vs Load Current
NEGATIVE CHARGE PUMP (VGL
)
Output Voltage Ripple
VIN = 3.3 V, VGL = –5.8 V IGL = 20 mA, VS = 9 V, IS = 100 mA
VIN = 3.3 V, VGL = –5.8 V IGL = 5 mA to 15 mA, VS = 9 V, IS = 100 mA
VIN = 4.2 V, VGL = –6 V, VS = 9 V
Figure 8
Figure 9
Figure 10
Load Transient Response
Output Voltage vs Load Current
POWER ON SEQUENCING
Power On Sequence
VIN = 3.3 V, VS = 9 V, VGH = 24 V, VGL = –5.8 V
VIN = 3.3 V, VS = 9 V, VGH = 24 V, VGL = –5.8 V
VIN = 3.3 V, VGH = 24 V, C(VDPM) = 100 nF, RE = 80 KΩ
VIN = 3.3 V, VGH = 24 V, C(VDPM) = 100 nF, RE = 80 KΩ
VIN = 3.3 V, VGH = 24 V, f(VFLK) = 10 KHz, RE = 80 KΩ
VIN = 3.3 V, VIN(LIM) = 2.7 V
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Power Off Sequence
Power On Sequence of VGHM
Power Off Sequence of VGHM
Gate Voltage Shaping
Reset (XAO)
WLED DRIVER
Load Efficiency of WLED Driver
Load Efficiency of WLED Driver
Dimming Linearity
VBAT = 10 V, VOUT = 19 V, 25 V and 33 V, L = 10 µH
VBAT = 10 V, 15 V and 19 V, VOUT = 35 V, L = 10 µH
VBAT = 10 V, IOUT = 120 mA, PWM Freq 100 Hz
VBAT = 15 V, IOUT = 120 mA, PWM Freq 1 kHz
VBAT = 12 V, VOUT = 30.6 V, Duty 100%, CO = 4.7 µF
VBAT = 12 V, VOUT = 30.6 V, Duty 50%, CO = 4.7 µF
VBAT = 12 V, ISET = 20 µA
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Dimming Linearity
Switching Waveform
Output Ripple at PWM Dimming
Power On Sequence
Open LED Protection
VBAT = 12 V, ISET = 20 µA
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100
90
80
VS = 100 mV/div
70
VIN = 3.3 V
VS = 9 V
60
IS = 50 mA to 250 mA
50
40
30
20
IS = 100 mA/div
10
0
0.001
0.010
0.100
1.000
Time = 2 ms / div
Load Current [A]
Figure 1. BOOST CONVERTER EFFICINECY
vs OUTPUT CURRENT
Figure 2. BOOST CONVERTER LOAD TRANSIENT
RESPONSE
SW = 5 V/div
SW = 5 V/div
IL = 200 mA/div
VS = 20 mV/div
VIN = 3.3 V
VS = 9 V, IS = 5 mA
VGH = 24 V, IGH = 1 mA
VS = 20 mV/div
IL = 200 mA/div
VIN = 3.3 V
VS = 9 V, IS = 200 mA
VGH = 24 V, IGH = 10 mA
Time = 400ns / div
Time = 400ns / div
Figure 3. BOOST CONVERTER CONTINUOUS
CONDUCTION MODE
Figure 4. BOOST CONVERTER DISCONTINOUS
CONDUCTION MODE
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SW = 5 V/div
VGH
VIN = 3.3 V
VS = 9 V, IS = 100 mA
VGH = 21.5 V,
DRVP = 5 V/div
VIN = 3.3 V
IGH = 5 mA to 15 mA
VS = 9 V, IS = 100 mA
VGH = 24 V, IGH = 20 mA
IGH
VGH = 20 mV/div
IL
Time = 2 ms / div
Time = 1 ms / div
Figure 5. POSITIVE CHARGE PUMP OUTPUT VOLTAGE
RIPPLE
Figure 6. POSITIVE CHARGE PUMP LOAD TRANSIENT
RESPONSE
27
VIN = 4.2 V
VS = 10 V
VGH = 24 V
26
25
24
-40oC
25oC
VIN = 3.3 V, VS = 9 V, IS = 100 mA
DRVN = 2 V/div
23
22
VGL = -5.8 V, IGL = 20 mA
85oC
21
20
VGL = 50 mV/div
Time = 1 ms / div
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current [A]
Figure 7. POSITIVE CHARGE PUMP VOLTAGE vs LOAD
CURRENT
Figure 8. NEGATIVE CHARGE PUMP OUTPUT VOLTAGE
RIPPLE
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-4.0
-4.2
-4.4
-4.6
-4.8
-5.0
-5.2
-5.4
VIN = 4.2 V
VS = 9 V
85oC
VGH = -6 V
25oC
VGL = 100 mV/div
VIN = 3.3 V,
-40oC
VS = 9 V, IS = 100 mA
VGH = -5.8 V, IGL = 5 mA to 15 mA
IGL = 10 mA/div
-5.6
-5.8
-6.0
Time = 2 ms / div
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current [A]
Figure 9. NEGATIVE CHARGE PUMP LOAD TRANSIENT
RESPONSE
Figure 10. NEGATIVE CHARGE PUMP VOLTAGE vs LOAD
CURRENT
VIN = 2 V/div
VS = 5 V/div
VIN = 2 V/div
VS = 5 V/div
V
GH = 10 V/div
VIN 3.3 V, VS = 9 V
VGH = 24 V, VGL = -5.8 V
V
GH = 10 V/div
VIN 3.3 V, VS = 9 V
VGH = 24 V, VGL = -5.8 V
VGL = 5 V/div
VGL = 5 V/div
Time = 4 ms / div
Time = 400 ms / div
Figure 11. POWER ON SEQUENCE
Figure 12. POWER OFF SEQUENCE
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VS = 2 V/div
VS = 5 V/div
VDPM = 1 V/div
VIN 3.3 V, VS = 9 V, VGH = 24
CVDPM = 100 nF, RE = 80 kW
VIN 3.3 V, VS = 9 V, VGH = 24
CVDPM = 100 nF, RE = 80 kW
VDPM = 1 V/div
VFLK = 5 V/div
VFLK = 5 V/div
VGHM = 10 V/div
VGHM = 10 V/div
Time = 4 ms / div
Time = 20 ms / div
Figure 13. POWER ON SEQUENCE OF VGHM
Figure 14. POWER OFF SEQUENCE OF VGHM
VFLK = 2 V/div
VIN = 1 V/div
VIN 3.3 V,
VIN 3.3 V, VGH = 24
VIN(LIM) = 2.7 V
VDET = 1 V/div
XAO = 2 V div
fVFLK = 10 KHz, RE = 80 kW
VGHM = 10 V/div
Time = 20 ms / div
Time = 40 ms / div
Figure 15. GATE VOLTAGE SHAPING
Figure 16. XAO SIGNAL
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100
100
VBAT = 19 V
VO = 19 V
95
90
85
80
75
70
65
60
55
95
90
85
80
75
70
65
60
55
VO = 25 V
VO = 33 V
VBAT = 10 V
VBAT = 15 V
VOUT = 35 V
L = 10 mH
50
50
0
0
Output Current [A]
Output Current [A]
Figure 17. LED DRIVER EFFICIENCY vs OUTPUT
CURRENT
Figure 18. LED DRIVER EFFICIENCY vs OUTPUT
CURRENT
0.12
0.10
0.08
0.06
0.04
0.02
0.12
0.10
0.08
0.06
0.04
ISET = 20 mA
ISET = 20 mA
0.02
0.00
VBAT = 15 V
VBAT = 15 V
PWM Frequency = 1 kHz
PWM Frequency = 1 kHz
0.00
0
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle [%]
10 20 30 40 50 60 70 80 90 100
Duty Cycle [%]
Figure 19. LED DRIVER PWM DIMMING LINEARITY 100Hz
Figure 20. LED DRIVER PWM DIMMING LINEARITY 1kHz
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VBAT = 100 mV/div
DCTRL = 5 V/div
BL_SW = 20 V/div
VBAT = 12 V, VO = 30.6 V (LED 10S6P)
V
O = 100 mV/div
Duty = 100%, L = 10 mH, CO = 4.7 mF
VO = 100 mV/div
IL = 1 A/div
VBAT = 12 V, VO = 30.6 V (LED 10S6P)
Duty = 50%, L = 10 mH, CO = 4.7 mF
IL = 1 A/div
Time = 1 ms / div
Figure 21. LED DRIVER SWITCHING WAVEFORM
Figure 22. LED DRIVER OUTPUT RIPPLE AT PWM
DIMMING
VO = 10 V/div
EN = 5 V/div
BL_SW = 10 V/div
VO = 10 V/div
VBAT = 12 V, VO = 30.6 V (LED 10S6P)
Duty = 100%, L = 10 mH, CO = 4.7 mF
VBAT = 12 V, VO = 30.6 V
(LED 10S1P)
IL = 1 A/div
Duty = 100%, L = 10 mH
CO = 4.7 mF
ILED (One String) = 20 mA/div
IL = 200 mA/div
Time = 20 ms / div
Time = 400 ms / div
Figure 23. LED DRIVER POWER ON SEQUENCE
Figure 24. LED DRIVER OPEN WLED PROTECTION
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FUNCTIONAL DESCRIPTION
The TPS65142 offers a compact and complete solution to the bias power and the WLED backlight in note-pc
TFT-LCD panels. The device features an AVDD boost regulator, a positive charge pump regulator, and a
negative charge pump regulator to power the source drivers and the gate drivers. A 150 mA unity-gain
high-speed buffer is provided to drive the VCOM plane. Gate voltage shaping and the LCD discharge function
are offered to improve the image quality. A reset function allows a proper reset of the TCON at power on or the
gate driver ICs during power off. The TPS65142 also includes the complete solution to drive up to 6 chains of
WLEDs with 1000:1 ratio PWM dimming.
AVDD BOOST REGULATOR
The AVDD boost regulator is designed for output voltages up to 16.5 V with a switch peak current limit of 1.8 A
minimum. The device, which operates in a current-mode scheme with quasi-constant frequency, is internally
compensated to minimize the pin and component counts. The switching frequency is selectable between 650
kHz and 1.2 MHz and the minimum input voltage is 2.3 V.
During the on-time, the current rises in the inductor. When the current reaches a threshold value set by the
internal GM amplifier, the power transistor is turned off. The polarity of the inductor voltage changes and forward
biases the Schottky diode, which lets the current flow towards the output of the boost regulator. The off-time is
fixed for a certain input voltage VIN and output voltage VS, and therefore maintains the same frequency when
varying these parameters. However, for different output loads, the frequency changes slightly due to the voltage
drop across the rDS(ON) of the power transistor which will have an effect on the voltage across the inductor and
thus on tON (tOFF remains fixed).
The fixed off-time maintains a quasi-fixed frequency that provides better stability for the system over a wide
range of input and output voltages than conventional boost converters. The TPS65142 topology has also the
benefits of providing very good load and line regulations, and excellent line and load transient responses.
VS
VIN
VIN
FREQ
SW
Current Limit
& Soft Start
Bias VBG = 1.24V
UVLO
Thermal Shutdown
SUP
TOFF
Generator
Over-Voltage
Protection
TON
PWM
Generator
Gate Driver of
Power Transister
R
2
GM Amplifier
FB
VFB
R
3
PGND
Figure 25. Boost Converter Block Diagram
Setting the Output Voltage
The output voltage is set by an external resistor divider. Typically, a minimum current of 50 µA flowing through
the feedback divider is enough to cover the noise fluctuation. If 70 µA is chosen for higher noise immunity, the
resistors shown in Figure 25 are then calculated as:
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æ
ç
è
ö
VFB
VS
R3
=
» 18.2 kΩ
R2 = R3
´
-1
÷
70 μA
where VFBP = 1.240 V
Soft-Start (AVDD Boost Converter)
VFB
ø
(1)
The AVDD boost converter has an internal digital soft-start to prevent high inrush current during start-up. The
typical soft-start time is 2ms.
Frequency Select Pin (FREQ)
The digital frequency-select pin FREQ allows to set the switching frequency of the device to 650 kHz (FREQ =
low) or 1.2MHz (FREQ = high). Higher switching frequency improves load transient response but reduces slightly
the efficiency. The other benefit of a higher switching frequency is the lower output voltage ripple. Usually, it is
recommended to use1.2 MHz switching frequency unless light load efficiency is a major concern.
Overvoltage Protection
The AVDD boost converter has an integrated over-voltage protection to prevent the power switch from exceeding
the absolute maximum switch voltage rating at pin SW in case the feedback (FB) pin is floating or shorted to
GND. In such an event, the output voltage rises and is monitored with the overvoltage protection comparator
over the SUP pin. As soon as the comparator trips at typically 18 V, the boost converter turns the N-Channel
MOSFET switch off. The output voltage falls below the overvoltage threshold and the converter continues to
operate. In order to detect overvoltage, the SUP pin must to be connected to the output voltage of the boost
converter VS.
Regulated Positive Charge Pump
The positive charge pump sets the voltage applied on the VGH input pin, up to 32 V in tripler mode configuration.
The charge pump block regulates the VGH voltage by adjusting the drive current IDRVP. Typically, a minimum
current of 50 µA flowing through the feedback divider is usually enough to cover the noise fluctuation. If 70 µA is
chosen for higher noise immunity, the resistors of the divider used to set the VGH voltage are calculated as (refer
to Figure 26):
æ
ç
è
ö
VFBP
VGH
R8
=
» 18.2 kΩ
R7 = R8
´
-1
÷
70 μA
VFBP
ø
(2)
where VFBP = 1.240 V
VIN
VS
SW
SUP
SW
Clock of
Boost
Converter
?2
Positive
Charge
Pump
DRVP
Driver
VGH
R
7
FBP
R
8
VFBP
Figure 26. Block Diagram of the Positive Charge Pump Regulator
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Negative Charge Pump
Figure 27 shows the block diagram of the negative charge pump. The negative charge pump needs to generate
a voltage of –6 V to –7 V with a negative inverter or –12 V to –13 V with a negative doubler. The reference
voltage from the REF pin is 3.15 V. The bias to the REF block comes from the SUP pin. The error amplifier is
referenced to the ground. The VGL can be set with the following equation:
R4
VGL = -
´ VREF
R5
(3)
where VREF = 3.15 V
SUP
Clock of
Boost
converter
?2
Negative
Charge
Pump
VGL
DRVN
Regulator
R4
R5
FBN
REF
SUP
Reference
Regulator
Figure 27. Block Diagram of the Negative Charge Pump Regulator with a Negative Inverter Configuration
SW
VGL
R4
FBN
REF
DRVN
R5
Figure 28. Negative Doubler Configuration for the Negative Charge Pump Regulator
Gate Voltage Shaping
The VGHM output is controlled by the VFLK logic input and the VDPM voltage level.
The VDPM pin allows the user to set a delay before the Gate Voltage Shaping starts. The voltage of the VDPM
pin is zero volt at power on. When the output voltage of the AVDD boost converter rises above a power-good
threshold, a power-good signal enables a 20 µA current source that charges the capacitor connected between
the VDPM pin and the ground. When the VDPM-pin voltage rises to 1.240 V, the Gate Voltage Shaping is
enabled.
The VFLK input controls the M1 and the M2 transistors, as shown in Figure 29, after the Gate Voltage Shaping is
enabled:
When VFLK = “low”, M1 is turned on so VGHM is connected to the VGH input.
When VFLK = “high”, M2 is turned on so VGHM voltage is discharged through M2 and the resistor
connected to the RE pin.
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SUP
20 mA
VGH
VDPM
M1
M2
VGHM
1.240 V
Gate Voltage
Shaping
VFLK
RE
Figure 29. Block Diagram of the Gate Voltage Shaping Function
Boost
Power Good
VFKL = ’high’
VFLK
VFKL=’low’
Unknown state
VGH
Delay set
by VDPM
VGHM
Slope set
by RE
0V
Figure 30. Gate Voltage Shaping Timing
VCOM Buffer
The VCOM Buffer power supply pin is the SUP pin connected to the AVDD boost converter VS. To achieve good
performance and minimize the output noise, a 1-µF ceramic bypass capacitor is required directly from the SUP
pin to ground. The buffer is not designed to drive high capacitive loads; therefore, it is recommended to connect
a series resistor at the output to provide stable operation when driving a high capacitive load. With a 3.3-Ω series
resistor, a capacitive load of 10 nF can be driven, which is usually sufficient for typical LCD applications.
Reset
The device has an integrated reset function with an open-drain output capable of sinking 1 mA. The reset
function monitors the voltage applied to its sense input V(DET). As soon as the voltage on V(DET) falls below the
threshold voltage, V(DET), of typically 1.1 V, the reset function asserts its reset signal by pulling XAO low.
Typically, a minimum current of 50 µA flowing through the feedback divider is enough to cover the noise
fluctuation. Therefore, to select R12 and R13 (see Figure 33), one has to set the input voltage limit (VIN(LIM)) at
which the reset function will pull XAO to low state. VIN(LIM) must be higher than the UVLO threshold. If 70 µA is
chosen,
æ
ö
V
V
IN(LIM)
(DET)
R13
=
» 18.2 kΩ
R12 = R13
´
-1
ç
ç
è
÷
÷
ø
70 μA
V
(DET)
(4)
where VDET = 1.1 V.
The XAO output is also controlled by the UVLO function. When the input voltage is below the UVLO threshold,
XAO output is forced low until the input voltage is lower than 1.6 V. The XAO output is in an unknown state when
the input voltage is below the 1.6 V threshold.
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VDET
VDET_threshold+
Hys
VDET_threshold
Min. Operating
Voltage
1.6V
GND
Unknown state
XAO
GND
Figure 31. Voltage Detection and XAO Pin
When the input voltage VIN rises, once the voltage on VDET pin exceeds its threshold voltage plus the
hysteresis, the XAO signal will go high.
The reset function is operational for VIN ≥ 1.6 V.
The reset function is configured as a standard open-drain and requires a pull-up resistor. The resistor R(XAO) (R14
in Figure 33), which must be connected between the XAO pin output and a positive voltage VX greater than 2 V –
'high' logic level can be chosen as follows:
VX
VX - 2 V
R14
>
and
R14<
1 mA
2 μA
(5)
Under-voltage Lockout (UVLO)
The TPS65142 monitors both VIN and VBAT inputs for under-voltage lockout. When the VIN input in under its
UVLO threshold, the whole IC is disabled to avoid mis-operation. When the VIN input rises above its UVLO
threshold, all functions are enabled except the WLED driver. The WLED driver, including the WLED boost
converter and the current sinks, will be enabled when the VBAT input is also higher than its UVLO threshold.
Thermal Shutdown
A thermal shutdown is implemented to prevent damages because of excessive heat and power dissipation.
Typically the thermal shutdown threshold for the junction temperature is 150°C. When the thermal shutdown is
triggered the device stops switching until the junction temperature falls below typically 136°C. Then the device
starts switching again.
WLED BOOST REGULATOR
The WLED boost regulator is a current-mode PWM regulator with internal loop compensation. The internal
compensation ensures a stable output over the full input and output voltage range. The WLED boost regulator
switches at fixed 1 MHz. The output voltage of the boost regulator is automatically set by the TPS65142 to
minimize the voltage drop across the current-sink IFBx pins. The lowest IFB-pin voltage to regulated to 400 mV.
When the output voltage is too close to the input, the WLED boost regulator may not be able to regulate the
output due to the limitation of the minimum duty cycle. In that case, the user needs to increase the number of
WLED in series or to include series ballast resistors to provide enough headroom for the boost converter to
operate. The WLED boost regulator cannot regulate its output to a voltage below 15 V.
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Current Sinks
The six current sink regulators can each provide a maximum of 25 mA. The IFB current must be programmed to
the highest WLED current expected using an ISET-pin resistor with the following equation:
V
(ISET)
I(FB) = K(ISET)
R(ISET)
(6)
where
K(ISET) = Current multiple (1000 typical)
V(ISET) = ISET pin voltage (1.229 V typical)
R(ISET) = ISET-pin resistor value
The TPS65142 has built-in precise current sink regulators. The current matching error among 6 current sinks is
below 2.5%. This means the differential values between the maximum and minimum currents of the six current
sinks divided by the average current of the six is less than 2.5%.
Unused IFB Pins
If the application requires less than 6 WLED strings, one can easily disable unused IFBx pins by simply leaving
the unused IFB pin open or shorting it to ground. If the IFB pin is open, the boost output voltage ramps up to VO
overvoltage threshold during start up. The IC then detects the zero current string and removes it from the
feedback loop. If the IFB pin is shorted to ground, the IC detects the short immediately after WLED driver is
enable, and the boost output voltage does not go up to VO overvoltage threshold. Instead, it ramps to the
regulation voltage after the soft start.
PWM Dimming
The WLED brightness is controlled by the PWM signal on the DCTRL pin. The frequency and duty cycle of the
DCTRL signal is replicated on the IFB pin current. Keep the dimming frequency in the range of 100 Hz to 1 kHz
to avoid screen flickering and to maintain dimming linearity. Screen flickering may occur if the dimming frequency
is below the range. The minimum achievable duty cycle increases with the dimming frequency. For example,
while a 0.1% dimming duty cycle, giving a 1000:1 dimming range, is achievable at 100 Hz dimming frequency,
only 1% duty cycle, giving a 100:1 dimming range, is achievable with a 1 kHz dimming frequency, and 5%
dimming duty cycle is achievable with 5 kHz dimming frequency. The device can work at high dimming frequency
such as 20KHz, but then only 15% duty cycle can be achieved. The TPS65142 is designed to minimize the AC
ripple on the output capacitor during PWM dimming. Careful passive component selection is also critical to
minimize AC ripple on the output capacitor.
ENABLING THE WLED DRIVER
The WLED driver (including the WLED boost converter and the six current sinks) is enabled when all following
four conditions are satisfied:
1. the VBAT input voltage is higher than its under-voltage-lockout (UVLO) threshold;
2. the REF regulator output is higher than its power-good threshold;
3. the output voltage VO is within 2V of the input voltage VBAT
;
4. and the enable input from the EN pin is high.
Pulling the EN pin low shuts down the WLED driver.
SOFT-START of WLED BOOST REGULATOR
Once the above four conditions are satisfied, the WLED boost converter begins the internal soft-start. The
soft-start function gradually ramps up the reference voltage of the error amplifier to prevent the output-voltage
over shoot and inrush current from the VBAT input.
Protection of WLED Driver
The TPS65142 has multiple protection mechanisms to secure the safe operation of the WLED driver.
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Current Limit Protection
The WLED boost regulator switching MOSFET has a pulse-by-pulse over-current limit of 1.5 A (minimum value).
The PWM switch turns off when the inductor current reaches this current threshold and remains off until the
beginning of the next switching cycle. This protects the IC and external components under over-load conditions.
When there is sustained overcurrent condition for more than 16 ms (under 100% dimming duty cycle), the IC
turns off and requires VBAT POR or the EN pin toggling to restart.
Under severe over load and/or short-circuit conditions, the VO pin can be pulled below the input (VBAT pin
voltage). Under this condition, the current can flow directly from the input to the output through the inductor and
the Schottky diode. Turning off the PWM switch alone does not limit current anymore. In this case, the
TPS65142 relies on the fuse at the input to protect the whole system. When the TPS65142 detects the output
voltage to be 1 V (short-circuit detection threshold) below the input voltage, it shuts down the WLED driver. The
IC restarts after input power-on reset (VBAT POR) or EN pin logic toggling.
Open WLED String Protection
If one of the WLED strings is open, the boost output rises to its over-voltage threshold (39V typically). The IC
detects the open WLED string by sensing no current in the corresponding IFBx pin. As a result, the IC removes
the open IFBx pin from the voltage feedback loop. The output voltage drops and is regulated to the voltage for
the remaining connected WLED strings. The IFBx current of the connected WLED string remains in regulation
during the whole transition.
The IC shuts down if it detects that all of the WLED strings are open.
Overvoltage Protection
If the overvoltage threshold is reached, but the current sensed on the IFBx pin is below the regulation target, the
IC regulates the boost output at the overvoltage threshold. This operation could occur when the WLED is turned
on under cold temperature, and the forward voltages of the WLEDs exceed the over-voltage threshold.
Maintaining the WLED current allows the WLED to warm up and their forward voltages to drop below the
overvoltage threshold.
If any IFBx pin voltage exceeds IFB overvoltage threshold (17 V typical), the IC turns off the corresponding
current sink and removes this IFB pin from VO regulation loop. The remaining IFBx pins’ current regulation is not
affected. This condition often occurs when there are several shorted WLEDs in one string. WLED mismatch
typically does not create such large voltage difference among WLED strings.
POWER UP/DOWN SEQUENCE
The power up and power down sequences are shown in Figure 32.
The operation of the bias converters are gated by the UVLO of the VIN voltage. The start-up of the WLED boost
converter is gated by the UVLO of the VBAT input, the power good of the REF output, the (VBAT-2 V) and VO
comparator output, and the EN input. The REF output is powered by the output of the AVDD boost converter
through the SUP pin; and hence, the WLED boost converter will not start before the AVDD boost converter.
Power Up Sequence
The power up sequence of the bias portion is as following. When the VIN rises above the ULVO threshold, and
the internal device enable signal is asserted. The AVDD boost converter begins the soft-start, the REF regulator
starts to rise, the VCOM buffer is enabled, and both charge pumps begins to operate. When the REF output
reaches its regulation voltage, a VREF power good signal is asserted for the WLED section. The AVDD boost
converter continues the soft start until its output voltage reaches the AVDD power good threshold when an AVDD
power good signal is asserted. The AVDD power good signal enables the 20µA current to the VDPM pin to start
the gate voltage shaping delay timer. The delay is programmed by the external capacitor connected to the VDPM
pin and should be long enough to ensure that both charge pumps are ready before the delay ends. Once the
delay ends, the gate voltage shaping (VGHM) output is enabled to be controlled by the VFLK input.
The power up sequence of the WLED driver section is as following. When the four conditions for the Enabling the
WLED Driver section are satisfied, the WLED boost converter begins the soft start, together with the start of the
current sinks. When any of the four conditions is not satisfied, the WLED boost converter will stop switching.
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TPS65142
SLVSAX5 –JULY 2011
www.ti.com
Power Down Sequence and LCD Discharge Function
The power down sequence of the bias section is as following. When the input voltage VIN falls below a
predefined threshold set by V(DET_THRESHOLD), XAO is driven low and the VGHM output is driven to VGH. (Note
that when VIN falls below the UVLO threshold, all IC functions are disabled except XAO and VGHM outputs).
Since VGHM is connected to VGH, it tracks the output of the positive charge pump as it decays. This feature,
together with XAO, can be used to discharge the panel by turning on all the pixel TFTs and discharging them into
the gradually decaying VGHM voltage. VHGM is held low during power-up.
The REF regulator will be disabled when VIN falls below the UVLO threshold, hence, the WLED boost converter
as well.
VDET threshold
VIN UVLO
VIN
VIN UVLO
Internal Device
Enable
Power Good of VS
VS
Power Good of VREF
VREF
VCOM
VGH
VGL
VREF
VDPM
Unknown state
Unknown state
Connect to
VFLK
VGHM
VGH
VBAT UVLO
VBAT
VO
EN
Figure 32. Power Up/Down Sequence
24
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Product Folder Link(s) :TPS65142
TPS65142
www.ti.com
SLVSAX5 –JULY 2011
APPLICATION INFORMATION
This section describes the application information of various functions.
AVDD
9V/200mA
VIN
3.3V
L
1
D
1
10 mH
C
C
C
4
10 mF/25 V
C
2
3
1
10 mF/10V
10 mF/25 V
1 mF/25 V
R
2
113 kW
SUP
SW
VIN
R
10W
1
FB
R
3
C
5
Boost
18.2 kW
1 mF/10 V
PGND
(ePAD)
FREQ
D
3
BAT54S
R
6
VGL
-6V/20 mA
FBN
REF
SW
DRVP
R
66.5 kW
5
VGH
24V/20mA
C
9
0.1 mF/50 V
0.1 mF/50 V
C
10
R
4
Positive
Charge
Pump
Negative
Charge
Pump
C
6
124 kW
C
7
1 mF/10 V
1 mF/16 V
C
11
D
4
BAT54S
R
7
C
12
1 mF/50 V
0.1 mF/50 V
332 kW
DRVN
FBP
D
2
C
8
BAT54S
R
8
18.2 kW
0.1mF
VFLK
VDPM
OPI
VGH
VGHM
100nF
C
Gave Voltage
Shaping
13
AVDD
R
RE
R
9
10
VIN
OPO
Unity Gain VCOM Buffer
R
20 kW
11
R
12
27.4 kW
R
14
10 kW
VDET
R
Reset
13
XAO
IFB6
18.2 kW
AGND
PGND
(ePAD)
IFB5
IFB4
IFB3
DCTRL
EN
R
15
61.9 kW
ISET
IFB2
IFB1
VBAT
BL_SW
VO
R
16
C
14
BL_PWR
4.5V to 25V
51 W
0.1 mF
L
2
D
5
C
16
10 mH
C
15
4.7 mF
4.7 mF
Figure 33. Typical Application Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Sep-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS65142RTGR
ACTIVE
WQFN
RTG
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65142RTGR
WQFN
RTG
32
3000
330.0
16.4
3.3
6.3
1.0
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTG 32
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
TPS65142RTGR
3000
Pack Materials-Page 2
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相关型号：
TPS65145PWPRG4
4-CH LCD Bias w/ Fully Int. Pos. Charge Pump, 3.3V LDO Contr., 0.96A Min. Boost Ilim & Fault Detect 24-HTSSOP -40 to 85
TI
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