TPS65233-1 [TI]
具有 1MHz、I2C 接口电源管理 IC (PMIC) 的 LNB 稳压器;
| 型号： | TPS65233-1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1MHz、I2C 接口电源管理 IC (PMIC) 的 LNB 稳压器 集成电源管理电路 稳压器 |
| 文件： | 总30页 (文件大小：2841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
TPS65233-1 具有 I2C 接口的 LNB 稳压器
1 特性
3 说明
•
•
•
•
针对 LNB 和 I2C 的完整集成解决方案
TPS65233-1 针对模拟和数字卫星接收器而设计，是一
款具有 I2C 接口的单片稳压器，专门为碟形天线内的
LNB 下变频器或卫星多路切换开关盒提供 13V/18V 电
源和 22kHz 音调信号。该器件将极少的组件数量，低
功率耗散以及简单设计和 I2C 标准接口等特性完美结
合，提供了一套完整的解决方案。
1
与数字卫星设备控制 (DiSEqC) 1.x 兼容
支持 9V 和 12V 电源总线
高达 1000mA 的精确输出电流限值，可通过外部电
阻和 I2C 进行调节
•
•
•
•
•
•
•
•
具有低 Rdson 内部电源开关的升压转换器
针对非 I2C 应用的专用使能引脚
具有推挽输出级的低噪声、低压降输出
内置精确 22kHz 音调发生器或外部引脚
可调软启动和 13V/18V 电压转换时间
符合主要卫星接收器系统规范
TPS65233-1 具备 高功率效率。此升压转换器集成了
一个以 1MHz 开关频率运行的 120mΩ 功率金属氧化
物半导体场效应晶体管 (MOSFET)。线性稳压器中的
压降电压为 0.8V，能够最大限度地降低功率损耗。
TPS65233-1 提供了多种方法来生成 22kHz 信号。具
有推挽输出级的集成线性稳压器在输出上生成洁净的
22kHz 音调信号，即使在零负载时也是如此。可由外
部电阻器以 ±10% 的精度来设定线性稳压器的电流限
值。 由 I2C 读取的全范围诊断可用于系统监视。
LNB 短路动态保护
针对输出电压电平、输入电源欠压闭锁 (UVLO) 和
DiSEqC 音调输出的诊断
•
•
电缆断开诊断
采用 16 引脚 WQFN 3.00mm × 3.00mm (RTE) 封
装
该器件采用 16 引脚 WQFN 3.00mm × 3.00mm (RTE)
封装。
2 应用
器件信息(1)
•
•
•
机顶盒卫星接收器
器件型号
TPS65233-1
封装
WQFN (16)
封装尺寸（标称值）
电视卫星接收器
3.00mm x 3.00mm
PC 卡卫星接收器
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
12
11
10
9
100 kꢀ
VOUT
VLNB
FAULT
13
8
7
100 nF
EN/ADDR
ISEL
14 VCP
1 µF
TPS65233-1
130 kꢀ
6
15
16
BOOST
PGND
2 × 22 µF
(35 V)
TCAP
5
22 nF
1
2
3
4
4.7 µH
VIN
1 µF
22 µF
(25 V)
1 µF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD66
TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
7.5 Programming........................................................... 14
7.6 Register Map........................................................... 15
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
Power Supply Recommendations...................... 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 I2C Interface Timing Requirements........................... 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 8
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 社区资源................................................................ 23
11.2 商标....................................................................... 23
11.3 静电放电警告......................................................... 23
11.4 术语表 ................................................................... 23
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 9 月
*
最初发布版本。
2
Copyright © 2015, Texas Instruments Incorporated
TPS65233-1
www.ti.com.cn
ZHCSFC6 –SEPTEMBER 2015
5 Pin Configuration and Functions
RTE Package
12-Pin WQFN
Top View
12
11
10
9
VLNB
13
8
FAULT
EN/
ADDR
VCP 14
7
6
TPS65233-1
ISEL
15
16
BOOST
PGND
TCAP
5
1
2
3
4
Exposed pad must be soldered to PCB for optimal thermal performance.
Pin Functions
PIN
DESCRIPTION
NAME
AGND
NUMBER
4
Analog ground. Connect all ground pins and power pad together.
BOOST
15
Output of the boost regulator and input voltage of the internal linear regulator
Enable pin to enable the whole chip; pull to ground to disable output, output will be pulled to ground. For I2C
EN/ADDR
7
interface, pulling this pin high or low gives different I2C addresses.
External modulation logic input pin which activates the 22-kHz tone output, feeding signal can be 22-kHz tone
or logic high or low.
EXTM
12
FAULT
ISEL
LX
8
6
This pin is an open drain output pin, it goes low if any fault flag is set.
Connect a resistor to this pin to set the LNB output current limit.
Switching node of the boost converter
1
PGND
16
Power ground for boost converter
I2C compatible clock input; if I2C function is not used, connect this pin to low set output voltage 13 V/18 V,
connect to high set output voltage 13.4 V/18.6 V
SCL/VADJ
9
SDA
10
5
I2C compatible bi-directional data
TCAP
Connect a capacitor to this pin to set the rise time and fall time of the LNB output between 13 V and 18 V.
Internal 6.5-V power supply bias. Connect a 1-µF ceramic capacitor from this pin to ground. When VIN is 5 V,
VCC
3
connect VCC to VIN
.
VCP
14
11
2
Gate drive supply voltage, output of charge pump, connect a capacitor between this pin to pin BOOST.
Logic control pin for 13-V or 18-V voltage selection at LNB output
Input of internal linear regulator
VCTRL
VIN
VLNB
13
Output of the LNB power supply connected to satellite receiver or switch
Must be soldered to PCB for optimal thermal performance. Have thermal vias on the PCB to enhance power
dissipation.
Thermal pad
—
Copyright © 2015, Texas Instruments Incorporated
3
TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted)(1)
MIN
MAX
UNIT
VIN, LX, BOOST, VLNB
–1
30
VCP
BOOST + 7
LX
–1
30
7
Voltage
V
VCC, EN, FAULT, SCL, SDA, VCTRL, ISEL, EXTM
–0.3
–0.3
–0.3
–40
–55
TCAP
3.6
0.3
125
150
PGND, AGND
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
2000
6000
500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, other pins(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, pin 13 (VLNB)(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
20
UNIT
V
VIN
TA
Input operating voltage
Junction temperature
–40
85
°C
6.4 Thermal Information
TPS65233-1
THERMAL METRIC(1)
RTE (WQFN)
UNIT
16 PINS
43.4
45.6
15
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
15
RθJC(bot)
3.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
TPS65233-1
www.ti.com.cn
ZHCSFC6 –SEPTEMBER 2015
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
VIN
4.5
12
20
V
IDDSDN
Shutdown supply current
EN = 0
160
µA
EN = 1, IOUT = 0 A, VBOOST = 14
V, ILNB = 0 mA
IDDQ
LDO input quiescent current
VIN under voltage lockout
10.5
mA
Rising VIN
Falling VIN
Hysteresis
4.05
3.6
4.25
3.8
4.45
4.1
V
UVLO
450
mV
OUTPUT VOLTAGE
VCTRL = 1, SCL = 0,
IOUT = 500 mA
18
18.6
13
VCTRL = 1, SCL = 1,
IOUT = 500 mA
18.2
13.1
19
VOUT
Regulated output voltage (non-I2C mode)
V
VCTRL = 0, SCL = 0,
IOUT = 500 mA
VCTRL = 0, SCL = 1,
IOUT = 500 mA
13.4
0.2
13.7
VIN = 7.5 V to 16 V,
IOUT = 500 mA
VLINEREG
Line regulation-DC
%/V
VLOADREG
IOCP
Tr, Tf
Load regulation-DC
IOUT = (10-90%) × IOUTMAX
RSEL = 200 kΩ, TJ = 25°C
CTCAP = 5.6 nF
0.7
650
0.33
1040
3.2
%/A
mA
ms
kHz
A
Output short circuit current limit
13-V/18-V transition rising/falling time
Boost switching frequency
Switching current limit
580
720
fSW
Ilimitsw
Rdson_LS
Vdrop
VIN = 12 V, VOUT = 18.6 V
VIN = 12 V
On resistance of low side FET on CH
Linear regulator voltage drop-out
Reverse bias current
120
0.8
mΩ
V
IOUT = 500 mA
Irev
EN = 1, VLNB = 21 V
EN = 0, VLNB = 21 V
50
mA
mA
Irev_dis
Disabled reverse bias current
3
LOGIC SIGNALS
VEN
Enable threshold level
1.15
80
V
VENH
Enable threshold level hysteresis
mV
High level input voltage
Low level input voltage
2
VLOGICh
VLOGICl
,
VCTRL, EXTM Logic threshold level
V
0.8
0.4
VOL FAULT
fI2C
FAULT output low voltage
Maximum I2C clock frequency
FAULT open drain, IOL= 1 mA
V
400
kHz
TONE
ftone
Tone frequency
Tone amplitude
Tone duty cycle
20
550
22
680
24
750
kHz
mV
IOUT = 0 mA to 500 mA,
COUT = 100 nF
Atone
Dtone
45%
50%
55%
PROTECTION
TON
Over current protection on time
Over current protection off time
4
ms
ms
TOFF
128
THERMAL SHUTDOWN
TTRIP
Thermal shut down trip point
Thermal shut down hysteresis
Rising temperature
160
20
°C
°C
THYST
Copyright © 2015, Texas Instruments Incorporated
5
TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C READ BACK FAULT STATUS
Feedback voltage low side rising
Feedback voltage low side falling
Feedback voltage high side rising
95.3%
94.7%
VPGOOD
PGOOD trip levels
105.3%
Feedback voltage high side
falling
104.7%
125
Twarn
Temperature warning threshold
°C
I2C INTERFACE
VIH
VIL
II
SDA,SCL input high voltage
2
–10
400
V
V
SDA,SCL input low voltage
Input current
0.8
10
SDA, SCL, VI = 0.4 V to 4.5 V
SDA open drain, IOL = 2 mA
µA
V
VOL
f(SCL)
SDA output low voltage
Maximum SCL clock frequency
0.4
kHz
Capacitance of one bus line (SCL and
SDA)
CB
400
pF
6.6 I2C Interface Timing Requirements
MIN
MAX
UNIT
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
1.3
0.6
tHD, STA
tSU, STO
tLOW
Hold time (Repeated) START condition
Setup time for STOP condition
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data setup time
0.6
1.3
tHIGH
tSU, STA
tSU, DAT
tHD, DAT
tRCL
0.6
0.6
0.1
Data hold time
0
0.9
300
300
300
300
300
Rise time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
tRCL1
tf
Rise time of SCL signal after a repeated START condition and after an acknowledge BIT
Fall time of SCL signal
tr
Rise time of SDA signal
tFDA
Fall time of SDA signal
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT VOLTAGE
Tr, Tf
TONE
Trtone
Tftone
13-V/18-V Transition rising falling time
Ccap = 5.6 nF
0.33
ms
Tone rise time
Tone fall time
IOUT = 0 to 500 mA, COUT = 100 nF
IOUT = 0 to 500 mA, COUT = 100 nF
10
10
µs
µs
6
Copyright © 2015, Texas Instruments Incorporated
TPS65233-1
www.ti.com.cn
ZHCSFC6 –SEPTEMBER 2015
SDA
tSU, STA
tHD, STA
tBUF
tSU, STO
tSU, DAT
tHD, DAT
tLOW
SCL
tHD, STA
tHIGH
tSP
Start
Condition
Repeated Start
Condition
Stop Start
Condition Condition
tr
tf
Figure 1. I2C Interface Timing Diagram
Copyright © 2015, Texas Instruments Incorporated
7
TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
6.8 Typical Characteristics
TA = 25°C, VIN = 12 V, fSW = 1 MHz, L = 4.7 µH, CBoost = 2 × 22 µF/35 V (unless otherwise noted)
0.95
0.9
18.68
18.66
18.64
18.62
18.6
VLNB = 13.4 V
VLNB = 18.6 V
0.85
0.8
0.75
0.7
0.01
0.02 0.03 0.050.07 0.1
IOUT (A)
0.2 0.3
0.5 0.7
1
0.005 0.01
0.020.03 0.05
0.1
0.2 0.3 0.5 0.70.95
IOUT (A)
D001
D002
Figure 2. Power Efficiency
Figure 3. Load Regulation, VLNB = 18.6 V
13.5
13.48
13.46
13.44
13.42
13.4
11
10.5
10
9.5
9
0.005 0.01
0.020.03 0.05
0.1
0.2 0.3 0.5 0.70.95
-55
-25
5
35
65
95
125 140
IOUT (A)
Junction Temperature (°C)
D003
D004
Figure 4. Load Regulation, VLNB = 13.4 V
Figure 5. LDO Input Quiescent Current and Junction
Temperature, VBOOST = 14 V, ILNB = 0 mA
250
200
150
100
50
700
680
660
640
620
600
580
0
-55
-25
5
35
65
95
125 140
-55
-25
5
35
65
95
125 140
Junction Temperature (°C)
Junction Temperature (°C)
D005
D006
Figure 6. Shutdown Current and Junction Temperature
Figure 7. LNB Current Limit and Junction Temperature
(ILIM = 650 mA)
8
Copyright © 2015, Texas Instruments Incorporated
TPS65233-1
www.ti.com.cn
ZHCSFC6 –SEPTEMBER 2015
7 Detailed Description
7.1 Overview
The TPS65233-1 is a power management IC that integrates a boost converter, a LDO, and a 22-kHz tone
generator that serves as a LNB power supply. This solution compiles the DiSEqC 1.x standard with or without
I2C interface. Output current can be precisely programmed by an external resistor. There are five ways to
generate the 22-kHz tone signal with or without I2C. Integrated boost features low Rdson MOSFET and internal
compensation. A fixed 1-MHz switching frequency is designed to reduce components size.
7.2 Functional Block Diagram
VIN
VIN
LX
VCC
EN
REF_Boost
Internal
PWM Controller
Regulator
PGND
REF_Boost
REF_LDO
TCAP
BOOST
REF
VCTRL
Charge
Pump
VCP
REF_LDO
I2C EN
TGATE
SDA
SCL
I2C Interface
EN/ADDR
TGATE
22-kHz
Tone
Generator
VLNB
ISEL
OCP
OTP
UVL
Fault Diagnose
FAULT
EXTM
AGND
7.3 Feature Description
7.3.1 Boost Converter
The TPS65233-1 consists of an internal compensated boost converter and linear regulator. The boost converter
tracks the output LNB voltage to within 800 mV even at loading 950 mA, to minimize power dissipation. Under
conditions where the input voltage, VBOOST, is greater than the output voltage, VLNB, the linear regulator must
drop the differential voltage. When operating in these conditions, taken care to ensure that the safe operating
temperature range of the TPS65233-1 is not exceeded. The boost converter operates at 1 MHz typical. The
TPS65233-1 has internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the
LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is
limited. The current limit is set by the external resistor. And the IC will be shut down if the overcurrent condition
lasts for more than 4 ms, the converter enters hiccup mode and will retry startup in 128 ms. At extremely light
loads, the boost converter operates in a pulse-skipping mode.
Copyright © 2015, Texas Instruments Incorporated
9
TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
Feature Description (continued)
If two or more set top box LNB outputs are connected together, one output voltage could be set higher than
others. The output with lower set voltage would be effectively turned off. Once the voltage drops to the set level,
the LNB output with lower set output voltage will return to normal conditions.
7.3.2 Linear Regulator and Current Limit
The linear regulator is used to generate the 22-kHz tone signal by changing the reference voltage. The linear
regulator features low drop out voltage to minimize power loss while keeping enough head room for the 0.68-V,
22-kHz tone. It also implements a tight current limit for over current protection. The current limit is set by an
external resistor connected to the ISEL pin. The curve below shows the relationship between the current limit
threshold and the resistor value.
500
450
400
350
300
250
y = 124.11x-1.178
200
150
100
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
ISEL (A)
Figure 8. Linear Regulator Current Limit vs Resistor
RSEL(kW) = 124.11´ISEL-1.178(A)
(1)
A 280-kΩ resistor sets the current to 0.5 A. The current limit can also be set by I2C through a register.
7.3.3 Charge Pump
The charge pump circuitry generates a voltage to drive the NMOS of the linear regulator. One end the charge
pump capacitor is connected to the output of the boost converter. The voltage on the charge pump capacitor is
about 6.25 V.
7.3.4 Slew Rate Control
When LNB output voltage transits from 13 V to 18 V or vice versa, the capacitor at pin TCAP controls the
transition time. This transition is to make sure the boost converter can follow the voltage change. Usually boost
converter has low bandwidth and can’t response fast. The voltage at TCAP acts as the reference voltage of the
linear regulator. The boost converter’s reference is also based on TCAP with additional fixed voltage to generate
0.8 V above the output.
The charging and discharging current is 10 µA, thus the transition time can be calculated as:
Css(nF)
Tcad(ms) = 0.5´
Iss(mA)
(2)
A 22-nF capacitor generates a 1.1-ms transition time.
In light load conditions, when LNB output voltage is set from 18 to 13 V, the voltage might drops very slow, which
might cause wrong logic detection at LNB side. The TPS65233-1 has an integrated pull down circuit to pull down
the output during the transition. This ensures the voltage change can follow the voltage at TCAP. Meanwhile,
when the 22-kHz tone signal is superimposing on the LNB output voltage, the pull down current can also provide
a square wave instead of distorted waveforms, which could cause another detection problem.
10
Copyright © 2015, Texas Instruments Incorporated
TPS65233-1
www.ti.com.cn
ZHCSFC6 –SEPTEMBER 2015
Feature Description (continued)
7.3.5 Short Circuit Protection, Hiccup, and Overtemperature Protection
The LNB output limit can be set by an external resistor. When short circuit conditions occur, the output current is
clamped at the current limit for 4 ms. If the condition remains, the converter will shut down for 128 ms and then
try restart. This hiccup behavior prevents the IC from overheating.
The low side MOSFET of the boost converter has a current limit threshold at 3.2 A, which serves as secondary
protection. If the boost converter’s peak current limit is triggered, the peak current will clamp at 3.2 A. If loading
current continues to increase, output voltage starts to drop and output power drops.
Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die
temperature exceeds 160°C, the output shuts down. When the temperature drops below its lower threshold,
typically 140°C, the output is enabled.
When the chip is in over current protection or thermal shutdown, the I2C interface and some logic are still active.
The Fault pin is pulled down to signal the processor. The Fault pin signal will remain low unless the following
actions are taken:
1. If I2C interface is not used to control, Enable pin must be recycled in order to pull Fault pin back to high.
2. If I2C interface is used, the I2C master needs to read the OCP or OTP bit in the register, then the Fault pin
returns to high.
7.4 Device Functional Modes
7.4.1 Tone Generation
A 22-kHz tone signal is superimposed at the LNB output voltage as a carrier for DiSEqC command. This tone
signal can be generated by feeding an external 22-kHz clock at the EXTM pin. It can also be generated with its
internal tone generator gated by control logic. The output stage of the regulator facilitates a push-pull circuit, so
even at zero loading the 22-kHz tone at the output is still clear of distortion.
There are five ways to generate the 22-kHz tone signal at the output.
In non-I2C mode, only option 1 and option 2 are supported in TPS65233-1. EXTM can be tone envelope or 22
kHz burst pulse as shown in Figure 9. Option 3 and option 4 are designed for I2C interface communication mode.
In I2C communication mode, TGATE bit must be written through I2C bus. If there is no bandwidth of I2C bus to
write TGATE bit, there is a supplemental option 5 to generate 22-kHz tone, as shown in Figure 10. In option 5,
bit TMODE and TGATE must be set as 1.
Copyright © 2015, Texas Instruments Incorporated
11
TPS65233-1
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Device Functional Modes (continued)
EXTM
VLNB
TONE
Option 1, Non-I2C Mode, bit I2C_CON = 0
EXTM
VLNB
TONE
Option 2, Non-I2C Mode, bit I2C_CON = 0
EXTM
TMODE
TGATE
VLNB
TONE
Option 3, I2C Mode, bit I2C_CON = 1 and TMODE = 0
EXTM
TMODE
TGATE
VLNB
TONE
Option 4, I2C Mode, EXTM = 0, bit I2C_CON = 1, and TMODE = 1
Figure 9. Four Ways to Generate 22-kHz Tone
12
Copyright © 2015, Texas Instruments Incorporated
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ZHCSFC6 –SEPTEMBER 2015
Device Functional Modes (continued)
Stop at high
EXTM
TONE
VLNB
Option 5: I2C Mode, gated by EXTM, TMODE, and TGATE = 1
Figure 10. Supplemental Option for 22-kHz Tone in I2C Mode
7.4.2 Serial Interface
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and transmits data on the bus under control of the master device.
The TPS65233-1 device works as a slave and supports the following data transfer modes, as defined in the I2C-
Bus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the
power supply solution, enabling most functions to be programmed to new values depending on the instantaneous
application requirements. Register contents remain intact as long as supply voltage remains above 4.5 V
(typical).
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The TPS65233-1 device supports 7-bit addressing; 10-bit addressing and general
call address are not supported.
The TPS65233-1 device has a 7-bit address with the 2 LSB bits set by EN pin. Connecting EN to ground set the
address 0x60H, connecting to high set the address 0x61H.
Table 1. I2C Address Selection
ADDRESS FORMAT
EN/ADDR PIN
I2C ADDRESS
(A6...A0)
110 0000
110 0001
Connect to ground
Connect to high
0x60H
0x61H
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TPS65233-1
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7.5 Programming
7.5.1 I2C Update Sequence
The TPS65233-1 requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, the TPS65233-1 device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. The TPS65233-1 performs an update on the falling edge of the
LSB byte.
When the TPS65233-1 is disabled (EN pin tied to ground) the device can still be updated via the I2C interface.
7-Bit Slave Address
S
0
A
A
A
P
Register Address
Data Byte
A6….A0
Figure 11. I2C Write Data Format
7-Bit Slave Address
Sr
S
0
A
A
1
A
Register1 Address
7-Bit Slave Address
A6….A0
N
P
Data Byte
Figure 12. I2C Read Data Format
A: Acknowledge
N: Not Acknowledge
S: Start
System Host
P: Stop
Chip
Sr:Repeated Start
Figure 13. Legend
14
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ZHCSFC6 –SEPTEMBER 2015
7.6 Register Map
The registers are listed in Table 2 and described in the following sections.
Table 2. Register Map
REGISTER / ADDRESS
7
6
5
4
3
2
1
0
Control Register 1
Address: 0x00H
I2C_CON
Reserved
TGATE
TMODE
EN
VSEL2
VSEL1
VSEL0
Control Register 2
Address: 0x01H
TONE_
POS1
TONE_
POS0
—
—
—
—
CL1
CL0
CL_EXT
Status Register 1
Address: 0x02H
CABLE_
GOOD
VOUT_
GOOD
T125
LDO_ON
Reserved
TSD
OCP
7.6.1 Control Register 1 - Address: 0x00H
Table 3. Control Register 1 - Address: 0x00H
BIT
FIELD
TYPE
RESET
DESCRIPTION
1: I2C control enabled;
7
I2C_CON
Reserved
R/W
0
0
0: I2C control disabled
6
R/W
Reserved
Tone Gate. Allows either the internal or external 22-kHz
tone signals to be gated.
1: Tone Gate on use;
5
TGATE
R/W
0
0: Tone gate off
Tone mode. Select between the use of an external 22-kHz
or internal 22-kHz signal.
1: internal;
0: external
4
3
TMODE
EN
R/W
R/W
0
1
LNB output voltage Enable
1: output enabled;
0: output disabled
2
1
0
VSEL2
VSEL1
VSEL0
R/W
R/W
R/W
0
0
0
See Table 4 for output voltage selection
Table 4. Voltage Selection Bits
VSEL2
VSEL1
VSEL0
LNB(V)
13
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
13.4
13.8
14.2
18
18.6
19.2
19.8
7.6.2 Control Register 2 - Address: 0x01H
Table 5. Control Register 2 - Address: 0x01H
BIT
7
FIELD
—
TYPE
R/W
R/W
R/W
RESET
—
DESCRIPTION
—
—
—
6
—
—
5
—
—
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Table 5. Control Register 2 - Address: 0x01H (continued)
BIT
FIELD
TYPE
RESET
DESCRIPTION
4
TONE_POS1
R/W
0
00: tone above Vout;
01: tone in the middle of Vout;
10: tone below Vout
3
TONE_POS0
R/W
1
2
1
CL1
CL0
R/W
R/W
0
0
Current limit set bits
1: current limit set by external resistor;
0: current limit set by register
0
CL_EXT
R/W
1
Some tone detection circuits in LNB are sensitive to the position of the tone on the output voltage. The
TPS65233-1 provides options to select the position by setting the TONE_POS1 and TONE_POS0 bits, as
illustrated below.
Option 1, TONE_POS1=0, TONE_POS0=0, Tone above VLNB
Option 2, TONE_POS1=0, TONE_POS0=1, Tone in the middle of VLNB
Option 2, TONE_POS1=1, TONE_POS0=0, Tone below VLNB
Figure 14. Tone Position Programmed by TONE_POS1, TONE_POS0 Bits
In addition to programming the LDO’s current continuously via an external resistor, internal registers also provide
options to program the current limit. There are four options that can be selected.
Table 6. Current Limit Selection Bits
CL1
0
CL0
0
CURRENT LIMIT (mA)
400
600
0
1
1
0
750
1
1
1000
7.6.3 Status Register 1 - Address: 0x02H
The TPS65233-1 has a full range of diagnostic flags for operation and debug. If any of the flags are triggered,
the FAULT pin is pulled low sending an interrupt signal to processor. The processor then can read the status
register to check the error conditions. The status bits are described in the following table. Among these bits, TSD
and OCP are different from the others. Once TSD and OCP are set to 1, the FAULT pin logic is latched low and
the processor must reset the bits in order to release the fault conditions. Other bits change as conditions change
without latch.
16
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ZHCSFC6 –SEPTEMBER 2015
Table 7. Status Register 1 - Address: 0x02H
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
—
—
—
—
1: if die temperature T > 125°C;
0: if die temperature T < 125°C
6
T125
R
0
1: internal LDO is turned on and boost converter is on;
0: Internal LDO is turned off but boost converter is on
5
4
LDO_ON
Reserved
R
R
0
0
Reserved
1: thermal shutdown occurs;
3
TSD
R
0
0: thermal shutdown does not occur. FAULT pin pull low and
latch, I2C master need to read and release
Overcurrent protection. If over current conditions last for
more than 48 ms.
2
OCP
R
0
1: Overcurrent protection triggered.
0: Overcurrent protection conditions released. FAULT pin
pull low and latch, I2C master need to read and release
Cable connection good.
1
0
CABLE_GOOD
VOUT_GOOD
R
R
0
0
1: Output current above 50 mA;
0: Output current less than 50 mA
LNB output voltage in range.
1: In range;
0: Out of range
Copyright © 2015, Texas Instruments Incorporated
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TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPS65233-1 is a monolithic voltage regulator, specifically to provide the 13-V/18-V power supply and the 22-kHz
tone signaling to the LNB down-converter, with I2C interface. I2C GUI software is shared with TPS65233 which is
available on ti.com.
8.2 Typical Application
12
11
10
9
100 kꢀ
VOUT
VLNB
FAULT
13
8
7
100 nF
EN/ADDR
ISEL
14 VCP
1 µF
TPS65233-1
130 kꢀ
6
15
16
BOOST
PGND
2 × 22 µF
(35 V)
TCAP
5
22 nF
1
2
3
4
4.7 µH
VIN
1 µF
22 µF
(25 V)
1 µF
Figure 15. Application Schematic
8.2.1 Detailed Design Procedure
8.2.1.1 Capacitor Selection
In TPS65233-1, a 1-MHz non-synchronous boost converter is integrated and the boost converter features the
internal compensation network. 4.7 µH and 10 µH boost inductor are recommended. TPS65233-1 works fine with
both ceramic capacitor and electrolytic capacitor. The ceramic capacitors rated at least X7R, 1206 size are
preferred for the lower LNB output ripple. Table 8 shows the recommended ceramic capacitors list for both 4.7
µH and 10 µH boost inductors. Minimum output capacitor at the output of the boost converter is 2 × 10-µF/25-V
ceramic capacitor when 4.7-µH inductor is selected.
Boost converter is stable with both ceramic capacitor and electrolytic capacitor. If lower cost is demanded, a 100-
µF electrolytic and a 1-µF/35-V ceramic capacitor work well, this solution provides lower system cost.
18
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TPS65233-1
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ZHCSFC6 –SEPTEMBER 2015
Table 8. Boost Inductor and Capacitor Selections
BOOST INDUCTOR
BOOST OUTPUT CAPACITOR (CERAMIC)
2 × 22 µF, 25 V, 1206
10 µH
2 × 10 µF, 35 V, 1206
1 × 22 µF, 35 V, 1206
2 × 22 µF, 35 V, 1206
4.7 µH
2 × 10 µF, 25 V, 1206
2 × 22 µF, 25 V, 1206
1 × 22 µF, 35 V, 1206
2 × 10 µF, 35 V, 1206
2 × 22 µF, 35 V, 1206
8.2.2 Application Curves
Figure 16. Soft Start, VLNB = 13.4 V, Delay from EN High
to LNB Output High
Figure 17. Power Off, VLNB = 13.4 V, Delay from EN Low
to LNB Output Low
Figure 18. Soft Start, VLNB = 18.6 V, Delay from EN High
to LNB Output High
Figure 19. Power Off, VLNB = 18.6 V, Delay from EN Low
to LNB Output Low
Copyright © 2015, Texas Instruments Incorporated
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TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
Figure 20. VLNB = 13.4 V, No Load, 22-kHz Tone
Figure 21. VLNB = 13.4 V, 950 mA, 22-kHz Tone
Figure 22. VLNB = 18.6 V, No Load, 22-kHz Tone
Figure 23. VLNB = 18.6 V, 950 mA, 22-kHz Tone
Figure 24. No Load, 22-kHz Tone Delay from EXTM Turns
High to Output Tone, On
Figure 25. No Load, 22-kHz Tone Delay from EXTM Turns
Low to Output Tone, Off
20
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TPS65233-1
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ZHCSFC6 –SEPTEMBER 2015
Figure 26. No Load, 22-kHz Tone Delay from EXTM Turns
Figure 27. No Load, 22-kHz Tone Delay from EXTM Turns
Low to Output Tone, Off
High to Output Tone, On
Figure 28. No Load, 22-kHz Tone Delay from I2C SDA to
Output Tone, On
Figure 29. No Load, 22-kHz Tone Delay from I2C Gated,
EXTM Provides 22 kHz to Output Tone, On
Figure 30. No Load, 22-kHz Tone Delay from I2C SDA to
Output Tone, Off
Figure 31. No Load, 22-kHz Tone Delay from I2C Gated,
EXTM Provides 22 kHz to Output Tone, Off
Copyright © 2015, Texas Instruments Incorporated
21
TPS65233-1
ZHCSFC6 –SEPTEMBER 2015
www.ti.com.cn
9 Power Supply Recommendations
The devices are designed to operate from an input supply ranging from 4.5 V to 20 V. The input supply should
be well regulated. If the input supply is located more than a few inches from the converter an additional bulk
capacitance typically 100 μF may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
The TPS65233-1 is designed to layout in a 2-layer PCB. Figure 32 shows the recommended layout practice. It is
critical to make sure the GND of the input capacitor, output capacitor, and boost converter are connected at one
point on the same layer as shown below. PGND and AGND are in different regions and are connected to the
thermal pad. Other components are connected to AGND.
10.2 Layout Example
12
9
11
10
VOUT
VLNB
VCP
13
14
15
16
FAULT
8
EN/
ADDR
7
6
130 kꢀ
ISEL
BOOST
PGND
22 nF
TCAP
5
2x22 µF
22 µF
1
2
3
4
VIN
1 µF
1 µF
4.7 µH
Figure 32. 2-Layer PCB Layout
22
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TPS65233-1
www.ti.com.cn
ZHCSFC6 –SEPTEMBER 2015
11 器件和文档支持
11.1 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范和
标准且不一定反映 TI 的观点；请见 TI 的使用条款。
TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com
中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏
版权 © 2015, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65233-1RTER
TPS65233-1RTET
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
652331
652331
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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