TPS65263-Q1 [TI]
支持 I2C 控制的动态电压调节的 4.0V-18V 输入电压、3A/2A/2A 三路同步降压转换器;型号: | TPS65263-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 支持 I2C 控制的动态电压调节的 4.0V-18V 输入电压、3A/2A/2A 三路同步降压转换器 转换器 |
文件: | 总48页 (文件大小:2680K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS65263-Q1
ZHCSDM4D –DECEMBER 2014 –REVISED MAY 2023
TPS65263-Q1 具有I2C 控制型动态电压调节功能的汽车类4.0V 至18V 输入电
压、3A/2A/2A 输出电流三路同步降压转换器
1 特性
3 说明
• 符合汽车应用要求
• 通过AEC-Q100 资质认证,结果如下所示:
TPS65263-Q1 包含三个同步降压转换器,并且具有
4.0V 至 18V 的宽输入电压范围。这款转换器具有恒定
频率峰值电流模式,专用于简化应用,同时方便设计人
员根据目标应用来优化系统。可通过外部电阻在
200kHz 至 2.3MHz 范围内调节转换器的开关频率。
buck1 和 buck 2,buck3 之间的 180° 异相运行
(buck2 和 buck3 同相运行)可最大限度降低对输入
滤波器的要求。
– 器件温度等级1:–40°C 至125°C 的工作结温
范围
– 器件HBM ESD 分类等级H2
– 器件CDM ESD 分类等级C4B
• 工作输入电压范围4V 至18V,最大连续输出电流
3A/2A/2A
• Buck2 的I2C 控制型7 位VID 可编程输出电压范围
为0.68V 至1.95V,阶跃为10mV
• Buck2 的I2C 控制型VID 电压转换压摆率
• I2C 回读电源正常状态、过流警告和裸片温度警告
• 具有支持标准模式(100kHz) 和快速模式(400kHz)
的I2C 兼容接口
• 反馈基准电压为0.6V ±1%
• 可调节时钟频率范围为
200kHz 至2.3MHz
• 外部时钟同步
每个降压转换器的初始启动电压都可通过外部反馈电阻
设定。可使用 I2C 控制 7 位 VID 对 buck2 的输出电压
进行动态调整,范围为 0.68V 至 1.95V,步长为
10mV。可通过I2C 总线3 位控制对VID 电压转换率进
行编程,以优化VID 电压转换期间的过冲/下冲。
TPS65263-Q1 中的每个降压转换器都可通过 I2C 加以
控制,从而执行以下操作:启用/禁用输出电压、设置
脉冲跳跃模式 (PSM) 或轻负载条件下的强制持续电流
模式 (FCC) 以及读取电源正常状态、过流警告和温度
警告。
• 针对每次降压的专用使能引脚和软启动引脚
• 输出电压电源正常状态指示器
• 热过载保护
TPS65263-Q1 具有过压保护、过流保护、短路保护和
过热保护功能。
2 应用
封装信息(1)
• 汽车
封装尺寸(标称值)
器件型号
封装
• 汽车音频和视频
• 家庭网关和接入点网络
• 监控
TPS65263-Q1
RHB(VQFN,32) 5.00mm × 5.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
100%
90%
80%
70%
60%
50%
40%
30%
20%
Vout1
Vin
PVINx
VIN
LX1
TPS65263Q1
FB1
LX2
PGOOD
ENx
SSx
Vout2
Vout3
Vout2
VOUT2
ROSC
FB2
LX3
DVCC
SDA
SCL
SDA
SCL
VIN 12 V VOUT 3.3 V
10%
VIN 5 V VOUT 3.3 V
AGND
FB3
PGND
0
0.01 0.02
0.05
0.1 0.2 0.3 0.5 0.7
Output Load (A)
1
2
3
D002
应用原理图
效率与输出负载之间的关系
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSCS9
TPS65263-Q1
ZHCSDM4D –DECEMBER 2014 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................23
7.5 Register Maps...........................................................25
8 Application and Implementation..................................28
8.1 Application Information............................................. 28
8.2 Typical Application.................................................... 28
8.3 Power Supply Recommendations.............................36
8.4 Layout....................................................................... 36
9 Device and Documentation Support............................39
9.1 接收文档更新通知..................................................... 39
9.2 支持资源....................................................................39
9.3 Trademarks...............................................................39
9.4 静电放电警告............................................................ 39
9.5 术语表....................................................................... 39
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
Information.................................................................... 39
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision C (November 2015) to Revision D (May 2023)
Page
• 在数据表标题中添加了“汽车”一词..................................................................................................................1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 通篇去除了图像的颜色........................................................................................................................................1
• Change description of V7V pin in 表5-1 ............................................................................................................3
• Update the ESD table to be in accordance with automotive specification..........................................................5
• Changed the recommended value of capacitor from V7V pin to power ground in V7V Low-Dropout Regulator
and Bootstrap................................................................................................................................................... 19
• Changed all instances of legacy terminology to controller and target where I2C is mentioned........................ 23
• Changed recommended value of C9 in 图8-1................................................................................................. 28
Changes from Revision B (January 2015) to Revision C (November 2015)
Page
• Added more pin information for SDA and SCL ..................................................................................................3
• Added more information about SDA and SCL pins ......................................................................................... 12
• Added Community Resources .........................................................................................................................39
Changes from Revision A (January 2015) to Revision B (January 2015)
Page
• 已将器件状态更新为量产数据.............................................................................................................................1
Changes from Revision * (December 2014) to Revision A (January 2015)
Page
• 将特性中的反馈基准电压从 0.6V ±2% 更改为0.6V ±1%.................................................................................. 1
• Updated values for feedback voltage, PGOOD pin leakage, V7V LDO output voltage, buck1 low-side sink
current limit, and buck2/buck3 low-side sink current limit in Electrical Characteristics ......................................6
• Updated current value in 节7.3.8, 方程式6, and 图7-10 ............................................................................... 20
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSCS9
2
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5 Pin Configuration and Functions
24
23 22
21 20 19
18 17
16
15
BST3
25
26
BST1
LX1
LX3
14
13
12
11
PGND3
PVIN3
PVIN2
PGND2
PGND1 27
28
29
PVIN1
VIN
Thermal Pad
V7V 30
EN1 31
10 LX2
BST2
9
32
EN2
2
3
1
4
5
6
7
8
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal
performance.
图5-1. RHB Package 32-Pin VQFN Top View
表5-1. Pin Functions
PIN
DESCRIPTION
NAME
NO.
1
EN3
SDA
SCL
Enable for buck3. Float to enable. Can use this pin to adjust the input UVLO of buck3 with a resistor divider.
I2C interface data pin; float or connect to GND to disable I2C communication
2
3
I2C interface clock pin; float or connect to GND to disable I2C communication
Analog ground common to buck controllers and other analog circuits. It must be routed separately from high-current
power grounds to the (–) terminal of bypass capacitor of input voltage VIN.
AGND
4
VOUT2
FB2
5
6
Buck2 output voltage sense pin
Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the
control loop of buck2 with peak current PWM mode.
COMP2
SS2
7
Soft-start and tracking input for buck2. An internal 5.2-µA pullup current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
8
Boot-strapped supply to the high-side floating gate driver in buck2. Connect a capacitor (recommend 47 nF) from BST2
pin to LX2 pin.
BST2
LX2
9
Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN2 voltage.
10
11
12
13
14
15
16
17
Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input ceramic
capacitor.
PGND2
PVIN2
PVIN3
PGND3
LX3
Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input ceramic
capacitor.
Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN3 voltage.
Boot-strapped supply to the high-side floating gate driver in buck3. Connect a capacitor (recommend 47 nF) from BST3
pin to LX3 pin.
BST3
SS3
Soft-start and tracking input for buck3. An internal 5.2-µA pullup current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
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English Data Sheet: SLVSCS9
TPS65263-Q1
ZHCSDM4D –DECEMBER 2014 –REVISED MAY 2023
www.ti.com.cn
表5-1. Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
Error amplifier output and loop compensation pin for buck3. Connect a series resistor and capacitor to compensate the
control loop of buck3 with peak current PWM mode.
COMP3
18
FB3
19
20
Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
PGOOD
Output voltage supervision pin. When all bucks are in PGOOD monitor’s regulation range, PGOOD is asserted high.
Clock frequency adjustment pin. Connect a resistor from this pin to ground to adjust the clock frequency. When
connected to an external clock, the internal oscillator synchronizes to the external clock.
ROSC
FB1
21
22
23
Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the
control loop of buck1 with peak current PWM mode.
COMP1
Soft-start and tracking input for buck1. An internal 5.2-µA pullup current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
SS1
24
25
26
27
28
Boot-strapped supply to the high-side floating gate driver in buck1. Connect a capacitor (recommend 47 nF) from BST1
pin to LX1 pin.
BST1
LX1
Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN1 voltage.
Power ground connection of buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input ceramic
capacitor.
PGND1
PVIN1
Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
VIN
29
30
31
32
Buck controller power supply
V7V
EN1
EN2
Internal LDO for gate driver and internal controller. Connect a 10-µF ceremic capacitor from the pin to power ground.
Enable for buck1. Float to enable. Can use this pin to adjust the input UVLO of buck1 with a resistor divider.
Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider.
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
PAD
—
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English Data Sheet: SLVSCS9
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
–0.3
–1.0
–0.3
–0.3
–0.3
–0.3
–40
–55
MAX
20
UNIT
V
PVIN1, PVIN2, PVIN3,VIN
LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns)
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
EN1, EN2, EN3, V7V, VOUT2, SCL, SDA, PGOOD
FB1, FB2, FB3, COMP1 , COMP2, COMP3, ROSC, SS1, SS2, SS3
AGND, PGND1, PGND2, PGND3
20
V
7
V
7
V
3.6
0.3
150
150
V
V
TJ
Operating junction temperature
Storage temperature
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2, all pins (1)
Charged device model (CDM), per AEC Q100-011 CDM ESD classification level C4B
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
18
UNIT
V
PVIN1, PVIN2, PVIN3,VIN
4
–0.8
–0.1
–0.1
–0.1
–40
LX1, LX2, LX3 (Maximum withstand voltage transient <20 ns)
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA
FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3
Operating junction temperature
18
V
6.8
6.3
3
V
V
V
TJ
125
°C
6.4 Thermal Information
TPS65263-Q1
THERMAL METRIC(1)
RHB (VQFN)
32 PINS
33.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
25.7
Junction-to-board thermal resistance
7.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
7.3
ψJB
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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English Data Sheet: SLVSCS9
TPS65263-Q1
ZHCSDM4D –DECEMBER 2014 –REVISED MAY 2023
www.ti.com.cn
6.5 Electrical Characteristics
VIN = 12 V, FSW = 500 kHz, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VIN
Input voltage range
4
3.5
3.1
18
4
V
V
VIN rising
3.8
3.3
500
9.5
UVLO
VIN UVLO
VIN falling
3.5
V
Hysteresis
mV
µA
IDDSDN
Shutdown supply current
EN1 = EN2 = EN3 = 0 V
4
18
EN1 = EN2 = EN3 = 5 V, FB1 = FB2
= FB3 = 0.8 V
IDDQ_NSW
550
780
370
370
370
1150
µA
µA
µA
µA
EN1 = 5 V, EN2 = EN3 = 0 V, FB1 =
0.8 V
IDDQ_NSW1
IDDQ_NSW2
IDDQ_NSW3
180
180
180
590
590
590
Input quiescent current without buck1/2/3 switching
EN2 = 5 V, EN1 = EN3 = 0 V, FB2 =
0.8V
EN3 = 5 V, EN1 = EN2 = 0 V, FB3 =
0.8 V
V7V
V7V LDO output voltage
V7V LDO current limit
V7V load current = 0 A
6.3
V
IOCP_V7V
78
185
260
mA
FEEDBACK VOLTAGE REFERENCE
VFB Feedback voltage
BUCK1, BUCK2, BUCK3
VCOMP = 1.2 V
0.594
0.6 0.606
V
VENXH
EN1/2/3 high-level input voltage
1.12
1.05
2.5
5.1
2.6
3.9
50
1.2
1.15
3.9
6.9
3
1.26
1.21
5.9
V
V
VENXL
EN1/2/3 low-level input voltage
EN1/2/3 pullup current
IENX1
ENx = 1 V
µA
µA
µA
µA
ns
IENX2
EN1/2/3 pullup current
ENx = 1.5 V
9.2
IENhys
Hysteresis current
3.3
ISSX
Soft-start charging current
5.2
75
6.5
tON_MIN
Minimum on-time
110
450
Gm_EA
Error amplifier transconductance
COMP1/2/3 voltage to inductor current Gm
Buck1 peak inductor current limit
Buck1 low-side sink current limit
Buck2/buck3 peak inductor current limit
Buck2/buck3 low-side sink current limit
Buck1 high-side switch resistance
Buck1 low-side switch resistance
Buck2 high-side switch resistance
Buck2 low-side switch resistance
Buck3 high-side switch resistance
Buck3 low-side switch resistance
140
300
7.4
5.4
1.3
3.3
1
µs
–2 µA < ICOMPX < 2 µA
(1)
Gm_PS1/2/3
ILIMIT1
ILIMITSINK1
ILIMIT2/3
ILX = 0.5 A
A/V
A
4.3
0.7
6.5
1.8
3.9
1.4
A
2.55
0.5
A
ILIMITSINK2/3
Rdson_HS1
Rdson_LS1
Rdson_HS2
Rdson_LS2
Rdson_HS3
Rdson_LS3
HICCUP TIMING
tHiccup_wait
tHiccup_re
A
VIN = 12 V
VIN = 12 V
VIN = 12 V
VIN = 12 V
VIN = 12 V
VIN = 12 V
105
65
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
140
90
140
90
Overcurrent wait time(1)
256
cycles
cycles
Hiccup time before restart(1)
8192
POWER GOOD
FBx undervoltage falling
FBx undervoltage rising
FBx overvoltage rising
FBx overvoltage falling
92.5
95
Vth_PG
Feedback voltage threshold
%VREF
107.5
105
tDEGLITCH(PG)_F
tRDEGLITCH(PG)_R
PGOOD falling edge deglitch time
PGOOD rising edge deglitch time
112
cycles
cycles
616
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSCS9
6
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6.5 Electrical Characteristics (continued)
VIN = 12 V, FSW = 500 kHz, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.1
UNIT
µA
IPG
PGOOD pin leakage
VLOW_PG
OSCILLATOR
FSW
PGOOD pin low voltage
ISINK = 1 mA
0.4
V
Switching frequency
430
200
80
500
560
kHz
kHz
ns
ROSC = 88.7 kΩ
FSW_range
TSYNC_w
FSYNC_HI
VSYNC_LO
FSYNC
Switching frequency
2300
Clock sync minimum pulse width
Clock sync high threshold
Clock sync low threshold
Clock sync frequency range
2
V
0.4
V
200
2300
kHz
THERMAL PROTECTION
TTRIP_OTP
Temperature rising
Hysteresis
160
20
°C
°C
Thermal protection trip point(1)
THYST_OTP
I2C INTERFACE
Addr
Address(2)
0x60H
VIH SDA,SCL
VIL SDA,SCL
II
Input high voltage
Input low voltage
2
V
V
0.4
Input current
SDA, SCL, VI = 0.4 to 4.5 V
SDA open drain, IOL = 4 mA
10
µA
V
–10
VOL SDA
ƒ(SCL)
SDA output low voltage
Maximum SCL clock frequency(2)
0.4
400
1.3
kHz
Bus free time between a STOP and START
condition(2)
tBUF
µs
tHD_STA
tSU_STO
tLOW
Hold time (repeated) START condition(2)
Setup time for STOP condition(2)
Low period of the SCL clock(2)
High period of the SCL clock(2)
Setup time for a repeated START condition(2)
Data setup time(2)
0.6
µs
µs
µs
µs
µs
µs
µs
ns
0.6
1.3
tHIGH
0.6
tSU_STA
tSU_DAT
tHD_DAT
tRCL
0.6
0.1
0
Data hold time(2)
0.9
Rise time of SCL signal(2)
Capacitance of one bus line (pF)
Capacitance of one bus line (pF)
20 + 0.1CB
300
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit(2)
tRCL1
20 + 0.1CB
300
ns
tFCL
tRDA
tFDA
CB
Fall time of SCL signal(2)
Capacitance of one bus line (pF)
Capacitance of one bus line (pF)
Capacitance of one bus line (pF)
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
300
300
300
400
ns
ns
ns
pF
Rise time of SDA signal(2)
Fall time of SDA signal(2)
Capacitance of bus line(SCL and SDA)(2)
(1) Lab validation result
(2) Not production tested
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6.6 Typical Characteristics
TA = 25°C,VIN = 12 V, VOUT1 = 1.5 V, VOUT2 = 1.2 V, VOUT3 = 2.5 V, FSW = 500 kHz (unless otherwise noted)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VOUT 1.8 V
VOUT 2.5 V
VOUT 5.0 V
VOUT 1.2 V
VOUT 1.5 V
VOUT 3.3 V
0.01
0.02
0.05
0.1 0.2 0.3 0.5 0.7
Output Load (A)
1
2
0.01 0.02
0.05
0.1 0.2 0.3 0.5 0.7
Output Load (A)
1
2
3
D003
D001
图6-1. BUCK1 Efficiency
图6-2. BUCK2 Efficiency
1.52
1.515
1.51
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN 5 V
VIN 12 V
1.505
1.5
1.495
1.49
VOUT 1.8 V
VOUT 2.5 V
VOUT 5.0 V
1.485
1.48
0
0.5
1
1.5
Output Load (A)
2
2.5
3
0.01
0.02
0.05
0.1 0.2 0.3 0.5 0.7
Output Load (A)
1
2
D005
D004
图6-4. BUCK1, Load Regulation
图6-3. BUCK3 Efficiency
1.22
1.215
1.21
2.52
2.515
2.51
VIN 5 V
VIN 12 V
VIN 5 V
VIN 12 V
1.205
1.2
2.505
2.5
1.195
1.19
2.495
2.49
1.185
1.18
2.485
2.48
0
0.5
1
Output Load (A)
1.5
2
0
0.5
1
Output Load (A)
1.5
2
D006
D007
图6-5. BUCK2, Load Regulation
图6-6. BUCK3, Load Regulation
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6.6 Typical Characteristics (continued)
TA = 25°C,VIN = 12 V, VOUT1 = 1.5 V, VOUT2 = 1.2 V, VOUT3 = 2.5 V, FSW = 500 kHz (unless otherwise noted)
1.51
1.505
1.5
1.21
1.205
1.2
1.495
1.49
1.195
1.19
IOUT 0.1 A
IOUT 1.5 A
IOUT 3 A
IOUT 0.1 A
IOUT 1 A
IOUT 2 A
4
6
8
10 12
Input Voltage (V)
14
16
18
4
6
8
10 12
Input Voltage (V)
14
16
18
D008
D009
图6-7. BUCK1, Line Regulation
图6-8. BUCK2, Line Regulation
2.51
2.505
2.5
0.606
0.604
0.602
0.6
IOUT 0.1 A
IOUT 1A
IOUT 2A
0.598
0.596
0.594
2.495
2.49
4
6
8
10 12
Input Voltage (V)
14
16
18
-50
-30
-10
10
30
TJ (èC)
50
70
90
110 130
D010
D011
图6-9. BUCK3, Line Regulation
图6-10. Voltage Reference vs Temperature
540
520
500
480
460
15
13
11
9
7
5
-50
-30
-10
10
30
TJ (èC)
50
70
90
110 130
-50
-30
-10
10
30
TJ (
50
C)
70
90
110 130
è
D012
D013
VIN = 12 V
ROSC = 88.7 kΩ
图6-11. Oscillator Frequency vs Temperature
图6-12. Shutdown Quiescent Current vs Temperature
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6.6 Typical Characteristics (continued)
TA = 25°C,VIN = 12 V, VOUT1 = 1.5 V, VOUT2 = 1.2 V, VOUT3 = 2.5 V, FSW = 500 kHz (unless otherwise noted)
5
4.8
4.6
4.4
4.2
4
8
7.8
7.6
7.4
7.2
7
3.8
3.6
3.4
3.2
3
6.8
6.6
6.4
6.2
6
-50
-30
-10
10
30
50
70
90
110 130
-50
-30
-10
10
30
50
70
90
110 130
TJ (èC)
TJ (èC)
D014
D015
EN = 1 V
VIN = 12 V
EN = 1.5 V
VIN = 12 V
图6-13. EN Pin Pullup Current vs Temperature, EN = 1.0 V
图6-14. EN Pin Pullup Current vs Temperature, EN = 1.5 V
1.28
1.23
1.19
1.15
1.11
1.07
1.24
1.2
1.16
1.12
-50
-30
-10
10
30
50
70
90
110 130
-50
-30
-10
10
30
50
70
90
110 130
TJ (èC)
TJ (èC)
D017
D016
VIN = 12 V
图6-16. EN Pin Threshold Falling vs Temperature
VIN = 12 V
图6-15. EN Pin Threshold Rising vs Temperature
5.6
5.8
5.4
5.2
5
5.6
5.4
5.2
5
4.8
4.6
-50
-30
-10
10
30
50
70
90
110 130
-50
-30
-10
10
30
50
70
90
110 130
TJ (èC)
TJ (èC)
D018
D019
VIN = 12 V
图6-17. SS Pin Charge Current vs Temperature
VIN = 12 V
图6-18. Buck1 High-Side Current Limit vs Temperature
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6.6 Typical Characteristics (continued)
TA = 25°C,VIN = 12 V, VOUT1 = 1.5 V, VOUT2 = 1.2 V, VOUT3 = 2.5 V, FSW = 500 kHz (unless otherwise noted)
3.8
3.6
3.4
3.2
3
3.8
3.6
3.4
3.2
3
2.8
2.8
-50
-30
-10
10
30
50
70
90
110 130
-50
-30
-10
10
30
50
70
90
110 130
TJ (èC)
TJ (èC)
D020
D021
VIN = 12 V
VIN = 12 V
图6-19. Buck2 High-Side Current Limit vs Temperature
图6-20. Buck3 High-Side Current Limit vs Temperature
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7 Detailed Description
7.1 Overview
The TPS65263-Q1 is a monolithic, triple-synchronous step-down (buck) converter with 3-A/2-A/2-A output
currents. A wide 4- to 18-V input supply voltage range encompasses most intermediate bus voltages operating
off 5-, 9-, 12-, or 15-V power bus. The feedback voltage reference for each buck is 0.6 V. Each buck is
independent with dedicated enable, soft-start, and loop compensation pins.
The TPS65263-Q1 is equipped with an I2C compatible bus for communication with SoC to control buck
converters. Through the I2C interface, SoC can enable or disable the buck converters, set output voltage
(BUCK2 only), and read status registers. External feedback divider resistors can set the initial start-up voltage of
the buck2. After the voltage identification VID DAC is updated via the I2C, output voltage of the buck2 can be
independently programmed with 7 bits VID from 0.68 to 1.95 V in 10-mV voltage step resolution. Output voltage
of the buck2 transition begins after the I2C interface receives the command for the GO bit in the command
register.
If SDA and SCL pins are floated or are connected to GND, the I2C communication is rejected and the
TPS65263-Q1 operates as a traditional triple buck. Each buck on or off is separately controlled by the relevant
enable pin. Buck2’s output voltage is set with the external feedback divider resistors.
In the light load condition, the converter automatically operates in pulse skipping mode (PSM) to save power.
PSM can be disabled through I2C so that the converter operates at continuous current mode (CCM) at light load
with a fixed frequency for optimized output ripple.
The TPS65263-Q1 implements a constant frequency, peak current mode control that simplifies external loop
compensation. The wide switching frequency of 200 kHz to 2.3 MHz allows for optimizing system efficiency,
filtering size, and bandwidth. The switching frequency can be adjusted with an external resistor connecting
between the ROSC pin and ground. The TPS65263-Q1 also has an internal phase locked loop (PLL) controlled
by the ROSC pin that can be used to synchronize the switching cycle to the falling edge of an external system
clock. The switching clock of buck1 is 180° out-of-phase operation from the clocks of buck2 and buck3 channels
to reduce input current ripple, input capacitor size, and power-supply-induced noise.
The TPS65263-Q1 is designed for safe monotonic start-up into prebiased loads. The default start-up is when
VIN is typically 3.8 V. The ENx pin can also be used to adjust the input voltage undervoltage lockout (UVLO) with
an external resistor divider. In addition, the ENx pin has an internal 3.9-µA current source, so the EN pin can be
floating for automatically powering up the converters.
The TPS65263-Q1 reduces the external component count by integrating the bootstrap circuit. The bias voltage
for the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO circuit
monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the threshold,
LX pin is pulled low to recharge the bootstrap capacitor. The TPS65263-Q1 can operate at 100% duty cycle as
long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold, which is typically 2.1 V.
The TPS65263-Q1 has power-good comparators with hysteresis, which monitor the output voltages through
internal feedback voltages. I2C can read the power-good status with the command register. The device also
features the PGOOD pin to supervise output voltages of the buck converter. When all bucks are in regulation
range and power sequence is done, PGOOD is asserted high.
The SS (soft-start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing during
power up. A small value capacitor or resistor divider is connected to the pin for soft start or voltage tracking.
The TPS65263-Q1 is protected from overload and overtemperature fault conditions. The converter minimizes
excessive output overvoltage transients by taking advantage of the power-good comparator. When the output is
over, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105% of the 0.6-V
reference voltage. The TPS65263-Q1 implements both high-side MOSFET overload protection and bidirectional
low-side MOSFET overload protections to avoid inductor current runaway. If the overcurrent condition has lasted
for more than the OC wait time (256 clock cycle), the converter shuts down and restarts after the hiccup time
(8192 clock cycles). The TPS65263-Q1 shuts down if the junction temperature is higher than thermal shutdown
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trip point. When the junction temperature drops 20°C typically below the thermal shutdown trip point, the
TPS65263-Q1 is restarted under control of the soft-start circuit automatically.
7.2 Functional Block Diagram
21
ROSC
VIN 29
V7V 30
VIN
CLK/SYNC/
Phase Shift
EN1
EN2
EN3
V7V LDO
Bias
DVCC
V7V
clk
V7V
VIN
28
25
26
27
PVIN1
BST1
LX1
en_buck1
enable
VIN
ien_buck1
ien_buck2
ien_buck3
ien_buck1
BST
LX
SDA
SCL
2
3
BUCK1
I2C
I2C
Bus
7
PGND1
COMP
vfb
PGND
SS
24 SS1
22
23
FB1
Over
Temp
COMP1
clk
V7V
VIN
12
9
PVIN2
BST2
LX2
en_buck2
ien_buck2
enable
VIN
vfb1
vfb2
Power
Good
BST
LX
20
PGOOD
vfb3
BUCK2
10
11
8
PGND2
SS2
COMP
vfb
PGND
SS
3.9 uA
3 uA
3 uA
3 uA
6
5
FB2
MUX
31
EN1
EN2
EN3
VOUT2
en_buck1
2 K
2 K
2 K
6.3 V
1.2 V
1.2 V
1.2 V
I2C Reg.
7-BIT
I2C Reg.
3.9 uA
32
en_buck2
en_buck3
7
COMP2
6.3 V
3.9 uA
V7V
1
clk
V7V
VIN
6.3 V
13
16
15
14
PVIN3
BST3
LX3
en_buck3
ien_buck3
enable
VIN
BST
LX
BUCK3
PGND3
COMP
vfb
PGND
SS
17 SS3
19
FB3
AGND
4
18 COMP3
7.3 Feature Description
7.3.1 Adjusting the Output Voltage
The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. TI
recommends to use 1% tolerance or better resistors.
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Vout
R1
R2
FB
COMP
0.6 V
图7-1. Voltage Divider Circuit
0.6
R2 = R1 ´
Vout - 0.6
(1)
To improve efficiency at light loads consider using larger value resistors. If the values are too high, the regulator
is more sensitive to noise. 表7-1 shows the recommended resistor values.
表7-1. Output Resistor Divider Selection
OUTPUT VOLTAGE
(V)
R1
(kΩ)
R2
(kΩ)
1
10
10
15
10
1.2
1.5
1.8
2.5
3.3
3.3
5
15
10
20
10
31.6
45.3
22.6
73.2
36.5
10
10
4.99
10
5
4.99
The output voltage of the buck converter can be dynamically scaled by I2C-controlled 7-bit register,
VOUTx_SEL. Before I2C communication, the output voltage is set with the resistor divider from the output of
buck to the FB pin. When the GO bit is set to 1 through the I2C interface, the buck converter switches the
external resistor divider to the internal resistor divider as shown in 图 7-2. The output voltage can be selected
among 128 voltages with voltage identifications (VID) shown in 表 7-2. The output voltage range of dynamic
voltage scaling is 0.68 to 1.95 V with 10-mV resolution of each voltage step.
Vout2
VOUT2
VOUT_SEL<0:6>
R1
R1
7.5 K - 207 K
FB2
0
COMP2
1
0.6 V
R2
150 K
R2
AGND
VOUT_SEL<7>
“GO”Bit
图7-2. Voltage Divider Circuit
表7-2. VOUT Output Voltage Setting
OUT_SEL
<7:0>
VOUT
(V)
VOUT_SEL
<7:0>
VOUT
(V)
VOUT_SEL
<7:0>
VOUT
(V)
VOUT_SEL
<7:0>
VOUT
(V)
0
0.68
20
1
40
1.32
60
1.64
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表7-2. VOUT Output Voltage Setting (continued)
OUT_SEL
<7:0>
VOUT
(V)
VOUT_SEL
<7:0>
VOUT
(V)
VOUT_SEL
<7:0>
VOUT
(V)
VOUT_SEL
<7:0>
VOUT
(V)
1
2
0.69
0.7
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.1
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
1.33
1.34
1.35
1.36
1.37
1.38
1.39
1.4
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
1.65
1.66
1.67
1.68
1.69
1.7
3
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.8
4
5
6
7
1.71
1.72
1.73
1.74
1.75
1.76
1.77
1.78
1.79
1.8
8
9
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
A
B
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.2
C
D
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.9
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.9
1.51
1.52
1.53
1.54
1.55
1.56
1.57
1.58
1.59
1.6
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.3
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.91
1.92
1.93
1.94
1.95
1.61
1.62
1.63
1.31
7.3.2 Enable and Adjusting UVLO
The ENx pin provides electrical on and off control of the device. After the ENx pin voltage exceeds the threshold
voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters a low Iq state.
The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If
an application requires controlling the EN pin, use open-drain or open-collector output logic to interface with the
pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500 mV. If an
application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVINx in split
rail applications, then the user can configure the ENx pin as shown in 图7-3, 图7-4, and 图7-5. When using the
external UVLO function, TI recommends to set the hysteresis >500 mV.
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The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih after the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using 方程式2 and 方程式3.
æ
ö
÷
ø
VENFALLING
V
- V
STOP
START ç
VENRISING
è
R1
=
æ
ö
VENFALLING
I
1-
+ I
÷
h
P ç
VENRISING
è
ø
(2)
(3)
R1 ´ VENFALLING
VSTOP - VENFALLING + R I + I
R2
=
1 (h )
p
where
• Ih = 3 µA
• Ip = 3.9 µA
• VENRISING = 1.2 V
• VENFALLING = 1.15 V
VIN
PVIN
ih
ih
R1
R1
R2
ip
ip
EN
EN
R2
图7-3. Adjustable VIN UVLO
图7-4. Adjustable PVIN UVLO, VIN > 4 V
PVIN
VIN
ih
R1
R2
ip
EN
图7-5. Adjustable VIN and PVIN UVLO
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7.3.3 Soft-Start Time
The voltage on the respective SS pin controls the start-up of buck output. When the voltage on the SS pin is less
than the internal 0.6-V reference, The TPS65263-Q1 regulates the internal feedback voltage to the voltage on
the SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output
of buck to track another supply during start-up. The device has an internal pullup current source of 5.2 µA
(typical) that charges an external soft-start capacitor to provide a linear ramping voltage at the SS pin. The
TPS65263-Q1 regulates the internal feedback voltage to the voltage on the SS pin, allowing VOUT to rise
smoothly from 0 V to its regulated voltage without inrush current. The soft-start time can be calculated
approximately by 方程式4.
Css(nF)´ Vref(V)
Tss(ms) =
Iss(mA)
(4)
Many of the common power-supply sequencing methods can be implemented using the SSx and ENx pins. 图
7-6 shows the method implementing ratiometric sequencing by connecting the SSx pins of three buck channels
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start
time, the pullup current source must be tripled in 方程式4.
EN
31
EN threshold = 1.2 V
EN1
32
EN2
1
EN3
Vout3 = 2.5 V
24
SS1
Vout1 1.5 V
8
SS2
Vout2 1.2 V
17
SS3
Css
CSS × 0.6 V
tSS
=
15.6 µA
图7-6. Ratiometric Power-Up Using SSx Pins
The user can implement simultaneous power-supply sequencing by connecting the capacitor to the SSx pin,
shown in 图7-7. Using 方程式4 and 方程式5, the capacitors can be calculated.
Css1
Css2
Css3
=
=
Vout1 Vout2 Vout3
(5)
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EN
31
EN threshold = 1.2 V
EN1
32
EN2
1
EN3
Vout3 = 2.5 V
24
SS1
Css1
Vout1 1.5 V
Vout2 1.2 V
8
SS2
Css2
17
SS3
Css3
CSS3 × 0.6 V
5.2 µA
tSS
=
图7-7. Simultaneous Start-up Sequence Using SSx Pins
7.3.4 Power-Up Sequencing
The TPS65263-Q1 has a dedicated enable pin and soft-start pin for each converter. The converter enable pins
are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling
the converter with an active pulldown transistor on the ENx pin allows for predictable power-down timing
operation. 图 7-8 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at
the ENx pin.
A typical 1.4-µA current is charging the ENx pin from input supply. When the ENx pin voltage rises to typical 0.4
V, the internal V7V LDO turns on. A 3.9-µA pullup current is sourcing ENx. After the ENx pin voltage reaches the
ENx enabling threshold, a 3.0-µA hysteresis current sources to the pin to improve noise sensitivity. The internal
soft-start comparator compares the SS pin voltage to 1.2 V. When the SS pin voltage ramps up to 1.2 V, PGOOD
monitor is enabled. After PGOOD deglitch time, PGOOD is deasserted. The SS pin voltage is eventually
clamped around 2.1 V.
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VIN
V7V
EN Threshold
ENx Rise Time
Dictated by CEN
EN
Threshold
Charge CEN
with 6.9 µA
1.2 V
t = CSS × 0.6 V / 5.2 µA
Soft Start Rise Time
Dictated by CSS
ENx
SSx
About 2.1 V
0.4 V
1.2 V
0.6 V
Pre-Bias Startup
PGOOD Deglitch Time
VOUTx
t = CSS × 1.2 V / 5.2 µA
t = CENx × (1.2 - 0.4) V / 3.9 µA
t = CENx × 0.4 V / 1.4 µA
PGOOD
图7-8. Start-up Power Sequence
7.3.5 V7V Low-Dropout Regulator and Bootstrap
Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V
pin. The internal built-in low-dropout linear regulator (LDO) supplies 6.3 V (typical) from VIN to V7V. The user
must connect a 10-µF ceramic capacitor from V7V pin to power ground.
If the input voltage, VIN, decreases to the UVLO threshold voltage, the UVLO comparator detects the V7V pin
voltage and forces the converter off.
Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in 图 7-9, which is
normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than VIN and BST-LX voltage is below regulation. TI recommends a 47-nF ceramic capacitor. TI recommends a
ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher because of the
stable characteristics over temperature and voltage. Each low-side MOSFET driver is powered from the V7V pin
directly.
To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between BST and LX
drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.
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VIN
LDO
(VBSTx –VLXx)
+
nBootUV
–
2.1 V
PVINx
V7V
BSTx
CBIAS
10 µF
High-side
MOSFET
nBootUV
PWM
UVLO Bias Buck
Controller
Gate
Driver
CB
LXx
Low-side
MOSFET
nBootUV
PWM
Gate
Driver
BootUV
Protection
CLK
图7-9. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram
7.3.6 Out-of-Phase Operation
To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.
This enables the system having less input current ripple to reduce input capacitors’size, cost, and EMI.
7.3.7 Output Overvoltage Protection (OVP)
The device incorporates an OVP circuit to minimize output voltage overshoot. When the output is overloaded,
the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is
lower than the internal reference voltage for a considerable time, the output of the error amplifier demands
maximum output current. After the condition is removed, the regulator output rises and the error amplifier output
transitions to the steady-state voltage. In some applications with small output capacitance, the load can respond
faster than the error amplifier. This leads to the possibility of an output overshoot. Each buck compares the FB
pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET
is turned off preventing current from flowing to the output and minimizing output overshoot. When the FB voltage
drops lower than the OVP threshold, the high-side MOSFET turns on at the next clock cycle.
7.3.8 PSM
The TPS65263-Q1 can enter high-efficiency PSM operation at light load current. To disable PSM operation, set
the VOUTx_COM registers’bit 1 to '1' through I2C interface.
When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 310-mA
current typically. Because the integrated current comparator catches the peak inductor current only, the average
load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak
inductor current is clamped at 310 mA, shown in 图7-10.
When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current
comparator turns off the low-side MOSFET when the inductor current reaches 0, preventing it from reversing and
going negative.
Due to the delay in the circuit and current comparator, tdly (typical 50 nS at Vin = 12 V), the real peak inductor
current threshold to turn off high-side power MOSFET can shift higher depending on inductor inductance and
input/output voltages. Calculate the threshold of peak inductor current to turn off high-side power MOSFET with
方程式6.
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Vin - Vout
ILPEAK =310 mA +
´ tdly
L
(6)
After the charge accumulated on the Vout capacitor is more than loading need, the COMP pin voltage drops to a
low voltage driven by the error amplifier. There is an internal comparator at COMP pin. If the comp voltage is
<0.35 V, the power stage stops switching to save power.
310 mA
Turn off
high-side power MOSFET
+
Inductor
Current Peak
œ
Current
Sensing
x1
Current Comparator
Delay: tdly
ILPEAK
Inductor Peak Current
图7-10. PSM Current Comparator
7.3.9 Slope Compensation
To prevent the subharmonic oscillations when the device operates at duty cycles greater than 50%, the
TPS65263-Q1 adds built-in slope compensation, which is a compensating ramp to the switch current signal.
7.3.10 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and low-side MOSFET.
7.3.10.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control that uses the COMP pin voltage to control the turn off of the high-
side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference, the high-side switch is turned off.
7.3.10.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-
side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 256 switching cycles shown in 图 7-11, the device shuts down and
restarts after the hiccup time of 8192 cycles. The hiccup mode helps to reduce the device power dissipation
under severe overcurrent condition.
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OCP peak inductor current threshold
OC limiting (waiting) time
hiccup time
8192 cycles
soft start time
t = Css × 0.6 V/5.2 µA
256 cycles
Output over loading
iL
Inductor Current
Soft-start is reset after OC waiting time
About 2.1 V
0.6 V
OC fault removed, soft-start, and output recovery
SS
SS Pin Voltage
Output hard short circuit
Vout
Output Voltage
图7-11. Overcurrent Protection
7.3.11 Power Good
The PGOOD pin is an open-drain output. When feedback voltage of each buck is between 95% (rising) and
105% (falling) of the internal voltage reference, the PGOOD pin pulldown is deasserted and the pin floats. TI
recommends to use a pullup resistor between the values of 10 and 100 kΩ to a voltage source that is 5.5 V or
less. The PGOOD is in a defined state when the VIN input voltage is greater than 1 V, but with reduced current
sinking capability. The PGOOD achieves full current sinking capability after the VIN input voltage is above UVLO
threshold, which is 3.8 V.
The PGOOD pin is pulled low when any feedback voltage of buck is lower than 92.5% (falling) or greater than
107.5% (rising) of the nominal internal reference voltage. Also, when the PGOOD is pulled low, if the input
voltage is undervoltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in
soft-start period.
The power-good indicator for each buck channel can be read back through I2C. The bits in SYS_STATUS[2:0]
(address 0x06H) present the feedback voltage in regulation (logic 1) or not (logic 0) for buck1, buck2, and buck3
respectively
7.3.11.1 Adjustable Switching Frequency
The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching
frequency of the device is adjustable from 200 kHz to 2.3 MHz.
To determine the ROSC resistance for a given switching frequency, use 方程式 7 or the curve in 图 7-12. To
reduce the solution size, the user must set the switching frequency as high as possible, but consider tradeoffs of
the supply efficiency and minimum controllable on-time.
ƒosc kHz = 37254´R(KW)-0.966
(
)
(7)
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2300
2000
1700
1400
1100
800
500
200
10 30 50 70 90 110 130 150 170 190 210 230
ROSC (kW)
D022
图7-12. ROSC vs Switching Frequency
When an external clock applies to ROSC pin, the internal PLL has been implemented to allow internal clock
synchronizing to an external clock between 200 and 2300 kHz. To implement the clock synchronization feature,
connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to 80%. The clock signal
amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the switching cycle is synchronized
to the falling edge of ROSC pin.
In applications where both resistor mode and synchronization mode are needed, the user can configure the
device as shown in 图 7-13. Before an external clock is present, the device works in resistor mode and ROSC
resistor sets the switching frequency. When an external clock is present, the synchronization mode overrides the
resistor mode. The first time the ROSC pin is pulled above the ROSC high threshold (2.0 V), the device switches
from the resistor mode to the synchronization mode and the ROSC pin becomes high impedance as the PLL
starts to lock onto the frequency of the external clock. TI does not recommend to switch from the synchronization
mode back to the resistor mode because the internal switching frequency drops to 100 kHz first before returning
to the switching frequency set by ROSC resistor.
Mode
Selection
IC
ROSC
ROSC
图7-13. Works With Resistor Mode and Synchronization Mode
7.3.12 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 140°C
typically.
7.4 Device Functional Modes
7.4.1 Serial Interface Description
I2C is a 2-wire serial interface developed by NXP Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus
through open-drain I/O pins, SDA and SCL. A controller device, usually a microcontroller or a digital signal
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processor, controls the bus. The controller is responsible for generating the SCL signal and device addresses.
The controller also generates specific conditions that indicate the START and STOP of data transfer. A target
device receives and/or transmits data on the bus under control of the controller device.
The TPS65263-Q1 device works as a target and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
power-supply solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as supply voltage remains
above 3.8 V (typical).
The data transfer protocol for standard and fast modes is exactly the same. Therefore, they are referred to as
F/S-mode in this document. The TPS65263-Q1 device supports 7-bit addressing. 10-bit addressing and general
call address are not supported.
SDA
tSU,DAT
tBUF
tSU,STA
tHD,STA
tLOW
tHD,DAT
tSU,STO
SCL
tHD,STA
tHIGH
tSP
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
tr
tf
CONDITION
图7-14. I2C Interface Timing Diagram
7.4.2 I2C Update Sequence
The TPS65263-Q1 requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS65263-Q1 device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I2C address selects the TPS65263-Q1. TPS65263-Q1
performs an update on the falling edge of the LSB byte.
When the TPS65263-Q1 is in hardware shutdown (EN1, EN2, and EN3 pin tied to ground) the device cannot be
updated through the I2C interface. Conversely, the I2C interface is fully functional during software shutdown
(EN1, EN2, and EN3 bit = 0).
S
0
A
A
A P
7-Bit Target Address
Register Address
Data Byte
图7-15. I2C Write Data Format
S
0
A
A
Sr
1
A
7-Bit Target Address
Data Byte
Register1 Address
P
7-Bit Target Address
N
A: Acknowledge
N: Not Acknowledge
S: Start
System Host
Chip
P: Stop
Sr: Repeated Start
图7-16. I2C Read Data Format
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7.5 Register Maps
表7-3. Register Addresses
NAME
BITS
ADDRESS
0x01H
VOUT2_SEL
VOUT1_COM
VOUT2_COM
VOUT3_COM
SYS_STATUS
8
8
8
8
8
0X03H
0x04H
0X05H
0x06H
7.5.1 VOUT2_SEL: Vout2 Voltage Selection Register (Address = 0x01H)
图7-17. VOUT2_SEL: Vout2 Voltage Selection Register
7
6
5
4
3
2
1
0
Vout2_Bit7
Vout2_Bit6
Vout2_Bit5
Vout2_Bit4
Vout2_Bit3
Vout2_Bit2
Vout2_Bit1
Vout2_Bit0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-4. VOUT2_SEL: Vout2 Voltage Selection Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
“Go”bit, must set 1 to enable I2C controlled VID voltages
Vout2_Bit7
Vout2_Bit6
Vout2_Bit5
Vout2_Bit4
Vout2_Bit3
Vout2_Bit2
Vout2_Bit1
Vout2_Bit0
0
0
0
0
0
0
0
0
6
128 voltage selections with 7-bits control
Voltage range: 0.68 to 1.95 V
Voltage step resolution: 10 mV
5
4
0x00H: Vout2 = 0.68 V;
0x7FH: Vout2 = 1.95 V
3
2
1
0
7.5.2 VOUT1_COM: Buck1 Command Register (offset = 0x03H)
图7-18. VOUT1_COM: Buck1 Command Register
7
6
5
4
3
2
1
0
N/A
Mode1
nEN1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-5. VOUT1_COM: Buck1 Command Register Field Descriptions
Bit
7:2
1
Field
N/A
Type
R/W
R/W
Reset
000000
0
Description
Not used
Mode1
0: Enable buck 1 PSM operation at light load;
1: Forced buck 1 PWM mode operation
0
nEN1
R/W
0
0: Enable buck1;
1: Disable buck1
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7.5.3 VOUT2_COM: Buck2 Command Register (offset = 0x04H)
图7-19. VOUT2_COM: Buck2 Command Register
7
6
5
4
3
2
1
0
N/A
SR3
SR2
SR1
N/A
N/A
Mode2
nEN2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-6. VOUT2_COM: Buck2 Command Register Field Descriptions
Bit
7
Field
N/A
Type
R/W
R/W
R/W
R/W
Reset
Description
0
0
0
0
Not used
6
SR3
SR2
SR1
Vout2 VID voltage transition Slew Rate control.
000: 10 mV/cycle;
001: 10 mV/2 cycles;
5
010: 10 mV/4 cycles;
100: 10 mV/16 cycles;
110: 10 mV/64 cycles;
011: 10 mV/8 cycles;
101: 10 mV/32 cycles;
111: 10 mV/128 cycles
4
3
2
1
N/A
R/W
R/W
R/W
0
0
0
Not used
Not used
N/A
Mode2
0: Enable buck 2 PSM operation at light load;
1: Forced buck 2 PWM mode operation
0
nEN2
R/W
0
0: Enable buck2;
1: Disable buck2
7.5.4 VOUT3_COM: Buck3 Command Register (offset = 0x05H)
图7-20. VOUT3_COM: Buck3 Command Register
7
6
5
4
3
2
1
0
N/A
Mode3
nEN3
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-7. VOUT3_COM: Buck3 Command Register Field Descriptions
Bit
7:2
1
Field
N/A
Type
R/W
R/W
Reset
000000
0
Description
Not used
Mode3
0: Enable buck 3 PSM operation at light load;
1: Forced buck 3 PWM mode operation
0
nEN3
R/W
0
0: Enable buck3;
1: Disable buck3
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7.5.5 SYS_STATUS: System Status Register (offset = 0x06H)
图7-21. SYS_STATUS: System Status Register
7
6
5
4
3
2
1
0
OTP
OC3
OC2
OC1
OTW
PGOOD3
PGOOD2
PGOOD1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-8. SYS_STATUS: System Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OTP
R
0
1: Die temperature over 160°C, which triggers over temperature protection;
0: Die overtemperature protection is not triggered.
1: Buck3 over current limiting and hiccup protection is triggered;
0: Buck3 current not beyond the current limit.
6
5
4
3
2
OC3
R
R
R
R
R
0
0
0
0
0
OC2
1: Buck2 overcurrent limiting and hiccup protection is triggered;
0: Buck2 current not beyond the current limit.
OC1
1: Buck1 overcurrent limiting and hiccup protection is triggered;
0: Buck1 current not beyond the current limit.
OTW
PGOOD3
1: Die temperature over 125°C;
0: Die temperature below 125°C.
1:
0:
1:
0:
1:
0:
Vout3 in power good monitor’s range;
Vout3 not in power good monitor’s range.
Vout2 in power good monitor’s range;
Vout2 not in power good monitor’s range.
Vout1 in power good monitor’s range ;
Vout1 not in power good monitor’s range.
1
0
PGOOD2
PGOOD1
R
R
0
0
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The device is triple-synchronous step-down dc/dc converter with I2C interface. It is typically used to convert a
higher dc voltage to lower dc voltages with continuous available output current of 3 A/2 A/2 A.
8.2 Typical Application
The following design procedure can be used to select component values for the TPS65263-Q1. This section
presents a simplified discussion of the design process.
图8-1. Typical Application Schematic
8.2.1 Design Requirements
This example details the design of triple-synchronous step-down converter. A few parameters must be known to
start the design process. These parameters are typically determined at the system level. For this example, we
start with the following known parameters:
表8-1. Design Parameters
PARAMETER
VALUE
Vout1
1.5 V
Iout1
3 A
Vout2
Iout2
1.2 V
2 A
Vout3
2.5 V
Iout3
2 A
±5%
Transient response 1-A load step
Input voltage
12 V normal, 4 to 18 V
±1%
Output voltage ripple
Switching frequency
500 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Inductor Selection
To calculate the value of the output inductor, use 方程式 8. LIR is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for
the majority of applications.
V
- Vout
Vout
Vinmax ´ ƒsw
inmax
L =
´
Io ´LIR
(8)
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
Calculate the RMS and peak inductor current from 方程式10 and 方程式11.
V
- Vout
´
Vout
Vinmax ´ ƒsw
inmax
Iripple
=
L
(9)
æ
ö2
Vout ´ V
- Vout
(
)
inmax
ç
ç
÷
÷
Vinmax ´L ´ ƒsw
è
ø
ILrms
=
IO2 +
12
(10)
(11)
Iripple
ILpeak =Iout
+
2
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
8.2.2.2 Output Capacitor Selection
The three primary considerations for selecting the value of the output capacitor are:
• Output capacitor determines the modulator pole
• Output voltage ripple
• How the regulator responds to a large change in load current
The output capacitance must be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor needs to
supply the load with current when the regulator cannot. This situation can occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of droop in the output voltage. 方程式 12 shows the minimum output capacitance necessary to
accomplish this.
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2´ DIout
Co =
ƒsw ´ DVout
(12)
where
• ΔIout is the change in output current
• ƒsw is the regulators switching frequency
• ΔVout is the allowable change in the output voltage
方程式13 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
1
1
Co >
´
Voripple
8´ ƒsw
Ioripple
(13)
where
• ƒsw is the switching frequency
• Voripple is the maximum allowable output voltage ripple
• Ioripple is the inductor ripple current
方程式 14 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
Voripple
Resr
<
Ioripple
(14)
Additional capacitance deratings for aging, temperature, and DC bias must be factored in, which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. The user must specify an output capacitor that can support the inductor ripple current.
Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Use 方程
式15 to calculate the RMS ripple current the output capacitor needs to support.
Vout ´ V
- Vout
(
)
12 ´ Vinmax ´L ´ ƒsw
inmax
Icorms
=
(15)
8.2.2.3 Input Capacitor Selection
The TPS65263-Q1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10
µF of effective capacitance on the PVIN input voltage pins. In some applications, additional bulk capacitance can
also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of
the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple
current rating greater than the maximum input current ripple of the TPS65263-Q1. The input ripple current can
be calculated using 方程式16.
V
(
- Vout
)
Vout
inmin
I
=Iout
´
´
inrms
V
V
inmin
inmin
(16)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
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decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple
voltage of the regulator. Use 方程式17 to calculate the input voltage ripple.
I
outmax ´ 0.25
DV
=
in
Cin ´ ƒsw
(17)
8.2.2.4 Loop Compensation
The TPS65263-Q1 incorporates a peak current mode control scheme. The error amplifier is a transconductance
amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase margin
between 40° and 90°. Cb adds a high-frequency pole to attenuate high-frequency noise when needed. To
calculate the external compensation components, follow these steps.
1. Select switching frequency, ƒsw, that is appropriate for application depending on L and C sizes, output ripple,
EMI, and so forth. Switching frequency between 500 kHz to 1 MHz gives best trade-off between
performance and cost. To optimize efficiency, lower switching frequency is desired.
2. Set up crossover frequency, ƒc, which is typically between 1/5 and 1/20 of ƒsw.
3. RC can be determined by:
2p´ ƒc ´ Vo´ Co
RC
=
Gm-EA ´ Vref ´ Gm-PS
(18)
where
• Gm_EA is the error amplifier gain (300 µS).
• Gm_PS is the power stage voltage to current conversion gain (7.4 A/V).
1
æ
ö
=
çƒp
è
÷
Co ´ RL ´ 2p
ø
4. Calculate CC by placing a compensation zero at or before the dominant pole
.
RL ´ Co
CC
=
RC
(19)
(20)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
R
ESR ´ Co
Cb =
RC
6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly
higher loop bandwidths and higher phase margins. If used, calculate C1 from 方程式21.
1
C1 =
2p þ R1 ì ƒC
(21)
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LX
VOUT
iL
RESR
RL
Current Sense
I/V Converter
Gm_PS = 7.4 A / V
Co
C1
R1
Vfb
–
EA
+
FB
COMP
Vref = 0.6 V
R2
Gm_EA = 300 uS
Rc
Cb
Cc
图8-2. DC/DC Loop Compensation
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8.2.3 Application Curves
Iout = 3 A
Iout = 2 A
图8-3. BUCK1, Soft Start
图8-4. BUCK2, Soft Start
Iout = 2 A
A.
Iout = 3 A
图8-5. BUCK3, Soft Start
图8-6. BUCK1, Output Voltage Ripple
Iout = 2 A
Iout = 2 A
图8-7. BUCK2, Output Voltage Ripple
图8-8. BUCK3, Output Voltage Ripple
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0.75 to 1.5 A
SR = 0.25 A/µs
1.5 to 2.25 A
SR = 0.25 A/µs
图8-9. BUCK1, Load Transient
图8-10. BUCK1, Load Transient
0.5 to 1.0 A
SR = 0.25 A/µs
1.0 to 1.5 A
SR = 0.25 A/µs
图8-11. BUCK2, Load Transient
图8-12. BUCK2, Load Transient
0.5 to 1.0 A
SR = 0.25 A/µs
1.0 to 1.5 A
SR = 0.25 A/µs
图8-13. BUCK3, Load Transient
图8-14. BUCK3, Load Transient
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图8-15. BUCK1, Hiccup and Recovery
图8-16. BUCK2, Hiccup and Recovery
图8-17. BUCK3, Hiccup and Recovery
图8-18. PGOOD
图8-19. VID2 from 00 to 7F, SR = 10 mV/Cycle
图8-20. VID2 from 7F to 00, SR = 10 mV/Cycle
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图8-21. 180° Out-of-Phase
图8-22. Synchronization with External Clock
VIN = 12 V, VOUT1 = 1.5 V/3 A, VOUT2 = 1.2 V/2 A,
VOUT3 = 2.5 V/2 A,
图8-23. Operation at VIN Drop to 2.5 V
TA = 26.8°C EVM condition 4 layers, 75 mm × 75 mm
图8-24. Thermal Signature of TPS65263-Q1EVM
Operating
8.3 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4 and 18 V. This input power
supply must be well regulated. If the input supply is located more than a few inches from the TPS65263-Q1
converter, additional bulk capacitance can be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 47 µF is a typical choice.
8.4 Layout
8.4.1 Layout Guidelines
图8-25 shows the TPS65263-Q1 on a 2-layer PCB.
Layout is a critical portion of good power-supply design. See 图8-25 for a PCB layout example. The top contains
the main power traces for PVIN, VOUT, and LX. The top layer also has connections for the remaining pins of the
TPS65263-Q1 and a large top-side area filled with ground. The top-layer ground area must be connected to the
bottom layer ground using vias at the input bypass capacitor, the output filter capacitor, and directly under the
TPS65263-Q1 device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer
acts as ground plane connecting analog ground and power ground.
For operation at full rated load, the top-side ground area together with the bottom-side ground plane must
provide adequate heat dissipating area. Several signals paths conduct fast changing currents or voltages that
can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies'
performance. To help eliminate these problems, bypass the PVIN pin to ground with a low-ESR ceramic bypass
capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor
connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a
low-ESR ceramic capacitor with X5R or X7R dielectric.
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Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground must use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this
conductor length while maintaining adequate width. The small signal components must be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as
possible to the IC and routed with minimal lengths of trace. The additional external components can be placed
approximately as shown.
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8.4.2 Layout Example
VOUT1
VOUT3
BST1
LX1
BST3
LX3
PGND1
PVIN1
VIN
PGND3
PVIN3
PVIN2
PGND2
LX2
PVIN
PVIN
VIN
V7V
EN1
EN2
BST2
VOUT2
TOPSIDE
GROUND
AREA
0.010-inch Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
图8-25. PCB Layout
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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English Data Sheet: SLVSCS9
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65263QRHBRQ1
TPS65263QRHBTQ1
ACTIVE
VQFN
VQFN
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TPS
65263Q
Samples
Samples
ACTIVE
RHB
NIPDAU
TPS
65263Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2023
OTHER QUALIFIED VERSIONS OF TPS65263-Q1 :
Catalog : TPS65263
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65263QRHBRQ1
TPS65263QRHBTQ1
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65263QRHBRQ1
TPS65263QRHBTQ1
VQFN
VQFN
RHB
RHB
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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