TPS65265 [TI]
4.5V 至 17V 输入电压、5A/3A/2A 输出电流、三路降压转换器;型号: | TPS65265 |
厂家: | TEXAS INSTRUMENTS |
描述: | 4.5V 至 17V 输入电压、5A/3A/2A 输出电流、三路降压转换器 转换器 |
文件: | 总49页 (文件大小:3374K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS65265
ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
TPS65265 4.5V 至17V 输入电压、5A/3A/2A 输出电流三路同步降压转换器
1 特性
3 说明
• 工作输入电压范围:4.5V 至17V
• 反馈基准电压为0.6V ±1.33%
• 持续输出电流:5A/3A/2A
• 可调节时钟频率范围为250kHz 至
2.3MHz
• 外部同步振荡器
• Buck1、Buck2 和Buck3 之间具有120° 相位差
• 针对每个降压转换器的专用使能引脚
• 针对每个降压转换器的固定软启动(SS) 时间
(2.4ms)
TPS65265 整合了三路同步降压转换器,支持 4.5V 至
17V 宽范围输入电压,该电压范围包括大部分中间总
线关闭电压为 5、9、12 或 15V 的电源总线或电池。
这款转换器具有恒定频率峰值电流模式,专用于简化应
用,同时方便设计人员根据目标应用来优化系统。可通
过外部电阻或外部时钟在 250kHz 至2.3MHz 范围内调
节转换器的开关频率。Buck1、Buck2 和 Buck3 之间
的 120° 异相运行可最大限度降低对输入滤波器的要
求。
TPS65265 可通过将 MODE 引脚驱动为高电平或保持
悬空进入脉冲跳跃模式 (PSM),通过将 MODE 引脚连
接至 GND 进入强制持续电流模式 (FCC)。PSM 模式
通过减少轻负载时的开关损耗来提供高效率,而 FCC
模式可降低噪声灵敏度和射频(RF) 干扰。
• 自动加电/断电序列以及各降压转换器间可调节的间
隔时间(6 种组合)
• 支持脉冲跳跃模式(PSM) 和强制持续电流模式
(FCCM)
• 输出电压电源正常状态指示器和可调节延迟时间
• 热过载保护
• 32 引脚QFN (RHB) 5mm × 5mm 封装
TPS65265 采用 32 引脚 5mm × 5mm 耐热增强型
QFN (RHB) 薄型封装。
2 应用
封装信息(1)
封装尺寸(标称值)
器件型号
TPS65265
封装
• 数字电视(DTV)
• 机顶盒/OTT
RHB(VQFN,32) 5.00mm × 5.00mm
• 家庭网关和接入点网络
• 监控
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
Vout1
100%
90%
80%
70%
60%
50%
40%
30%
20%
Vin
PVINx
LX1
FB1
LX2
MODE
PSM
Vout2
Vout3
PG_DLY
TPS65265
SEQ_DLY
ENx
FB2
LX3
PGOOD
ROSC
PSM Mode, VOUT = 1.2 V
10%
PWM Mode, VOUT = 1.2 V
AGND
FB3
PGND
0
0.01
0.1
Output Current (A)
1
5
D100
简化版应用电路
效率与输出负载之间的关系
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSD86
TPS65265
www.ti.com.cn
ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
Table of Contents
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................25
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 27
9.3 Power Supply Recommendations.............................38
9.4 Layout....................................................................... 38
10 Device and Documentation Support..........................40
10.1 接收文档更新通知................................................... 40
10.2 支持资源..................................................................40
10.3 Trademarks.............................................................40
10.4 静电放电警告.......................................................... 40
10.5 术语表..................................................................... 40
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................7
7.6 Typical Characteristics................................................9
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................14
Information.................................................................... 40
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2015) to Revision B (May 2023)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 通篇去除了图像的颜色........................................................................................................................................1
• Renamed section 5 to Device Comparison Table ..............................................................................................3
• Change the description of V7V pin in 表6-1 ......................................................................................................3
• Changed the recommended value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator
and Bootstrap .................................................................................................................................................. 21
• Changed the recommended value of C5 in 图9-1........................................................................................... 27
Changes from Revision * (December 2015) to Revision A (December 2015)
Page
• 将器件状态更改为量产数据并发布了完整数据表................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSD86
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ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
5 Device Comparison Table
PART
DESCRIPTION
NUMBER
COMMENTS
TPS65261,
4.5 V to 18 V, triple bucks with input Triple bucks 3-A/2-A/2-A output current, features an open drain RESET signal to
monitor input power failure, automatic power sequencing
TPS65261-1 voltage power failure indicator
TPS65262, 4.5 V to 18 V, triple bucks with dual Triple bucks 3-A/1-A/1-A output current, automatic power sequencing, dual LDOs
TPS65262-1 adjustable LDOs
100 mA/200 mA for TPS65262, 350 mA/150 mA for TPS65262-1
4.5 V to 18 V, triple bucks with I2C
interface
Triple bucks 3-A/2-A/2-A output current, I2C controlled dynamic voltage scaling
(DVS)
TPS65263
TPS65266
2.7 V to 6.5 V, triple bucks
Triple bucks 3 A/2 A/2 A
6 Pin Configuration and Functions
24
23
22
21
20
19
18
17
16
15
BST3
PGND3
LX3
BST1
PGND1
PGND1
LX1
25
26
27
14
13
12
PVIN3
PVIN2
LX2
28
29
Thermal Pad
LX1
PVIN1
11
10
9
30
31
32
PVIN1
PSM
PGND2
BST2
1
2
3
4
5
6
7
8
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal
performance.
图6-1. RHB Package 32-Lead Plastic QFN Top View
表6-1. Pin Functions
PIN
DESCRIPTION
NO.
NAME
1
2
V7V
Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground
An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal
shutdown, over-current, under-voltage or ENx shut down.
PGOOD
EN1
Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout (UVLO) of buck1
with a resistor divider.
3
4
5
6
EN2
EN3
FB2
Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider.
Enable for buck3. Float to enable. Can use this pin to adjust the input UVLO of buck3 with a resistor divider.
Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
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ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
表6-1. Pin Functions (continued)
PIN
DESCRIPTION
NO.
NAME
COMP2
Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to
compensate the control loop of buck2 with peak current PWM mode.
7
8
9
When floating, Buck1/2/3 are controlled separate by EN1/2/3. When tied to HIGH or tied to GND, an automatic
power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins.
MODE
BST2
Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF)
from BST2 pin to LX2 pin.
Power ground connection of buck2. Connect PGND2 pin as close as practical to the (-) terminal of PVIN2 input
ceramic capacitor.
10
11
12
13
14
15
16
17
18
PGND2
LX2
Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is
from a diode voltage below the ground up to PVIN2 voltage.
Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic
capacitor (suggest 10 µF).
PVIN2
PVIN3
LX3
Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic
capacitor (suggest 10 µF).
Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is
from a diode voltage below the ground up to PVIN3 voltage.
Power ground connection of buck3. Connect PGND3 pin as close as practical to the (-) terminal of PVIN3 input
ceramic capacitor.
PGND3
BST3
Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF)
from BST3 pin to LX3 pin.
Delay time programmable between bucks at automatic power sequencing mode. Connect an external capacitor
to set the interval delay time.
SEQ_DLY
COMP3
Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to
compensate the control loop of buck3 with peak current PWM mode.
19
20
21
22
FB3
Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.
Analog ground common to buck controllers and other analog circuits.
ROSC
AGND
FB1
Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to
compensate the control loop of buck1 with peak current PWM mode.
23
24
25
COMP1
PG_DLY
BST1
PGOOD delay programmable pin. Connect an external capacitor to set the delay time.
Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF)
from BST1 pin to LX1 pin.
Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (-) terminal of PVIN1 input
ceramic capacitor.
26, 27 PGND1
28, 29 LX1
Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is
from a diode voltage below the ground up to PVIN1 voltage.
Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic
capacitor (suggest 22 µF).
30, 31 PVIN1
32
PSM
Ties to HIGH or leaves floating, PSM mode; Ties to GND, FCCM mode.
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to
PCB for optimal thermal performance.
PAD
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ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–1.0
–1.0
–0.3
–0.3
–0.3
–0.3
–40
–55
MAX
20
UNIT
V
PVIN1, PVIN2, PVIN3, PGOOD
LX1, LX2, LX3
19
V
LX1, LX2, LX3 (maximum withstand voltage transient <10 ns)
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins, respectively
EN1, EN2, EN3, V7V, MODE, PSM
21
V
7
V
7
V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, ROSC, SEQ_DLY, PG_DLY
AGND, PGND1, PGND2, PGND3
3.6
0.3
150
150
V
V
Operating junction temperature, TJ
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
UNIT
PVIN1, PVIN2, PVIN3
17
19
V
V
LX1, LX2, LX3 (Maximum withstand voltage transient <10 ns)
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
EN1, EN2, EN3, V7V, MODE, PSM
–0.8
–0.1
–0.1
–0.1
–40
6.8
6.3
3.3
125
V
V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, ROSC, SEQ_DLY, PG_DLY
Operating junction temperature, TJ
V
°C
7.4 Thermal Information
TPS65265
RHB (QFN)
32 PINS
32
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
24.2
6.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
6.4
ψJB
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English Data Sheet: SLVSD86
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ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
TPS65265
RHB (QFN)
32 PINS
1.3
THERMAL METRIC(1)
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
7.5 Electrical Characteristics
TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VIN
Input voltage range
4.5
3.6
3.0
17
4
V
V
VIN rising
3.8
3.2
UVLO
VIN undervoltage lockout
VIN falling
Hysteresis
3.4
V
600
mV
PVIN = 12 V, EN1 = EN2 =
EN3 = MODE = 0 V
IDDSDN
Shutdown supply current
9
550
280
280
280
11.5
680
350
350
350
14
800
425
425
425
µA
µA
µA
µA
µA
EN1 = EN2 = EN3 = 5 V, FB1
= FB2 = FB3 = 0.8 V
IDDQ_NSW
IDDQ_NSW1
IDDQ_NSW2
IDDQ_NSW3
EN1 = 5 V, EN2 = EN3 = 0 V,
FB1 = 0.8 V
Input quiescent current without buck1/2/3
switching
EN2 = 5 V, EN1 = EN3 = 0 V,
FB2 = 0.8 V
EN3 = 5 V, EN1 = EN2 = 0 V,
FB3 = 0.8 V
PVIN1 = 12 V, V7V load
current = 0 A
V7V
V7V LDO output voltage
V7V LDO current limit
5.9
6.1
6.3
V
IOCP_V7V
110
177
235
mA
FEEDBACK VOLTAGE REFERENCE
VFB Feedback voltage
Buck1, Buck2, Buck3
VCOMP = 1.2 V
0.592
0.6
0.608
V
VENXH
VENXL
IENX1
EN1/2/3 high-level input voltage
1.08
1.06
2.3
1.15
1.12
2.9
6
1.22
1.17
3.4
V
EN1/2/3 low-level input voltage
EN1/2/3 pullup current
V
ENx = 1 V
µA
µA
µA
ns
µS
IENX2
EN1/2/3 pullup current
ENx = 1.5 V
5.1
6.8
IENhys
tON_MIN
Gm_EA
hysteresis current
3.1
75
Minimum on time
Iload = 100 mA
120
530
Error amplifier transconductance
COMP1/2/3 voltage to inductor current
174
350
–2 µA < ICOMPX < 2 µA
Gm_PS1/2/3
ILX = 0.5 A
12
A/V
(1)
Gm
ILIMIT1
buck1 peak inductor current limit
buck1 low-side source current limit
buck1 low-side sink current limit
buck2 peak inductor current limit
buck2 low-side source current limit
buck2 low-side sink current limit
buck3 peak inductor current limit
buck3 low-side source current limit
buck3 low-side sink current limit
Overcurrent wait time(1)
6.0
5.3
8.0
7.7
1.4
5.2
4.8
1.2
3.6
3.7
1.2
256
8192
39
9.6
10
A
A
ILIMITSOURCE1
ILIMITSINK1
ILIMIT2
A
3.85
3
6.65
5.5
A
ILIMITSOURCE2
ILIMITSINK2
ILIMIT3
A
A
2.6
2.6
4.45
4.6
A
ILIMITSOURCE3
ILIMITSINK3
tHiccup_wait
tHiccup_re
A
A
cycles
cycles
mΩ
mΩ
mΩ
mΩ
Hiccup time before restart(1)
Rdson_HS1
Rdson_LS1
Rdson_HS2
Rdson_LS2
buck1 high-side switch resistance
buck1 low-side switch resistance
buck2 high-side switch resistance
buck2 low-side switch resistance
PVIN = 12 V
PVIN = 12 V
PVIN = 12 V
PVIN = 12 V
25
52
43
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ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
7.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
70
MAX
UNIT
mΩ
Rdson_HS3
Rdson_LS3
buck3 high-side switch resistance
buck3 low-side switch resistance
PVIN = 12 V
PVIN = 12 V
65
mΩ
PGOOD, MODE, PSM, SEQ_DLY, PG_DLY
FBx undervoltage falling
FBx undervoltage rising
FBx overvoltage rising
FBx overvoltage falling
92.5
95
%VREF
%VREF
Vth_PG
Feedback voltage threshold
107.5
105
%VREF
%VREF
tDEGLITCH(PG)_F
tDEGLITCH(PG)_R
IPG
PGOOD falling edge deglitch time
PGOOD rising edge deglitch time
PGOOD pin leakage
256
cycles
256
cycles
µA
V
0.08
0.25
2.8
VLOW_PG
VMODE_H
VMODE_L
VPG_DLYTH
IPG_DLY
PGOOD pin low voltage
MODE high level input voltage
MODE low level input voltage
PG_DLY threshold
PVIN1 = 12 V, ISINK = 1 mA
2.4
0.11
1.4
2.0
0.7
1.4
2
2.6
0.16
1.5
3.0
0.75
1.5
3
V
0.23
1.6
V
V
PG_DLY pullup current
PG_DLY = 0.5 V
SEQ_DLY = 0.5 V
4.1
µA
V
VSEQ_DLYTH1
VSEQ_DLYTH2
ISEQ_DLY
SEQ_DLY threshold
0.8
SEQ_DLY threshold
1.58
4.1
V
SEQ_DLY pullup current
PSM pin high level input voltage
PSM pin low level input voltage
µA
V
VPSMH
1.3
1
1.4
1.1
1.55
1.2
VPSML
V
OSCILLATOR
FSW
Switching frequency
580
250
80
610
640
kHz
kHz
ns
ROSC = 82.5 kΩ
FSW_range
tSYNC_w
FSYNC_HI
VSYNC_LO
Switching frequency
2300
Clock sync minimum pulse width
Clock sync high threshold
Clock sync low threshold
2
V
0.4
V
THERMAL PROTECTION
TTRIP_OTP
Thermal protection trip point(1)
THYST_OTP
Temperature rising
Hysteresis
160
20
°C
°C
(1) Lab validation result
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ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
7.6 Typical Characteristics
0.606
650
630
610
590
570
0.604
0.602
0.6
0.598
0.596
0.594
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D001
Temperature (èC)
D002
图7-1. Voltage Reference vs Temperature
图7-2. Oscillator Frequency vs Temperature
18
16
14
12
10
8
4
3.9
3.8
3.7
3.6
3.5
3.4
6
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D004
D003
图7-4. Vin UVLO Raising vs Temperature
图7-3. Shutdown Quiescent vs Temperature
3.4
3.3
3.2
3.1
3
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.9
2.8
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D005
D006
图7-5. Vin UVLO Falling vs Temperature
图7-6. EN Pin Pullup Current vs Temperature, EN = 1.0 V
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7.6 Typical Characteristics (continued)
6.6
1.19
1.18
1.17
1.16
1.15
1.14
1.13
1.12
1.11
6.4
6.2
6
5.8
5.6
5.4
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D008
D007
图7-8. EN Pin Threshold Raising vs Temperature
图7-7. EN Pin Pullup Current vs Temperature, EN = 1.5 V
3.4
1.16
3.3
3.2
3.1
3
1.15
1.14
1.13
1.12
1.11
1.1
2.9
2.8
2.7
2.6
1.09
1.08
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D009
D010
图7-9. EN Pin Threshold Falling vs Temperature
图7-10. PG_DLY Pin Pullup Current vs Temperature, PG_DLY =
0.5 V
3.4
3.6
3.3
3
3.3
3.2
3.1
3
2.7
2.4
2.1
1.8
1.5
1.2
2.9
2.8
2.7
2.6
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D011
D012
图7-11. SEQ_DLY Pin Pullup Current vs Temperature, PG_DLY
图7-12. Soft-Start Time vs Temperature
= 0.5 V
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7.6 Typical Characteristics (continued)
9
8.75
8.5
8.25
8
6.2
6
5.8
5.6
5.4
5.2
5
7.75
7.5
7.25
7
4.8
4.6
4.4
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D013
D014
图7-13. Buck1 High-Side Current Limit vs Temperature
图7-14. Buck2 High-Side Current Limit vs Temperature
4.4
4.2
4
140
IOUT = 10 mA
IOUT = 100 mA
120
100
80
60
40
20
3.8
3.6
3.4
3.2
3
2.8
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D016
D015
图7-16. Minimum On Time vs Temperature
图7-15. Buck3 High-Side Current Limit vs Temperature
100%
90%
80%
70%
60%
50%
40%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
30%
PSM Mode, VOUT = 1.2 V
PSM Mode, VOUT = 1.8 V
PWM Mode, VOUT = 1.2 V
PWM Mode, VOUT = 1.8 V
PSM Mode, VOUT = 1.5 V
PSM Mode, VOUT = 3.3 V
PWM Mode, VOUT = 1.5 V
PWM Mode, VOUT = 3.3 V
20%
10%
0
0.01
0.1
Output Current (A)
1
5
0.01
0.1
Output Current (A)
1
3
D017
D018
图7-17. Buck1 Efficiency, VIN = 12 V, Fsw = 610 kHz
图7-18. Buck2 Efficiency, VIN = 12 V, Fsw = 610 kHz
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7.6 Typical Characteristics (continued)
100%
90%
80%
70%
60%
50%
40%
30%
1.22
1.21
1.2
PSM Mode, VIN = 12 V
PWM Mode, VIN = 12 V
1.19
1.18
PSM Mode, VOUT = 1.8 V
20%
10%
0
PSM Mode, VOUT = 3.3 V
PWM Mode, VOUT = 1.8 V
PWM Mode, VOUT = 3.3 V
0.01
0.1
Output Current (A)
1
2
0
1
2 3
Output Current (A)
4
5
D019
D020
图7-19. Buck3 Efficiency, VIN = 12 V, Fsw = 610 kHz
图7-20. Buck1, Load Regulation
1.52
1.82
1.81
1.8
PSM Mode, VIN = 12 V
PWM Mode, VIN = 12 V
PSM Mode, VIN = 12 V
PWM Mode, VIN = 12 V
1.51
1.5
1.79
1.78
1.49
1.48
0
0.2 0.4 0.6 0.8
1
Output Current (A)
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
Output Current (A)
2
2.5
3
D022
D021
图7-22. Buck3, Load Regulation
图7-21. Buck2, Load Regulation
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8 Detailed Description
8.1 Overview
The TPS65265 is a monolithic triple synchronous step-down (buck) converter with 5-A/3-A/2-A output currents. A
wide 4.5-V to 17-V input supply voltage range encompasses most intermediate bus voltages operating off 5-V, 9-
V, 12-V, or 15-V power bus. The feedback voltage reference for each buck is 0.6 V. Each buck is independent
with dedicated enable, soft-start and loop compensation pins.
The TPS65265 implements a constant frequency, peak current mode control that simplifies external loop
compensation. The wide switching frequency of 250 kHz to 2.3 MHz allows optimizing system efficiency, filtering
size and bandwidth. The switching frequency can be adjusted with an external resistor connecting between
ROSC pin and ground. The switching clock is 120° out-of-phase operation from the clocks of buck1, buck2, and
buck3 channels to reduce input current ripple, input capacitor size and power supply induced noise.
The TPS65265 has been designed for safe monotonic startup into pre-biased loads. The default start up is when
VIN is typically 3.8 V. The ENx pin also can be used to adjust the input voltage undervoltage lockout (UVLO) with
an external resistor divider. In addition, the ENx pin has an internal 2.9µA current source, so the EN pin can be
floating for automatically powering up the converters.
The TPS65265 reduces the external component count by integrating the bootstrap circuit. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO circuit
monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the
threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65265 can operate at 100% duty
cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is typically
2.2 V.
The TPS65265 features PGOOD pin to supervise each output voltage of buck converters. The TPS65265 has
power good comparators with hysteresis, which monitor the output voltages through feedback voltages. When all
bucks are in regulation range and power sequence is done, PGOOD is asserted to high after the adjustable
delay time.
The TPS65265 operates in PSM with connecting PSM pin to high or leaving float and operates in force
continuous current mode (FCC) with driving PSM pin to GND.
The TPS65265 is protected from overload and over temperature fault conditions. The converter minimizes
excessive output overvoltage transients by taking advantage of the power good comparator. When the output is
over, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105% of the 0.6V
reference voltage. The TPS65265 implements both high-side MOSFET overload protection and bidirectional low-
side MOSFET overload protections to avoid inductor current runaway. If the overcurrent condition has lasted for
more than the OC wait time (256 clock cycle), the converter will shut down and restart after the hiccup time
(8192 clock cycles). The TPS65265 shuts down if the junction temperature is higher than thermal shutdown trip
point. When the junction temperature drops 20°C typically below the thermal shutdown trip point, the TPS65265
will be restarted under control of the soft start circuit automatically.
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8.2 Functional Block Diagram
ROSC
V7V
V3V
OSC/Phase Shift
V7V LDO
Bias
V7V
VIN
clk
PVIN2
BST2
LX2
V7V
VIN
clk
VIN
en_buck2
enable
PVIN1
BST1
VIN
enable
en_buck1
BST
LX
psm
mode
BUCK2
BST
LX
psm
BUCK1
seq_dly
LX1
mode
PGND2
PGND
Comp
vfb
seq_dly
PGND1
PGND
Comp
vfb
FB2
FB1
COMP1
-
1.5 V
COMP2
3 µA
1 µA
PG_DLY
PGOOD
+
Power
Good
1.4 V
clk
V7V
VIN
PSM
FB1
FB2
FB3
PVIN3
BST3
LX3
en_buck3
enable
VIN
-
0.75 V
BST
LX
psm
mode
BUCK3
+
+
3 µA
mode
psm
seq_dly
SEQ_DLY
PGND3
PGND
Comp
vfb
seq_dly
-
1.5 V
2.6 V
-
State
Machine
FB3
en_buck1
en_buck2
en_buck3
+
MODE
-
COMP3
AGND
+
0.16 V
OT
Over
Temp
2.9 µA
3.1 µA
EN1(EN2, EN3)
6.3 V
1.15 V
2 kꢀ
8.3 Feature Description
8.3.1 Adjusting the Output Voltage
The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. TI
recommends to use 1% tolerance or better resistors.
VOUT
R1
FB
COMP
0.6V
R2
图8-1. Voltage Divider Circuit
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0 .6
œ 0 .6
R 2 = R 1
ì
V
o u t
(1)
To improve efficiency at light loads consider using larger value resistors. If the values are too high, the regulator
is more sensitive to noise. The recommended resistor values are shown in 表8-1.
表8-1. Output Resistor Divider Selection
OUTPUT VOLTAGE
(V)
R1
(kΩ)
R2
(kΩ)
1
10
10
15
10
1.2
1.5
1.8
2.5
3.3
3.3
5
15
10
20
10
31.6
45.3
22.6
73.2
36.5
10
10
4.99
10
5
4.99
8.3.2 Mix PGOOD, PG_DLY Functions
The PGOOD pin is an open drain output and withstands voltage higher to 17 V. After feedback voltage of each
buck is between 95% (rising) and 105% (falling) of the internal voltage reference and PG_DLY pin voltage overs
1.5 V, the PGOOD pin pull-down is deasserted and the pin floats. TI recommends to use a pullup resistor
between the values of 10 kΩ and 100 kΩ to a voltage source that is below 17 V.
The PGOOD pin is pulled low when any feedback voltage of buck is lower than 92.5% (falling), greater than
107.5% (rising) of the nominal internal reference voltage, or PG_DLY pin voltage is below 1.5V (typical). Also,
the PGOOD is pulled low, if the input voltage is under-voltage locked up, thermal shutdown is asserted, the EN
pin is pulled low or the converter is in soft-start period.
Different combinations of PGOOD, PG_DLY can implement different functions.
8.3.2.1 Programmable PGOOD DELAY
An internal 3-µA pullup current source is connected to PG_DLY pin. The PGOOD delay time can be
programmed by connecting a capacitor between PG_DLY pin and ground. The delay time can be calculated as
方程式2.
VP G _ D L Y ì C 1
tp g o o d _ d e la y
=
Ip
(2)
where
• VPG_DLY = 1.5 V
• Ip = 3 µA
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VDD_1.8V
3 µA
PGOOD
PG_DLY
Power
Good
Logic
C1
1.5 V
State Machine
BUCK1,2,3
PG_DLY
PGOOD deglitch time 256 cycles
1.5 V
tpgood_delay = 1.5 V × C1 / 3 µA
PGOOD
图8-2. Power Good Delay Timing Diagram
8.3.2.2 Relay Control
PGOOD pin can implement one buck output’s relay control through an N-MOSFET, circuit as in 图8-3.
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BUCKx
PVIN_12V
Q1
3 µA
R1
C2
PGOOD
PG_DLY
C1
Power
Good
Logic
1.5 V
Relay_BUCKx
State Machine
BUCK1,2,3
PG_DLY
PGOOD deglitch time 256 cycles
1.5 V
tpgood_delay = 1.5 V × C1 / 3 µA
Q1 gate threshold
PGOOD
Determined by R1 and C2
Relay_BUCKx
图8-3. Relay Control Circuit
8.3.3 Enable and Adjusting UVLO
The EN1/2/3 pin provides electrical on/off control of the device. After the EN1/2/3 pin voltage exceeds the
threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the
regulator stops switching and enters low Iq state.
The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If
an application requires controlling the EN pin, use open drain or open collector output logic to interface with the
pin.
The device implements internal UVLO circuitry on the PVIN1 pin. The device is disabled when the PVIN1 pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 600
mV. If an application requires a higher UVLO threshold on the PVIN1, in split-rail applications, then the ENx pin
can be configured as shown in 图 8-4. When using the external UVLO function TI recommends to set the
hysteresis to be greater than 500 mV.
The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih after the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using 方程式3 and 方程式4.
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≈
∆
«
’
÷
◊
VE N F A L L IN G
VE N R IS IN G
V
œ V
S T O P
S T A R T
R 1
=
≈
∆
’
÷
VE N F A L L IN G
I
1 œ
+ I
h
P
VE N R IS IN G
«
◊
(3)
(4)
R 1 ì VE N F A L L IN G
+ R
R 2
=
V
œ
V
I
+ I
h P
S T O P
E N F A L L IN G
1
where
• Ih = 3.1µA
• Ip = 2.9 µA
• VENRISING = 1.15 V
• VENFALLING = 1.12 V
PVIN
ih
R1
R2
ip
EN
图8-4. Adjustable PVIN UVLO, PVIN > 4.5 V
8.3.4 Soft-Start Time
TPS65265 has fixed 2.4-ms (typical) soft-start time.
8.3.5 Power-Up Sequencing
TPS65265 features a comprehensive sequencing circuit for the three bucks. If MODE pin was tied to HIGH or
tied to GND and at the same time EN1 or EN2 (or both) was (were) pulled high, the automatic power-up and
power-down sequence function is active. If MODE pin was left floating, three Buck on/off were separately
controlled by three enable pin.
8.3.5.1 External Power Sequencing
The TPS65265 has dedicated enable pin and soft-start pin for each converter. The converter enable pins are
biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the
converter with an active pulldown transistor on the ENx pin allows for a predictable powerdown timing operation.
The 图 8-5 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx
pin.
A typical 1.4-µA current is charging ENx pin from input supply. When ENx pin voltage rise to typical 0.4 V, the
internal V7V LDO turns on. A 2.9-µA pullup current is sourcing ENx. After ENx pin voltage reaches to ENx
enabling threshold, 3.1-µA hysteresis current sources to the pin to improve noise sensitivity. After soft start time
of 2.4 ms (typical), PGOOD monitor is enabled. If all output voltages are in the regulation and after PGOOD
delay time, PGOOD is asserted.
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VIN
V7V
EN Threshold
EN Threshold
ENx Rise Time
Dictated by CEN
Charge CEN
with 6 µA
ENx
Pre-Bias Startup
PGOOD Delay Time
VOUTx
2.4 ms
t = CENx × (1.2 œ 0.4) V / 2.9 µA
t = CENx × 0.4 V / 1.4 µA
PGOOD
图8-5. Startup Power Sequence
8.3.5.2 Automatic Power Sequencing
The TPS65265 starts with a predefined power-up and power-down sequence when MODE pin ties HIGH or ties
to GND. As shown in 表 8-2, the sequence is determined by the different combinations of EN1 and EN2 status.
EN3 is used to start and stop the converters. 图 8-6 shows the power sequencing when MODE ties to GND,
EN1, and EN2 are tied to HIGH.
An internal 3-µA pullup current source is connected to SEQ_DLY pin. The interval time between bucks can be
programmed by connecting a capacitor between SEQ_DLY pin and ground. The interval time can be calculated
with 方程式5.
V1 ì C 1
t1
=
ip
(5)
(6)
V
œ
V1 ì C
(
)
2
1
t2
=
ip
where
• V1 = 0.75 V
• V2 = 1.5 V
• Ip = 3 µA
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表8-2. Power Sequencing
START
SEQUENCING
SHUTDOWN
SEQUENCING
MODE
Connect to GND
EN1
EN2
EN3
buck1 →buck2 →
buck3 →buck2 →
High
Low
High
High
Low
High
High
Low
High
High
buck3
buck1
buck2 →buck1 →
buck3 →buck1 →
Connect to GND
Connect to GND
buck3
buck2
buck2 →buck3 →
buck1 →buck3 →
Used to start and
stop bucks in
sequence
buck1
buck2
Connect to high or
float
buck1 →buck3 →
buck2 →buck3 →
Automatic
Power
Sequencing
buck2
buck1
Connect to high or
float
buck3 →buck1 →
buck2 →buck1 →
buck2
buck3
Connect to high or
float
buck3 →buck2 →
buck1 →buck2 →
High
Low
Low
Low
Low
Low
buck1
buck3
Connect to GND
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Connect to high or
float
Externally
Controlled
Sequencing
Used to start Used to start
Used to start and
stop buck3
Floating
and stop
buck1
and stop
buck2
x
x
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High or Low
MODE
High or Low
High or Low
EN1
EN2
1.5 V
EN3
State Machine
3uA
SEQ_DLY
C1
0.75 V
Example
MODE(Low)
EN1(High)
EN2(High)
EN3
V2 = 1.5 V
V1 = 0.75 V
SEQ_DLY
t1 = 0.75 V × C1 / 3 µA
Buck1
Buck2
Buck3
t2 = (1.5 V œ 0.75 V) × C1 / 3 µA
t1
t2
t3
t4
t1 = t2 = t3 = t4
图8-6. Automatic Power Sequencing
8.3.6 V7V Low Dropout Regulator and Bootstrap
Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V
pin. The internal built-in low dropout linear regulator (LDO) supplies 6.1 V (typical) from PVIN1 to V7V. A 10-µF
ceramic capacitor must be connected from V7V pin to power ground.
If the input voltage, PVIN1, decreases to UVLO threshold voltage, the UVLO comparator detects V7V pin voltage
and forces the converter off.
Each high-side MOSFET driver is biased from the floating bootstrap capacitor CB, shown in 图 8-7, which is
normally recharged during each cycle through an internal low-side MOSFET or the body diode of low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than PVIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47 nF.
A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended
because of the stable characteristics over temperature and voltage. Each low-side MOSFET driver is powered
from V7V pin directly.
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To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.2 V. When the voltage between BST and LX
drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.
PVIN1
PVINx
LDO
+
–
(VBSTx-VLXx)
+2.2 V
nBootUV
V7V
BSTx
High-side
MOSFET
Vbias
10 µF
CB
UVLO
Bias
Buck Controller
nBootUV
Gate Driver
PWM
LXx
Low-side MOSFET
nBootUV
PWM
BootUV
Protection
Gate Driver
Clk
图8-7. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram
8.3.7 Out of Phase Operation
To reduce input ripple current, three switching clocks are 120° out-of-phase. This enables the system having less
input current ripple to reduce input capacitors’size, cost, and EMI.
8.3.8 Output Overvoltage Protection (OVP)
The device incorporates an output OVP circuit to minimize output voltage overshoot. When the output is
overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin
voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier
demands maximum output current. After the condition is removed, the regulator output rises and the error
amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the
load can respond faster than the error amplifier. This leads to the possibility of an output overshoot. Each buck
compares the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the
high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot.
When the FB voltage drops lower than the OVP threshold, the high-side MOSFET turns on at the next clock
cycle.
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8.3.9 PSM
The TPS65265 can enter high-efficiency PSM operation at light load current when PSM pin connects to high or
leave floating.
When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 180 mA
current typically. Because the integrated current comparator catches the peak inductor current only, the average
load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak
inductor current is clamped at 180 mA.
When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current
comparator turns off the low-side MOSFET when the inductor current reaches zero, preventing it from reversing
and going negative.
Due to the delay in the circuit and current comparator tdly (typical 50 ns at PVIN = 12 V), the real peak inductor
current threshold to turn off high-side power MOSFET must shift higher depending on inductor inductance and
input/output voltages. The threshold of peak inductor current to turn off high-side power MOSFET can be
calculated by 方程式7.
Vin
œ Vo u t
IL P E A K = 1 8 0 m A
+
ì td ly
L
(7)
After the charge accumulated on Vout capacitor is more than loading need, COMP pin voltage drops to low
voltage driven by error amplifier. There is an internal comparator at COMP pin. If comp voltage is lower than 0.35
V, power stage stops switching to save power.
180 mA
Turn off
high-side Power MOSFET
+
œ
Inductor Current
Peak Current
Sensing
Current Comparator
Delay: tdly
x1
IL_Peak
Inductor Peak Current
图8-8. PSM Current Comparator
8.3.10 Slope Compensation
To prevent the sub-harmonic oscillations when the device operates at duty cycles greater than 50%, the device
adds built-in slope compensation, which is a compensating ramp to the switch current signal.
8.3.11 Overcurrent Protection
The device is protected from over current conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
8.3.11.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-
side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference, the high-side switch is turned off.
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8.3.11.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 256 switching cycles shown in 图 8-9, the device will shut down
itself and restart after the hiccup time of 8192 cycles. The hiccup mode helps to reduce the device power
dissipation under severe overcurrent condition.
OCP peak inductor current threshold
OC limiting (waiting) time
256 cycles
Hiccup time
8192 cycles
Soft-start time
2.4-ms typical
Output overloading
iL
Inductor Current
Output hard short circuit
OC fault removed, soft-start, and output recovery
Vout
Output Voltage
图8-9. Overcurrent Protection
8.3.12 Adjustable Switching Frequency
The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching
frequency of the device is adjustable from 250 kHz to 2.3 MHz.
To determine the switching frequency for a given ROSC resistance, use 方程式 8 or the curve in 图 8-10. To
reduce the solution size one must set the switching frequency as high as possible, but tradeoffs of the supply
efficiency and minimum controllable on time must be considered.
ƒosc (kHz) = 30975 × Rosc (kΩ)–0.889
(8)
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2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
20
40
60
80
100
120
140
160
180
200
Oscillator Resistance (kW)
D023
图8-10. Switching Frequency versus ROSC
When an external clock applies to ROSC pin, the internal phase locked loop (PLL) has been implemented to
allow internal clock synchronizing to an external clock between 250 kHz and 2.3 MHz. To implement the clock
synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to
80%. The clock signal amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the
switching cycle is synchronized to the falling edge of ROSC pin.
In applications where both resistor mode and synchronization mode are needed, the device can be configured
as shown in 图 8-11. Before an external clock is present, the device works in resistor mode and ROSC resistor
sets the switching frequency. When an external clock is present, the synchronization mode overrides the resistor
mode. The first time the ROSC pin is pulled above the ROSC high threshold (2.0 V), the device switches from
the resistor mode to the Synchronization mode and the ROSC pin becomes high impedance as the PLL starts to
lock onto the frequency of the external clock. TI does not recommend to switch from the synchronization mode
back to the resistor mode because the internal switching frequency drops to 100 kHz first before returning to the
switching frequency set by ROSC resistor.
Mode
Selection
IC
ROSC
ROSC
图8-11. Works With Resistor Mode and Synchronization Mode
8.3.13 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 140°C
typically.
8.4 Device Functional Modes
8.4.1 Operation With VIN < 4 V (Minimum VIN)
The device operates with input voltages above 4 V. The maximum UVLO voltage is 4 V and will operate at input
voltages above 4 V. The typical UVLO voltage is 3.8 V and the device can operate at input voltages above that
point. The device also can operate at lower input voltages, the minimum UVLO voltage is 3.6V (rising) and 3V
(falling). At input voltages below the UVLO minimum voltage, the devices will not operate.
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8.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.08 V minimum and 1.22 V maximum. With EN held below that
voltage the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When
input voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the
device becomes active. Switching is enabled, and the internal soft-start sequence is initiated as shown in 图 8-7
to 图9-5.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The device is triple synchronous step down dc/dc converter. It is typically used to convert a higher dc voltage to
lower dc voltages with continuous available output current of 5 A/3 A/2 A. .
9.2 Typical Application
The following design procedure can be used to select component values for the TPS65265. This section
presents a simplified discussion of the design process
C15
22pF
C26
82pF
R153
10k
R263
10k
R262
10k
R152 20k
C231
C181
2.7nF
2.7nF
R20
82.5k
C232
22pF
R23
10k
R18
6.8k
C182
22pF
C24
10nF
C17
10nF
R16
0
R25
0
16
25
BST3
BST1
C25
47nF
C16
47nF
VOUT3
1.8V
15
26
27
28
PGND1
PGND1
LX1
PGND3
LX3
L3
4.7µH
Max. 2A
VOUT1
14
13
1.2V
Max. 5A
L1
C152
22µF
C151
22µF
Vin
C12
PVIN3
PVIN2
LX2
2.2uH
C13
10µF
TPS65265
10µF
C261 C262
22µF 22µF
C263
22µF
29
30
12
11
LX1
L2
4.7µH
C101
22µF
C102
22µF
Vin
PVIN1
PVIN1
PSM
C29
22µF
VOUT2
1.5V
Max. 3A
10
9
31
32
PGND2
BST2
C9
47nF
R9
0
0
DNI
R29
R7
6.8k
0
C72
22pF
DNI
C5
R2
10µF
C71
2.7nF
100K
R102 15k
R103
10k
C10
22pF
图9-1. Typical Application Circuit
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9.2.1 Design Requirements
This example details the design of triple synchronous step-down converter. A few parameters must be known to
start the design process. These parameters are typically determined at the system level. For this example, start
with the following known parameters shown in 表9-1.
表9-1. Design Parameters
PARAMETER
VALUE
Vout1
Iout1
Vout2
Iout2
Vout3
Iout3
1.2 V
5 A
1.5 V
3 A
1.8 V
2 A
Transient response 1-A load step
Input voltage
±5%
12-V normal, 4.5 V to 17 V
±1%
Output voltage ripple
Switching frequency
610 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Output Inductor Selection
To calculate the value of the output inductor, use 方程式 9. LIR is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for
the majority of applications.
V
- VOUT
VOUT
VIN max ´ ƒSW
IN max
L =
´
IO ´LIR
(9)
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS and peak inductor current can be found from 方程式11 and 方程式12.
V
- VOUT
´
VOUT
VIN max ´ ƒSW
IN max
Iripple
=
L
(10)
æ
ö2
VOUT ´ V
- VOUT
(
)
IN max
ç
ç
÷
÷
VIN max ´L ´ ƒSW
2
è
ø
ILrms
= IO +
12
(11)
(12)
Iripple
I
Lpeak= IOUT
+
2
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
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9.2.2.2 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator cannot. This situation must occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of droop in the output voltage. 方程式 13 shows the minimum output capacitance necessary to
accomplish this.
2´ DIOUT
CO
=
ƒSW ´ DVOUT
(13)
where
• ΔIout is the change in output current
• ƒsw is the regulators switching frequency
• ΔVout is the allowable change in the output voltage.
方程式14 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
1
1
CO
>
´
VOripple
8 ´ ƒSW
IOripple
(14)
where
• ƒsw is the switching frequency.
• Vripple is the maximum allowable output voltage ripple.
• Iripple is the inductor ripple current.
方程式 15 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
VOripple
<
Resr
IOripple
(15)
Additional capacitance de-ratings for aging, temperature and DC bias must be factored in which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some
capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. 方程式 16 can
be used to calculate the RMS ripple current the output capacitor needs to support.
VOUT ´ V
- VOUT
(
12 ´ VIN max ´L ´ ƒSW
)
IN max
ILrms
=
(16)
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9.2.2.3 Input Capacitor Selection
The TPS65265 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 µF of
effective capacitance on the PVIN input voltage pins. In some applications additional bulk capacitance can also
be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the
input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current
rating greater than the maximum input current ripple of The TPS65265. The input ripple current can be
calculated using 方程式17.
V
IN min ´ VOUT
VOUT
(
)
I
= IOUT
´
´
INrms
V
V
IN min
IN min
(17)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be calculated using 方程式18.
IOUTmax ´0.25
DV
=
IN
CIN ´ ƒSW
(18)
9.2.2.4 Loop Compensation
The TPS65265 incorporates a peak current mode control scheme. The error amplifier is a trans-conductance
amplifier with a gain of 350 µS. A typical type II compensation circuit adequately delivers a phase margin
between 30 and 90 degrees. Cb adds a high frequency pole to attenuate high frequency noise when needed. To
calculate the external compensation components, follow the following steps.
1. Select switching frequency fsw that is appropriate for application depending on L and C sizes, output ripple,
EMI, and so forth. Switching frequency between 600 kHz to 1 MHz gives best trade-off between
performance and cost. To optimize efficiency, lower switching frequency is desired.
2. Set up crossover frequency, ƒc, which is typically between 1/5 and 1/20 of ƒsw.
3. RC can be determined by
2 p ì ƒ c ì Vo ì C o
R C
=
G m
ì Vre f ì G m _ P S
_ E A
(19)
where
• Gm_EA is the error amplifier gain (350 µS).
• Gm_PS is the power stage voltage to current conversion gain (12 A/V).
1
ƒ p
=
C o ì R L ì 2 p
4. Calculate CC by placing a compensation zero at or before the dominant pole (
).
R L ì C o
C c
=
R C
(20)
(21)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
R E S R ì C o
C b
=
R C
6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C1 is calculated from 方程式22.
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1
C 1
=
2 p ì R ì ƒ
1
c
(22)
LX
VOUT
iL
RESR
Current
Sense I/V
Converter
Gm_PS = 12 A / V
RL
Co
C1
R1
Vfb
EA
FB
COMP
Vref = 0.6 V
Gm_EA = 350
Rc
s
Cb
Cc
GND
图9-2. DC-DC Loop Compensation
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9.2.3 Application Curves
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 1.5 V, VOUT3 = 1.8 V FSW = 610 kHz (unless otherwise noted)
图9-3. Buck1, PSM Mode, Soft-Start, Iout = 0 A
图9-4. Buck1, FCC Mode, Soft-Start, Iout = 0 A
图9-5. Buck1, PSM Mode, Soft-Start, Iout = 5 A
图9-6. Buck1, FCC Mode, Soft-Start, Iout = 5 A
图9-7. Buck2, PSM Mode, Soft-Start, Iout = 0 A
图9-8. Buck2, FCC Mode, Soft-Start, Iout = 0 A
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图9-9. Buck2, PSM Mode, Soft-Start, Iout = 3 A
图9-10. Buck2, FCC Mode, Soft-Start, Iout = 3 A
图9-12. Buck3, FCC Mode, Soft-Start, Iout = 0 A
图9-14. Buck3, FCC Mode, Soft-Start, Iout = 2 A
图9-11. Buck3, PSM Mode, Soft-Start, Iout = 0 A
图9-13. Buck3, PSM Mode, Soft-Start, Iout = 2 A
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图9-15. Buck1, PSM Mode, Output Ripple, Light
图9-16. Buck1, FCC Mode, Iout = 0 A
Load
图9-17. Buck1, Output Ripple, Iout = 5 A
图9-18. Buck2, PSM Mode, Output Ripple, Light
Load
图9-19. Buck2, FCC Mode, Iout = 0 A
图9-20. Buck2, Output Ripple, Iout = 3 A
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图9-21. Buck3, PSM Mode, Output Ripple, Light
图9-22. Buck3, FCC Mode, Iout = 0 A
Load
图9-23. Buck3, Output Ripple, Iout = 2 A
图9-24. Buck1, Load Transient, 1.25 A to 2.5 A, SR
0.25 A/µs
图9-25. Buck1, Load Transient, 2.5 A to 3.75 A, SR 图9-26. Buck2, Load Transient, 0.75 A to 1.5 A, SR
0.25 A/µs
0.25 A/µs
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图9-27. Buck2, Load Transient, 1.5 A to 2.25 A, SR
图9-28. Buck3, Load Transient, 0.5 A to 1 A, SR
0.25 A/µs
0.25 A/µs
图9-29. Buck3, Load Transient, 1 A to 1.5 A, SR
图9-30. Buck1, Hiccup and Recovery
0.25 A/µs
图9-31. Buck2, Hiccup and Recovery
图9-32. Buck3, Hiccup and Recovery
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图9-33. Automatic Power Sequencing, MODE =
图9-34. Automatic Power Sequencing, MODE =
LOW, EN1 = HIGH, EN2 = HIGH
LOW, EN1 = LOW, EN2 = HIGH
图9-35. Automatic Power Sequencing, MODE =
图9-36. Automatic Power Sequencing, MODE =
LOW, EN1 = HIGH, EN2 = LOW
HIGH, EN1 = HIGH, EN2 = HIGH
图9-37. Automatic Power Sequencing, MODE =
图9-38. Automatic Power Sequencing, MODE =
HIGH, EN1 = LOW, EN2 = HIGH
HIGH, EN1 = HIGH, EN2 = LOW
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图9-39. 120° Out of Phase for Buck1, Buck2,
图9-40. PGOOD Delay, CPG_DLY = 10 nF
Buck3
9.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4.5 V and 17 V. This input power
supply must be well regulated. If the input supply is located more than a few inches from the TPS65265
converter additional bulk capacitance can be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 47 μF is a typical choice.
9.4 Layout
9.4.1 Layout Guidelines
The TPS65265 can be layout on 2-layer PCB, illustrated 图9-41.
Layout is a critical portion of good power supply design. See 图9-41 for a PCB layout example. The top contains
the main power traces for PVIN, VOUT, and LX. Also on the top layer are connections for the remaining pins of
the TPS65265 and a large top side area filled with ground. The top layer ground area must be connected to the
bottom layer ground using vias at the input bypass capacitor, the output filter capacitor and directly under the
TPS65265 device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer acts
as ground plane connecting analog ground and power ground.
For operation at full rated load, the top-side ground area together with the bottom side ground plane must
provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or
voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power
supplies performance. To help eliminate these problems, the PVIN pin must be bypassed to ground with a low-
ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the
bypass capacitor connections, the PVIN pins, and the ground connections. The PVIN pin must also be bypassed
to ground using a low-ESR ceramic capacitor with X5R or X7R dielectric.
Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground must use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this
conductor length while maintaining adequate width. The small signal components must be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as
possible to the IC and routed with minimal lengths of trace. The additional external components can be placed
approximately as shown.
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9.4.2 Layout Example
VOUT1
VOUT3
BST1
PGND1
PGND1
LX1
BST3
PGND3
LX3
PVIN3
PVIN2
LX2
VIN
LX1
PVIN1
PVIN1
PSM
VIN
PGND2
BST2
VOUT2
TOPSIDE
GROUND
AREA
0.010 in. Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
图9-41. PCB Layout
Copyright © 2023 Texas Instruments Incorporated
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39
Product Folder Links: TPS65265
English Data Sheet: SLVSD86
TPS65265
www.ti.com.cn
ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023
10 Device and Documentation Support
10.1 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSD86
40
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65265RHBR
TPS65265RHBT
ACTIVE
VQFN
VQFN
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TPS
65265
Samples
Samples
ACTIVE
RHB
NIPDAU
TPS
65265
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65265RHBR
TPS65265RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65265RHBR
TPS65265RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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