TPS65631WDSKR [TI]
+4.6V/-1.4V 至 -4.4V 双输出 200mA AMOLED 显示屏电源 | DSK | 10 | -40 to 85;
| 型号： | TPS65631WDSKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +4.6V/-1.4V 至 -4.4V 双输出 200mA AMOLED 显示屏电源 | DSK | 10 | -40 to 85 驱动 光电二极管 接口集成电路 |
| 文件： | 总27页 (文件大小：2173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
TPS65631W 双输出有源矩阵有机发光二极管 (AMOLED) 显示屏电源
1 特性
3 说明
1
•
2.9V 至 4.5V 输入电压范围
4.6V 固定正输出电压
TPS65631W 被设计用于驱动需要正负电源轨的
AMOLED 显示屏。 此器件集成了一个针对 VPOS 的升
压转换器和一个针对 VNEG 的反相降压升压转换器，非
常适合于电池供电类产品。 数字控制引脚 (CTRL) 允
许用数字步长设定负输出电压。 TPS65631W 采用创
新技术，能够实现出色线路瞬态性能。
•
•
•
•
25ºC 至 85ºC 温度范围内，VPOS 精度 0.5%
单独的 VPOS 输出感测引脚
-1.4V 至 -4.4V 的数字可编程负输出电压（缺省值 -
4V）
•
•
•
•
•
支持高达 200mA 的输出电流
出色的线路瞬态稳压
短路保护功能
器件信息(1)
部件号
封装
封装尺寸（标称值）
TPS65631W
QFN (10)
2.50mm x 2.50mm
热关断
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
采用 2.5mm x 2.5mm 10 引脚四方扁平无引线
(QFN) 封装
空白
空白
空白
空白
空白
2 应用范围
AMOLED 显示屏
4 简化电路原理图
L1
4.7 µH
效率与输出电流间的关系
100
90
80
70
60
50
40
30
20
VI
PVIN
AVIN
SWP
OUTP
FBS
2.9 V to 4.5 V
VPOS
4.6 V, 300 mA
C1
2×10 µF
C2
10 µF
TPS65631
EN / Program VNEG
CTRL
VNEG
±4.0 V, 300 mA
OUTN
SWN
C3
2×10 µF
PGND
AGND
L2
4.7 µH
VPOS = 4.6 V
VNEG = –4.0 V
10
VI = 3.7 V
175 200
0
0
25
50
75
100
125
150
Output Current (mA)
G001
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSC27
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
目录
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 10
8.5 Programming........................................................... 11
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
9
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 器件和文档支持 ..................................................... 18
12.1 第三方产品免责声明.............................................. 18
12.2 相关链接................................................................ 18
12.3 商标....................................................................... 18
12.4 静电放电警告......................................................... 18
12.5 术语表 ................................................................... 18
13 机械封装和可订购信息 .......................................... 18
8
5 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2013) to Revision A
Page
•
添加了器件信息表和处理额定值表，特性描述部分，器件功能模式，编程部分，应用和实施部分，电源相关建议部
分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分 ................................................................................ 1
2
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65631W
www.ti.com.cn
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
SON (DSK) PACKAGE
10-PINS
(TOP VIEW)
(BOTTOM VIEW)
SWP
PGND
OUTP
FBS
1
2
3
4
5
10 PVIN
PVIN 10
1
2
3
4
5
SWP
9
8
7
6
AVIN
SWN
OUTN
CTRL
AVIN
SWN
9
8
7
6
PGND
OUTP
FBS
Exposed
Thermal
Pad
Exposed
Thermal
Pad
OUTN
CTRL
AGND
AGND
Pin Functions
NAME
AGND
AVIN
NO.
I/O
—
—
I
DESCRIPTION
5
9
6
Analog ground.
Input supply voltage for internal analog circuits (both converters).
CTRL
Control pin. Combined device enable and inverting buck-boost converter output
voltage programming pin.
FBS
PGND
PVIN
SWN
SWP
4
2
I
Feedback sense pin of the boost converter output voltage.
Power ground of the boost converter.
—
—
O
O
O
O
—
12
8
Input supply voltage pin for the inverting buck-boost converter.
Switch pin of the inverting buck-boost converter.
Switch pin of the boost converter.
1
OUTN
OUTP
7
Rectifier pin of the inverting buck-boost converter.
Rectifier pin of the boost converter.
3
Exposed Thermal
Pad
13
Connect this pad to AGND and PGND.
Copyright © 2013–2014, Texas Instruments Incorporated
3
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
7 Specifications
(1)
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–6
MAX
6
UNIT
V
SWP, OUTP, FBS, PVIN, AVIN
OUTN
–6
V
(2)
Input voltage
SWN
CTRL
6
V
–0.3
–40
5.5
150
V
Operating junction temperature range, TJ
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) With respect to AGND pin.
7.2 Handling Ratings
MIN
MAX
UNIT
TSTG
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
–65
150
°C
–2
2
kV
(1)
all pins
VESD
Electrostatic discharge Charged device model (CDM), per JEDEC specification
–500
–200
500
200
V
V
(2)
JESD22-C101, all pins
Machine model (MM) ESD stress voltage
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process..
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
3.7
MAX UNIT
VI
Input supply voltage range
Output voltage range
2.9
4.5
V
VPOS
VNEG
IPOS
4.6
VO
V
–4.4
0
–4
–1.4
200
200
85
IO
Output current range
mA
°C
INEG
0
TA
TJ
Operating ambient temperature
Operating junction temperature
–40
–40
25
85
125
7.4 Thermal Information
DSK
THERMAL METRIC(1)
UNIT
10 PINS
47.1
57.8
21.1
0.8
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
21.4
4.3
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65631W
www.ti.com.cn
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
7.5 Electrical Characteristics
VI = 3.7 V, V(CTRL) = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
II
Shutdown current into AVIN and
PVIN
CTRL pin connected to ground.
0.1
µA
VI rising.
VI falling.
2.4
2.1
VUVLO
Undervoltage lockout threshold
V
V
BOOST CONVERTER
Output voltage
4.6
VO
25°C ≤ TJ ≤ 85°C, no load
–40°C ≤ TJ < 85°C, no load
I(SWP) = 200 mA
–0.5%
–0.8%
0.5%
0.8%
Output voltage tolerance
Switch (low-side) on-resistance
Rectifier (high-side) on-resistance
Switching frequency
200
350
1.7
1
rDS(ON)
mΩ
I(SWP) = 200 mA
IO = 200 mA
MHz
A
Switch current limit
Inductor valley current
0.8
Short-circuit threshold voltage in
operation
VO falling
4.1
3
V
Short-circuit detection time during
operation
ms
mV
Output sense threshold voltage
using OUTP
V(OUTP) - V(FBS) increasing
300
Output sense threshold voltage
using FBS
V(OUTP) - V(FBS) decreasing
Between FBS pin and ground
200
4
mV
MΩ
Ω
Input resistance of FBS
CTRL pin connected to ground,
IO = 1 mA
Discharge resistance
30
Line regulation
Load regulation
IO = 200 mA
0.002
0.01
%/V
%/A
INVERTING BUCK-BOOST CONVERTER
Output voltage default
–4.0
VO
Output voltage range
–4.4
–1.4
0.05
V
Output voltage tolerance
Switch (high-side) on-resistance
Rectifier (low-side) on-resistance
Switching frequency
–0.05
I(SWN) = 200 mA
I(SWN) = 200 mA
IO = 10 mA
200
300
1.7
rDS(ON)
mΩ
MHz
A
Switch current limit
VI = 2.9 V
1.5
2.2
Short-circuit threshold voltage during
operation
Voltage drop from nominal VO
500
200
10
mV
Short-circuit threshold voltage during
start-up
180
230
Short-circuit detection time during
start-up
tSCP
ms
ms
Ω
Short-circuit detection time during
operation
3
CTRL pin connected to ground,
IO = 1 mA
Discharge resistance
150
Line regulation
Load regulation
IO = 200 mA
0.006
0.31
%/V
%/A
Copyright © 2013–2014, Texas Instruments Incorporated
5
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
Electrical Characteristics (continued)
VI = 3.7 V, V(CTRL) = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CTRL
High-level threshold voltage
Low-level threshold voltage
Pull-down resistance
1.2
V
V
0.4
150
400
300
860
kΩ
OTHER
tINIT
Initialization time
400
80
µs
µs
µs
°C
tOFF
Shut-down time
30
30
tSTORE
TSD
Data storage time
80
Thermal shutdown temperature
145
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
CTRL Interface
tHIGH
tLOW
High-level pulse duration
Low-level pulse duration
2
2
10
10
25
25
µs
µs
6
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65631W
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ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
7.7 Typical Characteristics
At TA = 25°C, unless otherwise noted.
4.0
3.0
0.5
0.4
0.3
0.2
0.1
0.0
2.0
1.0
0.0
−1.0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
G001
G002
Figure 1. Shutdown Current into AVIN and PVIN
Figure 2. Boost Converter Switch rDS(ON)
0.5
0.4
0.3
0.2
0.1
0.0
0.5
0.4
0.3
0.2
0.1
0.0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
G003
G004
Figure 3. Boost Converter Rectifier rDS(ON)
Figure 4. Inverting Buck-Boost Converter Switch rDS(ON)
1.0
0.8
0.6
0.4
0.2
0.0
−50
−25
0
25
50
75
100
125
Junction Temperature (°C)
G005
Figure 5. Inverting Buck-Boost Converter Rectifier rDS(ON)
Copyright © 2013–2014, Texas Instruments Incorporated
7
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS65631W consists of a boost converter and an inverting buck boost converter. The VPOS output is fixed at
4.6 V and VNEG output is programmable via a digital interface in the range of -1.4 V ~ -4.4 V, the default is -4 V.
The transition time of VNEG output is adjustable by the CT pin capacitor.
8.2 Functional Block Diagram
SWP
OUTP
1
3
Short-Circuit
Protection
DCHG
Gate
Driver
FBS
Output Sense
Control
PGND
4
±
PWM
Control
AVIN
+
9
VREF
Oscillator
CTRL
Digital
Interface
6
+
DAC
6
±
Constant
Off-Time
Controller
Short-Circuit
Protection
Gate Driver
PVIN
OUTN
VI
10
7
8
2
5
SWN
PGND
AGND
8.3 Feature Description
8.3.1 Boost Converter
The boost converter uses a fixed-frequency current-mode topology, and its output voltage (VPOS) is fixed at 4.6 V
For the highest output voltage accuracy, connect the output sense pin (FBS) directly to the positive pin of the
output capacitor. If not used, the FBS pin can be left floating or connected to ground. If the FBS pin is not used,
the boost converter senses its output voltage using the OUTP pin.
8.3.2 Inverting Buck-Boost Converter
The inverting buck-boost converter uses a constant-off-time peak-current mode topology. The converter's default
output voltage (VNEG) is –4 V, but it can be programmed to any voltage in the range –1.4 V to –4.4 V (see
Programming VNEG).
8
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65631W
www.ti.com.cn
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
Feature Description (continued)
8.3.3 Soft-Start and Start-Up Sequence
The TPS65631W features a soft-start function to limit inrush current. When the device is enabled by a high-level
signal applied to the CTRL pin, the boost converter starts switching with a reduced switch current limit. Ten
milliseconds after the CTRL pin goes high, the inverting buck-boost converter starts with a default value of –4 V.
A typical start-up sequence is shown in Figure 6.
CTRL
VPOS
10 ms (typ.)
VNEG
Figure 6. Typical Start-Up Sequence
8.3.4 Enable (CTRL)
The CTRL pin serves two functions. One is to enable and disable the device, and the other is to program the
output voltage (VNEG) of the inverting buck-boost converter (see Programming VNEG). If the digital interface is not
required, the CTRL pin can be used as a standard enable pin for the device, which will come up with its default
value on VNEG of –4 V. When CTRL is pulled high, the device is enabled. The device is shut down with CTRL
low.
8.3.5 Undervoltage Lockout
The TPS65631W features an undervoltage lockout function that disables the device when the input supply
voltage is too low for normal operation.
8.3.6 Short Circuit Protection
The TPS65631W is protected against short-circuits of VPOS and VNEG to ground and to each other.
8.3.6.1 Short-Circuits During Normal Operation
During normal operation an error condition is detected if VPOS falls below 4.1 V for more than 3 ms or VNEG is
pulled above the programmed nominal output by 500 mV for longer than 3 ms. In either case the device enters
shutdown mode: the converters are disabled and their outputs are disconnected from the input. To resume
normal operation either cycle the input supply voltage or toggle the CTRL pin low and then high again.
8.3.6.2 Short-Circuits During Start-Up
During start up an error condition is detected if:
•
•
•
VPOS is not in regulation 10 ms after a high-level is applied to the CTRL pin.
VNEG is higher than threshold level 10 ms after a high-level is applied to the CTRL pin.
VNEG is not in regulation 20 ms after a high-level is applied to the CTRL pin.
To resume normal operation either cycle the input supply voltage or toggle the CTRL pin low and then high
again.
8.3.7 Output Discharge During Shutdown
The TPS65631W actively discharges its outputs during shutdown. Figure 7 shows the output discharge control.
Copyright © 2013–2014, Texas Instruments Incorporated
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TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
Feature Description (continued)
VI
CTRL
VPOS
tVUVLO
tVUVLO
Discharge
Discharge
Discharge
Discharge
Discharge
Discharge
VNEG
t10 ms (typ.)
t10 ms (typ.)
Figure 7. Active Discharge of VPOS and VNEG During Shutdown
8.3.8 Thermal Shutdown
The TPS65631W enters thermal shutdown mode if its junction temperature exceeds 145°C (typical). During
thermal shutdown mode none of the device functions are available. To resume normal operation, either cycle the
input supply voltage or toggle the CTRL pin low and then high again.
8.4 Device Functional Modes
8.4.1 Operation with VI < 2.9 V
The recommended minimum input supply voltage for full performance is 2.9 V. The device continues to operate
with input supply voltages below 2.9 V; however, full performance is not guaranteed. The device does not
operate with input supply voltages below the UVLO threshold.
8.4.2 Operation with VI ≈ VPOS (Diode Mode)
The TPS65631W features a "diode" mode that enables it to regulate its output voltage even when the input
supply voltage is close to VPOS (that is, too high for normal boost operation). When operating in diode mode the
converter's high-side switch stops switching and its body diode is used as the rectifier. Boost converter efficiency
is reduced when operating in diode mode. At low output currents (≈2 mA and below), the boost converter
automatically transitions from pulse-width modulation to pulse-skip mode. This ensures that VPOS stays in
regulation but increases the output voltage ripple on VPOS
.
8.4.3 Operation with CTRL
When a low-level signal is applied to the CTRL pin the device is disabled and switching is inhibited. When the
input supply voltage is above the UVLO threshold and a high-level signal is applied to the CTRL pin the device is
enabled and its start-up sequence begins.
10
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65631W
www.ti.com.cn
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
8.5 Programming
8.5.1 Programming VNEG
The output voltage of the inverting buck-boost converter (VNEG) can be programmed using the CTRL pin. If
output voltage programming is not required, the CTRL pin can be used as a standard enable pin (see Enable
(CTRL)).
ttINIT
tLOW
t
ttHIGH
ttSTORE
ttOFF
CTRL
VPOS
VNEG
4.6 V
ttSCP
t
ttSET
±4.0 V
±4.2 V
Figure 8. Programming VNEG Using the CTRL Pin
When the CTRL pin is pulled high, the inverting buck-boost converter starts up with its default voltage of –4V.
The device now counts the rising edges applied to the CTRL pin and sets the output voltage (VNEG) according to
Table 1. For the timing diagram shown in Figure 8, VNEG is programmed to –4.2 V, since three rising edges are
detected.
The CTRL interface is designed to work with pulses whose duration is between 2 µs and 25 µs. Pulses shorter
than 2 µs or longer than 25 µs are not ensured to be recognized.
Table 1. Programming Table for VNEG
Number of Rising Edges
VNEG
Number of Rising Edges
VNEG
0 / no pulses
–4 V
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
–2.9 V
–2.8 V
–2.7 V
–2.6 V
–2.5 V
–2.4 V
–2.3 V
–2.2 V
–2.1 V
–2.0 V
–1.9 V
–1.8 V
–1.7 V
–1.6 V
–1.5 V
–1.4 V
1
2
–4.4 V
–4.3 V
–4.2 V
–4.1 V
–4.0 V
–3.9 V
–3.8 V
–3.7 V
–3.6 V
–3.5 V
–3.4 V
–3.3 V
–3.2 V
–3.1 V
–3.0 V
3
4
5
6
7
8
9
10
11
12
13
14
15
Copyright © 2013–2014, Texas Instruments Incorporated
11
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 9 shows a typical application circuit suitable for supplying AMOLED displays in smartphone applications.
The circuit is designed to operate from a single-cell Li-Ion battery and generates a positive output voltage VPOS of
4.6 V and a negative output voltage of –4 V. Both outputs are capable of supplying up to 300 mA of output
current.
9.2 Typical Application
L1
4.7 µH
VI
PVIN
AVIN
SWP
OUTP
FBS
2.9 V to 4.5 V
VPOS
4.6 V, 300 mA
C1
2×10 µF
C2
10 µF
TPS65631
EN / Program VNEG
CTRL
VNEG
±4.0 V, 300 mA
OUTN
SWN
C3
2×10 µF
PGND
AGND
L2
4.7 µH
Figure 9. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the following input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE
2.9 V to 4.5 V
VPOS = 4.6V, VNEG = –4 V
9.2.2 Detailed Design Procedure
In order to maximize performance, the TPS65631W has been optimized for use with a relatively narrow range of
component values, and customers are strongly recommended to use the application circuit shown in Figure 9
with the components listed in Table 3 and Table 4.
12
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TPS65631W
www.ti.com.cn
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
9.2.2.1 Inductor Selection
The boost converter and inverting buck-boost converter have been optimized for use with 10 µH inductors, and it
is recommended that this value be used in all applications. Customers using other values of inductor are strongly
recommended to characterize circuit performance on a case-by-case basis.
Table 3. Inductor Selection(1)
PARAMETER
VALUE
MANUFACTURER
Toko
PART NUMBER
DFE252012C-100M
LPP252012-100M
MDKK2020T-100M
L1, L2
10 µH
ABCO
Taiyo Yuden
(1) See Third-Party Products Disclaimer
9.2.2.2 Capacitor Selection
The recommended capacitor values are shown in Table 4. Applications using less than the recommended
capacitance (e.g. to save PCB area) may experience increased voltage ripple. In general, the lower the output
power, the lower the necessary capacitance.
Table 4. Capacitor Selection(1)
PARAMETER
VALUE
2 × 10 µF
10 µF
MANUFACTURER
Murata
PART NUMBER
C1
C2
C3
C4
GRM21BR71A106KE51
GRM21BR71A106KE51
GRM21BR71A106KE51
GRM21BR71E104KA01
Murata
2 × 10 µF
100 nF
Murata
Murata
(1) See Third-Party Products Disclaimer
9.2.2.3 Stability
Applications using component values that differ significantly from those recommended in Table 3 and Table 4
should be checked for stability over the full range of operating conditions.
Copyright © 2013–2014, Texas Instruments Incorporated
13
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
9.2.3 Application Curves
The performance shown in the following graphs was obtained using the circuit shown in Figure 9 and the
external components shown in Table 3 and Table 4. The output voltage settings for these measurements were
VPOS = 4.6 V and VNEG = –4 V.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VI = 2.9 V
VI = 3.7 V
VI = 4.3 V
VI = 2.9 V
VI = 3.7 V
VI = 4.3 V
VPOS = 4.6 V
VNEG = –4.0 V
VPOS = 4.6 V
VNEG = –4.0 V
0
25
50
75
100
125
150
175
200
1
10
100
200
Output Current (mA)
Output Current (mA)
G001
G002
Figure 10. Efficiency vs. Output Current
Figure 11. Efficiency vs. Output Current (Log Scale)
VPOS
10mV/div
CTRL
5V/div
SWP
5V/div
VPOS
2V/div
VNEG
2V/div
IINDUCTOR
100mA/div
IIN
200mA/div
2 ms/div
400 ns/div
Figure 12. Start-Up Waveforms
Figure 13. VPOS Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 100 mA)
VNEG
20mV/div
VPOS
10mV/div
SWP
5V/div
SWN
5V/div
IINDUCTOR
100mA/div
IINDUCTOR
200mA/div
400 ns/div
400 ns/div
Figure 15. VNEG Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 100 mA)
Figure 14. VPOS Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 200 mA)
14
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65631W
www.ti.com.cn
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
4.65
4.64
4.63
4.62
4.61
4.60
4.59
4.58
4.57
4.56
4.55
VNEG
20mV/div
SWN
5V/div
IINDUCTOR
200mA/div
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
IO = 100 mA
3.1 3.3
400 ns/div
2.9
3.5
3.7
3.9
4.1
4.3 4.5
Input Voltage (V)
G007
Figure 16. VNEG Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 200 mA)
Figure 17. Boost Converter Line Regulation
−3.95
4.65
−3.96
−3.97
−3.98
−3.99
−4.00
−4.01
−4.02
−4.03
−4.04
−4.05
4.64
4.63
4.62
4.61
4.60
4.59
4.58
4.57
4.56
4.55
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
IO = 100 mA
3.1 3.3
VI = 3.7 V
25
2.9
3.5
3.7
3.9
4.1
4.3
4.5
0
50
75
100
125
150
175
200
Input Voltage (V)
Output Current (mA)
G008
G009
Figure 18. Inverting Buck-Boost Converter Line Regulation
Figure 19. Boost Converter Load Regulation
−3.95
−3.96
−3.97
−3.98
−3.99
−4.00
−4.01
−4.02
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
−4.03
−4.04
−4.05
VI = 3.7 V
25
0
50
75
100
125
150
175
200
Output Current (mA)
G010
Figure 21. Line Transient Response
Figure 20. Inverting Buck-Boost Converter Load
Regulation
Copyright © 2013–2014, Texas Instruments Incorporated
15
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
Figure 22. Boost Converter Load Transient Response
Figure 23. Inverting Buck-Boost Converter Load Transient
Response
10 Power Supply Recommendations
The TPS65631W is designed to operate from an input voltage supply range between 2.9 V and 4.5 V. If the input
supply is located more than a few centimeters from the TPS65631W additional bulk capacitance may be
required. The 2×10 µF shown in the schematics in this data sheet are a typical choice for this function.
16
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65631W
www.ti.com.cn
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
11 Layout
11.1 Layout Guidelines
No PCB layout is perfect and compromises are always necessary. However, following the basic principles listed
below (in order of importance) should go a long way to achieving good performance:
•
Route switching currents on the top layer using short, wide traces. Do not route these signals through vias,
which have relatively high parasitic inductance and resistance.
•
Use a copper pour on layer 2 as a ground plane and thermal spreader, and connect the thermal pad to it
using a number of thermal vias.
•
•
•
•
•
•
•
Place C1 as close as possible to pin 10.
Place C2 as close as possible to pins 2 and 3.
Place C3 as close as possible to pin 7.
Place L1 as close as possible to pin 1.
Place L2 as close as possible to pin 10.
Use the thermal pad to join AGND and PGND.
Connect the FBS pin directly to the positive pin of C2, that is, keep this connection separate from the
connection between OUTP and C2.
Figure 24 illustrates how a PCB layout following the above principles may be realized in practice.
11.2 Layout Example
Figure 24 shows the above principles implemented for the circuit of Figure 9.
L1
C1
SWP
PGND
OUTP
FBS
1
2
3
4
5
10 PVIN
C2
9
8
7
6
AVIN
SWN
OUTN
L2
C3
AGND
CTRL
Via to signal layer on internal or bottom layer.
Thermal via to copper pour on internal or bottom layer.
Figure 24. PCB Layout Example
版权 © 2013–2014, Texas Instruments Incorporated
17
TPS65631W
ZHCSCV3A –JULY 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
12 器件和文档支持
12.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 5. 相关链接
部件
产品文件夹
请单击此处
样片与购买
请单击此处
技术文档
工具与软件
请单击此处
支持与社区
请单击此处
TPS65631W
请单击此处
12.3 商标
All trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
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都遵循在订单确认时所提供的TI 销售条款与条件。
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用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
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Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65631WDSKR
ACTIVE
SON
DSK
10
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SJN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65631WDSKR
SON
DSK
10
3000
180.0
8.4
2.8
2.8
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DSK 10
SPQ
Length (mm) Width (mm) Height (mm)
182.0 182.0 20.0
TPS65631WDSKR
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSK 10
2.5 x 2.5 mm, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225304/A
PACKAGE OUTLINE
DSK0010A
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
2.6
2.4
A
B
PIN 1 INDEX AREA
2.6
2.4
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
EXPOSED
THERMAL PAD
1.2 0.1
6
5
1
2X
2
11
2
0.1
10
8X 0.5
0.3
10X
0.45
0.35
0.2
0.1
0.05
10X
PIN 1 ID
(OPTIONAL)
C A B
C
4218903/B 10/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSK0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.6)
(1.2)
10
1
10X (0.25)
SYMM
(2)
11
8X (0.5)
(0.75)
(R0.05) TYP
5
6
(0.35)
(
0.2) VIA
TYP
SYMM
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218903/B 10/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DSK0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.6)
SYMM
1
10
METAL
TYP
10X (0.25)
SYMM
11
8X (0.5)
(0.89)
6
(R0.05) TYP
5
(1.13)
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218903/B 10/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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