TPS65632RTET [TI]

三路输出 AMOLED 显示电源 | RTE | 16 | -40 to 85;


型号：	TPS65632RTET
厂家：	TEXAS INSTRUMENTS
描述：	三路输出 AMOLED 显示电源 \| RTE \| 16 \| -40 to 85 驱动接口集成电路
文件：	总27页 (文件大小：1671K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS65632

ZHCSDG2 –MARCH 2015

TPS65632 三路输出 AMOLED 显示屏电源

1 特性

(WQFN) 封装

•

2.9V 至 4.5V 输入电压范围

升压转换器 1 (V_POS

2 应用范围

)

AMOLED 显示屏

–

4.6V 输出电压

0.5% 精度（25°C 至 85°C）

专用输出感测引脚

3 说明

TPS65632 设计用于驱动需要 3 个电源

300mA 输出电流

轨（V_POS、V_NEG和 AV_DD）的有源矩阵有机发光二极

管 (AMOLED) 显示屏。该器件分别为 V_POS、V_NEG和

AV_DD集成了升压转换器、反向降压-升压转换器以及升

压转换器，这些转换器均适用于电池供电产品。数字

控制引脚 (CTRL) 允许用数字步长设定负输出电压。

TPS65632 采用全新技术，可提供出色的线路与负载

调节性能。

•

反向降压-升压转换器 (V_NEG)

–

–1.5V 至 5.4V 可编程输出电压

–4V 默认输出电压

300mA 输出电流

升压转换器 2 (AV_DD

)

–

5.8V 或 7.7V 输出电压

30mA 输出电流

器件信息⁽¹⁾

•

出色的线路瞬态稳压

器件型号

封装

封装尺寸（标称值）

短路保护功能

TPS65632

WQFN (16)

3.00mm x 3.00mm

热关断

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

3mm × 3mm 16 引脚超薄型四方扁平无引线

4 简化电路原理图

4.7 µH

效率与输出电流间的关系

V_I

100

PVIN

AVIN

SWP1

2.9 V to 4.5 V

AV_DD

V_POS& V_NEG

V_POS

4.6 V / 300 mA

OUTP1

FBS

3×10 µF

100 nF

10 µF

TPS65632

10 µH

V_NEG

±4.0 V / 300 mA

SWP2

OUTN

2×10 µF

Enable AV_DD

Enable / Program V_NEG

CTRL

AV_DD

7.7 V / 30 mA

OUTP2

10 µF

SELP2

AGND

PGND1

PGND2

4.7 µH

SWN

V_POS= 4.6 V,V_NEG= –4.0 V,AV_DD= 7.7 V

100 nF

10m

100m

300m

Output Current (A)

G000

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLVSCY2

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

8.2 Functional Block Diagram ......................................... 8

8.3 Feature Description................................................... 9

8.4 Device Functional Modes........................................ 12

Application and Implementation ........................ 13

9.1 Application Information............................................ 13

9.2 Typical Application ................................................. 13

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements................................................ 6

7.7 Typical Characteristics.............................................. 7

Detailed Description .............................................. 8

8.1 Overview ................................................................... 8

10 Power Supply Recommendations ..................... 19

11 Layout................................................................... 19

11.1 Layout Guidelines ................................................. 19

11.2 Layout Example .................................................... 19

12 器件和文档支持 ..................................................... 20

12.1 器件支持................................................................ 20

12.2 商标....................................................................... 20

12.3 静电放电警告......................................................... 20

12.4 术语表 ................................................................... 20

13 机械、封装和可订购信息....................................... 20

5 修订历史记录

日期

修订版本

注释

2015 年 3 月

最初发布版本

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

6 Pin Configuration and Functions

RTE Package

16-Pin WQFN with Thermal Pad

Top View

SWP1

PGND1

OUTP1

FBS

12 PVIN

11 SWN

Exposed

Thermal

Pad

10 OUTN

CTRL

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

AGND

AVIN

NO.

GND

PWR

Analog ground.

Supply voltage for the device.

A capacitor connected between this pin and ground sets the transition time for V_NEG

when programmed to a new value.

I/O

CTRL

Boost converter 1 (V_POS) inverting buck-boost converter (V_NEG) enable/program.

Boost converter 2 (AV_DD) enable.

FBS

Boost converter 1 (V_POS) sense input.

OUTN

OUTP

OUTP2

PGND1

PGND2

PVIN

Inverting buck-boost converter output (V_NEG).

Boost converter 1 output (V_POS).

Boost converter 2 output (AV_DD).

GND

PWR

Boost converter 1 power ground.

Boost converter 2 power ground.

Inverting buck-boost converter power stage supply voltage.

Boost converter 2 output voltage selection pin. AV_DD= 7.7 V when SELP2 = low and

5.8 V when SELP2 = high.

SELP2

SWN

I/O

Inverting buck-boost converter switch pin.

Boost converter 1 switch pin.

SWP1

SWP2

Boost converter 2 switch pin.

Exposed thermal pad

—

Connect this pad to AGND, PGND1 and PGND2.

(1) GND = Ground, PWR = Power, I = Input, O = Output, I/O = Input/Output

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–6.0

–6.5

–0.3

–40

MAX

UNIT

SWP1, OUTP1, FBS, PVIN, AVIN

SWP2

OUTP2

8.5

0.3

4.8

5.5

3.6

150

Input supply voltage⁽²⁾

OUTN

SWN

CTRL, EN, SELP2

Operating virtual junction, T_J

Storage temperature, T_stg

°C

–65

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) With respect to GND pin.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

INPUT

V_I

Input supply voltage range

2.9

3.7

4.5

T_J

Operating junction temperature

–40

125

°C

7.4 Thermal Information

RTE [WQFN]

16 PINS

42.9

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

14.2

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JB

14.1

R_θJC(bot)

3.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

7.5 Electrical Characteristics

V_I= 3.7 V, CTRL = 3.7 V, EN = 3.7 V, V_POS= 4.6 V, V_NEG= –4.0 V, AV_DD= 7.7 V, T_J= –40°C to 85°C, typical values are at T_J

= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY CURRENT AND THERMAL PROTECTION

V_I

Input voltage range

Shutdown current

2.9

3.7

4.5

CTRL = GND, EN = GND, sum of current flowing into

AVIN and PVIN

I_SD

0.25

µA

V_Ifalling

V_Irising

1.8

2.1

2.5

V_UVLO

Under-voltage lockout threshold

BOOST CONVERTER 1 (V_POS

)

Positive output 1 voltage

4.6

V_POS

25°C ≤ T_A≤ 85°C, No load

–30°C ≤ T_A≤ 85°C, No load

–0.5%

–0.8%

0.5%

0.8%

Positive output 1 voltage

variation

r_DS(on)1ASwitch on-resistance

r_DS(on)1BRectifier on-resistance

200

350

1.7

mΩ

MHz

I_(SWP1)= 200 mA

f_SW1

Switching frequency

Switch current limit

I_POS= 200mA

I_SW1

Inductor valley current

V_POSfalling

0.8

1.4

V_SCP1

Short-circuit threshold in

operation

3.95

4.10

4.28

t_SCP1

Short-circuit detection time in

operation

V_(OUTP1)– V_(FBS)increasing

V_(OUTP1)– V_(FBS)decreasing

200

100

300

200

550

450

MΩ

V_T

Output voltage sense threshold

FBS pin pull-down resistance

R_(FBS)

R_DCHG1Discharge resistance

Line regulation

CTRL = GND, I_(SWP1)= 1mA

I_POS= 200mA

0.01

0.007

%/V

%/A

Load regulation

1 mA ≤ I_POS≤ 300 mA

INVERTING BUCK-BOOST CONVERTER (V_NEG

)

Output voltage default

–4.0

Output voltage range

V_NEG

–1.4

–50

–60

–5.4

25°C ≤ T_A≤ 85°C, no load

–30°C ≤ T_A≤ 85°C, no load

Output voltage accuracy

r_DS(on)2ASWN MOSFET on-resistance

200

300

mΩ

I_(SWN)= 200 mA

SWN MOSFET rectifier on-

r_DS(on)2B

resistance

f_SW2

I_SW2

SWN Switching frequency

SWN switch current limit

I_NEG= 10 mA

1.7

2.2

MHz

V_I= 2.9 V

1.5

300

180

700

230

Short circuit threshold in

operation

Voltage increase from nominal V_NEG

500

200

V_SCP2

Short circuit threshold in start up

Short circuit detection time in

start up

t_SCP2

Short circuit detection time in

operation

R_DCHG2Discharge resistance

Line regulation

CTRL = GND, I_(SWN)= 1 mA

I_NEG= 200 mA

130

150

0.004

0.1

170

%/V

%/A

Load regulation

BOOST CONVERTER 2 (AV_DD

)

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

Electrical Characteristics (continued)

V_I= 3.7 V, CTRL = 3.7 V, EN = 3.7 V, V_POS= 4.6 V, V_NEG= –4.0 V, AV_DD= 7.7 V, T_J= –40°C to 85°C, typical values are at T_J

= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

7.7

MAX UNIT

SELP2 = Low

SELP2 = High

Output voltage

5.8

AV_DD

25°C ≤ T_A≤ 85°C, no load

–30°C ≤ T_A≤ 85°C, no load

–1%

Output voltage accuracy

–1.3%

1.3%

r_DS(on)3ASWP2 switch on-resistance

r_DS(on)3BSWP2 rectifier on-resistance

400

650

1.7

I_(SWP2)= 200 mA

mΩ

f_SW3

I_LIM3

Switching frequency

Switch current limit

I_AVDD= 0 mA

MHz

Inductor valley current

EN = GND, I_(SWP2)= 1 mA

I_AVDD= 30 mA

0.25

0.35

0.45

R_DCHG3Discharge resistance

Line regulation

0.02

0.18

%/V

%/mA

Load regulation

CTRL INTERFACE (CTRL, EN, SELP2)

V_IH

Logic input high level voltage

Logic input low level voltage

Pull-down resistance

1.2

150

V_IL

0.4

400

860

kΩ

OTHER

R_CT

t_INIT

t_STORE

t_SDN

T_SD

CT pin resistance

300

500

400

kΩ

µs

°C

Initialization time

Data storage/accept time period

Shutdown time period

Thermal shutdown temperature Temperature rising

145

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

CTRL INTERFACE

t_LOW

t_HIGH

t_OFF

Low-level pulse duration

µs

High-level pulse duration

Shutdown pulse duration (CTRL = low)

200

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

7.7 Typical Characteristics

T_J= 25°C, V_I= 3.7 V, unless otherwise stated.

600

500

400

300

200

100

0.1

0.01

0.001

Low−Side

High−Side

−50

−25

100

125

−50

−25

100

125

Temperature (°C)

Junction Temperature (°C)

G000

Figure 1. Shutdown Current into AVIN and PVIN Pins

Figure 2. Boost Converter 1 (V_POS) r_DS(ON)

600

1000

900

800

700

600

500

400

300

200

100

500

400

300

200

100

Low−Side

High−Side

Low−Side

High−Side

−50

−25

100 125

−50

−25

100 125

Junction Temperature (°C)

G000

Figure 3. Inverting Buck-Boost Converter (V_NEG) r_DS(ON)

Figure 4. Boost Converter 2 (AV_DD) r_DS(ON)

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPS65632 consists of two boost converters and an inverting buck-boost converter. The V_POSoutput is fixed

at 4.6 V and V_NEGis programmable via a digital interface in the range of –1.4 V to –5.4 V; the default is –4 V.

AV_DDcan be selected between 7.7 V and 5.8 V, using the SELP2 pin. The transition time of V_NEGoutput is

adjustable by the CT pin capacitor.

8.2 Functional Block Diagram

V_I

SWP2

AVIN

SWP1

OUTP2

OUTP1

AV_DD

V_POS

Short-Circuit

Protection

Gate Driver

PGND2

PGND1

Output Sense

Control

FBS

SELP2

AVIN

SWP2

AVIN

SWP1

PWM

Control

PWM

Control

V_REF

Oscillator

CTRL

Digital

Interface

DAC

Control

Short-Circuit

Protection

Constant

Off-Time

Controller

50 mV

Gate Driver

PVIN

OUTN

V_I

V_NEG

AGND

SWN

PGND1

PGND2

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

8.3 Feature Description

8.3.1 Boost Converter 1 (V_POS

)

Boost converter 1 uses a fixed-frequency current-mode topology. Its output voltage (V_POS) is programmed at the

factory to 4.6 V and cannot be changed by the user.

For highest output voltage accuracy, connect the output sense pin (FBS) directly to the positive terminal of the

main output capacitor. If not used, the FBS pin can be left floating or connected to ground, in which case the

boost converter senses the output voltage via the OUTP1 pin.

8.3.1.1 V_(POS)Boost Output Sense (FBS Pin)

V_(POS)boost has a dedicated output sense pin (FBS). If FBS is floating or connected to ground, V_(POS)boost

senses the output through OUTP1 pin.

8.3.2 Inverting Buck-Boost Converter (V_NEG

)

The inverting buck-boost converter uses a constant-off-time current-mode topology. The converter's default

output voltage (V_NEG) is –4.0 V, but it can be programmed from –1.4 V to –5.4 V (see Programming V_NEG).

8.3.2.1 Programming V_NEG

The digital interface allows programming of V_NEGin discrete steps. If the output voltage setting function is not

required then the CTRL pin can also be used as a standard enable pin. The digital output voltage programming

of V_NEGis implemented using a simple digital interface with the timing shown in Figure 5.

tt_INIT

t_LOW

tt_HIGH

tt_STORE

tt_SDN

tt_OFF

CTRL

V_POS

V_NEG

4.6 V

tt_SCP2

tt_SET

±5.2 V

±4.0 V

Figure 5. Digital Interface Using CTRL

When CTRL is pulled high the device starts up with its default voltage of –4 V. The device includes a 6-bit DAC

that generates the output voltages shown in Table 1. The interface counts the rising edges applied to the CTRL

pin once the device is enabled. According toTable 1, V_NEGis programmed to –5.2 V since 3 rising edges are

detected.

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

Feature Description (continued)

Table 1.

Bit / Rising Edges

V_NEG

DAC Value

Bit / Rising Edges

V_NEG

DAC Value

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

0 / no pulse

–4.0 V

–5.4 V

–5.3 V

–5.2 V

–5.1 V

–5.0 V

–4.9 V

–4.8 V

–4.7 V

–4.6 V

–4.5 V

–4.4 V

–4.3 V

–4.2 V

–4.1 V

–4.0 V

–3.9 V

–3.8 V

–3.7 V

–3.6 V

–3.5 V

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

–3.4 V

–3.3 V

–3.2 V

–3.1 V

–3.0 V

–2.9 V

–2.8 V

–2.7 V

–2.6 V

–2.5 V

–2.4 V

–2.3 V

–2.2 V

–2.1 V

–2.0 V

–1.9 V

–1.8 V

–1.7 V

–1.6 V

–1.5 V

–1.4 V

8.3.2.2 Controlling V_NEGTransition Time

The transition time (t_SET) is the time required to move V_NEGfrom one voltage level to the next. Users can control

the transition time with a capacitor connected between the CT pin and ground. When the CT pin is left open or

connected to ground the transition time is as short as possible. When a capacitor is connected to the CT pin the

transition time is determined by the time constant (τ) of the external capacitor (C_(CT)) and the internal resistance

of the CT pin (R_CT). The output voltage reaches 70% of its programmed value after 1τ.

An example is given when using 100 nF for C_(CT)

τ = 300 kΩ × 100 nF = 30 ms

(1)

The output voltage is at 70% of its final value after 1τ (i.e. 30 ms in this case) and at its final value after

approximately 3τ (90 ms in this case).

8.3.3 Boost Converter 2 (AV_DD

)

Boost converter 2 uses a fixed-frequency current-mode topology. The TPS65632 device supports fixed output

voltages of 5.8 V and 7.7 V, selected by the SELP2 pin. AV_DD= 7.7 V when SELP2 is low or left floating, and

AV_DD= 5.8 V when SELP2 is high.

8.3.4 Soft Start and Start-Up Sequence

The devices feature a soft-start function to limit inrush current. Boost converter 2 (AV_DD) is enabled when EN

goes high. When CTRL goes high, boost converter 1 starts with a reduced switch current limit and 10 ms later

the inverting buck-boost converter (V_NEG) starts with its default value of –4 V. The typical start-up sequence is

shown in Figure 6. The two boost converters operate independently and boost converter 1 (V_POS) does not

require boost converter 2 (AV_DD) to be in regulation in order for it to start..

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

CTRL

AV_DD

V_POS

10 ms (typ.)

V_NEG

Figure 6. Start-Up Sequence

8.3.5 Enable (CTRL)

The CTRL pin serves two functions: one is to enable and disable the device, and the other is to program the

output voltage (V_NEG) of the inverting buck-boost converter (see Programming V_NEG). If the V_NEGprogramming

function is not required the CTRL pin can be used as a standard enable pin for the device, which will start up

with its default value of –4.0 V on V_NEG. The device is enabled when CTRL is pulled high and disabled when

CTRL is pulled low.

Note that to ensure proper start up CTRL must be pulled low for a minimum of 200 µs before being pulled high

again.

8.3.6 Undervoltage Lockout

The device features an undervoltage lockout function that disables it when the input supply voltage is too low for

proper operation.

8.3.7 Short-Circuit Protection

8.3.7.1 Short Circuits During Operation

The device is protected against short circuits of V_POSand V_NEGto ground and short circuit of these two outputs to

each other. During normal operation an error condition is detected if V_POSfalls below 4.1 V for longer than 3 ms

or V_NEGis pulled above the programmed nominal output by 500 mV for longer than 3 ms. In either case the

device goes into shutdown and the outputs are disconnected from the input. This state is latched, and to resume

normal operation, V_Ihas to cycle below the undervoltage lockout threshold, or CTRL has to toggle LOW and then

HIGH.

8.3.7.2 Short Circuits During Start Up

During start up an error condition is detected in the following cases:

•

V_POSis not in regulation 10 ms after CTRL goes HIGH

V_NEGis higher than threshold level 10 ms after CTRL goes HIGH

V_NEGis not in regulation 20 ms after CTRL goes HIGH

whitespace

If any of the above conditions is met the device goes into shutdown and the outputs are disconnected from the

input. This state is latched, and to resume normal operation V_Ihas to cycle below the undervoltage threshold, or

CTRL has to toggle LOW and HIGH.

8.3.8 Output Discharge During Shut Down

The device discharges outputs during shutdown. Figure 7 shows the discharge control.

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

V_IN

tV_UVLO

CTRL

Discharge

AV_DD

V_POS

Discharge

V_NEG

t10 ms (typ.)

Figure 7. Outputs Discharge During Shut Down

8.3.9 Thermal Shutdown

The TPS65632 device enters thermal shutdown if its junction temperature exceeds 145°C (typical). During

thermal shutdown none of the device's functions are available. To resume normal operation V_Ihas to cycle below

the undervoltage threshold, or CTRL has to toggle LOW and then HIGH.

8.4 Device Functional Modes

8.4.1 Operation with V_I< 2.9 V

The recommended minimum input supply voltage for full-performance is 2.9 V. The device continues to operate

with input supply voltages below 2.9 V, however, full performance is not guaranteed. The TPS65632 device does

not operate with input supply voltages below the UVLO threshold.

8.4.2 Operation with V_I≈ V_POS(Diode Mode)

The TPS65632 device features a "diode" mode that enables it to regulate its V_POSoutput even when the input

supply voltage is close to V_POS(that is, too high for normal boost operation). When operating in diode mode the

V_POSboost converter's high-side switch is disabled and its body diode used as the rectifier. Note that a minimum

load of ≈2 mA is required to proper output regulation in diode mode.

8.4.3 Operation with CTRL

When a low-level signal is applied to the CTRL pin the device is disabled and switching is inhibited. When the

input supply voltage is above the UVLO threshold and a high-level signal is applied to the CTRL pin the device is

enabled and its start-up sequence begins.

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS65632 device is intended to supply the main analog supplies required by AMOLED displays. V_POSis

fixed at 4.6 V, but V_NEGcan be programmed using the CTRL pin to voltages in the range –1.4 V to –5.4 V. The

SELP2 pin can be used to set AV_DDto either 5.8 V or 7.7 V. The device is highly integrated and requires few

external components.

9.2 Typical Application

Figure 8 shows a typical application circuit suitable for supplying AMOLED displays in smartphone applications.

The circuit is designed to operate from a single-cell Li-Ion battery and generates a positive output voltage V_POSof

4.6 V, a negative output voltage V_NEGof –4.0 V, and a positive output voltage AV_DDof 5.8 V or 7.7 V. The V_POS

and V_NEGoutputs are each capable of supplying up to 300 mA of current, and the AV_DDoutput of up to 30 mA.

4.7 µF

V_I

PVIN

AVIN

SWP1

2.9 V to 4.5 V

V_POS

4.6 V / 300 mA

3 × 10 µF

OUTP1

FBS

100 nF

10 µF

TPS65632

10 µH

V_NEG

±4.0 V / 300 mA

SWP2

OUTN

2×10 µF

Enable AV_DD

Enable / Program V_NEG

AV_DDSelect

CTRL

SELP2

AV_DD

5.8 V, 7.7 V / 30 mA

OUTP2

4.7 µH

10 µF

AGND

PGND1

PGND2

SWN

100 nF

Figure 8. Typical Application Circuit

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

Typical Application (continued)

9.2.1 Design Requirements

For this design example, use the parameters shown in Table 2

Table 2. Design Parameters

PARAMETER

VALUE

Input voltage range

2.9 V to 4.5 V

V_POS= 4.6 V

V_NEG= –4.0 V

AV_DD= 7.7 V

Output voltage

Current

I_(VPOS)= 300 mA

I_(VNEG)= 300 mA

I_(AVDD)= 30 mA

f_(SWP1)= 1.7 MHz

f_(SWN)= 1.7 MHz

f_(SWP2)= 1.7 MHz

Switching Frequency

9.2.2 Detailed Design Procedure

In order to maximize performance, the TPS65632 device has been optimized for use with a relatively narrow

range of component values, and customers are strongly recommended to use the application circuits shown in

Figure 8 with the components listed in Table 3 and Table 4.

9.2.2.1 Inductor Selection

The V_POSand V_NEGconverters have been optimized for use with 4.7-µH inductors and the AV_DDboost converter

has been optimized for use with 10-µH inductors. For optimum performance it is recommended that these values

be used in all applications. Customers using different inductors than the ones in Table 3 are strongly

recommended to characterize circuit performance fully before finalizing their design. Customers should pay

particular attention to the inductors' saturation current and ensure it is adequate for their application's worst-case

conditions (which may also be during start-up).

Table 3. Inductor Selection

REFERENCE

DESIGNATOR

VALUE

MANUFACTURER

PART NUMBER

L1, L3

4.7 µH

10 µH

Coilcraft

XFL4020-4R7ML

Coilmaster

MMPP252012-100N

9.2.2.2 Capacitor Selection

The recommended capacitor values are shown in Table 4. Applications using less than the recommended

capacitance (e.g. to save PCB area) may exhibit increased voltage ripple. In general, the lower the output

current, the lower the necessary capacitance. Customers should be aware that ceramic capacitors of the kind

typically used with the TPS65632 device exhibit dc bias effects, which means their effective capacitance under

normal operating conditions may be significantly lower than their nominal capacitance value. Customers must

ensure that the effective capacitance is sufficient for their application's performance requirements.

Table 4. Capacitor Selection

REFERENCE

DESIGNATOR

VALUE

MANUFACTURER

PART NUMBER

3 × 10 µF

10 µF

Murata

GRM21BR71A106KE51

GRM155B11A104KA01

C2, C6

2 × 10 µF

100 nF

C4, C5

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

9.2.3 Application Curves

Unless otherwise stated: T_A= 25°C, V_I= 3.7 V, V_POS= 4.6 V, V_NEG= –4.0 V, AV_DD= 7.7 V; L1 = L3 = XFL4020-

4R7ML, and L2 = MMPP252012-100N.

100

V_I= 2.9 V

V_I= 3.7 V

V_I= 4.3 V

V_I= 2.9 V

V_I= 3.7 V

V_I= 4.3 V

50m

100m

150m

200m

250m

300m

10m

15m

20m

25m

30m

Output Current (A)

G000

Figure 9. V_POSand V_NEGCombined Efficiency

Figure 10. AV_DDEfficiency

4.62

4.61

4.60

4.59

4.58

4.57

4.56

4.55

−3.98

−3.99

−4.00

−4.01

−4.02

−4.03

−4.04

−4.05

−4.06

I_O= 10 mA

I_O= 100 mA

I_O= 300 mA

I_NEG= 10 mA

I_NEG= 100 mA

I_NEG= 300 mA

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

Input Voltage (V)

G000

Figure 11. V_POSLine Regulation

Figure 12. V_NEGLine Regulation

7.76

7.75

7.74

7.73

7.72

7.71

7.70

4.62

4.61

4.60

4.59

4.58

4.57

4.56

4.55

I_O= 10 mA

I_O= 40 mA

I_O= 80 mA

V_I= 2.9 V

V_I= 3.7 V

V_I= 4.3 V

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

50m

100m

150m

200m

250m

300m

Input Voltage (V)

Output Current (A)

G000

Figure 13. AV_DDLine Regulation

Figure 14. V_POSLoad Regulation

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

−3.98

−3.99

−4.00

−4.01

−4.02

−4.03

−4.04

−4.05

−4.06

7.76

7.75

7.74

7.73

7.72

7.71

7.70

V_I= 2.9 V

V_I= 3.7 V

V_I= 4.3 V

V_I= 2.9 V

V_I= 3.7 V

V_I= 4.3 V

50m

100m

150m

200m

250m

300m

10m

15m

20m

25m

30m

Output Current (A)

G000

Figure 15. V_NEGLoad Regulation

Figure 16. AV_DDLoad Regulation

5 V/div

2 V/div

5 V/div

200 mA /div

2 ms/div

Figure 18. Start-Up: AV_DD

Figure 17. Start-Up: V_POSand V_NEG

10 mV/div

5 V/div

200 mA /div

500 ns/div

I_POS= 100 mA

I_POS= 300 mA

Figure 19. Switch Pin, Inductor Current and Output

Voltage Waveforms: V_POS

Figure 20. Switch Pin, Inductor Current and Output

Voltage Waveforms: V_POS

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

10 mV/div

5 V/div

500 mA /div

500 ns/div

I_NEG= 100 mA

I_NEG= 300 mA

Figure 21. Switch Pin, Inductor Current and Output

Voltage Waveforms: V_NEG

Figure 22. Switch Pin, Inductor Current and Output

Voltage Waveforms: V_NEG

10 mV/div

5 V/div

200 mA /div

500 ns/div

I_AVDD= 10 mA

I_AVDD= 30 mA

Figure 23. Switch Pin, Inductor Current and Output

Voltage Waveforms: AV_DD

Figure 24. Switch Pin, Inductor Current and Output

Voltage Waveforms: AV_DD

V_I= 3.0 V to 4.2 V in 50 µs

I_POS= 100 mA

V_I= 3.0 V to 4.2 V in 50 µs

I_NEG= 100 mA

Figure 25. V_POSLine Transient Response

Figure 26. V_NEGLine Transient Response

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

V_I= 3.0 V to 4.2 V in 50 µs

I_AVDD= 30 mA

I_POS= 10 mA to 100 mA in 100 ns

Figure 27. AV_DDLine Transient Response

Figure 28. V_POSLoad Transient Response

I_NEG= 10 mA to 100 mA in 100 ns

I_AVDD= 10 mA to 30 mA in 100 ns

Figure 29. V_NEGLoad Transient Response

Figure 30. AV_DDLoad Transient Response

2.0

1.9

1.8

1.7

1.6

1.5

(SWP1)

(SWN)

(SWP2)

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

Input Voltage (V)

G000

I_POS= 100 mA

I_NEG= 100 mA

I_AVDD= 30 mA

Figure 31. Switching Frequency

TPS65632

www.ti.com.cn

ZHCSDG2 –MARCH 2015

10 Power Supply Recommendations

The TPS65632 device is designed to operate with input supply voltages in the range 2.9 V to 4.5 V. If the input

supply voltage is located more than a few centimeters away from the device, additional bulk capacitance may be

required. The three 10-µF capacitors shown in Figure 8 are suitable for typical applications.

11 Layout

11.1 Layout Guidelines

•

Place the input capacitor on PVIN and the output capacitor on OUTN as close as possible to device. Use

short and wide traces to connect the input capacitor on PVIN and the output capacitor on OUTN.

•

Place the output capacitor on OUTP1 and OUTP2 as close as possible to device. Use short and wide traces

to connect the output capacitor on OUTP1 and OUTP2.

•

Connect the ground of CT capacitor with AGND, pin 7, directly.

Connect input ground and output ground on the same board layer, not through via hole.

Connect AGND, PGND1 and PGND2 with exposed thermal pad.

11.2 Layout Example

V_IN

GND

C1c

AV_DD

C1b

C1a

SWP1

12 PVIN

GND

V_POS

PGND1

OUTP1

FBS

11 SWN

10 OUTN

C3a

C3b

CTRL

Via to GND plane on layer 2

Via to other layer

Figure 32. Recommended PCB Layout

TPS65632

ZHCSDG2 –MARCH 2015

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 商标

12.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

11-Aug-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS65632RTER

TPS65632RTET

ACTIVE

WQFN

RTE

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 85

PC6I

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Aug-2022

Addendum-Page 2

GENERIC PACKAGE VIEW

RTE 16

3 x 3, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225944/A

www.ti.com

PACKAGE OUTLINE

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

SIDE WALL

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

1.68 0.07

(DIM A) TYP

EXPOSED

THERMAL PAD

12X 0.5

SYMM

1.5

0.30

16X

0.18

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

16X

4219117/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.68)

SYMM

16X (0.6)

16X (0.24)

SYMM

(2.8)

(0.58)

TYP

12X (0.5)

(

0.2) TYP

VIA

(R0.05)

ALL PAD CORNERS

(0.58) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219117/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.55)

16X (0.6)

16X (0.24)

SYMM

(2.8)

12X (0.5)

METAL

ALL AROUND

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4219117/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS65632RTET [TI]

相关型号：

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TPS65642YFF

TPS65642YFFR

TPS65642YFFT

TPS65651-1/2/3

TPS65653-Q1

TPS6565342RHDRQ1

TPS6565342RHDTQ1