TPS65640_技术文档

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

LCD Bias With Digital VCOM Buffer for Notebook PCs and Tablet PCs

Check for Samples: TPS65640

1

FEATURES

DESCRIPTION

The TPS65640 is a compact LCD bias solution

primarily intended for use in notebook and tablet PCs.

The device comprises two boost converters to supply

the LCD panel’s source driver and gate driver or level

shifter; one buck converters or a LDO regulator

alternatively to supply the time controller logic

voltages; a linear negative voltage regulator to supply

gate off voltage or provide negative voltage for

source driver; a programmable VCOM generator with

one high-speed amplifier; a gate voltage shaping

function and two high speed operational amplifiers.

•

2.5-V to 5.5-V Input Voltage Range

3.6 to 12.7 V Boost Converter (AV_DD

)

15 to 37 V Boost Converter with Temperature

Compensation (V_GH

–8 V to –3.8 V Linear Negative Voltage

Regulator (V_GLor NAV_DD

)

•

)

1.5-V to 3-V Alternative Buck Converter or Low

Dropout Regulator (V₂₅)

7 bits Programmable V_COMCalibrator With One

Integrated Buffer Amplifiers

All the regulators and V_COMvoltage outputs are

programmed through I²C interface and stored in the

TPS65640 integrated E²PROM. The TPS65640 is

available in 5.5-mm × 3.5-mm, 28-lead QFN package.

0.8 V to 5.1 V Programmable V_COMVoltage

Output for Full AV_DDApplication

–4.1 V to 0.2 V Programmable V_COMVoltage

Output for Positive and Negative AV_DD

Application

V_IN

Boost Converter1

AV_DD

•

Two Operational Amplifiers

Gate Voltage Shaping

Negative Charge

Pump Regulator

V_GL

Buck Converter

LDO Regulator

Programmable V_GHand V_COMTemperature

Compensation

V₂₅

•

T_CONReset Signal Generator With

Programmable Delay

V₂₅

Reset Generator

RST

V_GH

•

I²C Interface for E²PROM Programming

AV_DD

Boost Converter2

Operational Amplifier1

Operational Amplifier2

Thermal Shutdown

V_OUTA

V_OUTB

V_COM

V_GHM

Supports GIP and Non-GIP Displays

28 Pins, 5.5-mm × 3.5-mm 0.5-mm Pitch QFN

7

Programmable

V_COM+ Buffers

APPLICATIONS

•

Notebook PCs

Tablet PCs

V_GH

Gate Voltage Shaping

I²C Interface

2

I C

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

T_A

ORDERING

PACKAGE

PACKAGE MARKING

–40°C to 85°C

TPS65640

5.5-mm x 3.5-mm 28-pin QFN

PZXI

(1) The device is supplied taped and reeled, with 3000 devices per reel.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

7

VIN, V25, V25_LX, RESET, COMP, SCL, SDA, VFLK, VT

VIN (100ms) Pulse

–0.3

–5

V

12

AVDD, LX

Pin Voltage⁽²⁾

20

V

VCOM_OUT, INA+, INA–, OUTA, INB+, INB–, OUTB

5

V

VGH_LX, VGH, VGHM, RE

DRVN, VGL, NAVDD

Human Body Model

–0.3

–12

40

V

0.3

2000

200

700

85

V

ESD Rating⁽³⁾

Machine Model

V

Charged Device Model

Ambient temperature

Junction temperature

Storage temperature

V

T_A

–40

–65

°C

T_J

150

T_STG

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TPS65640

THERMAL METRIC⁽¹⁾

RHR

28 PINS

37.4

26.3

8.3

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

θ_JCtop

θ_JB

°C/W

ψ_JT

0.2

ψ_JB

8.1

θ_JCbot

1.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

2

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

V_IN

Input voltage range

2.5

5.5

V

BOOST CONVERTER 1

AV_DD

I_AVDD

L₁

Boost converter 1 output voltage range

3.6

11

400

10

V

Boost converter 1 output current when 5.5 V ≥ VIN ≥ 2.5 V

Boost converter #1 inductor range

mA

µH

µF

4.7

10

C_OUT1

Boost converter #1 output capacitance

BOOST CONVERTER 2

AV_DD

V_GH

I_GH

Input voltage range

3.6

15

11⁽¹⁾

37

V

Output voltage range

Output current

15

10

2.2

10

40

mA

µH

µF

kΩ

L₄

Inductor

4.7

1

10

C_OUT4

R_NTC

Output capacitance

Thermistor resistance at 25 °C

BUCK CONVERTER (V₂₅

)

V₂₅

I₂₅

Output voltage

1.5

3

V

Output current

Inductor

600

10

mA

µH

µF

L₂

2.2

4.7

10

C_OUT2

Output capacitance

22

LDO Regulator (V₂₅

)

V₂₅

Output voltage

1.5

1

3

V

I₂₅

Output current

350

mA

µF

C_OUT2

Output capacitance

4.7

(1) V_GH– AV_DDmust be greater than 6 volts.

ELECTRICAL CHARACTERISTICS

V_IN= 3.3 V; V₂₅= 2.5 V, AV_DD= 8.5 V, V_GH= 23 V, V_GL= –6 V, R_CAMP=200kΩ, C_CAMP=1 nF, NAV_DD= AGND = PGND = 0V,

T_A= –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

I_IN

Supply current into VIN

Supply current into AVDD

Supply current into VGH

Converters not switching

2

5

3

8.5

1

mA

No load on op-amp outputs

No load on V_GHM

0.1

UNDER VOLTAGE LOCKOUT

V_INrising

2.3

2.35

2.2

2.4

Undervoltage lockout threshold

V_UVLO

V_INfalling T_A= 25°C

V_INrising – V_INfalling

2.05

2.25

V

Hysteresis

BOOST CONVERTER 1 (AV_DD

0.15

)

Output voltage range

Tolerance

3.6

11

AV_DD

V_UVP1

–2%

2%

% of

AV_DD

Undervoltage threshold

AV_DDfalling

75

80

85

T_{DLY_UVP1}

V_SCP1

160

30

15

10

0.2

1

ms

%

V

Short circuit threshold

Over Voltage threshold

Switch leakage current

Switch ON resistance

AV_DDfalling

25

35

16

V_OVP1

AV_DDrising

14.5

I_LK1

AV_DD= 13.5 V

20

µA

Ω

r_DS(ON)1

I_LX= 1 A

0.3

1.2

2.4

AVDD ILIM = 0, T_A= 25 °C

AVDD ILIM = 1, T_A= 25 °C

0.8

1.6

I_LIM1

AVDD switch current limit

A

2

Submit Documentation Feedback

3

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.3 V; V₂₅= 2.5 V, AV_DD= 8.5 V, V_GH= 23 V, V_GL= –6 V, R_CAMP=200kΩ, C_CAMP=1 nF, NAV_DD= AGND = PGND = 0V,

T_A= –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

80%

480

600

720

800

TYP

MAX

UNIT

D_MAX1

Maximum Duty Cycle

FREQ1 = 01

FREQ1 = 00, T_A= 25°C

FREQ1 = 01, T_A= 25°C

FREQ1 = 10, T_A= 25°C

FREQ1 = 11, T_A= 25°C

600

750

720

900

f_SW1

Oscillator frequency

kHz

900

1080

1200

1000

Line regulation,

V_LIR=ΔAV_DD/(AV_DD×ΔV_IN

V_LIR1

V_IN= 2.5 V to 5.5 V, A_VDD= 8.5 V, T_A= 25 °C

±0.1

±0.15

%/V

%/A

)

Load regulation,

V_LOR=(AV_{DD_20mA}–AV_{DD_200mA})/AV_{DD_}

V_LOR1

V_IN= 3.3 V, AV_DD= 8.5 V, I_AVDD= 20 mA to 200 mA

1

20mA

SS1 = 00

20

40

SS1 = 01

V_SS1

AV_DDsoft stat duration

ms

SS1 = 10

60

SS1 = 11

80

LX1TS = 00

LX1TS = 01

LX1TS = 10

LX1TS = 11

0.5

0.7

0.9

1.1

T_f1

AV_DDswitch ON voltage slew rate

V/ns

BUCK CONVERTER (V_25Buck

)

Output voltage

V_25Buck

1.5

–2%

0.8

3

V

Tolerance

(V₂₅-V_{25_setting})/V_{25_seeting}

V₂₅falling

2%

1.2

Undervoltage threshold

Hysteresis

1

0.1

160

1.2

4

V_UVP2

V₂₅rising

T_{DLY_UVP2}

I_LIM2

ms

A

Switch current limit

Soft start duration

I_SW2Aramps from 0 A to 2 A

1

1.4

T_SS2

ms

r_DS(ON)2A

r_DS(ON)2B

f_SW2

High-side, I_SW2A= I_LIM2

250

100

1250

450

200

Switch ON resistance

mΩ

Low-side, I_SW2B= 1 A

Switching frequency

V_IN= 3.3 V; V₂₅= 2.5 V, I₂₅= 200 mA

1000

1500

kHz

%/V

Line regulation, V_LIR= ΔV₂₅

/

V_LIR2

V_IN= 2.5 V to 5.5 V

±0.1

1%

±0.15

(AV₂₅×ΔV_IN

)

V_LOR2

Load regulation

V_IN= 3.3 V, I₂₅= 1 mA to 400 mA

LINEAR REGULATOR (V_25LDO

)

Output voltage

1.5

–2.5%

0.8

3.0

2.5%

1.2

V_25LDO

V

Tolerance

Undervoltage threshold

Hysteresis

V25 falling

V25 rising

1

V_UVP3

0.1

160

300

T_{DLY_UVP3}

V_DO3

ms

Dropout voltage

I₂₅= 350 mA, V₂₅= –3%

500

mV

Line regulation, V_LIR= ΔV₂₅

/

V_LIR3

V_IN= 2.8 V to 5.5 V, I₂₅= 100 mA

V_IN= 3.3 V, I₂₅= 1 mA to 300 mA

0.1

1

±0.15

%/V

%/A

(V₂₅×ΔV_IN

)

V_LOR3

Load regulation

BOOST CONVERTER 2 (V_GH

)

Output voltage range

Tolerance

15

–3%

38

37

3%

40

V_GH

V

V_OVP4

V_UVP4

Overvoltage threshold

Undervoltage threshold

T_A= 25 °C

V_GHfalling

39

80

V

75

85

% of V_GH

Undervoltage protection shutdown

delay

T_{DLY_UVP4}

I_LK4

160

10

ms

µA

Switch leakage current

Switching off V_{VGH_LX}= 38 V

20

4

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.3 V; V₂₅= 2.5 V, AV_DD= 8.5 V, V_GH= 23 V, V_GL= –6 V, R_CAMP=200kΩ, C_CAMP=1 nF, NAV_DD= AGND = PGND = 0V,

T_A= –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

300

600

TYP

400

800

0.5

1.2

4

MAX

500

1000

1

UNIT

FREQ4 = 0

FREQ4 = 1

I_{VGH_LX}= 1 A

f_SW4

VGH swithching frequency

kHz

r_DS(ON)4

I_LIM4

VGH switch ON resistance

VGH switch current limit

Ω

0.9

1.5

A

SS4 = 00

SS4 = 01

SS4 = 10

SS4 = 11

8

T_SS4

VGH soft start duration

ms

12

16

D_MAX4

I_VT

88%

90%

40

Thermistor reference current

Line regulation

V_VT= 1 V

µA

V_LIR4

V_LOR4

AV_DD= 3.6 V to 11 V

I_GH= 5 mA to 40 mA

±0.1

1

±0.15

%/V

%/A

Load regulation

PROGRAMMABLE V_COMCALIBRATOR

V_S+– V_S–

V_COM

VCOM buffer supply voltage

15

6

V

V_COMvoltage accuracy,

V_COM–V_{COM_setting}

I_OUT= 0 mA

–6

LSB

AV_DD= 8.5 V, NAV_DD= 0 V, V_{COM_OUT}= AV_DD/ 2,

I_SOURCE= 1mA to 20mA

1

2

AV_DD= 5 V, NAV_DD= –5 V, V_{COM_OUT}= 0 V,

I_SOURCE= 1 mA to 20 mA

Load regulation

V/A

mA

AV_DD= 8.5 V, NAV_DD= 0 V, V_{COM_OUT}= AV_DD/ 2,

I_SINK= –1 mA to –20 mA

1

AV_DD= 5 V, NAV_DD= –5 V, V_{COM_OUT}= 0 V,

I_SINK= –1 mA to –20 mA

1

AV_DD= 5 V, V_{COM_OUT}= AVDD,

NAV_DD= –5 V

–200

200

I_SC2

Short circuit current

AV_DD= 5 V,

V_{COM_OUT}= NAV_DD= –5 V

SR₂

Slew rate

V_{COM_OUT}= AV_DD/ 2 + 1 V

12

V/µs

MHz

BW₂

Small signal 3dB bandwidth

V_{COM_OUT}= AV_DD/ 2, V_SIGNAL= 60 mV_PP, no load

OPERATIONAL AMPLIFIER 1 and 2 (AV_DD= 5 V, NAV_DD= –5 V, R_L= 10 kΩ, C_L= 10 pF, T_A= 25°C)

V_IO1

Input offset voltage

V_CM= (AV_DD+ NAV_DD) / 2

T_A= –40°C to 85°C

–15

15

3

mV

μV/°C

GΩ

pF

ΔV_IO/Δ_T

R_IN1

Average offset voltage drift

Input impedance

5

1

C_IN1

Input capacitance

1.35

V_CM1

A_VOL1

PSRR₁

CMRR₁

V_OL1

Input common mode voltage range

Open loop gain

AV_DD= 5 V, NAV_DD= –5 V

V_CM= (AV_DD+ NAV_DD) / 2

I_L= 5 mA

–4

75

60

50

V

95

70

dB

V

Power supply rejection ratio

Common mode rejection ration

Output swing low

80

4.85

–485

±35

4.92

V_OH1

Output swing High

I_L= –5 mA

–4.92

±120

V

I_OC1

Continuous output current

mA

V_IN+= (AV_DD+ NAV_DD) / 2, V_IN–= (AV_DD+ NAV_DD) / 2 ±1 V,

open-loop

I_PK1

Peak output current

mA

tS

Setting to ±0.1%

Slew rate

A_V= –1, V_IN–= (AV_DD+ NAV_DD) / 2 ±1 V

500

12

5

ns

V/µs

SR₁

BW₁

PM

A_V= –1, V_IN–= (AV_DD+ NAV_DD) / 2 ±1 V

Small signal 3 dB bandwidth

Phase margin

A_V= –1, V_CM= (AV_DD+ NAV_DD) / 2, V_SIGNAL= 60 mV_PP

MHz

50

Degree

A_V= –1, V_CM= (AV_DD+ NAV_DD) / 2, V_SIGNAL= 60 mV_PP, f =

5 MHz

CS

Channel Separation

75

dB

GATE OFF REGULATION CONTROLLER (V_GL

)

Submit Documentation Feedback

5

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.3 V; V₂₅= 2.5 V, AV_DD= 8.5 V, V_GH= 23 V, V_GL= –6 V, R_CAMP=200kΩ, C_CAMP=1 nF, NAV_DD= AGND = PGND = 0V,

T_A= –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

–3.8

–3%

1

TYP

MAX

-8

UNIT

Output voltage

Tolerance

V_GL

V_GLvoltage regulate accuracy

V

3%

6

I_DRVN

V_LIR5

DRVN source current

Line regulation

4

1

mA

mV

I_DRVN= 1 mA, V_IN= 2.5 V to 5.5 V

6

GATE VOLTAGE SHAPING

r_DS(ON)H

r_DS(ON)L

V_IH

VGH to VGHM ON resistance

V_GH= 24 V, I_GHM= 10 mA, V_FLK= 2.5 V

V_GHM= 24 V, I_GHM= 10 mA, V_FLK= 0 V

V_FLKrising

13

25

Ω

V

VGHM to RE ON resistance

High-level input voltage

Low-level input voltage

1.5

V_IL

V_FLKfalling

0.6

V_GHMrising, 2.5 V, 50% thresholds, C_OUT= 150 pF, R_E= 0

mΩ

t_PLH

t_PHL

100

200

Propagation delay

ns

V_GHMfalling, 2.5 V, 50% thresholds, C_OUT= 150 pF, R_E= 0

mΩ

200

DLY = 00

DLY = 01

DLY = 10

DLY = 11

0

20

40

60

Gate voltage shaping / LCD bias

ready delay range

t_DLY

ms

T_CONRESET GENERATOR

VDIV = 000

VDIV = 001

VDIV = 010

VDIV = 011

VDIV = 100

VDIV = 101

VDIV = 110

VDIV = 111

1.08

1.26

1.44

1.62

1.8

1.2

1.4

1.6

1.8

2

1.32

1.54

1.76

1.98

2.2

V_DIV

Detecting voltage falling threshold

V

1.98

2.16

2.34

2.2

2.4

2.6

150

2.42

2.64

2.86

Hysteresis

mV

V

V_OL(RST)

I_LK(RST)

Output voltage

Leakage current

I_RST= 1 mA (sinking)

V_RST= 2.5 V

RESET = 0000

…

0.5

1

µA

0

(1)

t_RESET

Reset delay time

…

30

ms

°C

RESET = 1111

THERMAL SHUTDOWN

T_SD

Thermal shutdown temperature

T_Jrising

150

I²C INTERFACE

Configuration parameters slave

address

E8

9E

ADDR

Programmable V_COMslave address

Low level input voltage

High level input voltage

Hysteresis

V_IL

Supply = 2.5 V, V_INfalling, standard and fast modes

Supply = 2.5 V, V_INrising, standard and fast⁴modes

Supply = 2.5 V, applicable to fast mode only

Sinking 3 mA

0.3 × V₂₅

V

V_IH

V_HYS

V_OL

C_I

0.7 × V₂₅

125

mV

pF

Low level output voltage

Input capacitance

500

10

Standard mode

Fast mode

100

400

f_SCL

Clock frequency

Clock low period

Clock high period

kHz

µs

Standard mode

Fast mode

4.7

1.3

4

t_LOW

Standard mode

Fast mode

t_HIGH

µs

0.6

(1) Refer to Table 12 for RESET time delay break down.

Submit Documentation Feedback

6

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.3 V; V₂₅= 2.5 V, AV_DD= 8.5 V, V_GH= 23 V, V_GL= –6 V, R_CAMP=200kΩ, C_CAMP=1 nF, NAV_DD= AGND = PGND = 0V,

T_A= –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

4.7

1.3

4

TYP

MAX

UNIT

Standard mode

Fast mode

Bus free time between a STOP and a

START condition

t_BUF

µs

Standard mode

Fast mode

Hold time for a repeated START

condition

t_hd:STA

µs

0.6

4

Standard mode

Fast mode

Set-up time for a repeated START

condition

t_su:STA

t_su:DAT

µs

ns

0.6

250

100

0.05

Data set-up time

Standard mode

Fast mode

Standard mode

Fast mode

3.45

0.9

t_hd:DAT

Data hold time

µs

ns

20 +

0.1C_B

Standard mode

Fast mode

1000

300

Rise time of SCL after a repeated

START condition and after an ACK

bit

t_RCL1

20 +

0.1C_B

20 +

0.1C_B

Standard mode

Fast mode

t_RCL

t_FCL

t_RDA

t_FDA

Rise time of SCL

Fall time of SCL

Rise time of SDA

Fall time of SDA

ns

20 +

0.1C_B

20 +

0.1C_B

Standard mode

Fast mode

300

20 +

0.1C_B

300

20 +

0.1C_B

Standard mode

Fast mode

1000

300

20 +

0.1C_B

20 +

0.1C_B

Standard mode

Fast mode

300

ns

µs

20 +

0.1C_B

300

Standard mode

Fast mode

4

t_su:STO

Set-up time for STOP condition

Capacitive load on SDA and SCL

0.6

Standard mode

Fast mode

400

C_B

pF

E²PROM

N_WRITE

t_WRITE

Number of write cycles

Write time

1000

100

ms

hrs

Data retention

Storage temperature = 150°C

100000

Submit Documentation Feedback

7

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

DEVICE INFORMATION

PIN ASSIGNMENT

28 PIN 5.5mm × 3.5mm RHR PACKAGE

TOP VIEW

24 23 22 21 20 19 18 17 16 15

25

26

14

13

12

11

PGND1

VGH_LX

VGH

VINA–

OUTA

OUTB

VINB–

PGND3

27

28

VGHM

1

2

3

4

5

6

7

8

9

10

PIN FUNCTIONS

TYPE

DESCRIPTION

NAME

AGND

AVDD

COMP

NO.

22

P

I

Ground

AVDD sense pin

23

21

O

Boost converter 1 compensation. Connect a suitable compensation network (typically a series R-C

combination) between this pin and ground

DRVN

FLK

6

2

O

I

Drive output for negative linear regulator

Gate voltage shaping flicker clock input

Boost convert 1 switch node

LX

24

8

P

I

NAVDD

OUTA

OUTB

PGND1

PGND2

PGND3

RE

Negative AVDD voltage input

13

12

25

16

29

1

O

P

O

I

Operational amplifier A output

Operational amplifier B output

Power Ground 1 for boost converter 2

Power Ground 2 for buck converter

Power Ground 3 for boost converter 1

Gate voltage shaping discharge resistor connection

T-CON reset output

RESET

SCL

5

4

I²C Interface serial clock

SDA

3

I/O

O

P

O

I

I²C Interface serial data

VCOM_OUT

VGH

9

VCOM amplifier output

27

26

28

7

Gate voltage shaping input and boost converter 2 output sense

Boost converter 2 switch node

Gate voltage shaping output

VGH_LX

VGHM

VGL

Negative linear regulator sense pin

Supply voltage

VIN

18

P

8

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

PIN FUNCTIONS (continued)

TYPE

DESCRIPTION

NAME

VINA+

VINA–

VINB+

VINB–

VT

NO.

15

14

10

11

20

19

17

I

Operational amplifier B non-inverting input

Operational amplifier A inverting input

I

Operational amplifier B non-inverting input

I

Operational amplifier B inverting input

I

Boost converter 2 and V_COMreference external thermistor network connection

Buck converter or LDO regulator output sense

Buck converter switch node or LDO regulator output

V25

O

P

V25_LX

Submit Documentation Feedback

9

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

PARAMETER

BOOSTER CONVERTER 1

Efficiency vs. Load Current

Output Voltage Ripple

Load Transient Response

Startup

CONDITIONS

FIGURE

V_IN= 3.3 V, AV_DD= 5.5 V and 8.5V, L = 10 µH, f_SW= 1 MHz

V_IN= 3.3 V, AV_DD= 5.5 V, I_AVDD= 200 mA, f_SW= 1 MHz

V_IN= 3.3 V, AV_DD= 5.5 V, I_AVDD= 20 mA to 200 mA

V_IN= 3.3 V, AV_DD= 5.5 V, f_SW= 1 MHz, I_LOAD= 55 Ω

V_IN= 3.3 V, AV_DD= 5.5 V, f_SW= 1 MHz

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Over Voltage Protection

Under Voltage Protection

BUCK CONVERTER

Efficiency vs. Load Current

Output Voltage Ripple

Load Transient Response

Startup

V_IN= 3.3 V, AV_DD= 5.5 V, f_SW= 1 MHz

V_IN= 3.3 V, V₂₅= 1.8 V and 2.5 V

V_IN= 3.3 V, V₂₅= 2.5 V, I_V25= 600 mA

V_IN= 3.3 V, V₂₅= 2.5 V, I_V25= 20 to 200 mA

V_IN= 3.3 V, V₂₅= 2.5 V, I_LOAD= 12.5 Ω

V_IN= 3.3 V, V₂₅= 2.5 V

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Undervoltage Protection

LDO VOLTAGE REGULATOR

Load Transient Response

Startup

V_IN= 3.3 V, V₂₅= 2.5 V, I_V25= 20 to 200 mA

V_IN= 3.3 V, V₂₅= 2.5 V, I_LOAD= 12.5 Ω

V_IN= 3.3 V, V₂₅= 2.5 V

Figure 12

Figure 13

Figure 14

Undervoltage Protection

BOOST CONVERTER 2

Efficiency vs. Load Current

Output Voltage Ripple

Load Transient Response

Startup

V_IN= 3.3 V, AV_DD= 5.5 V, V_GH= 16 V, L = 10 µH, f_SW= 800 kHz

V_IN= 3.3 V, AV_DD= 8.5 V, V_GH= 25 V, L = 10 µH, f_SW= 800 kHz

V_IN= 3.3 V, AV_DD= 5.5 V, V_GH= 16 V, L = 10 µH, I_VGH= 50 mA, f_SW= 800 kHz

V_IN= 3.3 V, AV_DD= 5.5 V, V_GH= 16 V, L = 10 µH, I_VGH= 10 to 50 mA

V_IN= 3.3 V, AV_DD= 5.5 V, V_GH= 16 V, L = 10 µH, f_SW= 800 kHz

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Under Voltage Protection

NEGATIVE CHARGE PUMP REGULATOR CONTROL

Output Voltage Ripple

V_IN= 3.3 V, AV_DD= 5.5 V, V_GL= –4.5 V, I_GL= 50 mA

Figure 21

Figure 22

Figure 23

Figure 24

Load Transient Response

GATE VOLTAGE SHAPING

V_IN= 3.3 V, AV_DD= 5.5 V, V_GL= –4.5 V, I_GL= 10 to 50 mA

V_IN= 3.3 V, AV_DD= 5 V, AV_DD= 5 V,

OPERATIONAL AMPLIFIER

SLEW RATE

V_IN= 3.3 V, V_GH= 16 V, NAV_DD= –5 V, INA+ = –1 V to 1 V

POWER ON SEQUENCY

POWER OFF SEQUENCY

V_IN= 3.3 V, AV_DD= 5.5 V, V_GH= 16 V, V_GL= –4.5 V

Figure 25

Figure 26

10

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

EFFICIENCY

vs

LOAD CURRENT

OUTPUT VOLTAGE RIPPLE

100

90

80

70

60

50

40

30

20

10

0

AV_DDVoltage 20mV/div

LX Voltage 2V/div

Inductor Current 300mA/div

DD = 5.5V

AV_DD= 5.5 V

AV = 8.5 V

DD = 8.5V

DD

1

10

100

1k

C001

Load Current (mA)

Time (1 µs/div)

Figure 1. Boost Converter 1 Efficiency

LOAD TRANSIENT RESPONSE

AV_DDVoltage 200mV/div

Figure 2. Boost Converter 1 Output Ripple

STARTUP

V_INVoltage 2V/div

AV_DDVoltage 2V/div

LX Voltage 2V/div

Inductor Current 200mA/div

Load Current 50mA/div

Time (2 ms/div)

Time (10 ms/div)

Figure 3. Boost Converter 1 Load Transient Response

Figure 4. Boost Converter 1 Startup

OVERVOLTAGE PROTECTION

UNDERVOLTAGE PROTECTION

AV_DDVoltage 5V/div

AV_DDVoltage 2V/div

LX Voltage 5V/div

LX Voltage 2V/div

V₂₅Voltage 1V/div

V₂₅Voltage 2V/div

Time (5 ms/div)

Time (50 ms/div)

Figure 5. Boost Converter 1 Overvoltage Protection

Figure 6. Boost Converter 1 Undervoltage Protection

Submit Documentation Feedback

11

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

EFFICIENCY

vs

LOAD CURRENT

OUTPUT VOLTAGE RIPPLE

100

90

80

70

60

50

40

30

20

10

V₂₅Voltage 10mV/div

V25_LX Voltage 2V/div

Inductor Current 300mA/div

V25 = 1.8V

V₂₅= 1.8 V

VV₂2₅5==22.5.5VV

0

1

10

100

1k

C002

Load Current (mA)

Time (2 µs/div)

Figure 7. Buck Converter Efficiency

LOAD TRANSIENT RESPONSE

V₂₅Voltage 100mV/div

Figure 8. Buck Converter Output Ripple

STARTUP

V_INVoltage 2V/div

V₂₅Voltage 1V/div

V25_LX Voltage 2V/div

Inductor Current 200mA/div

Load Current 50mA/div

Time (2 ms/div)

Time (10 ms/div)

Figure 9. Buck Converter Load Transient Response

Figure 10. Buck Converter Startup

UNDERVOLTAGE PROTECTION

LOAD TRANSIENT RESPONSE

V₂₅Voltage 200mV/div

V₂₅Voltage 1V/div

V25_LX Voltage 2V/div

AV_DDVoltage 5V/div

V_GHVoltage 10V/div

Load Current 50mA/div

Time (2 ms/div)

Time (50 ms/div)

Figure 11. Buck Converter Undervoltage Protection

Figure 12. LDO Load Transient Response

12

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

STARTUP

UNDERVOLTAGE PROTECTION

V_INVoltage 2V/div

V₂₅Voltage 1V/div

AV_DDVoltage 3V/div

V_GHVoltage 10V/div

AV_DDVoltage 2V/div

I_INCurrent 100mA/div

V_GLVoltage 4V/div

Time (10 ms/div)

Time (50 ms/div)

Figure 13. LDO Startup

Figure 14. LDO Undervoltage Protection

EFFICIENCY

vs

LOAD CURRENT

EFFICIENCY

vs

LOAD CURRENT

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

AV = 5.5 V

AV^DD^DD = 5.5V

V_GG_HH = 16V

AV = 8.5 V

AV^DD^DD = 8.5V

V_GG_HH = 25V

V

= 16 V

V

= 25 V

0

10

20

30

40

50

0

10

20

30

40

50

C003

C004

Load Current (mA)

Figure 15. Boost Converter 2 Efficiency

Figure 16. Boost Converter 2 Efficiency

LOAD TRANSIENT RESPONSE

V_GHVoltage 200mV/div

OUTPUT VOLTAGE RIPPLE

V_GHVoltage 10mV/div

VGH_LX Voltage 6V/div

Load Current 20mA/div

Time (2 ms/div)

Inductor Current 300mA/div

Time (1 µs/div)

Figure 17. Boost Converter 2 Output Ripple

Figure 18. Boost Converter 2 Load Transient Response

Submit Documentation Feedback

13

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

STARTUP

UNDERVOLTAGE PROTECTION

AV_DDVoltage 3V/div

V_GHVoltage 2V/div

V_GHVoltage 8V/div

VGH_LX Voltage 3V/div

VGH_LX Voltage 8V/div

AV_DDVoltage 3V/div

Inductor Current 300mA/div

Time (10 ms/div)

Time (50 ms/div)

Figure 19. Boost Converter 2 Startup

OUTPUT VOTLAGE RIPPLE

V_GLVoltage 20mV/div

Figure 20. Boost Converter 2 Undervoltage Protection

LOAD TRANSIENT RESPONSE

V_GLVoltage 50mV/div

Load Current 20mA/div

LX Voltage 2V/div

Inductor Current 100mA/div

Time (1 µs/div)

Time (2 ms/div)

Figure 21. Negative Charge Pump Output Ripple

Figure 22. Negative Charge Pump Load Transient Response

GATE VOLTAGE SHAPING

SLEW RATE

INA+ Voltage 500mV/div

V_GHVoltage 8V/div

VOUTA Voltage 500mV/div

V_GHMVoltage 8V/div

FLK Voltage 2V/div

Time (10 µs/div)

Time (20 ns/div)

Figure 23. Gate Voltage Shaping

Figure 24. Operational Amplifier Slew Rate

14

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

POWER ON SEQUENCY

POWER OFF SEQUENCY

V_IN

V₂₅

V_IN

V₂₅

RESET

AV_DD

RESET

AV_DD

V_GH

V_GL

V_GPM

V_COM

Time (10 ms/div)

Figure 25. Power Off Sequency

Figure 26. Power Off Sequency

Submit Documentation Feedback

15

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

DETAILED DESCRIPTION

An internal block diagram of the TPS65640 is shown in Figure 27.

COMP

AVDD

LX

Current

Limit

DAC

Gm

V_REF

Gate

Driver

VIN

PGND3

V25_LX

V_REF

LDO Mode

V25

R

S

DAC

V_REF

Gate

Driver

Latch

Off-Time

Control

RESET

PGND2

DAC

AGND

VT

VCOM_OUT

VGH_LX

1.25 V

40 µA

6

ADC

0.5 V

R

DAC

Gate

Driver

Latch

PGND1

VGHM

VGH

Off-Time

Control

S

Logic

Control

FLK

AVDD

RE

VINA+

VINA-

DRVN

V_IN

OUTA

V_CC

V_REF

VINB+

VINB-

OUTB

VGL

DAC

SDA

SCL

DAC

Register

EEprom

NAVDD

Figure 27. Internal Block Diagram

16

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

BOOST CONVERTER 1 (AV_DD)

V_IN

L1

D1

AV_DD

C_OUT1

AVDD

VIN

LX

R1

Current

Limit

DAC

Gm

V_REF

Gate

Q1

Driver

R2

COMP

PGND3

200 kΩ

1 nF

Figure 28. Boost Converter 1 Internal Block Diagram

Switching Frequency (Boost Converter 1)

Boost Converter 1 can be configured to operate at 600 kHz, 800 kHz, 1000 kHz, or 1200 kHz. In general, the

higher switching frequency offers better transient performance at the expense of slightly reduced efficiency. In

some applications, it may be necessary to select a particular switching frequency to minimize EMI problems. The

switching frequency is determined by the state of the FREQ1 configuration bit in the AVDDCONFIG register.

Compensation (Boost Converter 1)

Boost Converter 1 uses an external compensation network connected to its COMP pin to stabilize its feedback

loop. A simple series R-C network connected between this pin and ground is sufficient to achieve good

performance (that is, stable and with good transient response) in most applications. Good starting values, which

will work for many applications, are 200 kΩ and 1 nF.

In some applications (for example, those using electrolytic output capacitors), it may be necessary to include a

second compensation capacitor between the COMP pin and ground. This has the effect of adding an additional

pole in the feedback loop's frequency response, which can be used to cancel the zero introduced by the

electrolytic output capacitor's ESR.

Output Voltage (Boost Converter 1)

Boost converter 1's output voltage can be programmed from 3.6 V to 11 V with 100-mV increment using the

AVDD register. Because changing the output voltage in big steps can temporarily demand switch currents

greater than the switch's current limit, it is recommended that AV_DDbe changed in 100-mV steps, for example,

first change AV_DDfrom 7 V to 7.1 V, then to 7.2 V, then to 7.3 V, and so on until the desired output voltage has

been achieved.

Start-Up (Boost Converter 1)

Boost converter 1 starts immediately after the V₂₅voltage raming to its programmed voltage.

Submit Documentation Feedback

17

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

To minimize inrush current during start-up, boost converter 1 ramps its output voltage in t_SS1milliseconds. The

value of t_SS1can be programmed from 20ms to 80ms using the SS1 bits in AVDDCONFIG register.

Boost converter 1's internal power good signal is asserted when two conditions are met:

•

the converter's soft-start ramp has reached its final value

the converter's output voltage is greater than its UVP threshold.

The power good signal is latched and will only be reset when the supply voltage is cycled.

Current limit (Boost Converter 1)

The boost converter 1 has built-in cycle-by-cycle current limit for the power MOSFET. When the inducotr current

or the power MOSFET current reaches I_LIM, the power MOSFET will be tuned off immediately until the next

switching cycle. The I_LIMcan be programmed from 1 A to 2 A using the AVDD ILIM bit in AVDDCONFIG register.

Design Procedure (Boost Converter 1)

The first step in the design procedure is to verify whether the maximum possible output current of the boost

converter 1 supports the specific application requirements.

1. Converter Duty Cycle:

V ´ h

D = 1-

IN

V_AVDD

(1)

2. Inductor Ripple Current:

V ´D

DI_L=

IN

f_s´L

(2)

3. Maximum Output Current:

DI_L

æ

ö

÷

ø

I_{OUT _max}= I

-

´ 1- D

( )

ç LIM_min

2

è

(3)

(4)

4. Peak Switching Current:

I_OUTDI_L

I_SWPEAK

=

+

1- D

2

η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.9 as an estimation)

f_S= Switching frequency

L = Selected inductor value (typ. 10 µH)

I_{LIM_min}: Minimum current limit

I_SWPEAK= Peak switch current for the used output current

ΔI_L= Inductor peak-to-peak ripple current

The peak switch current I_SWPEAKis the current that the integrated switch, the inductor and the external Schottky

diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak

switch current is the highest.

Inducotr Selection (Boost Converter 1)

Higher the inductor value the lower the inductor current ripple and the output

voltage ripple but the slower the transient response.

Inductor Value:

4.7 µH ≤ L ≤ 10 µH

The inductor saturation current must be higher than the switch peak current for

Saturation Current:

DC Resistance:

I

_SAT≥ I_SWPEAKor I_SAT≥ I_{LIM_max}the max. peak output current or as a more conservative approach higher than

the max. switch current limit.

The lower the inductors resistance the lower the losses and the higher the efficiency.

18

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

Rectifier Diode Selection (Boost Converter 1)

Diode type: Schottky or super barrier rectifier (SBR) for better efficiency.

Forward voltage: The lower the forward voltage VF the higher the efficiency and the lower the diode temperature.

Reverse voltage: V_Rmust be higher than the output voltage and should be higher than the OVP voltage typically

15 V.

Thermal characteristics: The diode must be able to handle the dissipated power of P_D= V_Fx I_OUT

.

Output Capacitor Selection (Boost Converter 1)

For best output voltage filtering, TI recommends low-ESR ceramic capacitors. Two 4.7 µF (or four 2.2-µF)

ceramic capacitors work for most applications. To improve the load transient response more capacitance can be

added between the rectifier diode.

To calculate the output voltage ripple the following equations can be used:

V_AVDD- V

I_OUT

x

_AVDD´ f_sC_OUT

IN

DV_{C _RIPPLE}

=

+ DV_{C _ESR}

V

(5)

(6)

DV_{C _ESR}= I_SWPEAK´R_{C _ESR}

BUCK CONVERTER (V₂₅)

The buck converter uses a current mode, quasi-constant off-time topology that offers high efficiency, fast

transient response, and constant ripple current amplitude under all operating conditions (see Figure 29). The

converter's off time is inversely proportional V₂₅and therefore constant when the converter is in regulation. Thus

for a given V_INthe converter operates at a constant frequency that changes temporarily when the converter

reacts to load changes.

When the latch is set, transistor Q₁is turned on and transistor Q₂is turned off. As inductor L₂charges, the

current flowing through Q₁ramps up at a rate determined by the difference between V_INand V_COREand the value

of L₂. The ramping current is sensed across Q₁, and when it reaches the level demanded by error amplifier A₁

the output of comparator A₂goes high, resetting the latch. The reset latch turns off Q₁and turns on Q₂. Inductor

L₂now discharges through Q₂for a fixed off time. At the end of the off time, the latch is set, turning on Q₁and

turning off Q₂, and the cycle repeats.

The sensed output voltage is divided down by a multiplying DAC and used as negative feedback to amplifier A₁.

The output of A₁is the error signal required to regulate V₂₅at the desired voltage.

VIN

Q1

V_REF

DAC

R

S

A2

A1

L2

Gate

Driver

V₂₅

Latch

V25_LX

C_OUT2

Off-Time

Control

Q2

V25

PGND2

Figure 29. Buck Converter 1 Block Diagram

Output Voltage (Buck Converter)

Buck converter's output voltage can be programmed from 1.5 V to 3.0 V using the V25 register.

Submit Documentation Feedback

19

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Start-Up (Buck Converter)

Buck converter starts as soon as the supply voltage exceeds the under-voltage lockout threshold (the same time

as the linear regulator starts).

To minimize inrush current during start-up, buck converter ramps V₂₅from 0 V to programmed voltage in t_SS2

milliseconds. The value of t_SS2is around 0.5 ms to 4.0 ms.

The same ramp rate is used for both buck converter and the linear regulator (LDO).

Current limit (Buck Converter)

The buck converter has built-in cycle-by-cycle current limit for the high side power MOSFET, Q1 in Figure 29.

When the inductor current or the MOSFET Q1 current reaches I_LIM, the Q1 is tuned off immediately until the next

switching cycle. The I_LIMis typically 1.2 A.

Design Procedure (Buck Converter)

The first step in the design procedure is to verify whether the maximum possible output current of the buck

converter supports the specific application requirements.

1. Switching Frequency:

V ´ h - V₂₅

f_s=

IN

V ´ h´ T_off

IN

(7)

(8)

2. Converter Duty Cycle

V₂₅

D =

V ´ h

IN

3. Inductor Ripple Current:

V

_IN- V₂₅´D

)

(

DI_L=

f_s´L

(9)

(10)

(11)

4. Maximum Output Current:

DI_L

-

I_{OUT _max}= I_{LIM_min}

2

5. Peak Switching Current:

DI_L

I_SWPEAK= I_OUT

+

2

T_off= Buck boost switch duty off time (typ. 200 ns)

η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation)

f_S= Switching frequency

L = Selected inductor value (typ. 10 µH)

I_{LIM_min}: Minimum current limit

I_SWPEAK= Peak switch current for the used output current

ΔI_L= Inductor peak-to-peak ripple current

The peak switch current I_SWPEAKis the current that the integrated switch, the inductor and the external Schottky

diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak

switch current is the highest.

Inducotr Selection (Buck Converter)

Higher the inductor value the lower the inductor current ripple and the output

voltage ripple but the slower the transient response.

Inductor Value:

4.7 µH ≤ L ≤ 10 µH

20

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

The inductor saturation current must be higher than the switch peak current for

_SAT≥ I_SWPEAKor I_SAT≥ I_{LIM_max}the max. peak output current or as a more conservative approach higher than

the max. switch current limit.

Saturation Current:

DC Resistance:

I

The lower the inductors resistance the lower the losses and the higher the efficiency.

Output Capacitor Selection (Buck Converter)

For best output voltage filtering, TI recommends low-ESR ceramic capacitors. Two 4.7-µF (or four 2.2-µF)

ceramic capacitors work for most applications. To improve the load transient response more capacitance can be

added between the rectifier diode.

To calculate the output voltage ripple the following equations can be used:

V₂₅

I_OUT

DV_{C _RIPPLE}

=

´

V ´ f_sC_OUT

+ DV_{C _ESR}

IN

(12)

(13)

DV_{C _ESR}= I_SWPEAK´R_{C _ESR}

LDO REGULATOR (V₂₅)

A low-dropout (LDO) linear regulator generates V₂₅(see Figure 30). The linear regulator is supplied from V_INand

it’s an alternative option to buck converter. The V₂₅voltage could be supplied either by Buck converter or LDO

determined by the state of the BUCK/LDO configuration bit in the CONFIG register.

VIN

Body

diode

Q1

Q2

V₂₅

V25_LX

C_OUT3

V_REF

Q3

A1

DAC

V25

R1

AGND

Figure 30. Linear Regulator Block Diagram

Amplifier A₁regulates the current through Q₃by comparing a reduced version of the output voltage with a

bandgap voltage reference V_REF. The output of Q₃is mirrored by Q₁and Q₂to generate the desired output

voltage. In practice, Q₂is made much bigger than Q₁. This means that the current flowing through Q₁and Q₃is

smaller than the output current by the same ratio as the transistor areas.

The maximum output current is inherently limited by the maximum output voltage of A₁, the value of resistor R₁,

and the characteristics of transistor Q₃.

Output Voltage (LDO Regulator)

LDO's output voltage can be programmed from 1.5 V to 3.0 V using the V25 register. Because the V25_LX pin

alternates for LDO regulator's output voltage and buck converter's switch node, select buck converter with LDO

circuit configuration can make the permanent damage. The LDO regulator mode is factory default setup.

Start-Up (Low Dropout Regulator)

LDO starts as soon as the supply voltage exceeds the under-voltage lockout threshold (the same time as the

buck converter starts).

To minimize inrush current during start-up, LDO regulator ramps V₂₅from 0V to programmed voltage in t_SS2

milliseconds. The value of t_SS2is around 0.5 ms to 4.0 ms.

Submit Documentation Feedback

21

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

The same ramp rate is used for both buck converter and the linear regulator.

BOOST CONVERTER 2 (V_GH)

Boost converter 2 is a low-power boost converter that can be used to generate the LCD panel's gate ON voltage

V_GH. Operating the converter in DCM removes the right-half-plane zero from its transfer function, simplifying its

stabilization and allowing the use of small chip inductors. To simplify its application and to minimize the external

parts required, boost converter 2 features internal compensation and soft-start circuitry.

A simplified block diagram of boost converter 2 is shown in Figure 31.

D4

L4

AV_DD

V_GH

C_OUT4

VGH_LX

R

DAC

A2

A1

Q1

Gate

Driver

Latch

Off-Time

Control

S

VGH

PGND1

Figure 31. Boost Converter 2 Block Diagram

Switching Frequency (Boost Converter 2)

Boost Converter 2 can be configured to operate at 400 kHz or 800 kHz. The switching frequency is determined

by the state of the FREQ4 configuration bit in the VGHCONFIG register.

Output Voltage Temperature Compensation (Boost Converter 2)

Boost converter 2 can be temperature compensated, allowing its output voltage to transition from a higher

voltage at low temperatures V_GH(COLD)to a lower voltage at high temperatures V_GH(HOT)(see Figure 32 and

Figure 33).

V_GH

V_GHCOLD

V_GHHOT

Temperature

T_COLD

T_HOT

Figure 32. Boost Converter 2 Temperature Compensation Characteristic

22

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

1.25 V

40 µA

6

VT

ADC

PWM

Controller

A1

R1

0.5 V

DAC

VGHHOT

5 Bits

VGH

R2

R_T

VGHCOLD

5 Bits

Figure 33. Boost Converter 2 Temperature Compensation Block Diagram

(1)

Referring to Figure 33, The thermistor network formed by R1, R2, and R_T

generates a voltage at the VT pin

(2)

whose value decreases with increasing temperature. With proper selection of the external components R_T, R1

and R2, temperatures T_HOTand T_COLDcan be configured to suit each display's characteristics. A spreadsheet

allowing easy calculation of component values is available from Texas Instruments free of charge.

Output Voltage (Boost Converter 2)

The output voltage of boost converter 2 at cold temperatures can be programmed from 15 V to 37 V using the

VGHCOLD register.

The output voltage of boost converter 2 at hot temperatures can be programmed from 15 V to 37 V using the

VGHHOT register.

In applications that do not require temperature compensation, the VGHT bit in CONFIG register should be set to

1 and the VGHHOT register used to set the voltage of V_GH

.

Because changing the output voltage in big steps can temporarily demand switch currents greater than the

switch's current limit, it is recommended that V_GHbe changed in 1 V steps, i.e. first change V_GHfrom 15 V to 16

V, then to 16 V, then to 17 V, and so on until the desired output voltage has been achieved.

Start-Up (Boost Converter 2)

Boost converter 2 is enabled when AVDD has finished ramping to its programmed voltage.

To minimize inrush current during start-up, boost converter 2 ramps V_GHto its programmed value in t_SS4

seconds. The value of t_SS4can be programmed from 4 ms to 16 ms using the SS4 bits in VGHCONFIG register.

The same ramp rate is used for both boost converter 2 and the negative charge pump regulator.

Boost converter 2's internal power good signal is asserted when two conditions are met:

•

the converter's soft-start ramp has reached its final value

the converter's output voltage is greater than its UVP threshold.

The power good signal is latched and will only be reset when the supply voltage is cycled.

Current limit (Boost Converter 2)

The boost converter 2 has built-in cycle-by-cycle current limit for the power MOSFET. When the inducotr current

or the power MOSFET current reaches I_LIM, the power MOSFET will be tuned off immediately until the next

switching cycle. The I_LIMis typically 1.2 A for boost converter 2.

Design Procedure (Boost Converter 2)

The first step in the design procedure is to verify whether the maximum possible output current of the boost

converter supports the specific application requirements.

1. Converter Duty Cycle:

(1) R_Tshould be a negative temperature coefficient (NTC) type whose resistance at 25°C is 10kΩ.

(2) Texas Instruments can provide a spreadsheet that calculates suitable component values automatically.

Submit Documentation Feedback

23

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

V

AVDD

´ h

D = 1-

V

GH

(14)

2. Inductor Ripple Current:

_AVDD´D

f_s´L

3. Maximum Output Current:

DI_L

V

DI_L=

(15)

æ

ö

I_{OUT _max}= I

-

´ 1- D

( )

÷

ç LIM_min

2

è

ø

(16)

(17)

4. Peak Switching Current:

I_OUTDI_L

I_SWPEAK

=

+

1

-

D

2

η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.9 as an estimation)

f_S= Switching frequency

L = Selected inductor value (typ. 10 µH)

I_{LIM_min}: Minimum current limit

I_SWPEAK= Peak switch current for the used output current

ΔI_L= Inductor peak-to-peak ripple current

The peak switch current I_SWPEAKis the current that the integrated switch, the inductor and the external Schottky

diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak

switch current is the highest.

Inducotr Selection (Boost Converter 2)

Higher the inductor value the lower the inductor current ripple and the output

voltage ripple but the slower the transient response.

Inductor Value:

4.7 µH ≤ L ≤ 10 µH

The inductor saturation current must be higher than the switch peak current for

Saturation Current:

DC Resistance:

I

_SAT≥ I_SWPEAKor I_SAT≥ I_{LIM_max}the max. peak output current or as a more conservative approach higher than

the max. switch current limit.

The lower the inductors resistance the lower the losses and the higher the efficiency.

Rectifier Diode Selection (Boost Converter 2)

Diode type: Schottky or super barrier rectifier (SBR) for better efficiency.

Forward voltage: The lower the forward voltage VF the higher the efficiency and the lower the diode temperature.

Reverse voltage: V_Rmust be higher than the output voltage and should be higher than the OVP voltage 39 V.

Thermal characteristics: The diode must be able to handle the dissipated power of P_D= V_Fx I_OUT

.

Output Capacitor Selection

For best output voltage filtering, TI recommends low-ESR ceramic capacitors. Two 4.7-µF (or four 2.2-µF)

ceramic capacitors work for most applications. To improve the load transient response more capacitance can be

added between the rectifier diode.

To calculate the output voltage ripple the following equations can be used:

V

_GH- V_AVDDI_OUT

´

DV_{C _RIPPLE}

=

+ DV_{C _ESR}

V_GH´ f_s

C_OUT

(18)

(19)

DV_{C _ESR}= I_SWPEAK´R_{C _ESR}

24

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

NEGATIVE CHARGE PUMP VOLTAGE REGULATOR CONTROL (V_GL)

The negative charge pump voltage regulator control an external NPN transistor to regulate the V_GLoutput. As

typical application circuit Figure 34 illustrated, a one time negative voltage charge pump based on the AV_DD

boost switching provides the source voltage to the emitter of NPN transistor. Depending on the feedback voltage

applied on the VGL pin, A₁error amplifier regulates the current through Q3. The proportional current mirrored by

Q1 to Q2 sends to the base of NPN transistor from DRVN pin. Therefore, the regulation is achieved by controlled

voltage drop between collector and emitter of NPN transition.

Normally the negative charge pump regulator is to provide gate OFF voltage to the gate driver or level shift. In

additional, for positive and negative AV_DDapplication, it can also be used for negative AV_DDregulating. Because

of charge bump voltage loss, it is recommended to leave enough voltage guard band (for example, 1 V for 50-

mA load) between positive AV_DDto negative AV_DD

.

R1

LX

V_GL

C_OUT5

V_IN

Q1

Q2

DRVN

V_CC

V_REF

Q3

A1

DAC

VGL

AGND

Figure 34. Negative Charge Pump Block Diagram

Output Voltage (Negative Charge Pump)

Negative charge pump's output voltage can be programmed from –8 V to –3.8 V using the VGL register.

Start-Up (Negative Charge Pump)

Negative charge pump is enabled together with booster converter 2 when AVDD has finished ramping to its

programmed voltage.

The same ramp rate is shared for both boost converter 2 and negative charge pump regulator. The negative

charge pump regulator ramps V_GLto its programmed value from 0V in t_SS4seconds. The value of t_SS4can be

programmed from 4 ms to 16 ms using the SS4 bits in VGHCONFIG register.

NPN Transistor Selection (Negative Charge Pump)

The NPN transistor used to regulator V_GLor Negtive AV_DDshould have a DC gain (h_FE) of at least 100 when its

collector current is equal to the charge pump's output current. The transistor should also be able withstand

voltages up to V_INacross its collector-emitter (V_CE).

The power dissipated in the transistor is given by Equation 20. The transistor must be able to dissipate this

power without its junction becoming too hot. Note that the ability to dissipate power depends on adequate PCB

thermal design.

P_Q= [V -(2´ V_F)- | V_GL|]´I_GL

IN

(20)

Submit Documentation Feedback

25

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Where I_GLis the mean (not RMS) output current drawn from the charge pump.

Diode Selection (Negative Charge Pump)

Small-signal diodes can be used for most low current applications (<50 mA) and higher rated diodes for higher

power applications. The average current through the diode is equal to the output current, so that the power

dissipated in the diode is given by Equation 21

P_D= I_GL´ V_F

(21)

The peak current through the diode occurs during start-up and for a few cycles may be as high as a few amps.

However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive current

rating is much lower. The diodes’ reverse voltage rating should be equal to at least 2 × V_IN.

Capacitor Selecion (Negative Charge Pump)

For the lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not

critical and 1 µF to 10 µF is suitable for most applications. Large capacitors provide better performance in

applications where large load transient currents are present.

A flying capacitor in the range of 100 nF to 1 µF is suitable for most applications. Larger values experience a

smaller voltage drop by the end of each switching cycle, and allow higher output voltages or currents, or both, to

be achieved. Smaller values tend to be physically smaller and cheaper.

OVER-VOLTAGE AND UNDER-VOLTAGE PROTECTION (AV_DD, V₂₅, V_GH)

Each voltage regulator output is protected against under-voltages and over-voltages.

Over-voltage conditions are detected if AV_DDoutput rises over typical 15 V or V_GHoutput rises over typical 39 V,

in which cases the AV_DDboost switch or VGH boost switch will be turned off until the overvoltage conditions is

removed.

Undervoltage conditions are detected if a regulator output falls below certain level of its programmed voltage for

longer than a time period, in which case the relevant voltage regulator is disabled. To recover normal operation

following an under-voltage condition, the cause of the error condition must be removed and the supply voltage

V_INcycled.

Table 1. Under Voltage Protection

ERROR

TIME

UVP

PROTECT BEHAVIOR

RECOVERY CONDITION

CONDITI

ON

PERIOD

V₂₅buck converter or LDO, AV_DDboost converter, V_GH

> 160 ms boost converter and V_GLregulator are disabled. RESET

pin is pulled low.

Error condition is removed and V_INis

cycled (POR).

V₂₅

< 1 V

AV_DDboost converter, V_GHboost convert and V_GL

> 160 ms

Error condition is removed and V_INis

cycled (POR).

AV_DD

V_GH

< 80%

voltage regulator are disabled.

Error condition is removed and V_INis

cycled (POR).

> 160 ms V_GHboost converter is disabled.

RESET GENERATOR

The RESET pin generates an active-low reset signal for the T-CON (see Figure 35). During power-up the reset

timer (t_RESET) starts when V₂₅has finished ramping. The reset pulse duration can be programmed from 0 ms to

30 ms using the RESET register.

The RESET output is an open-drain type that requires an external pull-up resistor. Pull-up resistor values in the

range 10 kΩ to 100 kΩ are recommended for most applications.

26

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

RESET

V25

OSC

CLK

H

≥

D

V_REF

DAC

Reset

Q

EN

RST

Timer

RST

Figure 35. Reset Internal Block Diagram

GATE VOLTAGE SHAPING

The gate voltage shaping function can be used to reduce image sticking in LCD panels by modulating the LCD

panel's gate ON voltage (VGH). Figure 36 shows a block diagram of the gate voltage shaping function and

Figure 37 shows the typical waveforms during operation.

V_GH

VGH

Q1

VGHM

V_GHM

Control

Logic

FLK

C_VGHM

4.7 nF

Q2

RE

R_E

Figure 36. Gate Voltage Shaping Block Diagram

V_GHPG

FLK

Don’t Care

t_DLY

V_GHM

Figure 37. Gate Voltage Shaping Waveforms

Submit Documentation Feedback

27

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Gate voltage shaping is controlled by the FLK input. When FLK is high, Q₁is on, Q₂is off, and V_GHMis equal to

V_GH. On the falling edge of FLK, Q₁is turned off, Q₂is turned on, and the LCD panel load connected to the

VGHM pin discharges through the external resistor connected to the RE pin.

During power-up Q₂is held permanently on and Q₁permanently off, regardless of the state of the FLK signal,

until t_DLYmilliseconds after boost converter 2 (V_GH) has finished ramping. The value of t_DLYcan be programmed

from 0ms to 60ms using the DLY register.

During power-down Q₂is held permanently on and Q1 permanently off, regardless of the state of the FLK signal.

PROGRAMMABLE V_COMCALIBRATOR (V_COM

)

The programmable VCOM calibrator uses a DAC to generate an offset Voltage for LCD panel common voltage

reference.

AVDD

1.25 V

6

ADC

VT

VCOM

Temp

R1

40 µA

0.5 V

VCOM_OUT

R2

R_T

VCOMHOT

10-Bits RAM

VCOMHOT

10-Bits

DAC

VCOMCOLD

10-Bits

VCOMCOLD

10-Bits RAM

VCOM

7-Bits RAM

NAVDD

Figure 38. Programmable V_COMCalibrator Block Diagram

The VCOM voltage calibration needs two steps for adjustment.

First step is to set the central value of V_COMvoltage according to the AV_DD, V_GHand LCD panel characteristic.

The VCOM voltage is programmable from 1.5 V to 5.0 V or –4 V to 0.8 V by VCOMHOT register. The first step is

normally done by PCB assembly manufacturer.

Second step is to calibrate the V_COMvoltage on the LCD panel assembly line by VCOM RAM register through I²C

digital interface. The VCOM register value indicates the voltage increment or decrement of VCOM_OUT which is

preset by VCOMHOT. Once the proper value is identified, the VCOM_OUT voltage value can be renewed with

VCOM register value added. The default value for VCOM register is 1000000. If 1000001 is written into VCOM

register, the VCOM_OUT voltage will increase with one DAC step, 10mV. In the other hand if 0111111 is written

to VCOM register, the VCOM_OUT voltage will decrease with one DAC step, 10 mV.

The VCOM voltage also supports temperature compensation and allows its output voltage to transition from a

lower voltage at low temperatures V_COMCOLDto a higher voltage at high temperatures V_COMHOT(see Figure 39).

The temperature compensation for VCOM could be turn on/off by bit VCOMT in register CONFIG. If temperature

compensation for VCOM is ON state, both VCOMHOT and VCOMCOLD need to be input. Otherwise only

VCOMHOT is active for VCOM voltage setting without temperature compensation.

28

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

V_COM

V_COMHOT

V_COMCOLD

Temperature

T_COLD

T_HOT

Figure 39. V_COMTemperature Compensation Characteristic

OPERATIONAL AMPLIFIERS

Like most operational amplifiers, the V_COMamplifiers are not designed to drive purely capacitive loads, so it is not

recommended to connect a capacitor directly to their outputs in an attempt to increase performance; however,

the amplifiers are capable of delivering high peak currents that make such capacitors unnecessary.

To optimize performance, the V_COMamplifiers' positive supplies are connected internally to the AVDD pin and

negative supplies are connected internally to NAVDD pin (See Figure 40 for operational amplifier internal block

diagram).

AVDD

VINA+

OUTA

VINA-

VINB+

OUTB

VINB-

NAVDD

Figure 40. Operational Amplifier Block Diagram

The two integrated operational amplifiers are able to be disabled for non-used application to minimize the power

consumption. Setting the OPA_A bit or OPA_B bit in CONFIG register can turn on/off operational amplifier A or

B individually.

To minimize the addtional power dissipated when operational amplifier is turned off, it is recommanded to short

the both inverter input and non-inverter input to same voltage bias or leave them floating.

CONFIGURATION PARAMETERS

The TPS65640 divides the configuration parameters into two categories:

•

VCOM calibration

All other configuration parameters

In typical applications, all configuration parameters except VCOM are programmed by the subcontractor during

PCB assembly, and VCOM is programmed by the display manufacturer during display calibration.

RAM and E²PROM

Configuration parameters can be changed by writing the desired values to the appropriate RAM register or

registers. The RAM registers are volatile and their contents are lost when power is removed from the device. By

writing to the Control Register, it is possible to store the active configuration in non-volatile E²PROM so that it will

subsequently be used as the default setting upon when the device is powered up.

Submit Documentation Feedback

29

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Configuration Parameters (Excluding VCOM Calibration)

Table 2 shows the memory map of the configuration parameters.

Table 2. Configuration Memory Map

Register

Address

Register

Name

Factory

Default

Description

00h

01h

02h

03h

CONFIG

AVDD

FAh

3Ah

0Ah

09h

Sets function control bits

Sets the output voltage of AVDD boost converter

Sets miscellaneous configuration bits for AVDD boost converter

AVDDCONFIG

VGHHOT

Sets the output voltage of VGH boost converter at high temperatures (VGHT = 0) or

VGH boost converter (VGHT=1)

04h

05h

06h

07h

08h

09h

0Ah

0Bh

VGHCOLD

VGHCONFIG

VGL

09h

02h

1Fh

0Ah

01h

06h

01h

5Fh

Sets the output voltage of VGH boost converter at low temperatures (VGHT=0)

Sets miscellaneous configuration bits for VGH boost converter

Sets the output voltage of VGL linear regulator

Sets the output voltage of buck converter.

V25

VDIV

Sets the threshold of the /RST signals

RESET

DLY

Sets the reset pulse duration

Sets the gate voltage shaping delay

VCOMHOT

Presets the output voltage of VCOM reference at high temperatures (VCOMT = 0) or

VCOM reference (VCOMT=1)

0Ch

FFh

VCOMCOLD

Control

5Fh

00h

Presets the output voltage of VCOM reference at low temperatures (VCOMT=0)

Controls whether read and write operations access RAM or E²PROM registers

30

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

CONFIG (00h)

The CONFIG register can be written to and read from.

Table 3. CONFIG Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

VGHT

Bit 0

VCOMR

VCOMT

OPA_B

OPA_A

BUCK/LDO

VGL

VGH

Bit

0

This bit enables/disables the boost converter for VGH voltage regulator.

0

1

Enables the VGH boot converter

Disables the VGH boost converter

VGHT

Bit

1

This bit enables/disables the temperature compensation for VGH regulator.

0

1

Enables the temperature compensation for VGH voltage regulator

Disables the temperature compensation for VGH voltage regulator

VGL

Bit

2

This bit enables/disables the VGL linear voltage regulator.

0

1

Enables the VGL linear voltage regulator

Disables the VGL linear voltage regulator

BUCK/LDO

OPA_A

OPA_B

VCOMT

VCOMR

Bit

3

This bit selects the operation mode for V25 voltage regulator.

0

1

Selects the Buck converter for V25 voltage regulator

Selects the LDO for V25 voltage regulator

Bit

4

This bit enables/disables the OPA_A operational amplifier.

0

1

Enables the OPA_A operational amplifier

Disables the OPA_A operational amplifier

Bit

5

This bit enables/disables the OPA_B operational amplifier.

0

1

Enables the OPA_B operational amplifier

Disables the OPA_B operational amplifier

Bit

6

This bit enables/disables the temperature compensation for VCOM voltage

0

1

Enables the temperature compensation for VCOM voltage

Disables the temperature compensation for VCOM voltage

Bit

7

This bit sets the V_COMvoltage output range

0

1

V_COM= 0.8 V ~ 5 V for full AV_DDApplication

V_COM= –4.1 V ~ 0.2 V for PN AV_DDApplication

Submit Documentation Feedback

31

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

AVDD (01h)

The AVDD register can be written to and read from.

Table 4. AVDD Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

AVDD

Bits

6-0

These bits select boost converter 1's output voltage (AVDD)

0000000

……

N.A.

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

AV_DD= 6.6 V

1100010

AV_DD= 9.8 V

N.A.

AV_DD= 6.7 V

AV_DD= 6.8 V

AV_DD= 6.9 V

AV_DD= 7.0 V

AV_DD= 7.1 V

AV_DD= 7.2 V

AV_DD= 7.3 V

AV_DD= 7.4 V

AV_DD= 7.5 V

AV_DD= 7.6 V

AV_DD= 7.7 V

AV_DD= 7.8 V

AV_DD= 7.9 V

AV_DD= 8.0 V

AV_DD= 8.1 V

AV_DD= 8.2 V

AV_DD= 8.3 V

AV_DD= 8.4 V

AV_DD= 8.5 V

AV_DD= 8.6 V

AV_DD= 8.7 V

AV_DD= 8.8 V

AV_DD= 8.9 V

AV_DD= 9.0 V

AV_DD= 9.1 V

AV_DD= 9.2 V

AV_DD= 9.3 V

AV_DD= 9.4 V

AV_DD= 9.5 V

AV_DD= 9.6 V

AV_DD= 9.7 V

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

AV_DD= 9.9 V

AV_DD= 10.0 V

AV_DD= 10.1 V

AV_DD= 10.2 V

AV_DD= 10.3 V

AV_DD= 10.4 V

AV_DD= 10.5 V

AV_DD= 10.6 V

AV_DD= 10.7 V

AV_DD= 10.8 V

AV_DD= 10.9 V

AV_DD= 11.0 V

AV_DD= 11.1 V

AV_DD= 11.2 V

AV_DD= 11.3 V

AV_DD= 11.4 V

AV_DD= 11.5 V

AV_DD= 11.6 V

AV_DD= 11.7 V

AV_DD= 11.8 V

AV_DD= 11.9 V

AV_DD= 12.0 V

AV_DD= 12.1 V

AV_DD= 12.2 V

AV_DD= 12.3 V

AV_DD= 12.4 V

AV_DD= 12.5 V

AV_DD= 12.6 V

AV_DD= 12.7 V

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

AV_DD= 3.6 V

AV_DD= 3.7 V

AV_DD= 3.8 V

AV_DD= 3.9 V

AV_DD= 4.0 V

AV_DD= 4.1 V

AV_DD= 4.2 V

AV_DD= 4.3 V

AV_DD= 4.4 V

AV_DD= 4.5 V

AV_DD= 4.6 V

AV_DD= 4.7 V

AV_DD= 4.8 V

AV_DD= 4.9 V

AV_DD= 5.0 V

AV_DD= 5.1 V

AV_DD= 5.2 V

AV_DD= 5.3 V

AV_DD= 5.4 V

AV_DD= 5.5 V

AV_DD= 5.6 V

AV_DD= 5.7 V

AV_DD= 5.8 V

AV_DD= 5.9 V

AV_DD= 6.0 V

AV_DD= 6.1 V

AV_DD= 6.2 V

AV_DD= 6.3 V

AV_DD= 6.4 V

AV_DD= 6.5 V

32

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

AVDDCONFIG (02h)

The AVDDCONFIG register can be written to and read from.

Table 5. AVDDCONFIG Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

AVDD ILIM

SSI

FREQ1

LX1TS

Bit

These bits configure the falling speed of AVDD boost switch.

1-0

00

01

10

11

Tf = 0.5 V/ns

Tf = 0.7 V/ns

Tf = 0.9 V/ns

Tf = 1.1 V/ns

FREQ1

Bit

These bits configure the switching frequency of AVDD boost.

3-2

00

01

10

11

f_LX= 600 kHz

f_LX= 800 kHz

f_LX= 1000 kHz

fL_X= 1200 kHz

SSI

Bit

These bits configure the soft start duration for AVDD boost regulator

5-4

00

01

10

11

t_SS1= 20 ms

t_SS1= 40 ms

t_SS1= 60 ms

t_SS1= 80 ms

AVDD ILIM

Reserved

Bit

6

This bit select the AVDD boost current limite value

0

1

I_LIM= 1 A

I_LIM= 2 A

Bits

7

This bit is reserved for future use. During write operations data intended for these bits is ignored, and during

read operations 0 is returned.

Submit Documentation Feedback

33

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

VGHHOT (03h)

The VGHHOT register can be written to and read from.

Table 6. VGHHOT Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

VGHHOT

Bits

4-0

These bits select VGH output voltage at hot temperatures (VGHT=0) or all temperature range (VGHT=1).

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

N.A.

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

V_GHHOT= 22 V

V_GHHOT= 23 V

V_GHHOT= 24 V

V_GHHOT= 25 V

V_GHHOT= 26 V

V_GHHOT= 27 V

V_GHHOT= 28 V

V_GHHOT= 29 V

V_GHHOT= 30 V

V_GHHOT= 31 V

V_GHHOT= 32 V

V_GHHOT= 33 V

V_GHHOT= 34 V

V_GHHOT= 35 V

V_GHHOT= 36 V

V_GHHOT= 37 V

N.A.

V_GHHOT= 15 V

V_GHHOT= 16 V

V_GHHOT= 17 V

V_GHHOT= 18 V

V_GHHOT= 19 V

V_GHHOT= 20 V

V_GHHOT= 21 V

Reserved

Bits

7-5

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

VGHCOLD (04h)

The VGHCOLD register can be written to and read from.

Table 7. VGHCOLD Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

VGHCOLD

Bits

4-0

These bits select VGH output voltage at cold temperatures (VGHT=0)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

N.A.

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

V_GHCOLD= 22 V

V_GHCOLD= 23 V

V_GHCOLD= 24 V

V_GHCOLD= 25 V

V_GHCOLD= 26 V

V_GHCOLD= 27 V

V_GHCOLD= 28 V

V_GHCOLD= 29 V

V_GHCOLD= 30 V

V_GHCOLD= 31 V

V_GHCOLD= 32 V

V_GHCOLD= 33 V

V_GHCOLD= 34 V

V_GHCOLD= 35 V

V_GHCOLD= 36 V

V_GHCOLD= 37 V

N.A.

V_GHCOLD= 15 V

V_GHCOLD= 16 V

V_GHCOLD= 17 V

V_GHCOLD= 18 V

V_GHCOLD= 19 V

V_GHCOLD= 20 V

V_GHCOLD= 21 V

Reserved

Bits

7-5

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

34

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

VGHCONFIG (05h)

The VGHMISC register can be written to and read from.

Table 8. VGHCONFIG Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

FREQ4

SS4

LX4TS

Bit

These bits configure the falling speed of VGH boost switch.

1-0

00

01

10

11

Tf = 2.2 V/ns

Tf = 3.5 V/ns

Tf = 4.8 V/ns

Tf = 6 V/ns

SS4

Bit

These bits configure the soft start duration for VGH boost regulator

3-2

00

01

10

11

t_SS4= 4 ms

t_SS4= 8 ms

t_SS4= 12 ms

t_SS4= 16 ms

FREQ4

Bit

4

This bit configures the switching frequency of VGH boost regulator

0

1

F_{VGH_LX}= 400 kHz

F_{VGH_LX}= 800 kHz

Reserved

Bits

7-5

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

Submit Documentation Feedback

35

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

VGL (06h)

The VGL register can be written to and read from.

Table 9. VGL Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

VGL

Bits

5-0

These bits select VGL output voltage

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

N.A.

V_GL= –3.8 V

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

V_GL= –3.9 V

V_GL= –4.0 V

V_GL= –4.1 V

V_GL= –4.2 V

V_GL= –4.3 V

V_GL= –4.4 V

V_GL= –4.5 V

V_GL= –4.6 V

V_GL= –4.7 V

V_GL= –4.8 V

V_GL= –4.9 V

V_GL= –5.0 V

V_GL= –5.1 V

V_GL= –5.2 V

V_GL= –5.3 V

V_GL= –5.4 V

V_GL= –5.5 V

V_GL= –5.6 V

V_GL= –5.7 V

V_GL= –5.8 V

V_GL= –5.9 V

V_GL= –6.0 V

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

V_GL= –6.1 V

V_GL= –6.2 V

V_GL= –6.3 V

V_GL= –6.4 V

V_GL= –6.5 V

V_GL= –6.6 V

V_GL= –6.7 V

V_GL= –6.8 V

V_GL= –6.9 V

V_GL= –7.0 V

V_GL= –7.1 V

V_GL= –7.2 V

V_GL= –7.3 V

V_GL= –7.4 V

V_GL= –7.5 V

V_GL= –7.6 V

V_GL= –7.7 V

V_GL= –7.8 V

V_GL= –7.9 V

V_GL= –8.0 V

Reserved

Bits

7-6

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

36

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

V25 (07h)

The V25 register can be written to and read from.

Table 10. V25 Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

V25

Bits

3-0

These bits select V25 buck converter’s output voltage

0000

0001

0010

0011

0100

0101

0110

0111

V₂₅= 1.5 V

V₂₅= 1.6 V

V₂₅= 1.7 V

V₂₅= 1.8 V

V₂₅= 1.9 V

V₂₅= 2.0 V

V₂₅= 2.1 V

V₂₅= 2.2 V

1000

1001

1010

1011

1100

1101

1110

1111

V₂₅= 2.3 V

V₂₅= 2.4 V

V₂₅= 2.5 V

V₂₅= 2.6 V

V₂₅= 2.7 V

V₂₅= 2.8 V

V₂₅= 2.9 V

V₂₅= 3.0 V

Reserved

Bits

7-4

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

VDIV (08h)

The VDIV register can be written to and read from.

Table 11. VDIV Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

VDIV

Bits

3-0

These bits select the threshold voltage of the RESET signal

000

001

010

011

100

101

110

111

V_DIV= 1.2 V

V_DIV= 1.4 V

V_DIV= 1.6 V

V_DIV= 1.8 V

V_DIV= 2.0 V

V_DIV= 2.2 V

V_DIV= 2.4 V

V_DIV= 2.6 V

Reserved

Bits

7-4

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

Submit Documentation Feedback

37

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

RESET (09h)

The RESET register can be written to and read from.

Table 12. RESET Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

RESET

Bits

3-0

These bits select the RESET generate delay time period

0000

0001

0010

0011

0100

0101

0110

0111

T_RESET= 0 ms

T_RESET= 2 ms

T_RESET= 4 ms

T_RESET= 6 ms

T_RESET= 8 ms

T_RESET= 10 ms

T_RESET= 12 ms

T_RESET= 14 ms

1000

1001

1010

1011

1100

1101

1110

1111

T_RESET= 16 ms

T_RESET= 18 ms

T_RESET= 20 ms

T_RESET= 22 ms

T_RESET= 24 ms

T_RESET= 26 ms

T_RESET= 28 ms

T_RESET= 30 ms

Reserved

Bits

7-4

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

DLY (0Ah)

The DLY register can be written to and read from.

Table 13. DLY Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

DLY

Bits

1-0

These bits configure the gate voltage shaping delay time period

00

01

10

11

V_DLY= 0 ms

V_DLY= 20 ms

V_DLY= 40 ms

V_DLY= 60 ms

Reserved

Bits

7-2

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

38

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

VCOMHOT (0Bh)

The VCOMHOT1 register can be written to and read from.

Table 14. VCOMHOT Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VCOMHOT

Bits

These bits select VCOM output voltage at hot temperatures (VCOMT = 0) or all temperature range (VCOMT =

1).

VCOMR = 0

VCOMR = 1

00000000

00000001

00000010

…..

V_COMHOT= N.A

00100111

00101000

00101001

00101010

00101011

10111100

…..

V_COMHOT= 0.80 V V_COMHOT= 0.20 V

V_COMHOT= 0.82 V V_COMHOT= 0.18 V

V_COMHOT= 0.84 V V_COMHOT= 0.16 V

V_COMHOT= 0.86 V V_COMHOT= 0.14 V

V_COMHOT= 0.86 V V_COMHOT= 0.12 V

…..

11111101

11111110

11111111

V_COMHOT= 5.06 V V_COMHOT= –4.06 V

V_COMHOT= 5.08 V V_COMHOT= –4.08 V

V_COMHOT= 5.10 V V_COMHOT= –4.10 V

VCOMCOLD (0Ch)

The VCOMCOLD register can be written to and read from.

Table 15. VCOMCOLD Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VCOMCOLD

Bits

These bits select VCOM output voltage at cold temperatures (VCOMT=0)

VCOMR = 0

VCOMR = 1

00000000

00000001

00000010

…..

V_COMCOLD= N.A

00100111

00101000

00101001

00101010

00101011

10111100

…..

V_COMCOLD= 0.80 V V_COMCOLD= 0.20 V

V_COMCOLD= 0.82 V V_COMCOLD= 0.18 V

V_COMCOLD= 0.84 V V_COMCOLD= 0.16 V

V_COMCOLD= 0.86 V V_COMCOLD= 0.14 V

V_COMCOLD= 0.86 V V_COMCOLD= 0.12 V

…..

11111101

11111110

11111111

V_COMCOLD= 5.06 V V_COMCOLD= –4.06 V

V_COMCOLD= 5.08 V V_COMCOLD= –4.08 V

V_COMCOLD= 5.10 V V_COMCOLD= –4.10 V

Submit Documentation Feedback

39

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Control (FFh)

Table 16. Control Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WED

Reserved

RED

Bit

0

The state of this bit determines whether read operations return the contents of the DAC registers or the

contents of the E²PROM

0

1

Read operations return the contents of the DAC registers

Read operations return the contents of the E²PROM

Reserved

WED

Bits

6-1

These bits are reserved for future use. During write operations data intended for these bits is ignored, and

during read operations 0 is returned.

Bit

7

Setting this bit forces the contents of all DAC registers to be copied into E²PROM, thereby making them the

default values during power-up.

When the contents of all the DAC registers have been written to the E²PROM, the TPS65640 automatically

resets this bit.

40

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

Example – Writing to a Single RAM Register

1. Bus master sends START condition.

2. Bus master sends 7-bit slave address plus low R/W bit (E8h).

3. TPS65640 acknowledges.

4. Bus master sends address of RAM register (00h).

5. TPS65640 acknowledges.

6. Bus master sends data to be written.

7. TPS65640 acknowledges.

8. Bus master sends STOP condition.

E8h

00h

DATA

7-Bit Slave Address

RAM Register Address

RAM Register Data

S

0

A

A P

Figure 41. Writing to a Single RAM Register

Example – Writing to Multiple RAM Registers

1. Bus master sends START condition.

2. Bus master sends 7-bit slave address plus low R/W bit (E8h).

3. TPS65640 acknowledges.

4. Bus master sends address of first RAM register to be written to (00h).

5. TPS65640 acknowledges.

6. Bus master sends data to be written to first RAM register.

7. TPS65640 acknowledges.

8. Bus master sends data to be written to RAM register at next higher address (auto-increment).

9. TPS65640 acknowledges.

10. Steps (8) and (9) repeated until data for final RAM register has been sent.

11. TPS65640 acknowledges.

12. Bus master sends STOP condition.

E8h

00h

DATA

RAM Register Data (n+1)

7-Bit Slave Address

RAM Register Address (n)

RAM Register Data (n)

S

0

A

DATA

RAM Register Data (Last)

A

P

Figure 42. Writing to Multiple RAM Registers

Submit Documentation Feedback

41

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Example – Saving Contents of all RAM Registers to E²PROM

1. Bus master sends START condition.

2. Bus master sends 7-bit slave address plus low R/W bit (E8h).

3. TPS65640 acknowledges.

4. Bus master sends address of Control Register (FFh).

5. TPS65640 acknowledges.

6. Bus master sends data to be written to the Control Register (80h).

7. TPS65640 acknowledges.

8. Bus master sends STOP condition.

E8h

FFh

80h

7-Bit Slave Address

Control Register Address

Control Register Data

S

0

A

A P

Figure 43. Saving Contents of all RAM Registers to E²PROM

The TPS65640 needs 50ms time period after TPS65640 receiving STOP condition for saving all RAM registers

data to E²PROM. If bus master send 7-bit slave address to call TPS65640 again within 50ms period, the

TPS65640 will pull down the SCL line to LOW until the all RAM registers data saving to E²PROM is completed.

42

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

Example – Reading from a Single RAM Register

1. Bus master sends START condition.

2. Bus master sends 7-bit slave address plus low R/W bit (E8h).

3. TPS65640 acknowledges.

4. Bus master sends address of Control Register (FFh).

5. TPS65640 acknowledges.

6. Bus master sends data for Control Register (00h).

7. TPS65640 acknowledges.

8. Bus master sends STOP condition.

9. Bus master sends START condition.

10. Bus master sends 7-bit slave address plus low R/W bit (E8h).

11. TPS65640 acknowledges.

12. Bus master sends address of RAM register (00h).

13. TPS65640 acknowledges.

14. Bus master sends REPEATED START condition.

15. Bus master sends 7-bit slave address plus high R/W bit (E9h).

16. TPS65640 acknowledges.

17. TPS65640 sends RAM register data.

18. Bus master does not acknowledge.

19. Bus master sends STOP condition.

E8h

FFh

00h

7-Bit Slave Address

Control Register Address

Control Register Data

S

0

A

1

P

A

E8h

00h

E9h

DATA

7-Bit Slave Address

RAM Register Address

7-Bit Slave Address

RAM Register Data

A

Sr

A P

Figure 44. Reading from a Single RAM Register

Submit Documentation Feedback

43

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Example – Reading from a Single E²PROM Register

1. Bus master sends START condition.

2. Bus master sends 7-bit slave address plus low R/W bit (E8h).

3. TPS65640 acknowledges.

4. Bus master sends address of Control Register (FFh).

5. TPS65640 acknowledges.

6. Bus master sends data for Control Register (01h).

7. TPS65640 acknowledges.

8. Bus master sends STOP condition.

9. Bus master sends START condition.

10. Bus master sends 7-bit slave address plus low R/W bit (E8h).

11. TPS65640 acknowledges.

12. Bus master sends address of E²PROM register (00h).

13. TPS65640 acknowledges.

14. Bus master sends REPEATED START condition.

15. Bus master sends 7-bit slave address plus high R/W bit (E9h).

16. TPS65640 acknowledges.

17. TPS65640 sends E²PROM register data.

18. Bus master does not acknowledge.

19. Bus master sends STOP condition.

E8h

FFh

01h

7-Bit Slave Address

Control Register Address

Control Register Data

S

0

A

1

P

A

E8h

00h

E²PROM Register Address

E9h

DATA

E²PROM Register Data

7-Bit Slave Address

S

0

A

Sr

A P

Figure 45. Reading from a Single E²PROM Register

44

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

Example – Reading from Multiple RAM Registers

1. Bus master sends START condition.

2. Bus master sends 7-bit slave address plus low R/W bit (E8h).

3. TPS65640 acknowledges.

4. Bus master sends address of Control Register (FFh).

5. TPS65640 acknowledges.

6. Bus master sends data for Control Register (00h).

7. TPS65640 acknowledges.

8. Bus master sends STOP condition.

9. Bus master sends START condition.

10. Bus master sends 7-bit slave address plus low R/W bit (E8h).

11. TPS65640 acknowledges.

12. Bus master sends address of first register to be read (00h).

13. TPS65640 acknowledges.

14. Bus master sends REPEATED START condition.

15. Bus master sends 7-bit slave address plus high R/W bit (E9h).

16. TPS65640 acknowledges.

17. TPS65640 sends contents of first RAM register to be read.

18. Bus master acknowledges.

19. Bus master sends contents of second RAM register to be read.

20. Bus master acknowledges.

21. TPS65640 sends contents of third (last) RAM register to be read.

22. Bus master does not acknowledge.

23. Bus master sends STOP condition.

E8h

FFh

00h

7-Bit Slave Address

Control Register Address

Control Register Data

S

0

A

1

P

A

E8h

00h

E9h

DATA

7-Bit Slave Address

RAM Register Address (n)

7-Bit Slave Address

RAM Register Data (n)

S

0

A

Sr

A

P

DATA

RAM Register Data (Last)

RAM Register Data (n+1)

A

Figure 46. Reading from Multiple RAM Registers

Submit Documentation Feedback

45

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Example – Reading from Multiple E²PROM Registers

1. Bus master sends START condition.

2. Bus master sends 7-bit slave address plus low R/W bit (E8h).

3. TPS65640 acknowledges.

4. Bus master sends address of Control Register (FFh).

5. TPS65640 acknowledges.

6. Bus master sends data for Control Register (01h).

7. TPS65640 acknowledges.

8. Bus master sends STOP condition.

9. Bus master sends START condition.

10. Bus master sends 7-bit slave address plus low R/W bit (E8h).

11. TPS65640 acknowledges.

12. Bus master sends address of first E²PROM register to be read (00h).

13. TPS65640 acknowledges.

14. Bus master sends REPEATED START condition.

15. Bus master sends 7-bit slave address plus high R/W bit (E9h).

16. TPS65640 acknowledges.

17. TPS65640 sends contents of first E²PROM register to be read.

18. Bus master acknowledges.

19. Bus master sends contents of second E²PROM register to be read.

20. Bus master acknowledges.

21. TPS65640 sends contents of third (last) E²PROM register to be read.

22. Bus master does not acknowledge.

23. Bus master sends STOP condition.

E8h

FFh

01h

7-Bit Slave Address

Control Register Address

Control Register Data

S

0

A

1

P

A

E8h

00h

E²PROM Register Address (n)

E9h

DATA

E²PROM Register Data (n)

7-Bit Slave Address

S

0

A

Sr

A

P

DATA

E²PROM Register Data (n+1)

DATA

E²PROM Register Data (Last)

A

Figure 47. Reading from Multiple E²PROM Registers

46

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

Configuration Parameter VCOM

The VCOM register can be written to and read from.

Table 17. VCOM Register Bit Allocation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VCOM

P

Bit

0

During write operations, this bit determines the target for the data:

0 = Data written to E2PROM and RAM register

1 = Data written to RAM register only

During read operations this bit indicates whether the contents of the E2PROM and RAM register are the same

0 = E2PROM and RAM register contents are the same

1 = E2PROM and RAM register contents are different

VCOM

Bits

7-1

During write operations, these bits contain the data to be written.

During read operations, these bits return the contents of the RAM.

The factory default setting is 1000000.

Where VCOM is a 7-bit integer between 0 and 127 decimal.

Submit Documentation Feedback

47

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

Example – Writing a VCOM Value of 77h to VCOM Register Only

1. The bus master sends a START condition.

2. The bus Master sends (9E hexadecimal (7-bit slave address plus low R/W bit).

3. TPS65640 slave acknowledges.

4. The bus master sends EF hexadecimal (data to be written plus LSB = '1').

5. The TPS65640 slave acknowledges.

6. The bus master sends a STOP condition.

9Eh

EFh

7-Bit Slave Address

Data to be Written

S

0

A

1

A

P

Figure 48. Writing a VCOM Value of 77h to RAM Only

Example – Writing a VCOM Value of 77h to E²PROM and RAM

1. The bus master sends a START condition.

2. The bus Master sends 9E hexadecimal (7-bit slave address plus low R/W bit).

3. TPS65640 slave acknowledges.

4. The bus master sends EE hexadecimal (data to be written plus LSB = '0').

5. The TPS65640 slave acknowledges.

6. The bus master sends a STOP condition.

9Eh

EEh

7-Bit Slave Address

Data to be Written

S

0

A

0

A

P

Figure 49. Writing a VCOM Value of 77h to E²PROM and RAM

48

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

Example – Reading a VCOM Value of 77h from RAM when E²PROM Contents are Identical

1. The bus master sends a START condition.

2. The bus Master sends 9F hexadecimal (7-bit slave address plus low R/W bit).

3. TPS65640 slave acknowledges.

4. The bus master sends EE hexadecimal from E²PROM (data to be read plus LSB = '0').

5. The bus master does not acknowledge.

6. The bus master sends a STOP condition.

9Fh

EEh

7-Bit Slave Address

Data to be Read

S

1

A

0 A P

Figure 50. Reading 77h from RAM when E²PROM Contents are Identical

Example – Reading a VCOM Value of 77h from RAM when E²PROM Contents are Different

1. The bus master sends a START condition.

2. The bus Master sends 9F hexadecimal (7-bit slave address plus low R/W bit).

3. TPS65640 slave acknowledges.

4. The bus master sends EF hexadecimal from RAM (data to be read plus LSB = '1').

5. The bus master does not acknowledge.

6. The bus master sends a STOP condition.

9Fh

EFh

7-Bit Slave Address

Data to be Read

S

1

A

1 A P

Figure 51. Reading 77h from E²PROM when RAM Contents are Different

I²C INTERFACE

Configuration parameters and the V_COMvoltage setting are programmed via an industry standard I²C serial

interface. The TPS65640 always works as a slave device and supports standard (100kbps) and fast (400kbps)

modes of operation.

During write operations, all further attempts to access its slave addresses are ignored until the current write

operation has completed.

Submit Documentation Feedback

49

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

POWER SEQUENCY

Buck converter (V_25Buck) or the linear regulator (V_25LDO) start as soon as V_IN> V_UVLO

.

The reset generator holds RST low until t_RESETseconds after V₂₅has reached power good status.

Boost converter 1 starts after V₂₅reached power good status.

Boost converter 2 starts as soon as AV_DDhas reached power good status.

Figure 52 show the typical power-up/down characteristic of the TPS65640.

V_IN> V_UVLO

V₂₅< V_UVLO

V_IN

t_SS2

V₂₅> V_DIV

V₂₅< V_DIV

V₂₅

t_RESET

RST

AV_DD

V_GH

t_SS1

t_SS4

V_GL

t_DLY

V_GHM

Figure 52. Power-Up and Power-Down Sequencing

50

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

UNDERVOLTAGE LOCKOUT

An undervoltage lockout function disables the IC when the supply voltage is too low for proper operation. A low-

pass filter at the input of the UVLO comparator ensures that short transients on V_INdo not cause premature

shutdown of the IC.

Low Pass

VIN

Filter

UVLO

V_UVLO

Figure 53. Undervoltage Lockout Comparator with Low-Pass Filter

THERMAL SHUTDOWN

A thermal shutdown function automatically disables all functions if the device’s junction temperature exceeds the

safe maximum. The device automatically starts operating again once it has cooled down and operation may

safely continue. A restart after a thermal shutdown event follows the same sequence as following a normal

power-up condition (see Figure 52).

Submit Documentation Feedback

51

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

SLVSCE2 –NOVEMBER 2013

www.ti.com

APPLICATION INFORMATION

10 µH

2.5 V~5.5 V

AV_DD

V_IN

10 µF

LX

BOOST

AVDD

COMP

VIN

200 kΩ

1 nF

10 µF

CONVERTER 1

AV_DD

10 µH

BOOST

10 kΩ @ 25°C

R1

V_GH

CONVERTER 2

VT

VGH_LX

4.7 µF

R2

VGH

FLK

RE

GATE

VOLTAGE SHAPING

V_GHM

VGHM

R_E

µH

4.7

V₂₅

V25_LX

V25

LX

BUCK/LDO

10µF

CONVERTER

V₂₅

10 kΩ

220 nF

RESET

To T_CON

RESET

GENERATOR

100 kΩ

1µF

DRVN

VGL

NEGATIVE

LINEAR REGULATOR

V_GL

1µF

SDA

SCL

I²C INTERFACE

PROGRAMMABLE

VCOM

VCOM_OUT

BUFFER

VINA+

VINA-

VINB+

VINB-

OPERATIONAL

AMPLIFIER

VOUTA

VOUTB

PGND

AGND

Figure 54. Typical Application Circuit

52

Submit Documentation Feedback

Product Folder Links: TPS65640

TI INFORMATION – SELECTIVE DISCLOSURE

TPS65640

www.ti.com

SLVSCE2 –NOVEMBER 2013

LAYOUT RECOMMENDATION

As for all switching power supplies, especially those providing high current and using high switching frequencies,

layout is an important design step. If layout is not carefully done, the regulator could show instability as well as

EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor in the typical

application circuit, should also be placed close to the VIN pin, but also to the GND in order to reduce the input

ripple seen by the IC. The LX pin carries high current with fast rising and falling edges. Therefore, the connection

between the pin to the inductor and schottky diode should be kept as short and wide as possible. It is also

beneficial to have the ground of the output capacitor for both Boost converter 1, Boost converter 2 and Buck

converter close to the PGND pin since there is a large ground return current flowing between them. When laying

out signal grounds, it is recommended to use short traces separated from power ground traces, and connect

them together at a single point, for example on the thermal pad. The thermal pad needs to be soldered on to the

PCB and connected to the GND pin of the IC. An additional thermal via can significantly improve power

dissipation of the IC.

VIN

V25

PGND

VIN

PGND

AVDD

24 23 22 21 20 109 18 17 16 15

25

14

13

12

11

PGND

26

27

28

PGND

1

2

3

4

5

56

7

8

9 10

VGH

PGND

Submit Documentation Feedback

53

Product Folder Links: TPS65640

GENERIC PACKAGE VIEW

RHR 28

3.5 x 5.5, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4210249/B

www.ti.com

PACKAGE OUTLINE

RHR0028A

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

3.6

3.4

B

A

PIN 1 INDEX AREA

0.5

0.3

5.6

5.4

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

C

SEATING PLANE

0.08

0.05

0.00

2±0.1

2X 1.5

(0.2) TYP

EXPOSED

THERMAL PAD

11

14

24X 0.5

10

15

2X

4.5

4±0.1

SEE TERMINAL

DETAIL

1

24

0.3

28X

28

25

0.5

0.2

PIN 1 ID

(OPTIONAL)

0.1

C A

B

28X

0.3

0.05

4219075/A 11/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHR0028A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2)

SYMM

28X (0.6)

28X (0.25)

25

28

1

24

24X (0.5)

(0.66)

(5.3)

TYP

SYMM

(4)

(

0.2) TYP

VIA

15

10

11

14

(0.75) TYP

(3.3)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219075/A 11/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RHR0028A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.55) TYP

28

25

28X (0.6)

28X (0.25)

1

24

24X (0.5)

SYMM

(1.32)

TYP

(5.3)

METAL

TYP

6X (1.12)

15

10

14

11

6X (0.89)

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4219075/A 11/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65640
厂家：	TEXAS INSTRUMENTS
描述：	用于笔记本 PC 和平板 PC 的具有数字 VCOM 缓冲器的 LCD 偏置 PC CD
文件：	总62页 (文件大小：3586K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65640 [TI]

相关型号：

TPS65640RHRR

TPS65642

TPS65642A

TPS65642AYFFR

TPS65642YFF

TPS65642YFFR

TPS65642YFFT

TPS65651-1/2/3

TPS65653-Q1

TPS6565342RHDRQ1

TPS6565342RHDTQ1

TPS65680