TPS79601DCQ [TI]
ULTRALOW-NOISE, HIGH PSRR, FAST RF 1-A LOW-DROPOUT LINEAR REGULATORS; 超低噪声，高PSRR ，快速射频1 -A低压差线性稳压器
| 型号： | TPS79601DCQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ULTRALOW-NOISE, HIGH PSRR, FAST RF 1-A LOW-DROPOUT LINEAR REGULATORS |
| 文件： | 总18页 (文件大小：548K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
ULTRALOW-NOISE, HIGH PSRR, FAST RF 1-A
LOW-DROPOUT LINEAR REGULATORS
FEATURES
DESCRIPTION
•
1-A Low-Dropout Regulator With Enable
The TPS796xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power supply rejection ratio (PSRR), ultralow-noise,
fast start-up, and excellent line and load transient
responses in small outline, 3 x 3 SON, SOT223-6,
and 5-pin DDPAK packages. Each device in the
family is stable with a small 1-µF ceramic capacitor
on the output. The family uses an advanced, pro-
prietary BiCMOS fabrication process to yield ex-
tremely low dropout voltages (e.g., 250 mV at 1 A).
•
Available in 1.8-V, 2.5-V, 2.8-V, 3-V, 3.3-V, and
Adjustable (1.2-V to 5.5-V)
•
•
•
•
•
•
High PSRR (53 dB at 10 kHz)
Ultralow-Noise (40 µVRMS, TPS79630)
Fast Start-Up Time (50 µs)
Stable With a 1-µF Ceramic Capacitor
Excellent Load/Line Transient Response
Each device achieves
fast
start-up times
Very Low Dropout Voltage (250 mV at Full
Load, TPS79630)
(approximately 50 µs with a 0.001-µF bypass capaci-
tor) while consuming very low quiescent current
(265 µA typical). Moreover, when the device is placed
in standby mode, the supply current is reduced to
less than 1 µA. The TPS79630 exhibits approximately
40 µVRMS of output voltage noise at 3.0-V output, with
a 0.1-µF bypass capacitor. Applications with analog
components that are noise sensitive, such as portable
RF electronics, benefit from the high PSRR, low
noise features, and the fast response time.
•
3 x 3 SON, 6-Pin SOT223-6, and
5-Pin DDPAK Packages
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth™, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
DCQ PACKAGE
SOT223-6
(TOP VIEW)
DRB PACKAGE
3 x 3 SON
(TOP VIEW)
TPS79630
RIPPLE REJECTION
vs
TPS79630
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
0.7
IN
IN
1
2
3
4
FREQUENCY
8
7
6
5
EN
1
2
3
4
5
EN
IN
GND
OUT
NR/FB
NC
80
70
60
50
40
30
20
10
0
6
GND
V
= 4 V
V
C
C
= 5.5 V
IN
OUT
OUT
GND
NR
IN
0.6
0.5
0.4
0.3
0.2
0.1
0.0
C
C
= 10 µF
= 2.2 µF
OUT
= 0.01 µF
OUT
= 0.1 µF
NR
I
= 1 mA
OUT
NR
I
= 1 A
OUT
KTT (DDPAK) PACKAGE
(TOP VIEW)
I
= 1 mA
OUT
EN
IN
GND
OUT
NR/FB
1
2
I
= 1.5 A
1k
3
4
OUT
1
10 100
1k 10k 100k 1M 10M
100
10k
100k
5
Frequency (Hz)
Frequency (Hz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
TRANSPORT
MEDIA, QUANTITY
PRODUCT
VOLTAGE
PACKAGE
TJ
SYMBOL
PART NUMBER
TPS79601DCQ
TPS79601DCQR
TPS79601KTTT
TPS79601KTTR
TPS79618DCQ
TPS79618DCQR
TPS79618KTTT
TPS79618KTTR
TPS79625DCQ
TPS79625DCQR
TPS79625KTTT
TPS79625KTTR
TPS79628DCQ
TPS79628DCQR
TPS79628KTTT
TPS79628KTTR
TPS79628DRB
TPS79628DRBR
TPS79628DRBG4
TPS79628DRBG4R
TPS79630DCQ
TPS79630DCQR
TPS79630KTTT
TPS79630KTTR
TPS79633DCQ
TPS79633DCQR
TPS79633KTTT
TPS79633KTTR
Tube, 78
SOT223-6
PS79601
Tape and Reel, 2500
Reel, 50
TPS79601
1.2 to 5.5 V
DDPAK
SOT223-6
DDPAK
TPS79601
PS79618
TPS79618
PS79625
TPS79625
PS79628
TPS79628
Reel, 500
Tube, 78
Tape and Reel, 2500
Reel, 50
TPS79618
TPS79625
1.8 V
2.5 V
Reel, 500
Tube, 78
SOT223-6
DDPAK
Tape and Reel, 2500
Reel, 50
Reel, 500
Tube, 78
SOT223-6
DDPAK
Tape and Reel, 2500
Reel, 50
-40°C to +125°C
Reel, 500
TPS79628
2.8 V
Tube, 78
Tape and Reel, 2500
Tube, 78
3 x 3 SON
AMI
Tape and Reel, 2500
Tube, 78
SOT223-6
DDPAK
PS79630
TPS79630
PS79633
TPS79633
Tape and Reel, 2500
Reel, 50
TPS79630
TPS79633
3 V
Reel, 500
Tube, 78
SOT223-6
DDPAK
Tape and Reel, 2500
Reel, 50
3.3 V
Reel, 500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet.
2
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted)(1)
UNIT
VIN range
-0.3 V to 6 V
-0.3 V to VIN + 0.3 V
6 V
VEN range
VOUT range
Peak output current
ESD rating, HBM
Internally limited
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
See Dissipation Ratings Table
-40°C to 150°C
-65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
PACKAGE
DDPAK
BOARD
High-K(1)
Low-K(2)
RΘJC
RΘJA
2 °C/W
15 °C/W
23 °C/W
53 °C/W
56.2 °C/W
SOT223
3 x 3 SON
(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce
copper traces on top of the board.
3
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating temperature range (TJ = -40 to 125°C), VEN = VIN,, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,
COUT = 10 µF, CNR = 0.01 µF (unless otherwise noted). Typical values are at +25°C.
PARAMETER
VIN Input voltage(1)
IOUT Continuous output current(1)
TEST CONDITIONS
MIN TYP
MAX
5.5
UNIT
2.7
0
V
A
V
1
TPS79618
TPS79625
TPS79628
TPS79630
TPS79633
0 µA < IOUT < 1 A
2.8 V < VIN < 5.5 V
3.5 V < VIN < 5.5 V
3.8 V < VIN < 5.5 V
4 V < VIN < 5.5 V
4.3 V < VIN < 5.5 V
1.764
1.8
2.5
2.8
3.0
3.3
0.05
5
1.836
2.55
2.856
3.06
3.366
0.12
0 µA < IOUT < 1 A
0 µA < IOUT < 1 A
0 µA < IOUT < 1 A
0 µA < IOUT < 1 A
VOUT + 1 V < VIN ≤ 5.5 V
0 µA < IOUT < 1 A
IOUT = 1 A
2.45
2.744
2.94
Output voltage
V
3.234
(1)
Output voltage line regulation (∆VOUT%/VIN
)
%/V
mV
Load regulation (∆VOUT%/∆IOUT
)
TJ = 25°C
270
67
365
90
TPS79628
(2)
IOUT = 250 mA
IOUT = 1 A
Dropout voltage
mV
(VIN = VOUT (nom) - 0.1V)
TPS79630
TPS79633
250
220
345
325
4.2
385
1
IOUT = 1 A
Output current limit
Ground pin current
Shutdown current(3)
FB pin current
VOUT = 0 V
2.4
A
0 µA < IOUT < 1 A
VEN = 0 V, 2.7 V < VIN < 5.5 V
FB = 1.8 V
265
µA
µA
µA
0.07
1
f = 100 Hz
IOUT = 10 mA
IOUT = 1 A
59
54
53
42
54
46
41
40
50
75
110
f = 100 Hz
Power-supply ripple rejection
TPS79630
dB
f = 10 Hz
IOUT = 1 A
f = 100 Hz
IOUT = 1 A
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
CNR = 0.1 µF
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
BW = 100 Hz to 100 kHz,
IOUT = 1 A
Output noise voltage (TPS79630)
Time, start-up (TPS79630)
µVRMS
RL = 3 Ω, COUT = 1 µF
µs
EN pin current
VEN = 0V
-1
1.7
0
1
VIN
0.7
µA
V
High-level enable input voltage
Low-level enable input voltage
2.7 V < VIN < 5.5 V
2.7 V < VIN < 5.5 V
V
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
(2) VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7V.
(3) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
4
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
IN
OUT
Current
Sense
UVLO
SHUTDOWN
ILIM
R
1
_
GND
EN
+
FB
UVLO
R
2
Thermal
Shutdown
Quickstart
External to
the Device
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
IN
OUT
UVLO
Current
Sense
GND
EN
SHUTDOWN
ILIM
R
1
_
+
UVLO
Thermal
Shutdown
R
2
Quickstart
R = 40k
2
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
NR
Table 1. Terminal Functions
TERMINAL
DESCRIPTION
NAME
ADJ
FIXED
NR
N/A
5
Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This improves
power-supply rejection and reduces output noise.
EN
1
1
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. EN can be connected to IN if not used.
FB
5
N/A
This terminal is the feedback input voltage for the adjustable device.
GND
IN
3, Tab
3, Tab Regulator ground
2
4
2
4
Unregulated input to the device.
Output of the regulator.
OUT
5
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
TPS79630
OUTPUT VOLTAGE
vs
TPS79628
OUTPUT VOLTAGE
vs
TPS79628
GROUND CURRENT
vs
OUTPUT CURRENT
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.795
350
340
330
320
310
300
290
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
V
C
= 4 V
= 10 µF
OUT
= 25°C
V
C
= 3.8 V
V
= 3.8 V
IN
IN
IN
= 10 µF
C
OUT
= 10 µF
OUT
T
J
I
= 1 mA
OUT
2.790
2.785
I
= 1 A
I
= 1 A
OUT
OUT
2.780
I
= 1 mA
OUT
2.775
0.0
0.2
0.4
0.6
(A)
0.8
1.0
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
I
T
J
T
J
OUT
Figure 1.
Figure 2.
Figure 3.
TPS79630
TPS79630
TPS79630
OUTPUT SPECTRAL NOISE DEN-
OUTPUT SPECTRAL NOISE DEN-
OUTPUT SPECTRAL NOISE DEN-
SITY
vs
FREQUENCY
SITY
vs
FREQUENCY
SITY
vs
FREQUENCY
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.5
2.0
1.5
1.0
0.5
0.0
V
C
C
= 5.5 V
V
C
C
= 5.5 V
V
C
= 5.5 V
IN
IN
IN
= 2.2 µF
= 10 µF
= 10 µF
OUT
= 0.1 µF
OUT
= 0.1 µF
OUT
I = 1 A
OUT
NR
NR
C
NR
= 0.01 µF
C
NR
= 0.1 µF
I
= 1 mA
OUT
C
NR
= 0.0047 µF
I
= 1 mA
OUT
C
= 0.001 µF
NR
I
= 1 A
OUT
I
= 1.5 A
1k
OUT
100
10k
100k
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 4.
Figure 5.
Figure 6.
6
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS79630
ROOT MEAN SQUARED OUTPUT
TPS79628
DROPOUT VOLTAGE
vs
TPS79630
RIPPLE REJECTION
vs
NOISE
vs
BYPASS CAPACITANCE
JUNCTION TEMPERATURE
FREQUENCY
60
50
40
30
20
10
0
350
300
250
200
150
100
50
80
V
C
= 2.7 V
= 10 µF
OUT
= 1 A
V
C
C
= 4 V
IN
IN
70
60
50
40
30
20
10
0
= 10 µF
OUT
= 0.01 µF
I
= 1 mA
I
OUT
OUT
NR
I
= 1 A
OUT
I
C
= 250 mA
= 10 µF
OUT
OUT
BW = 100 Hz to 100 kHz
0
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
0.001 µF
0.0047 µF
0.01 µF
(µF)
0.1 µF
1
10
100
1k 10k 100k 1M 10M
C
NR
T
J
Frequency (Hz)
Figure 7.
Figure 8.
Figure 9.
TPS79630
RIPPLE REJECTION
vs
TPS79630
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
START-UP TIME
3
2.75
2.50
2.25
2
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
V
= 4 V,
= 10 µF,
IN
V
C
C
= 4 V
V
C
C
= 4 V
IN
= 2.2 µF
OUT
= 0.01 µF
NR
IN
C
=
NR
C
OUT
I = 1.0 A
OUT
= 10 µF
OUT
= 0.1 µF
0.0047 µF
I
= 1 mA
I
= 1 mA
OUT
OUT
NR
Enable
C
=
NR
0.001 µF
I
= 1 A
I
= 1 A
OUT
OUT
1.75
1.50
1.25
1
C
=
NR
0.01 µF
0.75
0.50
0.25
0
0
1
0
100
200
300
400
500
600
10
100
1k 10k 100k 1M 10M
1
10
100
1k 10k 100k 1M 10M
t (ns)
Frequency (Hz)
Frequency (Hz)
Figure 10.
TPS79618
Figure 11.
Figure 12.
TPS79630
LINE TRANSIENT RESPONSE
TPS79628
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
5
4
6
5
4
3
2
1
3
0
I
C
C
= 1 A
V
C
C
= 3.8 V
IN
= 10 µF
OUT
= 0.01 µF
NR
OUT
dv
dt
dv
dt
di
dt
1 V
ms
1 V
ms
1 A
ms
2
−1
I
C
C
= 1 A
= 10 µF
OUT
= 0.01 µF
OUT
+
+
+
= 10 µF
OUT
= 0.01 µF
NR
40
20
40
20
150
75
NR
0
0
0
−20
−40
−20
−40
−75
−150
0
0
20 40 60 80 100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200
100 200 300 400 500 600 700 800 900 1000
t (µs)
t (µs)
t (µs)
Figure 13.
Figure 14.
Figure 15.
7
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS79630
DROPOUT VOLTAGE
vs
TPS79601
DROPOUT VOLTAGE
vs
TPS79625
POWER UP/POWER DOWN
OUTPUT CURRENT
INPUT VOLTAGE
300
250
200
150
100
50
4.0
3.5
3.0
2.5
350
300
250
200
150
100
50
V
R
C
= 2.5 V
= 10 Ω
= 0.01 µF
OUT
L
NR
T
J
= 125°C
T
= 125°C
J
T
= 25°C
J
T
J
= 25°C
2.0
1.5
1.0
0.5
0
T
= −40°C
J
V
IN
T
J
= −40°C
I
C
C
= 1 A
= 10 µF
OUT
= 0.01 µF
OUT
V
OUT
NR
0
0
0
1
2
3
4
5
6
7
8
9
10
0
100 200 300 400 500 600 700 800 9001000
(mA)
2.5
3.0
3.5
4.0
4.5
5.0
I
V
(V)
IN
200 µs/Div
OUT
Figure 16.
Figure 17.
Figure 18.
TPS79630
TPS79630
TPS79630
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
EQUIVALENT SERIES RESISTANCE
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
(ESR)
vs
(ESR)
vs
OUTPUT CURRENT
OUTPUT CURRENT
OUTPUT CURRENT
100
100
10
100
10
C
OUT
= 10.0 µF
C
OUT
= 1 µF
C
OUT
= 2.2 µF
Region of
Instability
Region of
Instability
10
Region of
Instability
1
0.1
1
0.1
1
0.1
Region of Stability
Region of Stability
Region of Stability
0.01
1
10 30 60 125 250 500 750 1000
(mA)
0.01
0.01
I
OUT
1
10 30 60 125 250 500 750 1000
(mA)
1
10 30 60 125 250 500 750 1000
(mA)
I
I
OUT
OUT
Figure 19.
Figure 20.
Figure 21.
8
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
APPLICATION INFORMATION
The TPS796xx family of low-dropout (LDO) regulators
has been optimized for use in noise-sensitive equip-
ment. The device features extremely low dropout
voltages, high PSRR, ultralow output noise, low
quiescent current (265 µA typically), and enable input
to reduce supply currents to less than 1 µA when the
regulator is turned off.
For example, the TPS79630 exhibits 40 µVRMS of
output voltage noise using a 0.1-µF ceramic bypass
capacitor and a 10-µF ceramic output capacitor. Note
that the output starts up slower as the bypass
capacitance increases due to the RC time constant at
the bypass pin that is created by the internal 250-kΩ
resistor and external capacitor.
A typical application circuit is shown in Figure 22.
Board Layout Recommendation to Improve
PSRR and Noise Performance
VIN
VOUT
IN
OUT
TPS796xx
GND
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
2.2µF
1 µF
EN
NR
µ
0.01 F
Figure 22. Typical Application Circuit
External Capacitor Requirements
Regulator Mounting
Although not required, it is good analog design
practice to place a 0.1-µF — 2.2-µF capacitor near
the input of the regulator to counteract reactive input
sources. A 2.2-µF or larger ceramic input bypass
capacitor, connected between IN and GND and
located close to the TPS796xx, is required for stability
and improves transient response, noise rejection, and
ripple rejection. A higher-value input capacitor may be
necessary if large, fast-rise-time load transients are
anticipated and the device is located several inches
from the power source.
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat dissipation.
Solder pad footprint recommendations for the devices
are presented in an application bulletin Solder Pad
Recommendations for Surface-Mount Devices, litera-
ture number AB-132, available for download from the
TI web site (www.ti.com).
Like most low dropout regulators, the TPS796xx
requires an output capacitor connected between OUT
and GND to stabilize the internal control loop. The
minimum recommended capacitance is 1 µF. Any
1 µF or larger ceramic capacitor is suitable.
Programming the TPS79601 Adjustable LDO
Regulator
The output voltage of the TPS79601 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 28. The output voltage is
calculated using Equation 1:
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS796xx has an NR
pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
internal resistor, in conjunction with an external by-
pass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
order for the regulator to operate properly, the current
flow out of the NR pin must be at a minimum,
because any leakage current creates an IR drop
across the internal resistor, thus creating an output
error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor
should be no more than 0.1-µF in order to ensure that
it is fully charged during the quickstart time provided
by the internal switch shown in the functional block
diagram.
R1
R2
ǒ1 ) Ǔ
V
+ V
O
REF
(1)
where:
•
VREF = 1.2246 V typ (the internal reference
voltage)
Resistors R1 and R2 should be chosen for approxi-
mately 40-µA divider current. Lower value resistors
can be used for improved noise performance, but the
device wastes more power. Higher values should be
avoided, as leakage current at FB increases the
output voltage error.
9
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 40 µA, C1 =
15 pF for stability, and then calculate R1 using
Equation 2:
Regulator Protection
The TPS796xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (e.g.,
during power down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting might be appropriate.
V
O
R1 +
* 1 R2
ǒ Ǔ
V
REF
(2)
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB. The
approximate value of this capacitor can be calculated
as Equation 3:
The TPS796xx features internal current limiting and
thermal protection. During normal operation, the
TPS796xx limits output current to approximately 2.8
A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition
ends. While current limiting is designed to prevent
gross device failure, care should be taken not to
exceed the power dissipation ratings of the package.
If the temperature of the device exceeds approxi-
mately 165°C, thermal-protection circuitry shuts it
down. Once the device has cooled down to below
approximately 140°C, regulator operation resumes.
–7
(3 x 10 ) x (R1 ) R2)
C1 +
(R1 x R2)
(3)
The suggested value of this capacitor for several
resistor ratios is shown in the table below (see
Figure 23). If this capacitor is not used (such as in a
unity-gain configuration) then the minimum rec-
ommended output capacitor is 2.2 µF instead of 1 µF.
OUTPUT VOLTAGE
VOUT
VIN
PROGRAMMING GUIDE
IN
OUT
TPS79601
R1
R2
C1
OUTPUT
VOLTAGE
2.2 µF
EN
NR
1 µF
R1
R2
C1
GND
F
FB
1.8 V
3.6V
14.0 kΩ 30.1 kΩ
33 pF
µ
0.01
57.9 kΩ 30.1 kΩ 15 pF
Figure 23. TPS79601 Adjustable LDO Regulator Programming
10
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
THERMAL INFORMATION
temperature due to the regulator's power dissipation.
The temperature rise is computed by multiplying the
maximum expected power dissipation by the sum of
the thermal resistances between the junction and the
case (RΘJC), the case to heatsink (RΘCS), and the
heatsink to ambient (RΘSA). Thermal resistances are
measures of how effectively an object dissipates
heat. Typically, the larger the device, the more
surface area available for power dissipation and the
lower the object's thermal resistance.
The amount of heat that an LDO linear regulator
generates is directly proportional to the amount of
power it dissipates during operation. All integrated
circuits have a maximum allowable junction tempera-
ture (TJmax) above which normal operation is not
assured.
A
system designer must design the
operating environment so that the operating junction
temperature (TJ) does not exceed the maximum
junction temperature (TJmax). The two main environ-
mental variables that a designer can use to improve
thermal performance are air flow and external
heatsinks. The purpose of this information is to aid
the designer in determining the proper operating
environment for a linear regulator that is operating at
a specific power level.
Figure 24 illustrates these thermal resistances for (a)
a SOT223 package mounted in a JEDEC low-K
board, and (b) a DDPAK package mounted on a
JEDEC high-K board.
Equation 5 summarizes the computation:
In general, the maximum expected power (PD(max)
consumed by a linear regulator is computed as
Equation 4:
)
) P max x ǒR
θSAǓ
T
+ T
) R
) R
D
J
A
θJC
θCS
(5)
max + ǒVI(avg)
Ǔ
P
* V
I
) V
x I
The RΘJC is specific to each regulator as determined
by its package, lead frame, and die size provided in
the regulator's data sheet. The RΘSA is a function of
the type and size of heatsink. For example, black
body radiator type heatsinks can have RΘCS values
ranging from 5°C/W for very large heatsinks to
50°C/W for very small heatsinks. The RΘCS is a
function of how the package is attached to the
heatsink. For example, if a thermal compound is used
to attach a heatsink to a SOT223 package, RΘCS of
1°C/W is reasonable.
D
O(avg)
O(avg)
I(avg) (Q)
(4)
where:
•
•
•
•
VI(avg) is the average input voltage.
VO(avg) is the average output voltage.
IO(avg) is the average output current.
I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is
insignificant compared to the average output current;
therefore, the term VI(avg) x I(Q) can be neglected. The
operating junction temperature is computed by adding
the ambient temperature (TA) and the increase in
T
J
A
A
CIRCUIT BOARD COPPER AREA
R
θ
JC
B
C
T
C
B
B
R
R
θ
CS
A
C
θ
SA
C
DDPAK Package
(b)
SOT223 Package
(a)
T
A
Figure 24. Thermal Resistances
11
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
Even if no external black body radiator type heatsink
is attached to the package, the board on which the
regulator is mounted provides some heatsinking
through the pin solder connections. Some packages,
like the DDPAK and SOT223 packages, use a copper
plane underneath the package or the circuit board's
ground plane for additional heatsinking to improve
their thermal performance. Computer-aided thermal
modeling can be used to compute very accurate
approximations of an integrated circuit's thermal per-
formance in different operating environments (e.g.,
different types of circuit boards, different types and
sizes of heatsinks, and different air flows, etc.). Using
these models, the three thermal resistances can be
combined into one thermal resistance between junc-
tion and ambient (RΘJA). This RΘJA is valid only for the
specific operating environment used in the computer
model.
R
max + (125 * 55)°Cń2.5 W + 28°CńW
θJA
(9)
From Figure 25, DDPAK Thermal Resistance vs
Copper Heatsink Area, the ground plane needs to be
1 cm2 for the part to dissipate 2.5 W. The operating
environment used in the computer model to construct
Figure 25 consisted of a standard JEDEC High-K
board (2S2P) with a 1 oz. internal copper plane and
ground plane. The package is soldered to a 2 oz.
copper pad. The pad is tied through thermal vias to
the 1 oz. ground plane. Figure 26 shows the side
view of the operating environment used in the com-
puter model.
40
No Air Flow
35
Equation 5 simplifies into Equation 6:
150 LFM
30
T
+ T ) P max x R
D
J
A
θJA
(6)
Rearranging Equation 6 gives Equation 7:
T –T
250 LFM
25
J
A
R
+
θJA
P max
D
(7)
Using Equation 6 and the computer model generated
curves shown in Figure 25 and Figure 28, a designer
can quickly compute the required heatsink thermal
resistance/board area for a given ambient tempera-
ture, power dissipation, and operating environment.
20
15
0.1
1
10
100
2
Copper Heatsink Area − cm
DDPAK Power Dissipation
The DDPAK package provides an effective means of
managing power dissipation in surface mount appli-
cations. The DDPAK package dimensions are pro-
vided in the Mechanical Data section at the end of
the data sheet. The addition of a copper plane
directly underneath the DDPAK package enhances
the thermal performance of the package.
Figure 25. DDPAK Thermal Resistance vs Copper
Heatsink Area
2 oz. Copper Solder Pad
with 25 Thermal Vias
1 oz. Copper
Power Plane
To illustrate, the TPS72525 in a DDPAK package
was chosen. For this example, the average input
voltage is 5 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient tempera-
ture 55°C, the air flow is 150 LFM, and the operating
environment is the same as documented below.
Neglecting the quiescent current, the maximum aver-
age power is calculated as Equation 8:
1 oz. Copper
Ground Plane
Thermal Vias, 0.3 mm
Diameter, 1,5 mm Pitch
Figure 26. DDPAK Thermal Resistance
(
)
P max
5
2.5 V x 1 A
2.5 W
D
(8)
Substituting TJmax for TJ into Equation 6 gives
Equation 9:
From the data in Figure 27 and rearranging
Equation 6, the maximum power dissipation for a
different ground plane area and a specific ambient
temperature can be computed.
12
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
5
180
160
No Air Flow
T
A
= 55°C
140
120
100
250 LFM
4
3
150 LFM
80
60
No Air Flow
2
40
20
0
1
0.1
1
10
0.1
1
10
100
2
2
PCB Copper Area − in
Copper Heatsink Area − cm
Figure 28. SOT223 Thermal Resistance vs PCB
Area
Figure 27. Maximum Power Dissipation vs Copper
Heatsink Area
From the data in Figure 28 and rearranging
Equation 6, the maximum power dissipation for a
different ground plane area and a specific ambient
temperature can be computed (see Figure 29).
SOT223 Power Dissipation
The SOT223 package provides an effective means of
managing power dissipation in surface mount appli-
cations. The SOT223 package dimensions are pro-
vided in the Mechanical Data section at the end of
the data sheet. The addition of a copper plane
directly underneath the SOT223 package enhances
the thermal performance of the package.
6
T
A
= 25°C
5
4
To illustrate, the TPS72525 in a SOT223 package
was chosen. For this example, the average input
voltage is 3.3 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient tempera-
ture 55°C, no air flow is present, and the operating
environment is the same as documented below.
Neglecting the quiescent current, the maximum aver-
age power is calculated as Equation 10:
2
4 in PCB Area
3
2
2
0.5 in PCB Area
(
)
P max
3.3
2.5 V x 1 A
800 mW
D
(10)
1
0
Substituting TJmax for TJ into Equation 6 gives
Equation 11:
R
max + (125 * 55)°Cń800 mW + 87.5°CńW
0
25
50
75
100
125
150
θJA
(11)
T
A
(°C)
From Figure 28, RΘJA vs PCB Copper Area, the
ground plane needs to be 0.55 in2 for the part to
dissipate 800 mW. The operating environment used
to construct Figure 28 consisted of a board with 1 oz.
copper planes. The package is soldered to a 1 oz.
copper pad on the top of the board. The pad is tied
through thermal vias to the 1 oz. ground plane.
Figure 29. SOT223 Power Dissipation
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOP
SOP
Drawing
TPS79601DCQ
TPS79601DCQR
TPS79601KTT
ACTIVE
ACTIVE
DCQ
6
6
5
78
None
None
None
Call TI
Call TI
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
DCQ
2500
OBSOLETE DDPAK/
TO-263
KTT
TPS79601KTTR
TPS79601KTTT
ACTIVE
DDPAK/
TO-263
KTT
KTT
5
5
500
50
None
None
Call TI
Call TI
Level-3-240C-168 HR
Level-3-240C-168 HR
ACTIVE
DDPAK/
TO-263
TPS79618DCQ
TPS79618DCQR
TPS79618KTT
ACTIVE
ACTIVE
SOP
SOP
DCQ
DCQ
KTT
6
6
5
78
None
None
None
Call TI
Call TI
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
2500
OBSOLETE DDPAK/
TO-263
TPS79618KTTR
TPS79618KTTT
ACTIVE
DDPAK/
TO-263
KTT
KTT
5
5
500
50
None
None
Call TI
Call TI
Level-3-240C-168 HR
Level-3-240C-168 HR
ACTIVE
DDPAK/
TO-263
TPS79625DCQ
TPS79625DCQR
TPS79625KTT
ACTIVE
ACTIVE
SOP
SOP
DCQ
DCQ
KTT
6
6
5
78
None
None
None
Call TI
Call TI
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
2500
OBSOLETE DDPAK/
TO-263
TPS79625KTTR
TPS79625KTTT
ACTIVE
DDPAK/
TO-263
KTT
KTT
5
5
500
50
None
None
Call TI
Call TI
Level-3-240C-168 HR
Level-3-240C-168 HR
ACTIVE
DDPAK/
TO-263
TPS79628DCQ
TPS79628DCQR
TPS79628KTT
ACTIVE
ACTIVE
SOP
SOP
DCQ
DCQ
KTT
6
6
5
78
None
None
None
Call TI
Call TI
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
2500
OBSOLETE DDPAK/
TO-263
TPS79628KTTR
TPS79628KTTT
ACTIVE
DDPAK/
TO-263
KTT
KTT
5
5
500
50
None
None
Call TI
Call TI
Level-3-240C-168 HR
Level-3-240C-168 HR
ACTIVE
DDPAK/
TO-263
TPS79630DCQ
TPS79630DCQR
TPS79630KTT
ACTIVE
ACTIVE
SOP
SOP
DCQ
DCQ
KTT
6
6
5
78
None
None
None
Call TI
Call TI
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
2500
OBSOLETE DDPAK/
TO-263
TPS79630KTTR
TPS79630KTTT
ACTIVE
DDPAK/
TO-263
KTT
KTT
5
5
500
50
None
None
Call TI
Call TI
Level-3-240C-168 HR
Level-3-240C-168 HR
ACTIVE
DDPAK/
TO-263
TPS79633DCQ
TPS79633DCQR
TPS79633KTT
ACTIVE
ACTIVE
SOP
SOP
DCQ
DCQ
KTT
6
6
5
78
None
None
None
Call TI
Call TI
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
2500
OBSOLETE DDPAK/
TO-263
TPS79633KTTR
TPS79633KTTT
ACTIVE
DDPAK/
TO-263
KTT
KTT
5
5
500
50
None
None
Call TI
Call TI
Level-3-240C-168 HR
Level-3-240C-168 HR
ACTIVE
DDPAK/
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2004
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TO-263
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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