TPS7A4701-EP [TI]
36V、1A、4μVRMS、射频 LDO 稳压器（增强型产品）;
| 型号： | TPS7A4701-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36V、1A、4μVRMS、射频 LDO 稳压器（增强型产品） 射频 稳压器 |
| 文件： | 总30页 (文件大小：2099K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A4701-EP
ZHCSG07 –FEBRUARY 2017
TPS7A4701-EP 36V、1A、4μVRMS、射频 LDO 稳压器
1 特性
2 应用
1
•
•
输入电压范围：3V 至 36V
•
•
•
•
•
•
电压控制振荡器 (VCO)
频率合成器
输出电压噪声：
4µVRMS（10Hz、100kHz）
测试和测量
•
电源纹波抑制：
仪器仪表、医疗和音频
RX，TX，和 PA 电路
–
–
82dB (100Hz)
≥ 55dB (10Hz，10MHz)
用于运算放大器，
数模转换器 (DAC)，模数转换器 (ADC)，和其它高
精度模拟电路的电源轨
•
两个输出电压模式：
–
ANY-OUT™版本（经由 PCB 布局进行配置的
用户可编程输出）：
•
后置 DC/DC 转换器稳压和
纹波滤除
–
–
无需外部反馈电阻器或者前馈电容器
•
•
基站和电信基础设施
输出电压范围：1.4V 至 20.5V
12V 和 24V 工业总线
–
可调版本：
输出电压范围：1.4V 至 34V
–
3 说明
•
•
•
•
输出电流：1A
TPS7A4701-EP 是一款正电压 (36V)、超低噪声
(4µVRMS) 低压降线性稳压器 (LDO)，具有 1A 负载电
流灌入能力。
压降电压：1A 时为 307mV
与 CMOS 逻辑电平兼容的使能引脚
内置固定电流限制和
热关断
TPS7A4701-EP 输出电压可通过用户可编程的 PCB
布局进行配置（高达 20.5V），也可以使用外部反馈电
阻器进行调节（高达 34V）。
•
•
采用高性能散热封装：5mm × 5mm QFN
工作温度范围：
–55°C 至 125°C
TPS7A4701-EP 采用双极技术进行设计，主要用于高
精度、高精密仪表 应用 ，在这些应用中干净的电压轨
对于最大程度地提高系统性能而言至关重要。此特性使
得该器件非常适合为运算放大器、模数转换器
(ADC)、数模转换器 (DAC) 以及重要 应用 （如医疗、
射频 (RF) 和测试与测量）中的其他高性能模拟电路供
电。
•
支持国防、航天和医疗 应用：
–
–
–
–
–
–
–
受控基线
一个组装/测试场所
一个制造场所
在扩展温度范围（-55°C 至 125°C）内可用
延长的产品生命周期
延长的产品变更通知
产品可追溯性
此外，TPS7A4701-EP 还非常适合用于后置直流/直流
转换器稳压。通过滤除直流/直流开关转换所固有的输
出电压纹波，可确保在灵敏仪器、测试与测量、音频和
射频 应用中实现系统性能最大化。
简化原理图
TPS7A4701-EP
RF LDO
器件信息(1)
器件型号
封装
VQFN (20)
封装尺寸（标称值）
TPS7A4701-EP
5.00mm × 5.00mm
Amplifier
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
TPS7A33
Negative-Voltage
Regulator
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDQ3
TPS7A4701-EP
ZHCSG07 –FEBRUARY 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
Power Supply Recommendations...................... 19
9.1 Power Dissipation (PD)............................................ 19
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
7.5 Programming........................................................... 12
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
10.3 Thermal Protection................................................ 21
10.4 Estimating Junction Temperature ......................... 21
11 器件和文档支持 ..................................................... 22
11.1 文档支持................................................................ 22
11.2 接收文档更新通知 ................................................. 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
日期
修订版本
说明
2017 年2 月
*
初始发行版
2
Copyright © 2017, Texas Instruments Incorporated
TPS7A4701-EP
www.ti.com.cn
ZHCSG07 –FEBRUARY 2017
5 Pin Configuration and Functions
RGW Package
20-Pin VQFN
Top View
OUT
NC
1
2
3
4
5
15
14
13
12
11
IN
NR
Thermal
Pad
SENSE/FB
6P4V2
EN
0P1V
0P2V
6P4V1
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
When connected to GND, this pin adds 0.1 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 0.2 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 0.4 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 0.8 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 1.6 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 3.2 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
0P1V
12
I
I
I
I
I
I
I
I
0P2V
0P4V
0P8V
1P6V
3P2V
6P4V1
6P4V2
11
10
9
8
6
5
4
Enable pin. The device is enabled when the voltage on this pin exceeds the maximum enable
voltage, VEN(HI). If enable is not required, tie EN to IN.
EN
13
7
I
GND
—
Ground.
Input supply. A capacitor greater than or equal to 1 µF must be tied from this pin to ground to
assure stability.
IN
15, 16
I
A 10-µF capacitor is recommended to be connected from IN to GND (as close to the device as
possible) to reduce circuit sensitivity to printed circuit board (PCB) layout, especially when long
input traces or high source impedances are encountered.
NC
2, 17-19
—
This pin can be left open or tied to any voltage between GND and IN.
Copyright © 2017, Texas Instruments Incorporated
3
TPS7A4701-EP
ZHCSG07 –FEBRUARY 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Noise reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be
reduced to very low levels. A capacitor greater than or equal to 10 nF must be tied from this pin
to ground to assure stability. A 1-µF capacitor is recommended to be connected from NR to
GND (as close to the device as possible) to maximize ac performance and minimize noise.
NR
14
—
Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to
ground to assure stability. A 47-µF ceramic output capacitor is highly recommended to be
connected from OUT to GND (as close to the device as possible) to maximize ac performance.
OUT
1, 20
O
I
Control-loop error amplifier input.
This is the SENSE pin if the device output voltage is programmed using ANY-OUT (no external
feedback resistors). This pin must be connected to OUT. Connect this pin to the point of load to
maximize accuracy.
SENSE/FB
SENSE
3
3
This is the FB pin if the device output voltage is set using external resistors. See the Adjustable
Operation section for more details.
This is the SENSE pin of the device and must be connected to OUT. Connect this pin to the
point of load to maximize accuracy.
I
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected
to GND.
Thermal Pad
—
6 Specifications
6.1 Absolute Maximum Ratings
Over junction temperature range, unless otherwise noted(1)
MIN
–0.4
–0.4
–36
MAX
UNIT
V
IN pin to GND pin
36
EN pin to GND pin
EN pin to IN pin
36
V
0.4
V
OUT pin to GND pin
NR pin to GND pin
SENSE/FB pin to GND pin
0P1V pin to GND pin
0P2V pin to GND pin
0P4V pin to GND pin
0P8V pin to GND pin
1P6V pin to GND pin
3P2V pin to GND pin
6P4V1 pin to GND pin
6P4V2 pin to GND pin
Peak output
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
36
V
36
V
36
V
36
V
Voltage(2)
36
V
36
V
36
V
36
V
36
V
36
V
36
Internally limited
150
V
Current
TJ
Operating virtual junction
Storage temperature
–55
–65
°C
°C
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
4
Copyright © 2017, Texas Instruments Incorporated
TPS7A4701-EP
www.ti.com.cn
ZHCSG07 –FEBRUARY 2017
6.2 ESD Ratings
MIN MAX UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
–2500 2500
V
V(ESD) Electrostatic discharge
–500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over junction temperature range (unless otherwise noted)
MIN
3.0
1.4
0
NOM
MAX
35
UNIT
VI
V
V
V
A
VO
VEN
IO
34
VIN
1
0
6.4 Thermal Information
TPS7A4701-EP
THERMAL METRIC(1)
RGW
20 PINS
32.5
27
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
11.9
0.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
11.9
1.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2017, Texas Instruments Incorporated
5
TPS7A4701-EP
ZHCSG07 –FEBRUARY 2017
www.ti.com.cn
6.5 Electrical Characteristics
At –55°C ≤ TJ ≤ 125°C; VI = VO(nom) + 1 V or VI = 3 V (whichever is greater); VEN = VI; IO = 0 mA; CIN = 10 µF; COUT = 10 µF;
CNR = 10 nF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
3
35
V
VI rising
2.67
2.5
VUVLO
Under-voltage lockout threshold
V
VI falling
V(REF)
Reference voltage
V(REF) = V(FB)
1.4
V
VUVLO(HYS)
Under-voltage lockout hysteresis
177
VOUT
1.4
mV
Using ANY-OUT option
Using adjustable option
VNR
Noise reduction pin voltage
Output voltage range
V
V
Using ANY-
OUT option
1.4
1.4
20.5
34
VI ≥ VO(nom) + 1 V or 3 V
(whichever is greater),
COUT = 20 µF
Using
adjustable
option
VO
Nominal accuracy
Overall accuracy
TJ = 25°C, COUT = 20 µF
–1
1
%VO
VO(nom) + 1 V ≤ VI ≤ 35 V,
0 mA ≤ IO ≤ 1 A, COUT = 20 µF
–3.5
3.5
ΔVO(ΔVI)
ΔVO(ΔIO)
Line regulation
Load regulation
VO(nom) + 1 V ≤ VI ≤ 35 V
0 mA ≤ IO ≤ 1 A
VI = 95% VO(nom), IO = 0.5 A
VI = 95% VO(nom), IO = 1 A
VO = 90% VO(nom)
IO = 0 mA
0.092
0.3
%VO
%VO
216
V(DO)
I(CL)
Dropout voltage
Current limit
mV
A
307
450
1
1
1.26
0.58
6.1
I(GND)
Ground pin current
mA
IO = 1 A
VEN = VI
0.78
0.81
2.55
3.04
2
2
I(EN)
Enable pin current
µA
µA
VI = VEN = 35 V
VEN = 0.4 V
8
I(SHDN)
Shutdown supply current
VEN = 0.4 V, VI = 35 V
60
VI
V+EN(HI)
V+EN(LO)
I(FB)
Enable high-level voltage
Enable low-level voltage
Feedback pin current
2
0
V
V
0.4
350
78
nA
VI = 16 V, VO(nom) = 15 V, COUT = 50 µF,
IO = 500 mA, CNR = 1 µF, f = 1 kHz
PSRR
Power-supply rejection ratio
dB
VI = 3 V, VO(nom) = 1.4 V, COUT = 50 µF,
CNR = 1 µF, BW = 10 Hz to 100 kHz
4.17
4.67
Vn
Output noise voltage
µVRMS
VIN = 6 V, VO(nom) = 5 V, COUT = 50 µF,
CNR = 1 µF, BW = 10 Hz to 100 kHz
Shutdown, temperature increasing
Reset, temperature decreasing
170
150
Tsd
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–55
125
6
Copyright © 2017, Texas Instruments Incorporated
TPS7A4701-EP
www.ti.com.cn
ZHCSG07 –FEBRUARY 2017
6.6 Typical Characteristics
At –55°C ≤ TJ ≤ 125°C; VI = VO(nom) + 1 V or VI = 3 V (whichever is greater); VEN = VI; IO = 0 mA; CIN = 10 µF; COUT = 10 µF;
CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
400%
300%
200%
100%
0
100
10
œ55°C
œ40°C
œ20°C
0°C
25°C
85°C
105°C
125°C
VOUT = 1.4 V,VNOISE = 4.17 mVRMS
VOUT = 5 V,VNOISE = 4.67 mVRMS
VOUT = 10 V,VNOISE = 7.25 mVRMS
VOUT = 15 V,VNOISE = 12.28 mVRMS
1
-100%
-200%
-300%
-400%
0.1
0.01
10
100
1k
10k
100k
1M
Frequency (Hz)
0
5
10
15
20
25
30
35
40
G020
Input Voltage (V)
IOUT = 500 mA
COUT = 50 µF
CNR = 1 µF
D002
BWRMSNOISE (10 Hz, 100 kHz)
Figure 2. Line Regulation
Figure 1. Noise vs Output Voltage
400%
300%
200%
100%
0
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
œ55°C
œ40°C
œ20°C
0°C
25°C
85°C
105°C
125°C
UVLO Off
UVLO On
-100%
-200%
-300%
-400%
0
100 200 300 400 500 600 700 800 900 1000
-60 -40 -20
0
20
40
60
80 100 120 140
Output Current (mA)
Temperature (°C)
D003
D004
Figure 3. Load Regulation
Figure 4. UVLO Threshold vs Temperature
800
750
700
650
600
550
500
450
1.65
1.6
œ55°C
œ40°C
œ20°C
0°C
25°C
85°C
105°C
125°C
1.55
1.5
1.45
1.4
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
0.95
-60 -40 -20
0
20
40
60
80 100 120 140
0
5
10
15
20
25
30
35
40
Temperature (°C)
Input Voltage (V)
D005
D006
IOUT = 0 µA
Figure 6. Quiescent Current vs Input Voltage
Figure 5. Enable Voltage Threshold vs Temperature
Copyright © 2017, Texas Instruments Incorporated
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TPS7A4701-EP
ZHCSG07 –FEBRUARY 2017
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Typical Characteristics (continued)
At –55°C ≤ TJ ≤ 125°C; VI = VO(nom) + 1 V or VI = 3 V (whichever is greater); VEN = VI; IO = 0 mA; CIN = 10 µF; COUT = 10 µF;
CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
10
9
8
7
6
5
4
3
2
1
0
2
1.8
1.6
1.4
1.2
1
œ55°C
œ40°C
œ20°C
0°C
25°C
85°C
105°C
125°C
œ55°C
œ40°C
œ20°C
0°C
25°C
85°C
105°C
125°C
0.8
0.6
0.4
0.2
0
0
100 200 300 400 500 600 700 800 900 1000
0
5
10
15
20
25
30
35
40
Output Current (mA)
Inout Voltage (V)
D007
D008
Figure 7. Ground Current vs Output Current
Figure 8. Enable Current vs Input Voltage
10
9
8
7
6
5
4
3
2
1
0
3
2.5
2
œ55°C
œ40°C
œ20°C
0°C
25°C
85°C
105°C
125°C
œ55°C
œ40°C
œ20°C
0°C
25°C
85°C
105°C
125°C
1.5
1
0.5
0
0
5
10
15
20
25
30
35
40
2
4
6
8
10
12
14
16
18
20
Input Voltage (V)
Input Voltage (V)
D009
D010
VOUT = 90% VOUT(NOM)
Figure 9. Shutdown Current vs Input Voltage
Figure 10. Current Limit vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
CNR = 0.01 mF
CNR = 0.1 mF
CNR = 1 mF
CNR = 0.01 mF
CNR = 0.1 mF
CNR = 1 mF
CNR = 2.2 mF
CNR = 2.2 mF
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G011
G012
IOUT = 1 A
VOUT = 1.4 V
COUT = 50 µF
VIN = 3 V
IOUT = 0.5 A
VOUT = 1.4 V
COUT = 50 µF
VIN = 3 V
Figure 11. Power-Supply Rejection Ratio vs CNR
Figure 12. Power-Supply Rejection Ratio vs CNR
8
Copyright © 2017, Texas Instruments Incorporated
TPS7A4701-EP
www.ti.com.cn
ZHCSG07 –FEBRUARY 2017
Typical Characteristics (continued)
At –55°C ≤ TJ ≤ 125°C; VI = VO(nom) + 1 V or VI = 3 V (whichever is greater); VEN = VI; IO = 0 mA; CIN = 10 µF; COUT = 10 µF;
CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
IOUT = 0 mA
VDO = 200 mV
VDO = 300 mV
VDO = 500 mV
VDO = 1 V
IOUT = 50 mA
IOUT = 500 mA
IOUT = 1000 mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G013
G014
CNR = 1 µF
VOUT = 1.4 V
COUT = 50 µF
VIN = 3 V
VOUT = 3.3 V
IOUT = 50 mA
CNR = 1 µF
COUT = 50 µF
Figure 13. Power-Supply Rejection Ratio vs IO
Figure 14. Power-Supply Rejection Ratio vs Dropout
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VDO = 200 mV
VDO = 300 mV
VDO = 500 mV
VDO = 1 V
VDO = 200 mV
VDO = 300 mV
VDO = 500 mV
VDO = 1 V
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G015
G016
VOUT = 3.3 V
CNR = 1 µF
COUT = 50 µF
VOUT = 3.3 V
IOUT = 1 A
CNR = 1 µF
COUT = 50 µF
IOUT = 500 mA
Figure 15. Power-Supply Rejection Ratio vs Dropout
Figure 16. Power-Supply Rejection Ratio vs Dropout
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
VOUT = 1.4 V
VOUT = 3.3 V
VOUT = 5 V
VOUT = 1.4 V
VOUT = 3.3 V
VOUT = 5 V
VOUT = 10 V
VOUT = 15 V
VOUT = 10 V
VOUT = 15 V
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G017
G018
CNR = 1 µF
COUT = 50 µF
IOUT = 500 mA
CNR = 1 µF
COUT = 50 µF
IOUT = 1000 mA
Figure 17. Power-Supply Rejection Ratio vs Output Voltage
Figure 18. Power-Supply Rejection Ratio vs Output Voltage
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Typical Characteristics (continued)
At –55°C ≤ TJ ≤ 125°C; VI = VO(nom) + 1 V or VI = 3 V (whichever is greater); VEN = VI; IO = 0 mA; CIN = 10 µF; COUT = 10 µF;
CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
VIN
IOUT
(10 V/div)
(1 A/div)
VOUT
VOUT
(10 mV/div)
(10 mV/div)
Time (500 ms/div)
Time (5 ms/div)
G060
G061
VIN = 5 V
VOUT = 3.3 V
IOUT = 10 mA to 845 mA
VIN = 5 V to 15 V
VOUT = 3.3 V
IOUT = 845 mA
Figure 19. Load Transient
Figure 20. Line Transient
100
10
IOUT = 50 mA, VNOISE = 5 mVRMS
IOUT = 20 mA, VNOISE = 5.9 mVRMS
VEN
(2 V/div)
VOUT
(2 V/div)
1
IOUT
0.1
0.01
(200 mA/div)
10
100
1k
10k
100k
1M
Time (50 ms/div)
Frequency (Hz)
G062
G019
Startup Time = 65 ms
IOUT = 500 mA
VIN = 6 V
VOUT = 5 V
COUT = 50 µF
VOUT = 4.7 V
COUT = 10 µF
CNR = 1 µF
CIN = 10 µF
BWRMSNOISE (10 Hz, 100 kHz)
Figure 21. Startup
Figure 22. Noise vs Output Current
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7 Detailed Description
7.1 Overview
The TPS7A4701-EP is a positive voltage (36 V), ultra-low-noise (4 µVRMS) LDOs capable of sourcing a 1-A load.
The TPS7A4701-EP is designed with bipolar technology primarily for high-accuracy, high-precision
instrumentation applications where clean voltage rails are critical to maximize system performance. This feature
makes the device ideal for powering operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog
converters (DACs), and other high-performance analog circuitry.
7.2 Functional Block Diagram
IN
IN
OUT
OUT
Thermal
Shutdown
UVLO
CIN
COUT
Current
Limit
100 kW
Band
Gap
265.5 kW
SENSE/FB
3.2 MW
0P1V
0P2V
0P4V
0P8V
1.6 MW
800 kW
400 kW
1.572 MW
Fast
Charge
Enable
EN
1P6V 3P2V 6P4V 6P4V
NR
CNR
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Internal Current Limit (ICL
)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources
constant current. Therefore, the output voltage falls while load impedance decreases. Note also that when a
current limit occurs while the resulting output voltage is low, excessive power is dissipated across the LDO,
which results in a thermal shutdown of the output.
7.3.2 Enable (EN) And Under-Voltage Lockout (UVLO)
The TPS7A4701-EP only turns on when both EN and UVLO are above the respective voltage thresholds. The
UVLO circuit monitors input voltage (VI) to prevent device turnon before VI rises above the lockout voltage. The
UVLO circuit also causes a shutdown when VI falls below lockout. The EN signal allows independent logic-level
turnon and shutdown of the LDO when the input voltage is present. EN can be connected directly to VI if
independent turnon is not needed.
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Feature Description (continued)
7.3.3 Soft-Start and Inrush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turnon after EN and UVLO have
achieved threshold voltage. The noise reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turnon.
Inrush current is defined as the current through the LDO from IN to OUT during the time of the turnon ramp up.
Inrush current then consists primarily of the sum of load and charge current to the output capacitor. Inrush
current can be estimated by Equation 1:
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turnon ramp,
dVOUT(t)/dt is the slope of the VO ramp, and
RLOAD is the resistive load impedance
(1)
7.4 Device Functional Modes
The TPS7A4701-EP has the following functional modes:
1. Enabled: When EN goes above V+EN(HI), the device is enabled.
2. Disabled: When EN goes below V+EN(LO), the device is disabled. During this time, OUT is high impedance,
and the current into IN does not exceed I(SHDN)
.
7.5 Programming
7.5.1 ANY-OUT Programmable Output Voltage
TPS7A4701-EP can be used in ANY-OUT mode. For ANY-OUT operation, the device does not use external
resistors to set the output voltage, but uses device pins 4, 5, 6, 8, 9, 10, 11, and 12 to program the regulated
output voltage. Each pin is either connected to ground (active) or is left open (floating). The ANY-OUT
programming is set by Equation 2 as the sum of the internal reference voltage (V(REF) = 1.4 V) plus the
accumulated sum of the respective voltages assigned to each active pin; that is, 100 mV (pin 12), 200 mV (pin
11), 400 mV (pin 10), 800 mV (pin 9), 1.6 V (pin 8), 3.2 V (pin 6), 6.4 V (pin 5), or 6.4 V (pin 4). Table 1
summarizes these voltage values associated with each active pin setting for reference. By leaving all program
pins open, or floating, the output is thereby programmed to the minimum possible output voltage equal to V(REF)
.
VOUT = VREF + (S ANY-OUT Pins to Ground)
(2)
Table 1. ANY-OUT Programmable Output Voltage
ANY-OUT PROGRAM PINS (Active Low)
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 4 (6P4V2)
Pin 5 (6P4V1)
Pin 6 (3P2)
6.4 V
6.4 V
3.2 V
Pin 8 (1P6)
1.6 V
Pin 9 (0P8)
800 mV
400 mV
200 mV
100 mV
Pin 10 (0P4)
Pin 11 (0P2)
Pin 12 (0P1)
12
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Table 2 shows a list of the most common output voltages and the corresponding pin settings. The voltage setting
pins have a binary weight; therefore, the output voltage can be programmed to any value from 1.4 V to 20.5 V in
100-mV steps.
Table 2. Common Output Voltages and Corresponding Pin Settings
PIN NAMES AND VOLTAGE PER PIN
VO (V)
0P1V
100 mV
0P2V
200 mV
0P4V
400 mV
0P8V
800 mV
1P6V
1.6 V
3P2V
3.2 V
6P4V1
6.4 V
6P4V2
6.4 V
1.4
1.5
1.8
2.5
3
Open
GND
Open
GND
Open
GND
GND
Open
Open
Open
Open
Open
GND
Open
Open
Open
GND
Open
GND
GND
Open
GND
GND
Open
GND
GND
Open
Open
GND
Open
Open
Open
GND
GND
GND
Open
Open
GND
GND
Open
Open
Open
GND
Open
Open
GND
Open
Open
GND
GND
Open
GND
Open
Open
Open
Open
GND
GND
GND
Open
GND
Open
Open
Open
GND
Open
Open
Open
Open
Open
Open
Open
GND
Open
GND
Open
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
3.3
4.5
5
10
12
15
18
20.5
7.5.2 Adjustable Operation
The TPS7A4701-EP has an output voltage range of 1.4 V to 34 V. For adjustable operation, set the nominal
output voltage of the device using two external resistors, as shown in Figure 23.
VIN
VOUT
OUT
IN
CIN
R1
R2
TPS7A4701-EP
10 mF
EN
NR
FB
COUT
47 mF
GND
CNR/SS
1 mF
Copyright © 2017, Texas Instruments Incorporated
Figure 23. Adjustable Operation for Maximum AC Performance
R1 and R2 can be calculated for any output voltage within the operational range. The current through feedback
resistor R2 must be at least 5 µA to ensure stability. Additionally, the current into the FB pin (I(FB), typically 350
nA) creates an additional output voltage offset that depends on the resistance of R1. For high-accuracy
applications, select R2 such that the current through R2 is at least 35 µA to minimize any effects of I(FB) variation
on the output voltage; 10 kΩ is recommended. R1 can be calculated using Equation 3.
VOUT - VREF
R1 =
VREF
IFB
+
R2
where
•
•
VREF = 1.4 V
IFB = 350 nA
(3)
Use 0.1% tolerance resistors to minimize the effects of resistor inaccuracy on the output voltage.
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Table 3 shows the resistor combinations to achieve some standard rail voltages with commercially-available 1%
tolerance resistors. The resulting output voltages yield a nominal error of < 0.5%.
Table 3. Suggested Resistors for Common Voltage Rails
VOUT
1.4 V
1.8 V
3.3 V
5 V
R1, Calculated
0 Ω
R1, Closest 1% Value
0 Ω
R2
∞
2.782 kΩ
2.8 kΩ
9.76 kΩ
9.76 kΩ
10 kΩ
10.2 kΩ
10.5 kΩ
10 kΩ
10.2 kΩ
13.213 kΩ
25.650 kΩ
77.032 kΩ
101.733 kΩ
118.276 kΩ
164.238 kΩ
13.3 kΩ
25.5 kΩ
12 V
15 V
18 V
24 V
76.8 kΩ
102 kΩ
118 kΩ
165 kΩ
To achieve higher nominal accuracy, two resistors can be used in the place of R1. Select the two resistor values
such that the sum results in a value as close as possible to the calculated R1 value.
There are several alternative ways to set the output voltage. The program pins can be pulled low using external
general-purpose input/output pins (GPIOs), or can be hardwired by the given layout of the printed circuit board
(PCB) to set the ANY-OUT voltage. The TPS7A4701 evaluation module (EVM), available for purchase from the
TI eStore, allows the output voltage to be programmed using jumpers.
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A740x is a high-voltage, low-noise, 1-A LDO. Low-noise performance makes this LDO ideal for
providing rail voltages to noise-sensitive loads, such as PLLs, oscillators, and high-speed ADCs.
8.2 Typical Application
Output voltage is set by grounding the appropriate control pins, as shown in Figure 24. When grounded, all
control pins add a specific voltage on top of the internal reference voltage (V(REF) = 1.4 V). For example, when
grounding pins 0P1V, 0P2V, and 1P6V, the voltage values 0.1 V, 0.2 V, and 1.6 V are added to the 1.4-V
internal reference voltage for VO(nom) equal to 3.3 V, as described in the Programming section.
VIN = 5 V
VOUT = 3.3 V
IN
OUT
10 mF
47 mF
EN
NR
SENSE
GND
Load
TPS7A4701-EP
1 mF
0P1V
0P2V
0P4V 0P8V 1P6V 3P2V 6P4V1 6P4V2
Copyright © 2017, Texas Instruments Incorporated
Figure 24. Typical Application, VOUT = 3.3 V
8.2.1 Design Requirements
Table 4. Design Requirements Table
PARAMETER
Input Voltage
Output Voltage
Output Current
DESIGN REQUIREMENT
5 V, ±10%
3.3 V, ±3%
500 mA
Peak-to-Peak Noise, 10 Hz to 100 kHz
50 µVp-p
8.2.2 Detailed Design Procedure
8.2.2.1 Capacitor Recommendations
These LDOs are designed to be stable using low equivalent series resistance (ESR), ceramic capacitors at the
input, output, and at the noise reduction pin (NR, pin 14). Multilayer ceramic capacitors have become the industry
standard for these types of applications and are recommended here, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good
capacitive stability across temperature, but the use of Y5V-rated capacitors is discouraged precisely because the
capacitance varies so widely. In all cases, ceramic capacitance varies a great deal with operating voltage and the
design engineer must be aware of these characteristics. It is recommended to apply a 50% derating of the
nominal capacitance in the design.
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Attention must be given to the input capacitance to minimize transient input droop during load current steps
because the TPS7A4701-EP has a very fast load transient response. Large input capacitors are necessary for
good transient load response, and have no detrimental influence on the stability of the device. Note, however,
that using large ceramic input capacitances can also cause unwanted ringing at the output if the input capacitor,
in combination with the wire lead inductance, creates a high-Q peaking effect during transients. For example, a
5-nH lead inductance and a 10-µF input capacitor form an LC filter with a resonance frequency of 712 kHz at the
edge of the control loop bandwidth. Short, well-designed interconnect leads to the up-stream supply minimize
this effect without adding damping. Damping of unwanted ringing can be accomplished by using a tantalum
capacitor, with a few hundred milliohms of ESR, in parallel with the ceramic input capacitor.
8.2.2.1.1 Input and Output Capacitor Requirements
The TPS7A4701-EP is designed and characterized for operation with ceramic capacitors of 10 µF or greater at
the input and output. Optimal noise performance is characterized using a total output capacitor value of 50 µF.
Note especially that input and output capacitances must be located as near as practical to the respective input
and output pins.
8.2.2.1.2 Noise Reduction Capacitor (CNR
)
The noise reduction capacitor, connected to the NR pin of the LDO, forms an RC filter for filtering out noise that
might ordinarily be amplified by the control loop and appear on the output voltage. Larger capacitances, up to 1
µF, affect noise reduction at lower frequencies while also tending to further reduce noise at higher frequencies.
Note that CNR also serves a secondary purpose in programming the turnon rise time of the output voltage and
thereby controls the turnon surge current.
8.2.2.2 Dropout Voltage (VDO
)
Generally speaking, the dropout voltage often refers to the voltage difference between the input and output
voltage (V(DO) = VI – VO). However, in the Electrical Characteristics V(DO) is defined as the VI – VO voltage at the
rated current (I(RATED)), where the main current pass-FET is fully on in the Ohmic region of operation and is
characterized by the classic RDS(on) of the FET. V(DO) indirectly specifies a minimum input voltage above the
nominal programmed output voltage at which the output voltage is expected to remain within its accuracy
boundary. If the input falls below this V(DO) limit (VI < VO + V(DO)), then the output voltage decreases in order to
follow the input voltage.
Dropout voltage is always determined by the RDS(on) of the main pass-FET. Therefore, if the LDO operates below
the rated current, the V(DO) is directly proportional to the output current and can be reduced by the same factor.
The RDS(on) for the TPS7A4701-EP can be calculated using Equation 4:
VDO
RDS(ON)
=
IRATED
(4)
8.2.2.3 Output Voltage Accuracy
The output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected
nominal output voltage stated as a percent. This accuracy error typically includes the errors introduced by the
internal reference and the load and line regulation across the full range of rated load and line operating
conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage
accuracy also accounts for all variations between manufacturing lots.
8.2.2.4 Startup
The startup time for the TPS7A4701-EP depends on the output voltage and the capacitance of the CNR
capacitor. Equation 5 calculates the startup time for a typical device.
V + 5
≈
’
R
tSS = 100,000 • CNR • ln
∆
«
÷
◊
5
where
•
•
CNR = capacitance of the CNR capacitor
VR = VO voltage if using the ANY-OUT configuration, or 1.4 V if using the adjustable configuration
(5)
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8.2.2.5 AC Performance
AC performance of the LDO is typically understood to include power-supply rejection ratio, load step transient
response, and output noise. These metrics are primarily a function of open-loop gain and bandwidth, phase
margin, and reference noise.
8.2.2.5.1 Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control loop rejects ripple noise from the input source to make the DC
output voltage as noise-free as possible across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 6
gives the PSRR calculation as a function of frequency where input noise voltage [VS(IN)(f)] and output noise
voltage [VS(OUT)(f)] are understood to be purely ac signals.
VS(IN)(f)
PSRR (dB) = 20 Log10
VS(OUT)(f)
(6)
Noise that couples from the input to the internal reference voltage for the control loop is also a primary
contributor to reduced PSRR magnitude and bandwidth. This reference noise is greatly filtered by the noise
reduction capacitor at the NR pin of the LDO in combination with an internal filter resistor (RSS) for optimal
PSRR.
The LDO is often employed not only as a DC-DC regulator, but also to provide exceptionally clean power-supply
voltages that are free of noise and ripple to power-sensitive system components. This usage is especially true for
the TPS7A4701-EP.
8.2.2.5.2 Load Step Transient Response
The load step transient response is the output voltage response by the LDO to a step change in load current
whereby output voltage regulation is maintained. The worst-case response is characterized for a load step of
10 mA to 1 A (at 1 A per microsecond) and shows a classic, critically-damped response of a very stable system.
The voltage response shows a small dip in the output voltage when charge is initially depleted from the output
capacitor and then the output recovers as the control loop adjusts itself. The depth of the charge depletion
immediately after the load step is directly proportional to the amount of output capacitance. However, to some
extent, the speed of recovery is inversely proportional to that same output capacitance. In other words, larger
output capacitances act to decrease any voltage dip or peak occurring during a load step but also decrease the
control-loop bandwidth, thereby slowing response.
The worst-case, off-loading step characterization occurs when the current step transitions from 1 A to 0 mA.
Initially, the LDO loop cannot respond fast enough to prevent a small increase in output voltage charge on the
output capacitor. Because the LDO cannot sink charge current, the control loop must turn off the main pass-FET
to wait for the charge to deplete, thus giving the off-load step its typical monotonic decay (which appears
triangular in shape).
8.2.2.5.3 Noise
The TPS7A4701-EP is designed, in particular, for system applications where minimizing noise on the power-
supply rail is critical to system performance. This scenario is the case for phase-locked loop (PLL)-based
clocking circuits for instance, where minimum phase noise is all important, or in-test and measurement systems
where even small power-supply noise fluctuations can distort instantaneous measurement accuracy. Because
the TPS7A4701-EP is also designed for higher voltage industrial applications, the noise characteristic is well
designed to minimize any increase as a function of the output voltage.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker or 1/f noise that is a property of resistors and
dominates at lower frequencies as a function of 1/f, burst noise, and avalanche noise).
To calculate the LDO RMS output noise, a spectrum analyzer must first measure the spectral noise across the
bandwidth of choice (typically 10 Hz to 100 kHz in units of µV/√Hz). The RMS noise is then calculated in the
usual manner as the integrated square root of the squared spectral noise over the band, then averaged by the
bandwidth.
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8.2.3 Application Curves
VOUT (10 µV/DIV)
VEN (2 V/DIV)
VOUT (1 V/DIV)
ILOAD (500 mA/DIV)
Figure 25. Startup with EN Pin rising (10 ms/DIV)
Figure 26. Output Noise Voltage, 10 Hz to 100 kHz (10
ms/DIV)
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range of 3 V to 35 V. If the input supply is noisy,
additional input capacitors with low ESR can help improve the output noise performance.
9.1 Power Dissipation (PD)
Power dissipation must be considered in the PCB design. In order to minimize risk of device operation above
125°C, use as much copper area as available for thermal dissipation. Do not locate other power-dissipating
devices near the LDO.
Power dissipation in the regulator depends on the input to output voltage difference and load conditions. PD can
be calculated using Equation 7:
PD = (VOUT - VIN) ´ IOUT
(7)
It is important to note that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input voltage necessary for output
regulation to be obtained.
The primary heat conduction path for the QFN (RGW) package is through the thermal pad to the PCB. The
thermal pad must be soldered to a copper pad area under the device. Thermal vias are recommended to
improve the thermal conduction to other layers of the PCB.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 8.
TJ = TA + (qJA ´ PD)
(8)
Unfortunately, this thermal resistance (θJA) depends primarily on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
spreading planes. The θJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB,
and copper-spreading area and is to be used only as a relative measure of package thermal performance. Note
that for a well-designed thermal layout, θJA is actually the sum of the QFN package junction-to-case (bottom)
thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB copper. By knowing θJCbot, the
minimum amount of appropriate heat sinking can be used to estimate θJA with Figure 27. θJCbot can be found in
the Thermal Information table.
120
100
80
60
qJA (RGW)
40
20
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
NOTE: θJA value at a board size of 9-in2 (that is, 3-in × 3-in) is a JEDEC standard.
Figure 27. ΘJA vs Board Size
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10 Layout
10.1 Layout Guidelines
For best overall performance, all circuit components are recommended to be located on the same side of the
circuit board and as near as practical to the respective LDO pin connections. Ground return connections to the
input and output capacitor, and to the LDO ground pin, must also be as close to each other as possible and
connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit
connections is strongly discouraged and negatively affects system performance. This grounding and layout
scheme minimizes inductive parasitics and thereby reduces load-current transients, minimizes noise, and
increases circuit stability.
A ground reference plane is also recommended. This reference plane serves to assure accuracy of the output
voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when
connected to the PowerPAD™. In most applications, this ground plane is necessary to meet thermal
requirements.
Use the TPS7A4701 evaluation module (EVM), available for purchase from the TI eStore, as a reference for
layout and application design.
10.2 Layout Example
Signal Ground
10
6
11
5
R1
R2
Use R1 and R2
with adjustable
operation
SN/FB
NC
1
EN
NR
15
CNR
Connect if
ANYOUT
operation is
used.
16
20
Power
Ground
Input
Output
COUT
CIN
Orient input and output capacitors
vertically, so that the grounds are
separated.
Figure 28. Layout Example
20
Copyright © 2017, Texas Instruments Incorporated
TPS7A4701-EP
www.ti.com.cn
ZHCSG07 –FEBRUARY 2017
10.3 Thermal Protection
The TPS7A4701-EP contains a thermal shutdown protection circuit to turn off the output current when excessive
heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the main
pass-FET exceeds 170°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on)
when the temperature falls to 150°C (typical). Because the TPS7A4701-EP is capable of supporting high input
voltages, a great deal of power can be expected to be dissipated across the device at low output voltages, which
causes a thermal shutdown. The thermal time-constant of the semiconductor die is fairly short, and thus the
output oscillates on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.
For reliable operation, the junction temperature must be limited to a maximum of 125°C. To estimate the thermal
margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered
using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown must be
designed to occur at least 45°C above the maximum expected ambient temperature condition for the application.
This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A4701-EP is designed to protect against thermal overload conditions.
The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A4701-EP into
thermal shutdown degrades device reliability.
10.4 Estimating Junction Temperature
JEDEC standards now recommend the use of PSI thermal metrics to estimate the junction temperatures of the
LDO while in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These PSI metrics
are determined to be significantly independent of copper-spreading area. The key thermal metrics (ΨJT and ΨJB)
are given in the Thermal Information table and are used in accordance with Equation 9.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in Equation 7,
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the
package edge.
(9)
版权 © 2017, Texas Instruments Incorporated
21
TPS7A4701-EP
ZHCSG07 –FEBRUARY 2017
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
《TPS7A47XXEVM-094 评估模块》
《使用前馈电容器和低压降稳压器的优缺点》
11.2 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
ANY-OUT, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
22
版权 © 2017, Texas Instruments Incorporated
TPS7A4701-EP
www.ti.com.cn
ZHCSG07 –FEBRUARY 2017
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A4701MRGWREP
V62/17601-01XE
ACTIVE
ACTIVE
VQFN
VQFN
RGW
RGW
20
20
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
7A4701M
7A4701M
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGW 20
5 x 5, 0.65 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227157/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
5.1
4.9
B
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.15±0.1
2X 2.6
(0.1) TYP
10
6
16X 0.65
5
11
SYMM
21
2X
2.6
15
1
0.36
0.26
20X
PIN1 ID
(OPTIONAL)
0.1
C A B
C
20
16
0.05
SYMM
0.65
0.45
20X
4219039/A 06/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
(4.65)
3.15)
(2.6)
(
20
16
16X (0.65)
15
1
(1.325)
21
SYMM
(4.65) (2.6)
(R0.05) TYP
11
5
20X (0.31)
20X (0.75)
(Ø0.2) VIA
6
10
TYP
(1.325)
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219039/A 06/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
(4.65)
4X ( 1.37)
2X (0.785)
16
20
16X (0.65)
21
1
15
2X (0.785)
SYMM
(4.65) (2.6)
(R0.05) TYP
11
5
20X (0.31)
20X (0.75)
METAL
TYP
6
10
SYMM
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 15X
4219039/A 06/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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