TPS7A8400RGRR [TI]
具有电源正常指示功能的 3A、低输入电压、低噪声、高精度、超低压降稳压器 | RGR | 20 | -40 to 125;型号: | TPS7A8400RGRR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电源正常指示功能的 3A、低输入电压、低噪声、高精度、超低压降稳压器 | RGR | 20 | -40 to 125 输出元件 稳压器 调节器 |
文件: | 总50页 (文件大小:4571K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS7A84
ZHCSEI2B –JANUARY 2016 –REVISED JUNE 2021
TPS7A84 高电流(3A)、高效(1%)、
低噪声(4.4µVRMS) LDO 稳压器
1 特性
3 说明
• 低压降:3 A 时为180 mV(最大值)
• 整个线路、负载和温度范围内为1%(最高)精度
• 输出电压噪声:
– 输出电压为0.8V 时,噪声为4.4µVRMS
– 输出电压为5.0V 时,噪声为7.7µVRMS
• 输入电压范围:
TPS7A84 是一款低噪声 (4.4 µVRMS)、低压降 (LDO)
线性稳压器,可提供 3A 负载电流,其最高压降仅为
180mV。该器件的输出电压可通过引脚在 0.8V 至
3.95V 的范围内进行编程并可通过外部电阻分压器在
0.8V 至5.0V 范围内进行调节。
TPS7A84 将低噪声 (4.4µVRMS)、高 PSRR 和高输出
电流能力融为一体,非常适合为高速通信、视频、医疗
或测试和测量应用中的噪声敏感型组件供电。
TPS7A84 的高性能可限制电源生成的相位噪声和时钟
抖动,非常适合为高性能串行器和解串器 (SerDes)、
模数转换器 (ADC)、数模转换器 (DAC) 以及射频 (RF)
组件供电。RF 放大器尤其受益于该器件的高性能和
5.0V 输出性能。
– 无偏置:1.4V 至6.5V
– 有偏置:1.1V 至6.5V
• ANY-OUT™ 工作电压:
– 输出电压范围:0.8V 至3.95V
• 可调节工作电压:
– 输出电压范围:0.8 V 至5.0 V
• 电源纹波抑制:
– 500kHz 时为40dB
• 出色的负载瞬态响应
• 可调软启动浪涌控制
• 开漏电源正常(PG) 输出
• 使用47µF 或更大的陶瓷输出电容器实现稳定运行
• 3.5mm × 3.5mm 20 引脚VQFN
对于需要以低输入电压、低输出 (LILO) 电压运行的数
字负载 [如特定用途集成电路 (ASIC)、现场可编程门阵
列 (FPGA) 以及数字信号处理器 (DSP)],TPS7A84 优
异的精度特性( 负载和温度范围内的精度为
0.75%)、远程感测、出色的瞬态性能以及软启动功能
可确保最优系统性能。
2 应用
TPS7A84 器件的多功能性使其适用于许多严苛应用。
• 宏远程无线电单元(RRU)
• 室外回程单元
• 有源天线系统mMIMO (AAS)
• 超声波扫描仪
器件信息(1)
封装尺寸(标称值)
器件型号
TPS7A84
封装
VQFN (20)
3.50mm × 3.50mm
• 实验室和现场仪表
• 传感器、成像和雷达
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
TPS7A84
Bias Supply
Input Supply
OUT
IN
PG
BIAS
Input Supply
IN
VCC
VCC
TPS7A84
OUT
EN
EN Signal
EN
IQ Modulators
IQ Demodulators
PG
TRF372017
TRF3722
TRF371125
TRF371135
VDD
为射频组件供电
DSP,
ASIC,
FPGA
GPIO
C6000
为数字负载供电
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS233
TPS7A84
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ZHCSEI2B –JANUARY 2016 –REVISED JUNE 2021
Table of Contents
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Applications.................................................. 34
9 Power Supply Recommendations................................37
10 Layout...........................................................................38
10.1 Layout Guidelines................................................... 38
10.2 Layout Example...................................................... 38
11 Device and Documentation Support..........................39
11.1 Device Support........................................................39
11.2 Documentation Support.......................................... 39
11.3 接收文档更新通知................................................... 39
11.4 支持资源..................................................................39
11.5 Trademarks............................................................. 39
11.6 Electrostatic Discharge Caution..............................40
11.7 术语表..................................................................... 40
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configurations and Functions.................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................18
Information.................................................................... 40
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2016) to Revision B (June 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式........................................................................................1
• 添加了指向应用部分的链接................................................................................................................................1
• Changed title of Figure 8.................................................................................................................................... 8
• Added RMS noise BW condition to Figure 9 through Figure 12.........................................................................8
• Changed conditions of Figure 13 and Figure 14.................................................................................................8
• Changed the Bias Rail section for clarification ................................................................................................ 17
• Changed Programmable Soft-Start section for clarification..............................................................................17
• Added last paragraph to Internal Current Limit section.................................................................................... 17
• Moved Soft-Start and In-Rush Current section.................................................................................................20
• Added Charge Pump Noise section..................................................................................................................21
• Changed equation 4: changed VREF to VNR/SS ................................................................................................ 22
• Added Current Sharing section.........................................................................................................................25
• Changed Table 5 ..............................................................................................................................................25
• Changed Figure 47 ..........................................................................................................................................26
• Added RPJ to Figure 48.................................................................................................................................... 27
• Changed Undervoltage Lockout (UVLO) Operation section.............................................................................28
• Changed Behavior when Transitioning from Dropout into Regulation section..................................................29
• Changed Load Transient Response section.....................................................................................................29
• Changed title ofNegatively-Biased Output section........................................................................................... 30
• Added Reverse Current Protection section...................................................................................................... 30
• Changed equation 9 from PD = (VOUT –VIN) × IOUT to PD = (VIN –VOUT) × IOUT ......................................... 31
• Added equation 11............................................................................................................................................31
• Added Recommended Area for Continuous Operation section........................................................................32
• Changed Table 8 ..............................................................................................................................................39
Changes from Revision * (January 2016) to Revision A (January 2016)
Page
• 已投入量产..........................................................................................................................................................1
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ZHCSEI2B –JANUARY 2016 –REVISED JUNE 2021
5 Pin Configurations and Functions
OUT
SNS
FB
1
2
3
4
5
15 IN
14 EN
13 NR/SS
12 BIAS
11 1.6V
Thermal Pad
PG
50mV
图5-1. RGR Package, 3.5-mm × 3.5-mm, 20-Pin VQFN, Top View
表5-1. Pin Functions
PIN
NAME
50mV
NO.
5
I/O
DESCRIPTION
100mV
200mV
400mV
800mV
1.6V
6
ANY-OUT voltage setting pins. Connect these pins to ground, SNS, or leave floating. Connecting these pins to ground
increases the output voltage, whereas connecting these pins to SNS increases the resolution of the ANY-OUT network
but decreases the range of the network; multiple pins can be simultaneously connected to GND or SNS to select the
desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output
Voltage section for additional details.
7
I
9
10
11
BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.2
V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance
for VIN ≤2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used, this pin must be
left floating or tied to ground.
BIAS
EN
12
14
3
I
I
I
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable
functionality is not required, this pin must be connected to IN. If enable functionality is required, VEN must always be high
after VIN is established when a BIAS supply is used. See the Sequencing Requirements section for more details.
Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as
close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor can
disrupt PG (power good) functionality. See the ANY-OUT Programmable Output Voltage and Adjustable Operation
sections for more details.
FB
GND
IN
8, 18
Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
—
Input supply voltage pin. A 47-μF or larger ceramic capacitor (25 μF or greater of capacitance) from IN to ground is
recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as possible.
See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
15-17
I
Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference
voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended
to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. See the Noise-
Reduction and Soft-Start Capacitor (CNR/SS) section for more details.
NR/SS
13
—
Regulated output pin. A 47-μF or larger ceramic capacitor (25 μF or greater of capacitance) from OUT to ground is
required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to
the load. See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
OUT
PG
1, 19, 20
O
O
Active-high, power-good pin. An open-drain output indicates when the output voltage reaches 89.3% of the target. The
use of a feed-forward capacitor can disrupt PG (power good) functionality. See the Power-Good Function section for
more details.
4
2
Output voltage sense input pin. This pin connects the internal R1 resistor to the output. Connect this pin to the load side
of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin floating. See
the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
SNS
I
Thermal pad
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1)
MIN
MAX
7.0
UNIT
IN, BIAS, PG, EN
–0.3
–0.3
–0.3
–0.3
–0.3
IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs)
SNS, OUT
7.5
Voltage
VIN + 0.3(2)
3.6
V
NR/SS, FB
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V
OUT
VOUT + 0.3
Internally limited
A
Current
PG (sink current into device)
Operating junction, TJ
Storage, Tstg
5
mA
150
150
–55
–55
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The absolute maximum rating is VIN + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over junction temperature range (unless otherwise noted)
MIN
1.1
3.0
0.8
0
NOM
MAX
6.5
6.5
5
UNIT
V
VIN
Input supply voltage range
Bias supply voltage range(1)
Output voltage range(2)
Enable voltage range
Output current
VBIAS
VOUT
VEN
V
V
VIN
3
V
IOUT
CIN
0
A
Input capacitor
10
47
10
47
µF
µF
kΩ
nF
nF
COUT
RPG
CNR/SS
CFF
Output capacitor
47 || 10 || 10(3)
Power-good pullup resistance
NR/SS capacitor
100
10
10
Feed-forward capacitor
Top resistor value in feedback network for
adjustable operation
R1
12.1(4)
kΩ
Bottom resistor value in feedback network for
adjustable operation
R2
TJ
160(5)
125
kΩ
Operating junction temperature
°C
–40
(1) BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than
or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤2.2 V.
(2) This output voltage range does not include device accuracy or accuracy of the feedback resistors.
(3) The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency
range is a typical value for dc-dc supplies.
(4) The 12.1-kΩresistor is selected to optimize PSRR and noise by matching the internal R1 value.
(5) The upper limit for the R2 resistor is to ensure accuracy by making the current through the feedback network much larger than the
leakage current into the feedback node.
6.4 Thermal Information
TPS7A84
THERMAL METRIC(1)
RGR (VQFN)
20 PINS
35.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
47.6
12.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
12.4
ψJB
RθJC(bot)
1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V(2), OUT connected to 50 Ωto GND(3), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF,
CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Input supply voltage range(1)
Bias supply voltage range(1)
Feedback voltage
1.1
6.5
6.5
V
V
VBIAS
VIN = 1.1 V
3.0
VFB
0.8
0.8
V
VNR/SS
NR/SS pin voltage
V
VUVLO1(IN)
VHYS1(IN)
VUVLO2(IN)
VHYS2(IN)
VUVLO(BIAS)
VHYS(BIAS)
Input supply UVLO with BIAS
VUVLO1(IN) hysteresis
VIN rising with VBIAS = 3.0 V
VBIAS = 3.0 V
1.02
320
1.31
253
2.83
290
1.085
1.39
2.9
V
mV
V
Input supply UVLO without BIAS
VUVLO2(IN) hysteresis
VIN rising
mV
V
Bias supply UVLO
VBIAS rising, VIN = 1.1 V
VIN = 1.1 V
VUVLO(BIAS) hysteresis
mV
Using the ANY-OUT pins
Using external resistors(4)
3.95 + 1.0%
5.0 + 1.0%
0.8 –1.0%
0.8 –1.0%
Range
V
0.8 V ≤VOUT ≤5 V, 5 mA ≤IOUT ≤3 A, over
VIN
Accuracy(4) (5)
1.0%
VOUT
Output voltage
–1.0%
Accuracy with
BIAS
VIN = 1.1 V, 5 mA ≤IOUT ≤3 A,
3.0 V ≤VBIAS ≤6.5 V
0.75%
–0.75%
ΔVOUT
ΔVIN
/
/
Line regulation
Load regulation
0.0035
0.07
mV/V
mV/A
IOUT = 5 mA, 1.4 V ≤VIN ≤6.5 V
5 mA ≤IOUT ≤3 A, 3.0 V ≤VBIAS ≤6.5 V,
VIN = 1.1 V
ΔVOUT
ΔIOUT
0.08
0.4
5 mA ≤IOUT ≤3 A
5 mA ≤IOUT ≤3 A, VOUT = 5.0 V
VIN = 1.4 V, IOUT = 3 A, VFB = 0.8 V –3%
VIN = 5.4 V, IOUT = 3 A, VFB = 0.8 V –3%
156
220
250
340
VDO
Dropout voltage
mV
VIN = 1.1 V, VBIAS = 5.0 V,
IOUT = 3 A, VFB = 0.8 V –3%
110
4.2
180
4.7
VOUT forced at 0.9 × VOUT(nom)
VIN = VOUT(nom) + 0.4 V
,
ILIM
ISC
Output current limit
3.7
A
A
Short-circuit current limit
GND pin current
1.0
2.8
4.2
RLOAD = 20 mΩ
VIN = 6.5 V, IOUT = 5 mA
VIN = 1.4 V, IOUT = 3 A
4
5.5
25
mA
IGND
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V
VIN = 6.5 V, VEN = 0 V and 6.5 V
µA
µA
IEN
EN pin current
0.1
–0.1
VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 3 A
IBIAS
BIAS pin current
2.3
3.5
0.5
mA
V
EN pin low-level input voltage
(disable device)
VIL(EN)
VIH(EN)
VIT(PG)
0
1.1
EN pin high-level input voltage
(enable device)
6.5
V
88.3% ×
VOUT
PG pin threshold
For falling VOUT
For rising VOUT
82% × VOUT
93% × VOUT
V
V
V
VHYS(PG)
VOL(PG)
PG pin hysteresis
1% × VOUT
VOUT < VIT(PG), IPG = –1 mA
(current into device)
PG pin low-level output voltage
0.4
Ilkg(PG)
INR/SS
IFB
PG pin leakage current
NR/SS pin charging current
FB pin leakage current
VOUT > VIT(PG), VPG = 6.5 V
VNR/SS = GND, VIN = 6.5 V
VIN = 6.5 V
1
9.0
µA
µA
nA
4.0
6.2
100
–100
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6.5 Electrical Characteristics (continued)
over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V(2), OUT connected to 50 Ωto GND(3), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF,
CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f = 10 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V
42
f = 500 kHz, VOUT
VIN –VO UT = 0.4 V,
IOUT = 3 A, CNR/SS = 100 nF,
= 0.8 V, VBIAS
5.0 V
=
39
PSRR
Power-supply ripple rejection
dB
CFF = 10 nF, COUT
=
47 μF || 10 μF || 10 μF
f = 10 kHz,
VOUT = 5.0 V
40
25
f = 500 kHz, VOUT
= 5.0 V
BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 3 A,
CNR/SS = 100 nF, CFF = 10 nF,
4.4
7.7
COUT = 47 μF || 10 μF || 10 μF
Vn
Output noise voltage
μVRMS
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF
Shutdown, temperature increasing
Reset, temperature decreasing
160
140
Tsd
TJ
Thermal shutdown temperature
Operating junction temperature
°C
125
°C
–40
(1) BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than
or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤2.2 V.
(2) VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the
expected VOUT value set by the external feedback resistors.
(3) This 50-Ωload is disconnected when the test conditions specify an IOUT value.
(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(5) The device is not tested under conditions where VIN > VOUT + 1.7 V and IOUT = 3 A, because the power dissipation is higher than the
maximum rating of the package.
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6.6 Typical Characteristics
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted)
100
80
60
40
20
0
100
80
60
40
20
0
IOUT = 0.1 A
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 2.5 A
IOUT = 3.0 A
VIN = 1.10 V
VIN = 1.15 V
VIN = 1.20 V
VIN = 1.25 V
VIN = 1.30 V
VIN = 1.35 V
VIN = 1.40 V
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106
1x107
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106
1x107
VIN = 1.1 V, VBIAS = 5 V, COUT = 47 μF || 10 μF || 10 μF,
IOUT = 3 A, VBIAS = 5 V, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = 10 nF, CFF = 10 nF
CNR/SS = 10 nF, CFF = 10 nF
图6-1. PSRR vs Frequency and IOUT
图6-2. PSRR vs Frequency and VIN With Bias
100
100
VBIAS = 0 V
VBIAS = 3.0 V
VBIAS = 5.0 V
VBIAS = 6.5 V
80
80
60
40
60
40
20
0
VIN = 1.1 V, VBIAS = 5 V
VIN = 1.2 V, VBIAS = 5 V
VIN = 1.4 V, VBIAS = 0 V
20
VIN = 2.5 V, VBIAS = 0 V
VIN = 5.0 V, VBIAS = 0 V
0
1x101
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106
1x107
1x102
1x103 1x104
Frequency (Hz)
1x105
1x106
1x107
VIN = 1.4 V, IOUT = 1 A, COUT = 47 μF || 10 μF || 10 μF,
IOUT = 1 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CNR/SS = 10 nF, CFF = 10 nF
CFF = 10 nF
图6-3. PSRR vs Frequency and VBIAS
图6-4. PSRR vs Frequency and VIN
100
100
VOUT = 0.8 V
VOUT = 0.9 V
VOUT = 1.1 V
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VIN = 3.60 V
VIN = 3.65 V
VIN = 3.70 V
VIN = 3.75 V
VIN = 3.80 V
VIN = 3.85 V
80
80
60
60
VOUT = 2.5 V
VIN = 3.90 V
40
20
0
40
20
0
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106
1x107
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106
1x107
VIN = VOUT + 0.3 V, VBIAS = 5.0 V, IOUT = 3 A, COUT = 47 μF ||
10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CFF = 10 nF
图6-6. PSRR vs Frequency and VIN for VOUT = 3.3 V
图6-5. PSRR vs Frequency and VOUT With Bias
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted)
100
80
60
40
20
0
100
80
60
40
20
0
COUT = 47||10||10 mF
COUT = 47 mF
COUT = 100 mF
COUT = 200 mF
COUT = 500 mF
VBIAS = 3.0 V
VBIAS = 5.0 V
VBIAS = 6.5 V
1x101
1x102
1x103 1x104
Frequency (Hz)
1x105
1x106
1x107
1x101
1x102
1x103
1x104 1x105
Frequency (Hz)
1x106
1x107
VIN = VOUT + 0.3 V, VOUT = 1 V, IOUT = 3 A, CNR/SS = 10 nF,
CFF = 10 nF
VIN = VOUT + 0.3 V, VOUT = 1 V, IOUT = 3 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
图6-7. PSRR vs Frequency and COUT
图6-8. VBIAS PSRR vs Frequency
12
2
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
VOUT = 5.0 V, 11.7 mVRMS
1
VOUT = 3.3 V, 8.3 mVRMS
11
10
9
VOUT = 1.5 V, 5.4 mVRMS
VOUT = 0.8 V, 4.5 mVRMS
0.5
0.2
0.1
0.05
8
0.02
0.01
7
6
0.005
5
0.002
0.001
4
0.6
1.2
1.8
2.4
Output Voltage (V)
3
3.6
4.2
4.8
5.4
1x101
1x102
1x103 1x104
Frequency (Hz)
1x105
1x106 5x106
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤2.2 V,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10
nF, RMS noise BW = 10 Hz to 100 kHz
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤2.2 V,
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz
图6-9. Output Voltage Noise vs Output Voltage
图6-10. Output Noise vs Frequency and Output Voltage
2
2
VIN = 1.4 V, VBIAS = 5.0 V, 4.5 mVRMS
VIN = 1.4 V, 6.0 mVRMS
CNR/SS = 0 nF, 6.2 mVRMS
CNR/SS = 1 nF, 4.9 mVRMS
1
1
VIN = 1.5 V, 4.5 mVRMS
VIN = 1.8 V, 4.5 mVRMS
VIN = 2.5 V, 4.6 mVRMS
VIN = 5.0 V, 5.15 mVRMS
CNR/SS = 10 nF, 4.4 mVRMS
CNR/SS = 100 nF, 4.35 mVRMS
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
1x101
1x102
1x103 1x104
Frequency (Hz)
1x105
1x106 4x106
1x101
1x102
1x103 1x104
Frequency (Hz)
1x105
1x106 4x106
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT = 3 A, COUT = 47 μF ||
10 μF || 10 μF, CFF = 10 nF, RMS noise BW = 10 Hz to
100 kHz
CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz
图6-11. Output Noise vs Frequency and Input Voltage
图6-12. Output Noise vs Frequency and CNR/SS
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted)
2
1
2
1
CFF = 0 nF, 6.2 mVRMS
CFF = 0.1 nF, 5.8 mVRMS
CFF = 1 nF, 4.9 mVRMS
CFF = 10 nF, 4.4 mVRMS
CFF = 100 nF, 4.35 mVRMS
CNR/SS = 10 nF, 11.7 mVRMS
CNR/SS = 100 nF, 7.7 mVRMS
CFF = CNR/SS = 100 nF, 6.0 mVRMS
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
1x101
1x102
1x103 1x104
Frequency (Hz)
1x105
1x106 4x106
1x101
1x102
1x103 1x104
Frequency (Hz)
1x105
1x106 4x106
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT = 3 A, sequencing with a
dc/dc converter and PG, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = 10 nF, RMS noise BW = 10 Hz to 100 kHz
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
图6-13. Output Noise vs Frequency and CFF
图6-14. Output Noise at 5.0-V Output
1.2
10
50
40
30
20
10
0
Output Current
VOUT = 0.9 V
VOUT = 1.1 V
VOUT = 1.2 V
VOUT = 1.8 V
9
8
7
6
5
4
3
2
1
0
1
0.8
0.6
0.4
-10
-20
-30
-40
-50
VEN
0.2
0
VOUT, CNR/SS = 0 nF
VOUT, CNR/SS = 10 nF
VOUT, CNR/SS = 47 nF
VOUT, CNR/SS = 100 nF
-0.2
0
5
10
15
20
25
Time (ms)
30
35
40
45
50
0
0.25
0.5
0.75 1
Time (ms)
1.25
1.5
1.75
VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5.0 V, IOUT = 3 A,
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT, DC = 100 mA, slew rate =
1 A/μs, CNR/SS = CFF = 10 nF, COUT = 47 μF || 10 μF || 10
μF
COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF
图6-15. Start-Up Waveform vs Time and CNR/SS
图6-16. Load Transient vs Time and VOUT With Bias
10
9
8
7
6
5
4
3
2
1
0
50
50
Output Current
VOUT = 0.9 V
VOUT = 1.1 V
VOUT, 0.5 A/ms
VOUT, 1 A/ms
VOUT, 2 A/ms
40
30
25
0
20
10
0
-10
-20
-30
-40
-50
-25
-50
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (ms)
2
0
0.4
0.8
Time (ms)
1.2
1.6
2
IOUT, DC = 100 mA, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 3 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = CFF = 10 nF
图6-17. Load Transient vs Time and VOUT Without Bias
图6-18. Load Transient vs Time and Slew Rate
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted)
60
40
20
0
350
300
250
200
150
100
VOUT, 100 mA to 3 A
VOUT, 500 mA to 3 A
-40°C
0°C
25°C
85°C
125°C
-20
-40
0
25
50
75
Time (ms)
100
125
150
1
2
3
Input Voltage (V)
4
5
6
IOUT = 3 A, VBIAS = 0 V
VIN = 1.2 V, VBIAS = 5.0 V, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
图6-20. Dropout Voltage vs Input Voltage Without Bias
图6-19. Load Transient vs Time and DC Load (VOUT = 0.9 V)
350
220
-40°C
0°C
25°C
85°C
125°C
-40°C
200
0°C
25°C
85°C
125°C
180
160
140
120
100
80
300
250
200
150
100
60
40
20
0
1
2
3 4
Input Voltage (V)
5
6
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
IOUT = 3 A, VBIAS = 6.5 V
VIN = 1.4 V, VBIAS = 0 V
图6-21. Dropout Voltage vs Input Voltage With Bias
图6-22. Dropout Voltage vs Output Current Without Bias
160
250
-40°C
0°C
25°C
85°C
125°C
-40°C
0°C
25°C
200
85°C
225
140
120
100
80
125°C
175
150
125
100
75
60
40
50
20
25
0
0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
VIN = 1.1 V, VBIAS = 3 V
VIN = 5.5 V
图6-23. Dropout Voltage vs Output Current With Bias
图6-24. Dropout Voltage vs Output Current (High VIN)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted)
0.2
0.15
0.1
0.15
0.1
-40°C
0°C
25°C
85°C
125°C
-40°C
0°C
25°C
85°C
125°C
0.05
0
0.05
0
-0.05
-0.1
-0.05
-0.1
0.5
1
1.5
2
2.5
Output Voltage (V)
3
3.5
4
4.5
5
0
0.6
1.2 1.8
Output Current (A)
2.4
3
IOUT = 100 mA to 3 A
图6-25. Load Regulation vs Output Voltage
VIN = 1.4 V, VBIAS = 0 V
图6-26. Load Regulation With Bias
0.015
0.04
0.02
0
0
-0.015
-0.03
-0.045
-0.06
-0.02
-0.04
-0.06
-40°C
0°C
25°C
85°C
125°C
-40°C
0°C
25°C
85°C
125°C
0
0.6
1.2 1.8
Output Current (A)
2.4
3
0
0.6
1.2 1.8
Output Current (A)
2.4
3
VIN = 3.8 V
VIN = 5.5 V
图6-27. Load Regulation (3.3-V Output)
图6-28. Load Regulation (5-V Output)
0
-0.025
-0.05
25
0
-25
-50
-75
-100
-0.075
-0.1
-40°C
0°C
25°C
85°C
125°C
-40°C
0°C
25°C
85°C
125°C
-0.125
1
1.5
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
6
6.5
3
3.5
4
4.5 5
Bias Voltage (V)
5.5
6
6.5
VOUT = 0.8 V, VBIAS = 0 V, IOUT = 5 mA
VOUT = 0.8 V, VIN = 1.1 V, IOUT = 5 mA
图6-29. Line Regulation Without Bias
图6-30. Line Regulation Without Bias
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted)
0
-20
-40
-60
3.3
3
2.7
2.4
2.1
1.8
1.5
-40°C
0°C
25°C
85°C
125°C
-40°C
0°C
25°C
85°C
125°C
5.25
5.5
5.75
Input Voltage (V)
6
6.25
6.5
1
2
3
4
Input Voltage (V)
5
6
7
IOUT = 5 mA
VBIAS = 0 V, IOUT = 5 mA
图6-31. Line Regulation (5-V Output)
图6-32. Quiescent Current vs Input Voltage
2.4
2
5
4
3
2
1
-40°C
0°C
25°C
85°C
125°C
1.6
1.2
0.8
-40°C
0°C
25°C
85°C
125°C
0
1
3
3.5
4
4.5
Bias Voltage (V)
5
5.5
6
6.5
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
6.5
VIN = 1.1 V, IOUT = 5 mA
VBIAS = 0 V
图6-33. Quiescent Current vs Bias Voltage
图6-34. Shutdown Current vs Input Voltage
6
5
4
3
2
1
0
7.5
7
-40°C
0°C
25°C
85°C
125°C
6.5
6
5.5
5
-40°C
0°C
25°C
85°C
125°C
4.5
3
3.5
4
4.5
Bias Voltage (V)
5
5.5
6
6.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
6.5
VIN = 1.1 V
VBIAS = 0 V
图6-35. Shutdown Current vs Bias Voltage
图6-36. INR/SS Current vs Input Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ(unless otherwise noted)
1.4
1.2
1
3
2.9
2.8
2.7
2.6
2.5
VUVLO(BIAS), Rising
VUVLO(BIAS), Falling
0.8
0.6
0.4
0.2
VUVLO2(IN), Rising
VUVLO2(IN), Falling
VUVLO1(IN), Rising
VUVLO1(IN), Falling
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-60
-30
0
30 60
Temperature (°C)
90
120
150
VIN = 1.1 V
图6-37. VIN UVLO vs Temperature
图6-38. VBIAS UVLO vs Temperature
0.85
0.8
0.75
0.6
0.45
0.3
0.15
0
-40°C
0°C
25°C
85°C
125°C
0.75
0.7
0.65
0.6
VIH(EN), VIN = 1.4 V
VIH(EN), VIN = 6.5 V
VIL(EN), VIN = 1.4 V
VIL(EN), VIN = 6.5 V
0.55
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
0.5
1
PG Current Sink (mA)
1.5
2
2.5
3
VIN = 1.4 V, 6.5 V
图6-39. Enable Threshold vs Temperature
图6-40. PG Voltage vs PG Current Sink
0.4
0.32
0.24
0.16
0.08
0
90.25
90
-40°C
0°C
25°C
85°C
125°C
VIT(PG) Rising, VIN = 1.4 V
VIT(PG) Rising, VIN = 6.5 V
VIT(PG) Falling, VIN = 1.4V
VIT(PG) Falling, VIN = 6.5 V
89.75
89.5
89.25
89
88.75
88.5
88.25
88
87.75
-50
-25
0
25 50
Temperature (°C)
75
100
125
0
0.5
1
1.5
2
PG Current Sink (mA)
2.5
3
VIN = 6.5 V
图6-42. PG Threshold vs Temperature
图6-41. PG Voltage vs PG Current Sink
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7 Detailed Description
7.1 Overview
The TPS7A84 is a high-current (3 A), low-noise (4.4 µVRMS), high accuracy (1%) low-dropout linear voltage
regulator (LDO). These features make the device a robust solution to solve many challenging problems in
generating a clean, accurate power supply.
The TPS7A84 has several features that make the device useful in a variety of applications. As detailed in the
Functional Block Diagram section, these features include:
• Low-noise, high-PSRR output
• ANY-OUT resistor network
• Optional bias rail
• Power-good output
• Programmable soft-start
• Foldback current limit
• Enable circuitry
• Active discharge
• Thermal protection
Overall, these features make the TPS7A84 the component of choice because of its versatility and ability to
generate a supply for most applications.
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7.2 Functional Block Diagram
PSRR
Boost
Current
Limit
IN
OUT
Charge
Pump
BIAS
Active
Discharge
RNR/SS = 250 kW
0.8-V
VREF
+
Error
Amp
œ
INR/SS
SNS
FB
NR/SS
200 pF
R1 = 2×R = 12.1 kW
1×R = 6.05 kW
2×R = 12.1 kW
4×R = 24.2 kW
8×R = 48.4 kW
16×R = 96.8 kW
32×R = 193.6 kW
1.6V
Internal
Controller
800mV
400mV
200mV
100mV
50mV
UVLO
Circuits
ANY-OUT Network
Thermal
Shutdown
PG
œ
0.893 x VREF
+
EN
GND
For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual resistance can vary
significantly from the numbers listed.
7.3 Feature Description
7.3.1 Low-Noise, High-PSRR Output
The TPS7A84 includes a low-noise reference and error amplifier ensuring minimal noise during operation. The
NR/SS capacitor (CNR/SS) and feed-forward capacitor (CFF) are the easiest way to reduce device noise. CNR/SS
filters the noise from the reference and CFF filters the noise from the error amplifier. The noise contribution from
the charge pump is minimal. The overall noise of the system at low output voltages can be reduced by using a
bias rail because this rail provides more headroom for internal circuitry.
The high power-supply rejection ratio (PSRR) of the TPS7A84 ensures minimal coupling of input supply noise to
the output. The PSRR performance is primarily results from a high-bandwidth, high-gain error amplifier and an
innovative circuit to boost the PSRR between 200 kHz and 1 MHz.
The combination of a low noise-floor and high PSRR ensure that the device provides a clean supply to the
application; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR
performance.
7.3.2 Integrated Resistance Network (ANY-OUT)
An internal feedback resistance network is provided, allowing the TPS7A84 output voltage to be programmed
easily between 0.8 V to 3.95 V with a 50-mV step by tying the ANY-OUT pins to ground. Tying the ANY-OUT
pins to SNS increases the resolution but limits the range of the output voltage because the effective value of R1
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is decreased. Use the ANY-OUT network for excellent accuracy across output voltage and temperature; see the
Application and Implementation section for more details.
7.3.3 Bias Rail
The device features a bias rail to enable low-input voltage, low-output (LILO) voltage operation by providing
power to the internal circuitry of the device. The bias rail is required for operation with VIN < 1.4 V.
An internal power MUX supplies the greater of either the input voltage or the bias voltage to an internal charge
pump to power the internal circuitry. Unlike other LDOs that have a bias supply, the TPS7A84 does not have a
minimum bias voltage with respect to the input supply because an internal charge pump is used instead.
The internal charge pump multiples the output voltage of the power MUX by a factor of 4 to a maximum of
typically 8 V; therefore, using a bias supply with VIN ≤ 2.2 V is recommended for optimal dc and ac
performance. Sequencing requirements exist for when the bias rail is used; see the Sequencing Requirements
section for more details.
7.3.4 Power-Good Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.
When the feedback pin voltage falls below the PG threshold voltage (VIT(PG) + VHYS(PG), typically 89.3%), the PG
pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the
VIT(PG) threshold by an amount greater than VHYS(PG) (typically 91.3%), the PG pin becomes high impedance. By
connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic
signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic
signal for the receiving device or devices. Using a pullup resistor from 10 kΩto 100 kΩis recommended. Using
an external voltage detector device such as the TPS3702 is also recommended in applications where more
accurate voltage monitoring or overvoltage monitoring is required.
The use of a feed-forward capacitor (CFF) can cause glitches on start-up, and the power-good circuit may not
function normally below the minimum input supply range. For more details on the use of the power-good
circuitry, see the Power-Good Operation section.
7.3.5 Programmable Soft-Start
Soft-start refers to the ramp-up time of the output voltage during LDO turn-on after EN and UVLO exceed the
respective threshold voltages. The noise-reduction capacitor (CNR/SS) serves a dual purpose of both governing
output noise reduction and programming the soft-start ramp time during turn-on. The start-up ramp is monotonic.
The majority of the ramp is linear; however, there is an offset voltage in the error amplifier that can cause a small
initial jump in output voltage; see the Application and Implementation section on implementing a soft-start.
7.3.6 Internal Current Limit (ILIM
)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events.
During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased
load impedance. Thermal shutdown can activate during a current limit event because of the high power
dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the
inductances to the input and load. Continuous operation in current limit is not recommended.
The foldback current limit crosses 0 A when VOUT < 0 V and prevents the device from turning on into a
negatively-biased output. See the Negatively-Biased Output section on additional ways to ensure start-up when
the TPS7A84 output is pulled below ground.
If VOUT > VIN + 0.3 V, then reverse current can flow from the output to the input. The reverse current can cause
damage to the device; therefore, limit this reverse current to 10% of the rated output current of the device. See
the Reverse Current Protection section for more details.
7.3.7 Enable
The enable pin for the TPS7A84 is active high. The output of the TPS7A84 is turned on when the enable pin
voltage is greater than its rising voltage threshold (1.1 V, max), and the output of the TPS7A84 is turned off when
the enable pin voltage is less than its falling voltage threshold (0.5 V, min). A voltage less than 0.5 V on the
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enable pin disables all internal circuits. At the next turn-on this voltage ensures a normal start-up waveform with
in-rush control, provided there is enough time to discharge the output capacitance.
When the enable functionality is not desired, EN must be tied to VIN. However, when the enable functionality is
desired, the enable voltage must come after VIN is above VUVLO1(IN) when a BIAS rail is used. See the
Application and Implementation section for further details.
7.3.8 Active Discharge Circuit
The TPS7A84 has an internal pulldown MOSFET that connects a resistance of several hundred ohms to ground
when the device is disabled to actively discharge the output voltage when the device is disabled.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.3.9 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit monitors the input and bias voltage (VIN and VBIAS, respectively) to
prevent the device from turning on before VIN and VBIAS rise above the lockout voltage. The UVLO circuit also
disables the output of the device when VIN or VBIAS fall below the lockout voltage. The UVLO circuit responds
quickly to glitches on VIN or VBIAS and attempts to disable the output of the device if either of these rails collapse.
As a result of the fast response time of the input supply UVLO circuit, fast and short line transients well below the
input supply UVLO falling threshold can cause momentary glitches when asserted or when recovered from the
transient. See the Application and Implementation section for more details.
7.3.10 Thermal Protection
The TPS7A84 contains a thermal shutdown protection circuit to disable the device when thermal junction
temperature (TJ) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the
LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the
semiconductor die is fairly short, and thus the device cycles on and off when thermal shutdown is reached until
the power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C can cause
the device to exceed its operational specifications. Although the internal protection circuitry of the TPS7A84 is
designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat
sinking. Continuously running the TPS7A84 into thermal shutdown or above a junction temperature of 125°C
reduces long-term reliability.
7.4 Device Functional Modes
7.4.1 Operation with 1.1 V ≤VIN < 1.4 V
The TPS7A84 requires a bias voltage on the BIAS pin greater than or equal to 3.0 V if the high-current input
supply voltage is between 1.1 V to 1.4 V. The bias voltage pin consumes 2.3 mA, nominally.
7.4.2 Operation with 1.4 V ≤VIN ≤6.5 V
If the input voltage is equal to or exceeds 1.4 V, no BIAS voltage is required. The TPS7A84 is powered from
either the input supply or the BIAS supply, whichever is greater. For higher performance, a BIAS rail is
recommended for VIN ≤2.2 V.
7.4.3 Shutdown
Shutting down the device reduces the ground current of the device to a maximum of 25 µA.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The TPS7A84 is a linear voltage regulator with an input range of 1.1 V to 6.5 V and an output voltage range of
0.8 V to 5.0 V with a 1% accuracy and a 3-A maximum output current. The TPS7A84 has an integrated charge
pump for ease of use and an external bias rail to allow for the lowest dropout across the entire output voltage
range.
8.1.1 Recommended Capacitor Types
The TPS7A84 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the
input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry
standard for these types of applications and are recommended, but must be used with good judgment. Ceramic
capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive
stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations
in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors
recommended herein account for a capacitance derating of approximately 50%, but at high VIN and VOUT
conditions (that is, VIN = 5.5 V to VOUT = 5.0 V) the derating can be greater than 50% and must be taken into
consideration.
8.1.2 Input and Output Capacitor Requirements (CIN and COUT
)
The TPS7A84 is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or
greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. Using at
least a 47-µF capacitor is highly recommended at the input to minimize input impedance. Place the input and
output capacitors as near as practical to the respective input and output pins to minimize trace parasitics. If the
trace inductance from the input supply to the TPS7A84 is high, a fast current transient can cause VIN to ring
above the absolute maximum voltage rating and damage the device. This situation can be mitigated by
additional input capacitors to dampen the ringing and to keep it below the device absolute maximum ratings.
A combination of multiple output capacitors boosts the high-frequency PSRR, as illustrated in several of the
PSRR curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized,
10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes
PSRR for the frequency range of 400 kHz to 700 kHz, a typical range for dc-dc supply switching frequency. This
47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage
configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a
voltage derating of approximately 60% to 80% at 5.0 V, so the addition of the two 10-µF capacitors ensures that
the capacitance is at or above 22 µF.
8.1.3 Noise-Reduction and Soft-Start Capacitor (CNR/SS
)
The TPS7A84 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CNR/SS).The use of an external CNR/SS is highly recommended, especially to minimize in-rush current
into the output capacitors. This soft-start eliminates power-up initialization problems when powering field-
programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled
voltage ramp of the output also reduces peak in-rush current during start-up, minimizing start-up transients to the
input power bus.
To achieve a monotonic start-up, the TPS7A84 error amplifier tracks the voltage ramp of the external soft-start
capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start
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charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS). Soft-start ramp
time can be calculated with 方程式1:
tSS = (VNR/SS × CNR/SS) / INR/SS
(1)
Note that INR/SS is provided in the Electrical Characteristics table and has a typical value of 6.2 µA.
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that
filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the
device noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with 方程式 2. The
typical value of RNR is 250 kΩ. Increasing the CNR/SS capacitor has a greater affect because the output voltage
increases when the noise from the reference is gained up even more at higher output voltages. For low-noise
applications, a 10-nF to 1-µF CNR/SS is recommended.
fcutoff = 1/ (2 × π× RNR × CNR/SS
)
(2)
8.1.4 Feed-Forward Capacitor (CFF)
Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a
10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher
capacitance CFF can be used; however, the start-up time is longer and the power-good signal can incorrectly
indicate that the output voltage is settled. For a detailed description, see the Pros and Cons of Using a Feed-
Forward Capacitor with a Low Dropout Regulator application report.
8.1.5 Soft-Start and In-Rush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO
achieve threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turn-on.
In-rush current is defined as the current into the LDO at the IN pin during start-up. In-rush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
measure because the input capacitor must be removed, which is not recommended. However, this soft-start
current can be estimated by 方程式3:
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
(3)
where:
• VOUT(t) is the instantaneous output voltage of the turn-on ramp
• dVOUT(t) / dt is the slope of the VOUT ramp
• RLOAD is the resistive load impedance
8.1.6 Optimizing Noise and PSRR
The ultra-low noise floor and PSRR of the device can be improved by careful selection of:
• CNR/SS for the low-frequency range
• CFF in the mid-band frequency range
• COUT for the high-frequency range
• VIN –VOUT for all frequencies, and
• VBIAS at lower input voltages
A larger noise-reduction capacitor improves low-frequency PSRR by filtering any noise coupling from the input
into the reference. The feed-forward capacitor can be optimized to place a pole-zero pair near the edge of the
loop bandwidth and push out the loop bandwidth, thus improving mid-band PSRR. Larger output capacitors and
various output capacitors can be used to improve high-frequency PSRR.
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A higher input voltage improves the PSRR by giving the device more headroom to respond to noise on the input;
see the 图 6-2 curve. A bias rail also improves the PSRR at lower input voltages because greater headroom is
provided for the internal circuits.
The noise-reduction capacitor filters out low-frequency noise from the reference and the feed-forward capacitor
reduces output voltage noise by filtering out the mid-band frequency noise. However, a large feed-forward
capacitor can create some new issues that are discussed in the Pros and Cons of Using a Feed-Forward
Capacitor with a Low Dropout Regulator application report.
A large output capacitor reduces high-frequency output voltage noise. Additionally, a bias rail or higher input
voltage improves the noise because greater headroom is provided for the internal circuits.
表 8-1 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5.0-V output for a variety of conditions
with an input voltage of 5.4 V, an R1 of 12.1 kΩ, and a load current of 3 A. The 5.0-V output is chosen because
this output is the worst-case condition for output voltage noise.
表8-1. Output Noise Voltage at a 5.0-V Output
OUTPUT VOLTAGE NOISE
CNR/SS (nF)
CFF (nF)
COUT (µF)
(µVRMS
11.7
7.7
)
10
10
10
47 || 10 || 10
47 || 10 || 10
47 || 10 || 10
1000
100
100
100
100
6
100
10
7.4
5.8
100
1000
8.1.7 Charge Pump Noise
The device internal charge pump generates a minimal amount of noise, as shown in 图8-1.
Using a bias rail minimizes the internal charge pump noise when the internal voltage is clamped, thereby
reducing the overall output noise floor.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by
using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the
load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.
0.5
VIN = 1.5 V, 4.5 mVRMS
VIN = 1.4 V, VBIAS = 5.0 V, 4.5 mVRMS
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.007
0.005
0.003
0.002
0.001
1000000
2000000
3000000
4000000
5000000
6000000
7000000
8000000
9000000
1E+7
Frequency (Hz)
图8-1. Charge Pump Noise
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8.1.8 ANY-OUT Programmable Output Voltage
The TPS7A84 can use either external resistors or the internally-matched ANY-OUT feedback resistor network to
set output voltage. The ANY-OUT resistors are accessible via pin 2 and pins 5 to 11 and are used to program the
regulated output voltage. Each pin is can be connected to ground (active) or left open (floating), or connected to
SNS. ANY-OUT programming is set by 方程式 4 as the sum of the internal reference voltage (VNR/SS = 0.8 V)
plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV
(pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). 表8-2 summarizes these voltage values
associated with each active pin setting for reference. By leaving all program pins open or floating, the output is
thereby programmed to the minimum possible output voltage equal to VFB.
VOUT = VNR/SS + (ΣANY-OUT Pins to Ground)
(4)
表8-2. ANY-OUT Programmable Output Voltage
ANY-OUT PROGRAM PINS (Active Low)
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50mV)
50 mV
100 mV
200 mV
400 mV
800 mV
1.6 V
Pin 6 (100mV)
Pin 7 (200mV)
Pin 9 (400mV)
Pin 10 (800mV)
Pin 11 (1.6V)
表 8-3 provides a full list of target output voltages and corresponding pin settings when the ANY-OUT pins are
only tied to ground or left floating. The voltage setting pins have a binary weight; therefore, the output voltage
can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground. There
are several alternative ways to set the output voltage. The program pins can be driven using external general-
purpose input/output pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired by the
given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable operation, the
output voltage is set according to 方程式 5 except that R1 and R2 are internally integrated and matched for
higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback
network by lowering the value of R1. See the Increasing ANY-OUT Resolution for LILO Conditions section for
additional information.
VOUT = VNR/SS × (1 + R1 / R2)
(5)
Note
For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the Adjustable
Operation section).
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表8-3. User-Configurable Output Voltage Settings
VOUT(NOM)
(V)
VOUT(NOM)
50mV
100mV
200mV
400mV
800mV
1.6V
50mV
100mV
200mV
400mV
800mV
1.6V
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
3.75
3.80
3.85
3.90
3.95
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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8.1.9 ANY-OUT Operation
Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ) the
output voltage is set by grounding the appropriate control pins, as shown in 图 8-2. When grounded, all control
pins add a specific voltage on top of the internal reference voltage (VNR/SS = 0.8 V). The output voltage can be
calculated by 方程式6 and 方程式7. 图8-2 and 图8-3 show a 0.9-V output voltage, respectively, that provide an
example of the circuit usage with and without bias voltage.
BIAS
EN
IN
PG
OUT
SNS
FB
RPG
Input
Supply
To Load
COUT
CIN
Device
CFF
NR/SS
CNR/SS
GND 50mV 100mV 200mV 400mV 800mV 1.6V
图8-2. ANY-OUT Configuration Circuit (3.3-V Output, No External Bias)
VOUT(nom) = VNR/SS + 1.6 V + 0.8 V + 0.1 V = 0.8 V + 1.6 V + 0.8 V + 0.1 V = 3.3 V
(6)
CBIAS
Bias
Supply
BIAS
EN
IN
PG
OUT
SNS
FB
RPG
Input
Supply
To Load
COUT
CIN
Device
CFF
NR/SS
CNR/SS
GND 50mV 100mV 200mV 400mV 800mV 1.6V
图8-3. ANY-OUT Configuration Circuit (0.9-V Output with Bias)
VOUT(nom) = VNR/SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V
(7)
8.1.10 Increasing ANY-OUT Resolution for LILO Conditions
As with the adjustable operation, the output voltage is set according to 方程式 5, except that R1 and R2 are
internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the
resolution of the internal feedback network by lowering the value of R1. One of the more useful pin combinations
is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range. The new
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ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. The new additive output voltage levels are listed in
表8-4.
表8-4. ANY-OUT Programmable Output Voltage with 800mV Tied to SNS
ANY-OUT PROGRAM PINS (Active Low)
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50mV)
25 mV
50 mV
100 mV
200 mV
800 V
Pin 6 (100mV)
Pin 7 (200mV)
Pin 9 (400mV)
Pin 11 (1.6V)
8.1.11 Current Sharing
Current sharing is possible through the use of external operational amplifiers. For more details, see the 6A
Current-Sharing Dual LDO design guide.
8.1.12 Adjustable Operation
The TPS7A84 can be used either with the internal ANY-OUT network or by using external resistors. Using the
ANY-OUT network allows the TPS7A84 to be programmed from 0.8 V to 3.95 V. To extend this output voltage
range to 5.0 V, external resistors must be used. This configuration is referred to as the adjustable configuration
of the TPS7A84 throughout this document. Regardless whether the internal resistor network or whether external
resistors are used, the output voltage is set by two resistors, as shown in 图 8-4. Using the internal resistor
ensures a 1% accuracy and minimizes the number of external components.
Optional Bias
CBIAS
Supply
BIAS
EN
IN
PG
OUT
SNS
FB
RPG
Input
Supply
To Load
CIN
COUT
Device
CFF
R1
R2
NR/SS
CNR/SS
GND 50mV 100mV 200mV 400mV 800mV 1.6V
图8-4. Adjustable Operation
R1 and R2 can be calculated for any output voltage range using 方程式 8. This resistive network must provide a
current equal to or greater than 5 μA for dc accuracy. Using an R1 of 12.1 kΩ is recommended to optimize the
noise and PSRR.
VOUT = VNR/SS × (1 + R1 / R2)
(8)
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表 8-5 shows the resistor combinations required to achieve several common rails using standard 1%-tolerance
resistors.
表8-5. Recommended Feedback-Resistor Values(1)
FEEDBACK RESISTOR VALUES
CALCULATED OUTPUT
TARGETED OUTPUT VOLTAGE
(V)
VOLTAGE
(V)
R1 (kΩ)
R2 (kΩ)
0.9
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.1
12.4
12.1
12.1
11.8
12.1
11.8
12.4
100
66.5
49.9
33.2
24.9
14.3
10
0.899
0.949
0.999
1.099
1.198
1.494
1.798
1.89
0.95
1.00
1.10
1.20
1.50
1.80
1.90
2.50
2.85
3.00
3.30
3.60
4.5
8.87
5.9
2.48
4.75
4.42
3.74
3.48
2.55
2.37
2.838
2.990
3.324
3.582
4.502
4.985
5.00
(1) R1 is connected from OUT to FB; R2 is connected from FB to GND.
8.1.13 Sequencing Requirements
Supply and enable sequencing is only required when the bias rail is present. The start-up is always monotonic,
independent of the sequencing requirements. Under these conditions the following requirements apply:
• VBIAS and VIN can be sequenced in any order, as long as VEN is tied to VIN or established after VIN, as shown
in 图8-5.
tt0 ≥ 0t
VUVLO1(IN)
VIN
VIH(EN)
VEN
图8-5. Sequencing Diagram
Two typical application circuits for implementing the sequencing requirements are detailed in the Sequencing
with a Power-Good DC-DC Converter Pin and Sequencing with a Microcontroller (MCU) sections.
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8.1.13.1 Sequencing with a Power-Good DC-DC Converter Pin
When a dc-dc converter is used to power the device and the PG of the dc-dc converter is used to enable the
device, pull PGup to VIN, as shown in 图8-6.
From Input Supply
BIAS
Device
OUT
PG
IN
DC-DC
RPU
IN
EN
图8-6. Sequencing with a DC-DC Converter and PG
8.1.13.2 Sequencing with a Microcontroller (MCU)
If a push-pull output stage is used to provide the enable signal to the device and the enable signal can possibly
come before VIN when a bias is present (such as with an MCU), convert the enable signal to an open-drain
signal as shown in 图 8-7. Using an open-drain signal ensures that if the signal arrives before VIN, then the
enable voltage does not violate the sequencing requirement.
Bias Supply
Input Supply
RPU
BIAS
IN
Device
EN
Enable Signal
MCU
图8-7. Push-Pull Enable to Open-Drain Enable
8.1.14 Power-Good Operation
To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and
100 kΩ. The lower limit of 10 kΩresults from the maximum pulldown strength of the power-good transistor, and
the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup
resistor is outside of this range, then the power-good signal may not read a valid digital logic level.
Using a large CFF with a small CNR/SS causes the power-good signal to incorrectly indicate that the output
voltage has settled during turn-on. The CFF time constant must be greater than the soft-start time constant to
ensure proper operation of the PG during start-up. For a detailed description, see the Pros and Cons of Using a
Feed-Forward Capacitor with a Low Dropout Regulator application report.
The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO
events and at light loads, power-good does not assert because the output voltage is sustained by the output
capacitance.
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8.1.15 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input or bias supplies reach the minimum
operational voltage range, and ensures that the device shuts down when the input supply or bias supply
collapse.
The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a
downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the
UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device.
When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled.
The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall
time of the input supply when operating near the minimum VIN, or by using a bias rail.
图 8-8 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
• Region A: The device does not turn on until the input reaches the UVLO rising threshold.
• Region B: Normal operation with a regulated output
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold –UVLO hysteresis).
The output may fall out of regulation but the device is still enabled.
• Region D: Normal operation with a regulated output
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up then follows.
• Region F: Normal operation followed by the input falling to the UVLO falling threshold.
• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
图8-8. Typical UVLO Operation
8.1.16 Dropout Voltage (VDO
)
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (VDO = VIN –VOUT) that is required for regulation. When VIN drops below the required VDO for the
given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is proportional to the output current because the device is operating as a resistive switch; see the 图
6-22, 图6-23, and 图6-24 curves.
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect
to VIN on this device because of the internal charge pump. The charge pump causes a higher dropout voltage at
lower input voltages when a bias rail is not used, as illustrated in the 图6-20 curve.
For this device, dropout voltage increases exponentially when the input voltage nears its maximum operating
voltage because the charge pump is internally clamped to 8.0 V; see the 图6-20 and 图6-21 curves.
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8.1.17 Behavior when Transitioning from Dropout into Regulation
Some applications may have transients that place the device into dropout, especially because this device is a
high-current linear regulator. A typical application with these conditions requires setting VIN ≤ VDO in order to
keep the device junction temperature within its specified operating range. A load transient or line transient in
these conditions can place the device into dropout, such as a load transient from 1 A to 4 A at 1A/µs when
operating with a VIN of 5.4- V and a VOUT of 5.0 V.
The load transient saturates the error amplifier output stage when the pass element is fully driven on, thus
making the pass element function like a resistor from VIN to VOUT. The error amplifier response time to this load
transient (IOUT = 4 A to 1 A at 1 A/µs) is limited because the error amplifier must first recover from saturation and
then place the pass element back into active mode. During the recovery from the load transient, VOUT
overshoots because the pass element is functioning as a resistor from VIN to VOUT. If operating under these
conditions, apply a higher dc load or increase the output capacitance to reduce the overshoot because these
solutions provide a path to dissipate the excess charge.
8.1.18 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained; see the 图 6-16 curve. There are two key transitions during a load
transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The
regions shown in 图 8-9 are broken down in this section. Regions A, E, and H are where the output voltage is in
steady-state.
During transitions from a light load to a heavy load, the:
• Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B).
• Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C).
During transitions from a heavy load to a light load, the:
• Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F).
• Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G).
Transitions between current levels changes the internal power dissipation because the TPS7A84 is a high-
current device (region D). The change in power dissipation changes the die temperature during these transitions,
and leads to a slightly different voltage level. This different output voltage level shows up in the various load
transient responses; see the 图6-16 curve.
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor; see the 图6-18 curve.
tAt
tCt
tDt
tEt
tGt
tHt
B
F
图8-9. Load Transient Waveform
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8.1.19 Negatively-Biased Output
The device does not start or operate as expected if the output voltage is pulled below ground. This issue
commonly occurs when powering a split-rail system where the negative rail is established before the device is
enabled. Several application solutions are:
• Enable the device before the negative regulator and disable the device after the negative regulator.
• Delaying the EN voltage with respect to the IN voltage allows the internal pulldown resistor to discharge any
voltage at OUT. If the discharge circuit is not strong enough to keep the output voltage at ground, then use an
external pulldown resistor.
• Place a zener diode from IN to OUT to provide a small positive dc bias on the output when the input is
supplied to the device, as shown in 图8-10.
IN
VIN
OUT
To Load
COUT
GND
图8-10. Zener Diode Placed from IN to OUT
• Use a PFET to isolate the output of the device from the load causing the negative bias when the device is off,
as shown in 图8-11.
To All Other Loads
To Loads with
Negative Bias
IN
VIN
OUT
COUT
GND
图8-11. PFET to Isolate the Output from the Load
8.1.20 Reverse Current Protection
As with most LDOs, this device can be damaged by excessive reverse current.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the
absolute maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT, then the input supply collapses quickly and the load current becomes very
small
• The output is biased when the input supply is not established
• The output is biased above the input supply
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If an excessive reverse current flow is expected in the application, then external protection must be used to
protect the device. 图8-12 shows one approach of protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
Device
COUT
CIN
GND
图8-12. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.21 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. PD can be calculated using 方程式9:
PD = (VIN –VOUT) × IOUT
(9)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to
be obtained. The low dropout of the TPS7A84 allows for maximum efficiency across a wide range of output
voltages.
The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad
to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any
inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to 方程
式10. The equation is rearranged for output current in 方程式11.
TJ = TA + (RθJA × PD)
(10)
(11)
IOUT = (TJ –TA) / [RθJA × (VIN –VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the VQFN package junction-to-case (bottom) thermal
resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.
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8.1.22 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the Electrical Characteristics table and are used in accordance with 方程式12.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
(12)
where:
• PD is the power dissipated as explained in 方程式9
• TT is the temperature at the center-top of the device package, and
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.23 Recommended Area for Continuous Operation (RACO)
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator can be separated into the
following parts, and is shown in 图8-13:
• Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output
(VIN –VOUT) at a given output current level.
• Limited by rated output current: The rated output current limits the maximum recommended output current
level. Exceeding this rating causes the device to fall out of specification.
• Limited by thermals: The shape of the slope is given by 方程式11. The slope is nonlinear because the
junction temperature of the LDO is controlled by the power dissipation across the LDO; therefore, when VIN
–VOUT increases, the output current must decrease in order to ensure that the rated junction temperature of
the device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and
reduces long-term reliability.
• Limited by VIN range: The rated input voltage range governs both the minimum and maximum of VIN –VOUT
.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Minimum VIN
Limited by
Maximum VIN
VIN œ VOUT (V)
图8-13. Continuous Operation Slope Region Description
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图8-14 to 图8-19 show the recommended area of operation curves for this device on a JEDEC-standard high-K
board with a RθJA = 35.4°C/W, as given in the Electrical Characteristics table.
5
4.5
4
5
4.5
4
TA = 40èC
TA = 40èC
TA = 55èC
TA = 55èC
TA = 70èC
TA = 85èC
RACO at TA = 85èC
TA = 70èC
TA = 85èC
RACO at TA = 85èC
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
图8-14. Recommended Area for Continuous
图8-15. Recommended Area for Continuous
Operation for VOUT = 0.9 V With Bias
Operation for VOUT = 1.2 V With Bias
5
5
TA = 40èC
TA = 40èC
4.5
4.5
TA = 55èC
TA = 55èC
TA = 70èC
TA = 85èC
RACO at TA = 85èC
TA = 70èC
TA = 85èC
RACO at TA = 85èC
4
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
图8-16. Recommended Area for Continuous
图8-17. Recommended Area for Continuous
Operation for VOUT = 1.8 V
Operation for VOUT = 2.5 V
5
5
TA = 40èC
TA = 40èC
4.5
4.5
TA = 55èC
TA = 55èC
TA = 70èC
TA = 85èC
RACO at TA = 85èC
TA = 70èC
TA = 85èC
RACO at TA = 85èC
4
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
图8-18. Recommended Area for Continuous
图8-19. Recommended Area for Continuous
Operation for VOUT = 3.3 V
Operation for VOUT = 5.0 V
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8.2 Typical Applications
8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
This section discusses the implementation of the TPS7A84 using the ANY-OUT configuration to regulate a 3.0-A
load requiring good PSRR at high frequency with low-noise at 0.9 V using a 1.3-V input voltage and a 5.0-V bias
supply. The schematic for this typical application circuit is provided in 图8-20.
CBIAS
Bias
Supply
BIAS
EN
IN
PG
OUT
SNS
FB
RPG
Input
Supply
To Load
COUT
CIN
Device
CFF
NR/SS
CNR/SS
GND 50mV 100mV 200mV 400mV 800mV 1.6V
图8-20. Typical Application
8.2.1.1 Design Requirements
For this design example, use the parameters listed in 表8-6 as the input parameters.
表8-6. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
1.3 V, ±3%, provided by the dc-dc converter switching at 500 kHz
Bias voltage
5.0 V, ±5%
Output voltage
0.9 V, ±1%
Output current
3.0 A (maximum), 100 mA (minimum)
RMS noise, 10 Hz to 100 kHz
PSRR at 500 kHz
Start-up time
< 10 µVRMS
> 40 dB
< 25 ms
8.2.1.2 Detailed Design Procedure
At 3.0 A, the dropout of the TPS7A84 has 180-mV maximum dropout over temperature, thus a 400-mV
headroom is sufficient for operation over both input and output voltage accuracy. The bias rail is provided for
better performance for the LILO conditions. The PSRR is greater than 40 dB in these conditions, as per the 图
6-1 curve. Noise is less than 10 µVRMS, as per the 图6-8 curve.
The ANY-OUT internal resistor network is also used for maximum accuracy.
To achieve 0.9 V on the output, the 100mV pin is grounded. The voltage value of 100 mV is added to the 0.8-V
internal reference voltage for VOUT(nom) equal to 0.9 V, as described in 方程式13.
VOUT(nom) = VNR/SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V
(13)
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Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.
Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the
output are selected.
To satisfy the required start-up time and still maintain low-noise performance, a 100-nF CNR/SS is selected. This
value is calculated with 方程式14.
tSS = (VNR/SS × CNR/SS) / INR/SS
(14)
At the 3.0-A maximum load, the internal power dissipation is 1.2 W and corresponds to a 42.48°C junction
temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient
temperature, the junction temperature is at 97.5°C. To further minimize noise, a feed-forward capacitance (CFF)
of 10 nF is selected.
8.2.1.3 Application Curves
10
9
8
7
6
5
4
3
2
1
0
100
75
1.2
1
IOUT
VOUT, AC
50
25
0.8
0.6
0.4
0.2
0
0
-25
-50
-75
-100
-125
-150
VEN
VOUT, CNR/SS = 0 nF
VOUT, CNR/SS = 10 nF
VOUT, CNR/SS = 47 nF
VOUT, CNR/SS = 100 nF
0
10
20
30
40
50
Time (ms)
60
70
80
90 100
-0.2
0
5
10
15
20 25
Time (ms)
30
35
40
45
50
图8-21. Output Load Transient Response
图8-22. Output Start-Up Response
8.2.2 Typical Application for a 5.0-V Rail
This section discusses the implementation of the TPS7A84 using an adjustable feedback network to regulate a
3-A load requiring good PSRR at high frequency with low-noise at an output voltage of 5.0 V. The schematic for
this typical application circuit is provided in 图8-23.
Optional Bias
CBIAS
Supply
BIAS
EN
IN
PG
OUT
SNS
FB
RPG
Input
Supply
To Load
CIN
COUT
Device
CFF
R1
R2
NR/SS
CNR/SS
GND 50mV 100mV 200mV 400mV 800mV 1.6V
图8-23. Typical Application
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8.2.2.1 Design Requirements
For this design example, use the parameters listed in 表8-6 as the input parameters.
表8-7. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
5.50 V, ±1%, provided by the dc-dc converter switching at 500 kHz
Bias voltage
Not used because VOUT ≥2.20 V
Output voltage
5.0 V, ±1%
Output current
3.0 A (maximum), 10 mA (minimum)
RMS noise, 10 Hz to 100 kHz
PSRR at 500 kHz
Start-up time
< 10 µVRMS
> 40 dB
< 25 ms
8.2.2.2 Detailed Design Procedure
At 3.0 A and 5.0 VOUT, the dropout of the TPS7A84 has a 340-mV maximum dropout over temperature, thus a
500-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high
temperature on some devices, the TPS7A84 can enter dropout if both the input and output supply are beyond
the edges of their accuracy specification.
For a 5.0-V output. use external adjustable resistors. See the resistor values in listed 表 8-5 for choosing
resistors for a 5.0-V output.
Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.
Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the
output are selected.
To satisfy the required start-up time and still maintain low noise performance, a 100-nF CNR/SS is selected. This
value is calculated with 方程式14.
tSS = (VNR/SS × CNR/SS) / INR/SS
(15)
At the 3.0-A maximum load, the internal power dissipation is 1.5 W and corresponds to a 53.1°C junction
temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient
temperature, the junction temperature is at 108.1°C. To further minimize noise, a feed-forward capacitance (CFF)
of 10 nF is selected.
8.2.2.3 Application Curves
100
80
60
40
20
0
100
80
60
40
20
0
IOUT = 0.1 A
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 2.5 A
IOUT = 3.0 A
VIN = 5.30 V
VIN = 5.35 V
VIN = 5.40 V
VIN = 5.45 V
VIN = 5.50 V
VIN = 5.55 V
VIN = 5.60 V
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106
1x107
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106
1x107
图8-24. PSRR vs Frequency and IOUT for VOUT = 5.0 图8-25. PSRR vs Frequency and VIN for VOUT = 5.0
V
V at IOUT = 3.0 A
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9 Power Supply Recommendations
The TPS7A84 is designed to operate from an input voltage supply range between 1.1 V and 6.5 V. If the input
supply is less than 1.4 V, then a bias rail of at least 3.0 V must be used. The input voltage range provides
adequate headroom in order for the device to have a regulated output. This input supply must be well regulated.
If the input supply is noisy, additional input capacitors with low ESR can help improve output noise performance.
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10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. The grounding and layout scheme illustrated in 图 10-1 minimizes
inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability.
A ground reference plane is also recommended and is either embedded in the PCB itself or located on the
bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output
voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when
connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal
requirements.
10.2 Layout Example
Ground Plane for Thermal Relief and Signal
Ground
10
9
8
7
6
To PG Pullup Supply
PG Output
1.6V 11
BIAS
5
50mV
PG
CBIAS
RPG
To Bias Supply
To Signal Ground
Enable Signal
12
4
3
Thermal Pad
R2
NR/SS 13
EN 14
FB
To Signal Ground
To Load
CNR/SS
2
1
SNS
OUT
CFF R1
15
IN
16
18 19 20
17
Input Power Plane
Output Power Plane
CIN
COUT
Power Ground Plane
Vias used for application purposes.
图10-1. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A84. The summary information for this fixture is shown in 表11-1.
表11-1. Design Kits and Evaluation Modules
NAME
LITERATURE NUMBER
TPS7A8400EVM-753 evaluation module
SBVU028
The EVM can be requested at the Texas Instruments web site through the TPS7A84 product folder.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS7A84 is available through the TPS7A84 product folder
under simulation models.
11.1.2 Device Nomenclature
表11-2. Ordering Information(1)
PRODUCT
DESCRIPTION
YYY is the package designator.
Z is the package quantity.
TPS7A84YYYZ
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS3702 High-Accuracy, Overvoltage and Undervoltage Monitor data sheet
• Texas Instruments, TPS7A8400EVM-753 Evaluation Module user's guide
• Texas Instruments, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator
application report
• Texas Instruments, 6A Current-Sharing Dual LDO design guide
11.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.5 Trademarks
ANY-OUT™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A8400RGRR
TPS7A8400RGRT
ACTIVE
ACTIVE
VQFN
VQFN
RGR
RGR
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
11CI
11CI
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A8400RGRR
TPS7A8400RGRR
TPS7A8400RGRT
TPS7A8400RGRT
VQFN
VQFN
VQFN
VQFN
RGR
RGR
RGR
RGR
20
20
20
20
3000
3000
250
330.0
330.0
180.0
180.0
12.4
12.4
12.4
12.4
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A8400RGRR
TPS7A8400RGRR
TPS7A8400RGRT
TPS7A8400RGRT
VQFN
VQFN
VQFN
VQFN
RGR
RGR
RGR
RGR
20
20
20
20
3000
3000
250
335.0
367.0
210.0
182.0
335.0
367.0
185.0
182.0
25.0
35.0
35.0
20.0
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGR 20
3.5 x 3.5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228482/A
www.ti.com
PACKAGE OUTLINE
RGR0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
3.65
3.35
SIDE WALL
METAL THICKNESS
DIM A
1.0
0.8
OPTION 1
0.1
OPTION 2
0.2
C
SEATING PLANE
0.08 C
0.05
0.00
2X 2
(DIM A) TYP
SYMM
6
10
EXPOSED
THERMAL PAD
11
5
SYMM
21
2X 2
2.05 0.1
16X 0.5
1
15
0.30
20X
PIN 1 ID
20
16
0.18
0.5
0.3
0.1
C A B
20X
0.05
4219031/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGR0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
16
SEE SOLDER MASK
DETAIL
20
20X (0.6)
15
20X (0.24)
16X (0.5)
1
(2.05)
SYMM
21
(3.3)
(0.775)
5
11
(R0.05) TYP
(
0.2) TYP
VIA
6
10
(0.775)
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219031/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGR0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.56) TYP
16
20
20X (0.6)
1
20X (0.24)
16X (0.5)
15
(0.56) TYP
(3.3)
21
SYMM
4X (0.92)
11
(R0.05) TYP
5
6
10
4X (0.92)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 21
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219031/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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