TPS7A8701RTJT [TI]
500mA、低噪声、高 PSRR、双通道可调节超低压降稳压器 | RTJ | 20 | -40 to 125;
| 型号： | TPS7A8701RTJT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 500mA、低噪声、高 PSRR、双通道可调节超低压降稳压器 | RTJ | 20 | -40 to 125 输出元件 稳压器 调节器 |
| 文件： | 总48页 (文件大小：3609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A87
ZHCSF74A –MARCH 2016–REVISED JULY 2016
TPS7A87
双路 500mA 低噪声 (3.8 µVRMS) LDO 稳压器
1 特性
3 说明
1
•
•
•
•
•
•
两个独立的 LDO 通道
TPS7A87 是一款双路低噪声 (3.8µVRMS) 低压降
(LDO) 稳压器，每通道具有 500mA 的拉电流能力，其
最高压降仅为 100mV。
低输出噪声：3.8µVRMS (10Hz–100kHz)
低压降：电流为 0.5A 时最大 100mV
宽输入电压范围：1.4V 至 6.5V
宽输出电压范围：0.8V 至 5.2V
高电源纹波抑制：
TPS7A87 提供两个独立的 LDO，极具灵活性，解决方
案尺寸要比两个单通道 LDO 小 30% 左右。每个输出
可通过外部电阻在 0.8V 至 5.2 V 范围内进行调节。
TPS7A87 的宽输入电压范围支持其在 1.4V 至 6.5V 范
围内的电压下工作。
–
–
–
直流时为 75dB
100kHz 时为 40dB
1MHz 时为 40dB
TPS7A87 的输出电压精度（整个线路、负载和温度范
围内）达 1%，并且可通过软启动功能减少浪涌电流，
因此非常适合为敏感类模拟低压器件 [例如，压控振荡
器 (VCO)、模数转换器 (ADC)、数模转换器 (DAC)、
互补金属氧化物半导体 (CMOS) 传感器和视频特定用
途集成电路 (ASIC)] 供电。
•
•
•
•
•
•
整个线路、负载和温度范围内的精度达 1.0%
出色的负载瞬态响应
可调节的启动浪涌控制
可选软启动充电电流
独立开漏电源正常 (PGx) 输出
与 10µF 或更大的陶瓷输出电容一起工作时保持稳
定
TPS7A87 旨在为噪声敏感类组件供电，广泛适用于仪
器仪表、医疗、视频、专业音频、测试和测量以及高速
通信等 应用。此器件具有 3.8 µVRMS 的超低输出噪声
和宽带电源抑制比 (PSRR)（1MHz 时为 40dB），最
大限度减少了相位噪声和时钟抖动。这些 功能 最大限
度提升了计时器件、ADC 和 DAC 的性能。
•
4mm × 4mm 20 引脚超薄型四方扁平无引线
(WQFN) 封装
2 应用
•
高速模拟电路：
–
压控振荡器 (VCO)、模数转换器 (ADC)、数模
转换器 (DAC) 以及低压差分信令 (LVDS)
器件信息(1)
•
成像：互补金属氧化物半导体 (CMOS) 传感器，视
频专用集成电路 (ASIC)
器件型号
TPS7A87
封装
WQFN (20)
封装尺寸（标称值）
4.00mm x 4.00mm
•
•
•
测试和测量
仪器仪表和医疗
专业音频
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
为信号链供电
ENABLE
典型应用电路
LMK03328
LMX2581
Clock
PG1
VIN1
IN1
TPS7A87
VIN1
IN1
VOUT1
COUT1
OUT1
FB1
EN1
EN1
OUT1
OUT2
VDD_VCO
R11
CIN1
EN1
TPS7A87
VIN2
IN2
SS_CTRL1
EN2
EN2
R21
PG2
NR/SS1
CNR/SS1
VDD
SCLK
ADC
PG1
ADC3xxx
ADC3xJxx
ADC3xJBxx
ADS4xxBxx
ADS5xxx
VIN2
VOUT2
COUT2
OUT2
IN2
R12
CIN2
EN2
FB2
ADS52J90
SS_CTRL2
NR/SS2
ENABLE
R22
Copyright © 2016, Texas Instruments Incorporated
CNR/SS2
PG2
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS281
TPS7A87
ZHCSF74A –MARCH 2016–REVISED JULY 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 17
8
9
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 32
Power Supply Recommendations...................... 33
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 器件和文档支持 ..................................................... 36
11.1 器件支持 ............................................................... 36
11.2 文档支持 ............................................................... 36
11.3 接收文档更新通知 ................................................. 36
11.4 社区资源................................................................ 37
11.5 商标....................................................................... 37
11.6 静电放电警告......................................................... 37
11.7 Glossary................................................................ 37
12 机械、封装和可订购信息....................................... 37
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (March 2016) to Revision A
Page
•
已发布为“量产数据”................................................................................................................................................................. 1
2
Copyright © 2016, Texas Instruments Incorporated
TPS7A87
www.ti.com.cn
ZHCSF74A –MARCH 2016–REVISED JULY 2016
5 Pin Configuration and Functions
RTJ Package
4-mm × 4-mm, 20-Pin WQFN
Top View
IN1
IN1
1
2
3
4
5
15
14
OUT1
OUT1
GND
Thermal
13
GND
IN2
Pad
12
OUT2
OUT2
IN2
11
Not to scale
Pin Functions
PIN
NAME
NO.
20
6
I/O
DESCRIPTION
Enable pin for each channel. These pins turn the regulator on and off. If VENx(1) ≥ VIH(ENx), then the regulator is enabled.
If VENx ≤ VIL(ENx), then the regulator is disabled. The ENx pin must be connected to INx if the enable function is not used.
EN1
EN2
FB1
I
16
Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FBx to OUTx
(as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor
can disrupt PGx (power good) functionality. See the Feed-Forward Capacitor (CFFx) and Setting the Output Voltage
(Adjustable Operation) sections for more details.
I
FB2
10
Ground pin.
GND
IN1
3, 13
1, 2
—
These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
Input supply pin for LDO 1.
A 10 µF or greater input capacitor is required. Place the input capacitor as close to the input as possible.
I
I
Input supply pin for LDO 2.
A 10 µF or greater input capacitor is required. Place the input capacitor as close to the input as possible.
IN2
4, 5
19
NR/SS1
Noise-reduction and soft-start pin for each channel. Connecting an external capacitor between this pin and ground
reduces reference voltage noise and also enables the soft-start function. Although not required, a 10 nF or larger
capacitor is recommended to be connected from NR/SSx to GND (as close to the pin as possible) to maximize ac
performance. See the Noise-Reduction and Soft-Start Capacitor (CNR/SSx) section for more details.
—
NR/SS2
OUT1
7
Regulated output for LDO 1. A 10-μF or larger ceramic capacitor (5 μF or greater of effective capacitance) from OUTx to
ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the
OUT1 pin to the load. See the Input and Output Capacitor (CINx and COUTx) section for more details.
14, 15
O
O
O
Regulated output for LDO 2. A 10-μF or larger ceramic capacitor (5 μF or greater of effective capacitance) from OUTx to
ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the
OUT2 pin to the load. See the Input and Output Capacitor (CINx and COUTx) section for more details.
OUT2
11, 12
PG1
PG2
17
9
Open-drain power-good indicator pins for the LDO 1 and LDO 2 output voltages. A 10-kΩ to 100-kΩ external pullup
resistor is required. These pins can be left floating or connected to GND if not used. The use of a feed-forward capacitor
can disrupt power-good functionality. See the Feed-Forward Capacitor (CFFx) section for more details.
SS_CTRL1
SS_CTRL2
Thermal pad
18
8
Soft-start control pin for each channel. Connect these pins either to GND or INx to allow normal or fast charging of the
NR/SSx capacitor. If a CNR/SSx capacitor is not used, SS_CTRLx must be connected to GND to avoid output overshoot.
I
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.
Copyright © 2016, Texas Instruments Incorporated
3
TPS7A87
ZHCSF74A –MARCH 2016–REVISED JULY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
INx, PGx, ENx(2)
7.0
7.5
VINx + 0.3(3)
VINx + 0.3(3)
3.6
INx, PGx, ENx (5% duty cycle, pulse duration = 200 µs)
Voltage
OUTx
V
SS_CTRLx
NR/SSx, FBx(2)
OUTx(2)
PGx (sink current into device)(2)
Operating junction, TJ
Storage, Tstg
Internally limited
A
Current
5
mA
–55
–55
150
150
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.
(3) The absolute maximum rating is VINx + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
MAX
6.5
UNIT
VINx
Input supply voltage range
Output voltage range
1.4
V
V
VOUTx
IOUTx
CINx
0.8 – 1%
5.2 + 1%
500
Output current
0
10
10
mA
µF
µF
µF
kΩ
°C
Input capacitor, each input
Output capacitor
COUTx
CNR/SSx
RPGx
TJ
Noise-reduction capacitor
Power-good pullup resistance
Junction temperature range
1
100
125
10
–40
6.4 Thermal Information
TPS7A87
THERMAL METRIC(1)
RTJ (WQFN)
UNIT
20 PINS
33
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
26.8
8.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.0
RθJC(bot)
2.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
4
Copyright © 2016, Texas Instruments Incorporated
TPS7A87
www.ti.com.cn
ZHCSF74A –MARCH 2016–REVISED JULY 2016
6.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to +125°C), VINx = 1.4 V or VOUTx(TARGET) + 0.2 V (whichever is greater),
VOUTx(TARGET) = 0.8 V, IOUTx = 50 mA, VENx = 1.4 V, COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, SS_CTRLx = GND, PGx pin
pulled up to VINx with 100 kΩ, and for each channel (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
VINx
Input supply voltage range
Reference voltage
Input supply UVLOx
VUVLOx hysteresis
Output voltage range
VOUTx accuracy(2)
Line regulation
1.4
6.5
V
VREF
0.8
1.31
290
V
VUVLOx
VUVLOx(HYS)
VOUTx
VINx rising
1.39
V
VINx falling hysteresis
mV
V
0.8 – 1%
–1.0%
5.2 + 1%
1.0%
0.8 V ≤ VOUTx ≤ 5.2 V, 5 mA ≤ IOUTx ≤ 0.5 A
IOUTx = 5 mA, 1.4 V ≤ VINx ≤ 6.5 V
5 mA ≤ IOUTx ≤ 0.5 A
ΔVOUTx(ΔVINx)
ΔVOUTx(ΔIOUTx)
0.003
0.03
%/V
%/A
Load regulation
1.4 V ≤ VINx ≤ 5.3 V
IOUTx = 0.5 A, VFBx = 0.8 V – 3%
VDO
ILIM
Dropout voltage
100
1.5
3.5
mV
A
Output current limit
VOUTx forced at 0.9 × VOUTx(TARGET)
,
0.8
1.1
2.1
Both channels enabled, per channel,
VINx = 6.5 V, IOUTx = 5 mA
IGND
GND pin current
mA
Both channels enabled, per channel,
VINx = 1.4 V, IOUTx = 0.5 A
4
Both channels shutdown, per channel, PGx = (open),
VINx = 6.5 V, VENx = 0.4 V
ISDN
Shutdown GND pin current
ENx pin current
0.1
15
0.2
0.4
μA
μA
V
IENx
VINx = 6.5 V, 0 V ≤ VENx ≤ 6.5 V
–0.2
0
ENx pin low-level input voltage
(device disabled)
VIL(ENx)
ENx pin high-level input voltage
(device enabled)
VIH(ENx)
ISS_CTRLx
VIT(PGx)
1.1
–0.2
82%
6.5
0.2
V
SS_CTRLx pin current
PGx pin threshold
VINx = 6.5 V, 0 V ≤ VSS_CTRLx ≤ 6.5 V
μA
For PGx transitioning low with falling VOUTx
expressed as a percentage of VOUTx(TARGET)
,
88.9%
1%
93%
For PGx transitioning high with rising VOUTx
expressed as a percentage of VOUTx(TARGET)
,
Vhys(PGx)
PGx pin hysteresis
VOL(PGx)
Ilkg(PGx)
PGx pin low-level output voltage VOUTx < VIT(PGx), IPGx = –1 mA (current into device)
0.4
1
V
PGx pin leakage current
VOUTx > VIT(PGx), VPGx = 6.5 V
µA
VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V,
VSS_CTRLx = GND
4.0
6.2
9.0
INR/SSx
NR/SSx pin charging current
µA
VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V, VSS_CTRLx = VINx
65
100
150
100
IFBx
FBx pin leakage current
VINx = 6.5 V, VFBx = 0.8 V
–100
nA
dB
f = 500 kHz, VINx = 3.8 V, VOUTx = 3.3 V,
IOUTx = 250 mA, CNR/SSx = 10 nF, CFFx = 10 nF
PSRR
Power-supply rejection ratio
40
3.8
11
BW = 10 Hz to 100 kHz, VINx = 1.8 V, VOUTx = 0.8 V,
IOUTx = 0.5 A, CNR/SSx = 1 µF, CFFx = 100 nF
Vn
Output noise voltage
Noise spectral density
μVRMS
nV/√Hz
Ω
f = 10 kHz, VINx = 1.8 V, VOUTx = 0.8 V,
IOUTx = 0.5 A, CNR/SSx = 10 nF, CFFx = 10 nF
Output active discharge
resistance
Rdiss
VENx = GND
250
Shutdown, temperature increasing
Reset, temperature decreasing
160
140
Tsdx
Thermal shutdown temperature
°C
(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2.
(2) When the device is connected to external feedback resistors at the FBx pins, external resistor tolerances are not included.
版权 © 2016, Texas Instruments Incorporated
5
TPS7A87
ZHCSF74A –MARCH 2016–REVISED JULY 2016
www.ti.com.cn
6.6 Typical Characteristics
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
100
80
60
40
20
0
100
80
60
40
20
0
CNR/SS = 10 nF, CFF = 10 nF, COUT = 10 mF
CNR/SS = 0 nF, CFF = 0 nF, COUT = 10 mF
CNR/SS = 1000 nF, CFF = 1000 nF, COUT = 10 mF
CNR/SSx = 10 nF
CNR/SSx = 0 nF
CNR/SSx = 100 nF
CNR/SSx = 1000 nF
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
IOUTx = 500 mA, VINx = 5.3 V
VOUTx = 5 V, VINx = 5.3 V, VENx = 1.7 V, IOUTx = 500 mA,
COUTx = 10 µF, CFFx = 10 nF
图 2. Power-Supply Rejection Ratio vs
图 1. Power-Supply Rejection Ratio at VOUTx = 5.0 V
Frequency and CNR/SSx
100
100
VINx = 1.4 V
VINx = 1.45 V
VINx = 1.5 V
VINx = 1.55 V
VINx = 1.6 V
VINx = 1.65 V
VINx = 1.7 V
IOUTx = 10 mA
IOUTx = 50 mA
IOUTx = 100 mA
IOUTx = 250 mA
IOUTx = 500 mA
80
60
40
20
0
80
60
40
20
0
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
VOUTx = 1.2 V, IOUTx = 500 mA, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
VOUTx = 1.2 V, VINx = 1.4 V, VENx = 3.8 V, IOUTx = 500 mA,
COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
图 3. Power-Supply Rejection Ratio vs
图 4. Power-Supply Rejection Ratio vs
Frequency and Input Voltage
Frequency and Output Current
110
100
90
80
70
60
50
40
30
20
100
COUTx = 10 mF
COUTx = 100 mF
COUTx = 200 mF
COUTx = 500 mF
COUTx = 500 mF || 1 mF OSCON
80
60
40
20
0
VOUT1 to VOUT2
VOUT2 to VOUT1
10
0
10
100
1k
10k
100k
1M
10M
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VOUTx = 5.0 V, VINx = 5.3 V, VENx = 1.7 V, IOUTx = 500 mA,
COUTx = ceramic, CFFx = 10 nF
VOUTx = 1.8 V, IOUTx = 100 mA, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
图 5. Power-Supply Rejection Ratio vs
图 6. Channel-to-Channel Output Voltage Isolation vs
Frequency
Frequency and Output Capacitance
6
版权 © 2016, Texas Instruments Incorporated
TPS7A87
www.ti.com.cn
ZHCSF74A –MARCH 2016–REVISED JULY 2016
Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
14
12
10
8
50
Nominal Noise Figure
CNR/SSx = 1 mF, CFFx = 100 nF
CNR/SSx = 1 mF, CFFx = 100 nF, SS_CTRLx = GND
CNR/SSx = 10 nF, CFFx = 10 nF, COUTx = 22 mF||1 mF
CFFx = 10 nF, CNR/SSx = 10 nF
CFFx = 100 nF, CNR/SSx = 1 mF
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
6
0.002
0.001
0.0005
4
10
100
1k
10k
100k
1M
10M
0.8
1.6
2.4
3.2
4
4.8
5.6
Frequency
Output Voltage (V)
IOUTx = 500 mA
IOUTx = 500 mA
图 7. Output Noise vs Output Voltage
图 8. Output Noise at VOUTx = 5 V
10
1
10
1
VOUTx = 0.8 V, 3.94 mVRMS
VOUTx = 1.2 V, 4.31 mVRMS
VOUTx = 1.8 V, 5.1 mVRMS
VOUTx = 2.5 V, 6.03 mVRMS
VOUTx = 3.3 V, 7.43 mVRMS
VOUTx = 5.0 V, 10.3 mVRMS
CNR/SSx = None, 11.43 mVRMS
CNR/SSx = 0.01 mF, 4.94 mVRMS
CNR/SSx = 0.1 mF, 4.24 mVRMS
CNR/SSx = 1.0 mF, 4.22 mVRMS
0.1
0.1
0.01
0.01
0.001
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VINx = VOUTx + 1.0 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100
kHz, COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
VINx = 1.7 V, VOUTx = 1.2 V, IOUTx = 500 mA, VRMS BW = 10 Hz to
100 kHz, COUTx = 10 µF, CFFx = 10 nF
图 9. Noise vs Frequency and Output Voltage
图 10. Noise vs Frequency and CNR/SSx
10
10
CFFx = 0 mF
CFFx = 0.01 mF
CFFx = 0.1 mF
VINx = 1.5 V
VINx = 1.8 V
VINx = 2.5 V
VINx = 3.3 V
1
0.1
1
0.1
0.01
0.01
0.001
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VINx = 3.8 V, VOUTx = 3.3 V, IOUTx = 500 mA, VRMS BW = 10 Hz to
100 kHz, COUTx = 10 µF, CNR/SSx = 10 nF
VOUTx = 1.2 V, IOUTx = 500 mA, COUTx = 10 µF, CNR/SSx = 10 nF
图 11. Noise vs Frequency and CFFx
图 12. Noise vs Frequency and VINx
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
10
1
12
10
8
COUTx = 10 mF, 4.94 mVRMS
COUTx = 22 mF, 5.05 mVRMS
COUTx = 100 mF, 5.66 mVRMS
0.1
6
4
0.01
2
0.001
0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E-6
1E-5 0.0001 0.001
0.01
0.1
1
10
Frequency (Hz)
Noise Reduction Capacitor [CNR/SSx] (mF)
VOUTx = 1.8 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100 kHz,
CFFx = 0.01 µF
VOUTx = 1.8 V, IOUTx = 500 mA, CFFx = 0.01 µF,
BW = 10 Hz to 100 kHz
图 13. Noise vs Frequency and COUTx
图 14. RMS Output Noise vs CNR/SSx
12
50
25
0
2
VOUTx = 5.0 V
VOUTx = 3.3 V
VOUTx = 1.2 V
VOUTx = 0.9 V
IOUTx
10
8
1.5
1
6
4
-25
-50
0.5
2
0
0
1E-6
1E-5
0.0001
0.001
0.01
0.1
0
200
400
600
800
1000
Feed-Forward Capacitor [CFFx] (mF)
Time (ms)
VOUTx = 1.8 V, IOUTx = 500 mA, CNR/SSx = 1 µF,
BW = 10 Hz to 100 kHz
VINx = VOUTx + 0.3 V, IOUTx = 10 mA to 500 mA, COUTx = 10 µF,
CFFx = CNR/SSx = 10 nF
图 16. Load Transient Response vs VOUTx
图 15. RMS Output Noise vs CFFx
50
IOUTx = 1 mA to 500 mA
IOUTx = 10 mA to 500 mA
IOUTx = 50 mA to 500 mA
IOUTx = 100 mA to 500 mA
VINx
2 V/div
25
0
VOUTx
20 mV/div
-25
-50
VPGx
1 V/div
0
200
400
600
800
1000
Time (ms)
Time (200 ms/div)
VINx = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, VOUTx = 0.8 V,
IOUTx = 500 mA, CNR/SSx = CFFx = 10 nF
VINx = 5.3 V, COUTx = 10 µF, CFFx = CNR/SSx = 10 nF
图 17. Load Transient Response vs DC Load
图 18. Line Transient
8
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
1.25
1.2
VENx
VOUTx
200 mV/div
1 V/div
1.15
1.1
VPGx
200mV/div
1.05
1
0.95
-40èC
0èC
25èC
85èC
125èC
3 3.5
0.9
0
0.5
1
1.5
2
2.5
Output Voltage (V)
Time (50 ms/div)
VINx = 3.4 V, VOUTx = 3.3 V, 125°C curve truncated because of
device entering thermal shutdown
VINx = 1.4 V
图 20. Start-Up (SS_CTRLx = GND, CNR/SSx = 0 nF)
图 19. Current Limit Foldback
VEN1
1 V/div
VEN1
1 V/div
VOUT1
200 mV/div
VOUT1
200 mV/div
VPG1
200 mV/div
VPG1
200 mV/div
Time (50 ms/div)
Time (500 ms/div)
VINx = 1.4 V
VINx = 1.4 V
图 22. Start-Up (SS_CTRLx = VINx, CNR/SSx = 10 nF)
图 21. Start-Up (SS_CTRLx = GND, CNR/SSx = 10 nF)
80
60
40
20
0
VINx = 1.4 V
VINx = 1.8 V
VINx = 3.6 V
VINx = 4.8 V
VINx = 5.6 V
VINx = 5.8 V
VEN1
1 V/div
VOUT1
200 mV/div
VPG1
200 mV/div
0
0.1
0.2
0.3
0.4
0.5
Time (2 ms/div)
VINx = 1.4 V
Output Current (A)
图 23. Start-Up (SS_CTRLx = VINx, CNR/SSx = 1 µF)
图 24. Dropout Voltage vs Output Current
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
90
85
80
75
70
65
60
55
50
45
40
35
30
0.05
0.025
0
-40èC
0èC
25èC
85èC
125èC
-0.025
-0.05
-0.075
-40èC
0èC
25èC
85èC
125èC
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.1
0.2
0.3
0.4
0.5
0.5
0.5
Input Voltage (V)
Output Current (A)
IOUTx = 500 mA
图 25. Dropout Voltage vs Input Voltage
图 26. Load Regulation (VOUTx = 1.2 V)
0.045
0.03
0.5
0.25
0
-40èC
0èC
25èC
85èC
125èC
-40èC
0èC
25èC
85èC
125èC
0.015
0
-0.25
-0.5
-0.015
-0.03
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0
0.1
0.2
0.3
0.4
Input Voltage (V)
Output Current (A)
IOUTx = 50 mA
VINx = 3.8 V
图 27. Line Regulation (VOUTx = 0.8 V)
图 28. Load Regulation (VOUTx = 3.3 V)
0.5
0.25
0
0.06
0.03
0
-40èC
0èC
25èC
85èC
125èC
-0.03
-0.06
-0.09
-40èC
0èC
25èC
85èC
125èC
-0.25
-0.5
3
3.5
4
4.5
5
5.5
6
6.5
0
0.1
0.2
0.3
0.4
Input Voltage (V)
Output Current (A)
IOUTx = 5 mA
VINx = 5.5 V
图 29. Line Regulation (VOUTx = 3.3 V)
图 30. Load Regulation (VOUTx = 5.0 V)
10
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
5
4
3
2
1
0
2.2
2.15
2.1
-40èC
0èC
25èC
85èC
125èC
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
-40èC
0èC
25èC
85èC
125èC
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
Input Voltage (V)
D001
VINx = 1.4 V, both channels enabled
Both channels
图 32. Ground Current vs Output Current
图 31. Shutdown Current vs Input Voltage
5
500
400
300
200
100
0
-40èC
0èC
25èC
85èC
125èC
-40èC
0èC
25èC
85èC
125èC
4.5
4
3.5
3
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0
0.5
1
1.5
2
2.5
3
Input Voltage (V)
PG Current (mA)
D001
Both channels enabled
图 34. PGx Low Level vs PGx Current (VINx = 1.4 V)
图 33. Ground Current vs Input Voltage
90
500
-40èC
0èC
25èC
85èC
125èC
400
300
200
100
0
89.7
89.4
89.1
88.8
88.5
VINx = 1.4 V, Falling Threshold
VINx = 1.4 V, Rising Threshold
VINx = 6.5 V, Falling Threshold
VINx = 6.5 V, Rising Threshold
0
0.5
1
1.5
2
2.5
3
-40
0
40
80
120
160
PG Current (mA)
Temperature (èC)
图 35. PGx Low Level vs PGx Current (VINx = 6.5 V)
图 36. PGx Threshold vs Temperature
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
200
0.03
0.025
0.02
0.015
0.01
0.005
0
100
70
50
30
20
10
7
5
VNx = 1.4 V, SS_CTRLx = GND
VNx = 1.4 V, SS_CTRLx = VINx
VNx = 6.5 V, SS_CTRLx = GND
VNx = 6.5 V, SS_CTRLx = VINx
3
2
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40
0
40
80
120
160
Temperature (èC)
Temperature (èC)
VINx = VPGx = 6.5 V
图 37. PGx Leakage Current vs Temperature
图 38. Soft-Start Current vs Temperature
(SS_CTRLx = GND)
1.4
1.35
1.3
1
0.9
0.8
0.7
0.6
0.5
Rising Threshold
Falling Threshold
VINx = 1.4 V, Falling Threshold
VINx = 1.4 V, Rising Threshold
VINx = 6.5 V, Falling Threshold
VINx = 6.5 V, Rising Threshold
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40
0
40
80
120
160
Temperature (èC)
Temperature (èC)
图 40. Input UVLOx Threshold vs Temperature
图 39. Enable Threshold vs Temperature
12
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ZHCSF74A –MARCH 2016–REVISED JULY 2016
7 Detailed Description
7.1 Overview
The TPS7A87 is a monolithic, dual-channel, low-dropout (LDO) regulator, and each channel is low-noise, high-
PSRR, and capable of sourcing a 500-mA load with only 100 mV of maximum dropout. These features make the
device a robust solution to solve many challenging problems in generating a clean, accurate power supply.
The various features for each of the TPS7A87 fully independent LDOs simplify using the device in a variety of
applications. As detailed in the Functional Block Diagram section, these features are organized into three
categories, as shown in 表 1.
表 1. Features
VOLTAGE REGULATION
High accuracy
SYSTEM START-UP
Programmable soft-start
Sequencing controls
Power-good output
INTERNAL PROTECTION
Foldback current limit
Low-noise, high-PSRR output
Fast transient response
Thermal shutdown
7.2 Functional Block Diagram
Current
Limit
IN1
OUT1
Charge
Pump
Active
Discharge
0.8-V
VREF
+
Error
Amp
œ
Softstart
Control
INR/SSx
SS_CTRL1
NR/SS1
FB1
PG1
œ
0.89 x VREF
+
UVLO
Internal
Enable
Control
Thermal
Shutdown
EN1
IN2
Current
Limit
OUT2
Charge
Pump
Active
Discharge
0.8-V
VREF
+
Error
Amp
œ
Softstart
Control
INR/SSx
SS_CTRL2
NR/SS2
FB2
PG2
œ
0.89 x VREF
+
UVLO
Internal
Enable
Control
Thermal
Shutdown
EN2
GND
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7.3 Feature Description
7.3.1 Voltage Regulation Features
7.3.1.1 DC Regulation
An LDO functions as a class-B amplifier in which the input signal is the internal reference voltage (VREF), as
shown in 图 41. VREF is designed to have a very low-bandwidth at the input to the error amplifier through the use
of a low-pass filter (VNR/SSx).
As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes
from the combination of the output capacitor and pass element. The pass element also presents a high input
impedance to the source voltage when operating as a current source. A positive LDO can only source current
because of the class-B architecture.
This device achieves a maximum of 1% output voltage accuracy primarily because of the high-precision band-
gap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation
required by the device to regulate the output voltage at a given current level, thereby improving system
efficiency. Combined, these features help make this device a good approximation of an ideal voltage source.
This device replaces two stand-alone power-supplies, and also provides load-to-load isolation. The LDOs can
also be put in series (cascaded) to achieve even higher PSRR by connecting the output of one channel to the
input of the other channel.
VINx
To Load
R1
VREF
R2
GND
NOTE: VOUTx = VREF × (1 + R1x / R2x).
图 41. Simplified Regulation Circuit
7.3.1.2 AC and Transient Response
Each LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the
output current (load transient) resulting from the LDO high-input impedance and low output-impedance across
frequency. This same capability also means that each LDO has a high power-supply rejection-ratio (PSRR) and,
when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in ac (small-
signal) and large-signal conditions.
The performance and internal layout of the device minimizes the coupling of noise from one channel to the other
channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.
The choice of external component values optimizes the small- and large-signal response. The NR/SSx capacitor
(CNR/SSx) and feed-forward capacitor (CFFx) easily reduce the device noise floor and improve PSRR; see the
Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance.
7.3.2 System Start-Up Features
In many different applications, the power-supply output must turn-on within a specific window of time to either
ensure proper operation of the load or to minimize the loading on the input supply or other sequencing
requirements. Each LDO start-up is well-controlled and user-adjustable, solving the demanding requirements
faced by many power-supply design engineers in a simple fashion.
14
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Feature Description (接下页)
7.3.2.1 Programmable Soft-Start (NR/SSx)
Soft-start directly controls the output start-up time and indirectly controls the output current during start-up (in-
rush current).
The external capacitor at the NR/SSx pin (CNR/SSx) sets the output start-up time by setting the rise time of the
internal reference (VNR/SSx), as shown in 图 42. SS_CTRLx provides additional control over the rise time of the
internal reference by enabling control over the charging current (INR/SSx) for CNR/SSx. The voltage at the
SS_CTRLx pin (VSS_CTRLx) must be connected to ground (GND) or VINx
.
Note that if CNR/SSx = 0 nF and the SS_CTRLx pin is connected to VINx, then the output voltage overshoots during
start-up.
SW
INR/SSx
RNRx
NR/SSx Control
VREF
+
CNR/SSx
œ
VFBx
GND
图 42. Simplified Soft-Start Circuit
7.3.2.2 Sequencing
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of
the high power levels inherent in a PDN, and the variations between all of the supplies. Control of each channel
turn-on and turn-off time is set by the specific channel enable circuit (ENx) and undervoltage lockout circuit
(UVLOx), as shown in 图 43 and 表 2.
ENx
Internal Enable
Control
UVLOx
图 43. Simplified Turn-On Control
表 2. Sequencing Functionality Table
LDO
STATUS
ACTIVE
DISCHARGE
INPUT VOLTAGE
ENABLE STATUS
POWER-GOOD
ENx = 1
ENx = 0
On
Off
Off
Off
PGx = 1 when VOUTx ≥ VIT(PGx)
VINx ≥ VUVLOx
On
On(1)
PGx = 0
PGx = 0
VINx < VUVLOx – VHYS
ENx = don't care
(1) The active discharge remains on as long as VINx provides enough headroom for the discharge circuit to function.
7.3.2.2.1 Enable (ENx)
The enable signal (VENx) is an active-high digital control that enables the LDO when the enable voltage is past
the rising threshold (VENx ≥ VIH(ENx)) and disables the LDO when the enable voltage is below the falling threshold
(VENx ≤ VIL(ENx)). The exact enable threshold is between VIH(ENx) and VIL(ENx) because ENx is a digital control. In
applications that do not use the enable control, connect ENx to VINx
.
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7.3.2.2.2 Undervoltage Lockout (UVLOx) Control
The UVLOx circuit responds quickly to glitches on VINx and attempts to disable the output of the device if either
of these rails collapse.
As a result of the fast response time of the input supply UVLOx circuit, fast and short line transients well below
the input supply UVLOx falling threshold (brownouts) can cause momentary glitches during the edges of the
transient. These glitches are typical in most LDOs and, in most applications, the brownouts required for these
glitches do not result from the local input capacitance; see the Undervoltage Lockout (UVLOx) Control section for
more details.
7.3.2.2.3 Active Discharge
When either ENx or UVLOx is low, the device connects a resistor of several hundred ohms from VOUTx to GND,
discharging the output capacitance.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops
below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUTx > VINx
,
which can cause damage to the device (when VOUTx > VINx + 0.3 V); see the Reverse Current Protection section
for more details.
7.3.2.3 Power-Good Output (PGx)
The PGx signal provides an easy solution to meet demanding sequencing requirements because PGx signals
when the output nears its nominal value. PGx can be used to signal other devices in a system when the output
voltage is near, at, or above the set output voltage (VOUTx(Target)). A simplified schematic is shown in 图 44.
The PGx signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active
high. The power-good circuit sets the PGx pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFFx) delays the output voltage and, because the power-good circuit
monitors the FBx pin, the PGx signal can indicate a false positive. A simple solution to this scenario is to use an
external voltage detector device, such as the TPS3780; see the Feed-Forward Capacitor (CFFx) section for more
information.
VPGx
VBG
VINx
VFBx
œ
+
GND
ENx
GND
UVLOx
GND
图 44. Simplified PGx Circuit
16
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7.3.3 Internal Protection Features
In many applications, fault events can occur that damage devices in the system. Short-circuits and excessive
heat are the most common fault events for power supplies. The TPS7A87 implements circuitry for each LDO to
protect the device and its load during these events. Continuously operating in these fault conditions or above a
junction temperature of 125°C is not recommended because the long-term reliability of the device is reduced.
7.3.3.1 Foldback Current Limit (ICLx
)
The internal current limit circuit protects the LDO against short-circuit and excessive load current conditions. The
output current decreases (folds back) when the output voltage falls to better protect the device, as described in
图 19. Each channel features its own independent current limit circuit.
7.3.3.2 Thermal Protection (Tsdx
)
The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from current
limit or high ambient temperature. Each channel features its own independent thermal shutdown circuit.
The output of the LDO turns off when the LDO temperature (junction temperature, TJ) exceeds the rising thermal
shutdown temperature (Tsdx). The output turns on again after TJ decreases below the falling thermal shutdown
temperature (Tsdx).
A high power dissipation across the device, combined with a high ambient temperature (TA), can cause TJ to be
greater than or equal to Tsdx, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can
cycle on and off when thermal shutdown is reached under these conditions.
7.4 Device Functional Modes
表 3 provides a quick comparison between the regulation and disabled operation.
表 3. Device Functional Modes Comparison
PARAMETER
OPERATING MODE
VINx
ENx
IOUTx
IOUTx < ICLx
—
TJ
Regulation(1)
Disabled(2)
VINx > VOUTx(nom) + VDO
VINx < VUVLOx
VENx > VIH(ENx)
VENx < VIL(ENx)
TJ < Tsd
TJ > Tsd
(1) All table conditions must be met.
(2) The device is disabled when any condition is met.
7.4.1 Regulation
The device regulates the output to the targeted output voltage when all the conditions in 表 3 are met.
7.4.2 Disabled
When disabled, the pass device is turned off, the internal circuits are shutdown, and the output voltage is actively
discharged to ground by an internal resistor from the output to ground.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 External Component Selection
8.1.1.1 Setting the Output Voltage (Adjustable Operation)
Each LDO resistor feedback network sets the output voltage, as shown in 图 45, with an output voltage range of
0.8 V to 5.2 V.
TPS7A87
VIN1
IN1
VOUT1
COUT1
OUT1
FB1
R11
CIN1
EN1
SS_CTRL1
R21
NR/SS1
CNR/SS1
PG1
VIN2
VOUT2
COUT2
OUT2
IN2
R12
CIN2
EN2
FB2
SS_CTRL2
NR/SS2
R22
CNR/SS2
PG2
GND
Copyright © 2016, Texas Instruments Incorporated
图 45. Adjustable Operation
公式 1 relates the values R1x and R2x to VOUTx(Target) and VFBx. 公式 1 is a rearranged version of 公式 2,
simplifying the feedback resistor calculation. The current through the feedback network must be equal to or
greater than 5 μA for optimum noise performance and accuracy, as shown in 公式 3.
VOUTx = VFBx × (1 + R1x / R2x)
R1x = (VOUTx / VFBx – 1) × R2x
R2x < VREF / 5 µA
(1)
(2)
(3)
The input bias current into the error amplifier (feedback pin current, IFBx) and tighter tolerance resistors must be
taken into account for optimizing the output voltage accuracy.
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Application Information (接下页)
表 4 shows the resistor combinations for several common output voltages using commercially-available, 1%
tolerance resistors.
表 4. Recommended Feedback-Resistor Values
FEEDBACK RESISTOR VALUES(1)
TARGETED OUTPUT
VOLTAGE (V)
CALCULATED OUTPUT
VOLTAGE (V)
R1x (kΩ)
Short
1.37
R2x (kΩ)
Open
11.0
10.2
10.2
10.7
9.53
10.7
11.0
10.2
10.7
11.0
10.7
10.7
10.7
10.7
10.7
10.2
9.53
10.7
9.76
0.80
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.35
1.50
1.80
1.90
2.50
2.85
3.00
3.30
3.60
4.50
5.00
5.20
0.800
0.900
0.950
1.000
1.048
1.100
1.147
1.199
1.347
1.496
1.796
1.899
2.490
2.849
2.998
3.282
3.600
4.510
5.002
5.193
1.91
2.55
3.32
3.57
4.64
5.49
6.98
9.31
13.70
14.70
22.60
27.40
29.40
33.20
35.70
44.20
56.20
53.60
(1) R1x is connected from OUTx to FBx; R2x is connected from FBx to GND; see 图 45.
8.1.1.2 Capacitor Recommendations
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output pins. Multilayer ceramic capacitors have become the industry standard for these types of applications
and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors
recommended herein account for an effective capacitance derating of approximately 50%, but at higher VINx and
VOUTx conditions (that is, VINx = 5.5 V to VOUTx = 5.0 V) the derating can be greater than 50% and must be taken
into consideration.
8.1.1.3 Input and Output Capacitor (CINx and COUTx
)
The device is designed and characterized for operation with ceramic capacitors of 10 µF or greater (5 µF or
greater of effective capacitance) at each input and output. Locate the input and output capacitors as near as
practical to the respective input and output pins to minimize the trace inductance from the capacitor to the
device.
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8.1.1.4 Feed-Forward Capacitor (CFFx
)
Although a feed-forward capacitor (CFFx) from the FBx pin to the OUTx pin is not required to achieve stability, a
10-nF external CFFx optimizes the transient, noise, and PSRR performance. A higher capacitance CFFx can be
used; however, the start-up time is longer and the power-good signal can incorrectly indicate that the output
voltage is settled. The maximum recommended value is 100 nF.
To ensure proper PGx functionality, the time constant defined by CNR/SSx must be greater than or equal to the
time constant from CFFx. For a detailed description, see the Pros and Cons of Using a Feed-Forward Capacitor
with a Low Dropout Regulator application report (SBVA042).
8.1.1.5 Noise-Reduction and Soft-Start Capacitor (CNR/SSx
)
Although a noise-reduction and soft-start capacitor (CNR/SSx) from the NR/SSx pin to GND is not required, CNR/SSx
is highly recommended to control the start-up time and reduce the noise-floor of the device. The typical value
used is 10 nF, and the maximum recommended value is 10 µF.
8.1.2 Start-Up
8.1.2.1 Circuit Soft-Start Control (NR/SSx)
Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an
external capacitor (CNR/SSx). This soft-start eliminates power-up initialization problems when powering field-
programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled
voltage ramp of the output also reduces peak inrush current during start-up, thus minimizing start-up transients to
the input power bus.
The output voltage (VOUTx) rises proportionally to VNR/SSx during start-up as the LDO regulates so that the
feedback voltage equals the NR/SSx voltage (VFBx = VNR/SSx). As such, the time required for VNR/SSx to reach its
nominal value determines the rise time of VOUTx (start-up time).
The soft-start ramp time depends on the soft-start charging current (INR/SSx), the soft-start capacitance (CNR/SSx),
and the internal reference (VREF). The approximate soft-start ramp time (tSSx) can be calculated with 公式 4:
tSSx = (VREF × CNR/SSx) / INR/SSx
(4)
The SS_CTRLx pin for each output sets the value of the internal current source, maintaining a fast start-up time
even with a large CNR/SSx capacitor. When the SS_CTRLx pin is connected to GND, the typical value for the
INR/SSx current is 6.2 µA. Connecting the SS_CTRLx pin to INx increases the typical soft-start charging current to
100 µA. The larger charging current for INR/SSx is useful when smaller start-up ramp times are needed or when
using larger noise-reduction capacitors.
Not using a noise-reduction capacitor on the NR/SSx pin and tying the SS_CTRLx pin to VINx results in output
voltage overshoot of approximately 10%. Connecting the SS_CTRLx pin to GND or using a capacitor on the
NR/SSx pin minimizes the overshoot.
Values for the soft-start charging currents are provided in the Electrical Characteristics table.
8.1.2.1.1 In-Rush Current
In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
measure because the input capacitor must be removed, which is not recommended. However, this soft-start
current can be estimated by 公式 5:
C
OUTx ´ dVOUTx(t)
VOUTx(t)
RLOAD
IOUTx(t)
=
+
dt
where:
•
•
•
VOUTx(t) is the instantaneous output voltage of the turn-on ramp
dVOUTx(t) / dt is the slope of the VOUTx ramp
RLOAD is the resistive load impedance
(5)
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8.1.2.2 Undervoltage Lockout (UVLOx) Control
The UVLOx circuit ensures that the device stays disabled before its input or bias supplies reach the minimum
operational voltage range, and ensures that the device properly shuts down when the input supply collapses.
图 46 and 表 5 explain the UVLOx circuit response to various input voltage events, assuming VENx ≥ VIH(ENx)
.
UVLOx Rising Threshold
UVLOx Hysteresis
VINx
C
VOUTx
tAt
tBt
tDt
tEt
tFt
tGt
图 46. Typical UVLOx Operation
表 5. Typical UVLOx Operation Description
REGION
EVENT
VOUTx STATUS
COMMENT
A
B
C
D
Turn-on, VINx ≥ VUVLOx
Regulation
0
1
1
1
Start-up
Regulates to target VOUTx
Brownout, VINx ≥ VUVLOx – VHYS
Regulation
The output can fall out of regulation but the device is still enabled.
Regulates to target VOUTx
The device is disabled and the output falls because of the load and
active discharge circuit. The device is reenabled when the UVLOx
rising threshold is reached by the input voltage and a normal start-
up then follows.
E
Brownout, VINx < VUVLOx – VHYS
0
F
Regulation
1
0
Regulates to target VOUTx
G
Turn-off, VINx < VUVLOx – VHYS
The output falls because of the load and active discharge circuit.
Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During
this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time;
however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of
the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs
are not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall
time of the input supply when operating near the minimum VINx
.
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8.1.2.3 Power-Good (PGx) Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The
power-good circuit asserts whenever FBx, VINx, or ENx are below their thresholds. The PGx operation versus the
output voltage is shown in 图 47, which is described by 表 6.
PGx Rising Threshold
PGx Falling Threshold
VOUTx
E
C
PGx
tAt
tBt
tDt
tFt
tGt
图 47. Typical PGx Operation
表 6. Typical PGx Operation Description
REGION
EVENT
Turn-on
PGx STATUS
FBx VOLTAGE
A
B
C
D
E
F
0
VFBx < VIT(PGx) + VHYS(PGx)
Regulation
Output voltage dip
Regulation
Hi-Z
Hi-Z
Hi-Z
0
VFBx ≥ VIT(PGx)
Output voltage dip
Regulation
VFBx < VIT(PGx)
FBx ≥ VIT(PGx)
VFBx < VIT(PGx)
Hi-Z
0
V
G
Turn-off
The PGx pin is open-drain and connecting a pullup resistor to an external supply enables others devices to
receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply
voltage results in a valid logic signal for the receiving device or devices.
To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and
100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and
the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor
is outside of this range, then the power-good signal may not read a valid digital logic level.
Using a large CFFx with a small CNR/SSx causes the power-good signal to incorrectly indicate that the output
voltage has settled during turn-on. The CFFx time constant must be greater than the soft-start time constant to
ensure proper operation of the PGx during start-up. For a detailed description, see the Pros and Cons of Using a
Feed-Forward Capacitor with a Low Dropout Regulator application report (SBVA042).
The state of PGx is only valid when the device operates above the minimum supply voltage. During short
brownout events and at light loads, power-good does not assert because the output voltage (therefore VFBx) is
sustained by the output capacitance.
8.1.3 AC and Transient Performance
LDO ac performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output
isolation, output current transient response, and output noise. These metrics are primarily a function of open-loop
gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The
output noise is primarily a result of the reference and error amplifier noise.
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8.1.3.1 Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control-loop rejects signals from VINx to VOUTx across the frequency
spectrum (usually 10 Hz to 10 MHz). 公式 6 gives the PSRR calculation as a function of frequency for the input
signal [VINx(f)] and output signal [VOUTx(f)].
≈
∆
«
’
÷
◊
V
INx(f)
PSRR (dB) = 20 Log10
VOUTx(f)
(6)
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for
convenience.
A simplified diagram of PSRR versus frequency is shown in 图 48.
PSRR Boost Circuit Improves PSRR in This Region
Band-Gap
RC Filter
Error Amplifier,
Flat-Gain Region
Error Amplifier,
Gain Roll-Off
Output Capacitor
|ZCOUTx| Decreasing
Output Capacitor
|ZCOUTx| Increasing
Band Gap
Sub 10 Hz
10 Hzœ1 MHz
100 kHz +
Frequency (Hz)
图 48. Power-Supply Rejection Ratio Diagram
An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply
voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for
the TPS7A87.
The TPS7A87 features an innovative circuit to boost the PSRR between 200 kHz and 1 MHz; see 图 4. To
achieve the maximum benefit of this PSRR boost circuit, using a capacitor with a minimum impedance in the
100-kHz to 1-MHz band is recommended.
8.1.3.2 Channel-to-Channel Output Isolation and Crosstalk
Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting
the other output. This attenuation appears in load transient tests on the other output; however, to numerically
quantify the rejection, the output channel isolation is expressed in decibels (dB).
Output isolation performance is a strong function of the PCB layout. See the Layout section on how to best
optimize the isolation performance.
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8.1.3.3 Output Voltage Noise
The TPS7A87 is designed for system applications where minimizing noise on the power-supply rail is critical to
system performance. For example, the TPS7A87 can be used in a phase-locked loop (PLL)-based clocking
circuit can be used for minimum phase noise, or in test and measurement systems where even small power-
supply noise fluctuations reduce system dynamic range.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower
frequencies as a function of 1/f). 图 49 shows a simplified output voltage noise density plot versus frequency.
Charge Pump Spurs
Wide-Band Noise
Integrated Noise
From Band-Gap and Error Amplifier
Measurement Noise Floor
Frequency (Hz)
图 49. Output Voltage Noise Diagram
For further details, see the How to Measure LDO Noise white paper (SLYY076).
8.1.3.4 Optimizing Noise and PSRR
The ultra-low noise floor and PSRR of the device can be improved in several ways, as described in 表 7.
表 7. Effect of Various Parameters on AC Performance(1)(2)
NOISE
PSRR
PARAMETER
LOW-
MID-
HIGH-
LOW-
MID-
HIGH-
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
CNR/SSx
CFFx
+++
No effect
No effect
+++
++
+
No effect
+
++
No effect
+
+++
+
+
+++
+
+++
+
COUTx
No effect
+++
+++
++
VINx – VOUTx
PCB layout
+
+++
+++
++
++
+
+
+++
(1) The number of +'s indicates the improvement in noise or PSRR performance by increasing the parameter value.
(2) Shaded cells indicate the easiest improvement to noise or PSRR performance.
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that
filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the
output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with 公式 7.
The typical value of RNR is 250 kΩ. The effect of the CNR/SSx capacitor increases when VOUTx(Target) increases
because the noise from the reference is gained up when the output voltage increases. For low-noise
applications, a 10-nF to 10-µF CNR/SSx is recommended.
fcutoff = 1 / (2 × π × RNR × CNR/SSx
)
(7)
The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-
forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing
out the loop bandwidth, thus improving mid-band PSRR.
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A larger COUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing
the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the
internal circuits. However, a high power dissipation across the die increases the output noise because of the
increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heatsinking at low frequencies and
isolating VOUTx at high frequencies.
表 8 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions with
an input voltage of 5.4 V, an R1x of 12.1 kΩ, and a load current of 0.5 A. The 5-V output is chosen because this
output is the worst-case condition for output voltage noise.
表 8. Output Noise Voltage at a 5-V Output with a 5.4-V Input
OUTPUT VOLTAGE
CNR/SSx (nF)
CFFx (nF)
COUTx (µF)
SS_CTRLx
NOISE (µVRMS
)
10
10
22
22
VINx
VINx
GND
VINx
10.8
5.6
1000
1000
1000
100
100
100
22
5.6
22 || 1000
5.0
8.1.3.4.1 Charge Pump Noise
The device internal charge pump generates a minimal amount of noise.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by
using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the
load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.
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8.1.3.5 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in 图 50
are broken down in this section and are described in 表 9. Regions A, E, and H are where the output voltage is in
steady-state.
VOUTx
B
F
A
C
D
E
G
H
IOUTx
图 50. Load Transient Waveform
表 9. Load Transient Waveform Description
REGION
DESCRIPTION
COMMENT
A
B
Regulation
Regulation
Output current ramping
Initial voltage dip is a result of the depletion of the output capacitor charge.
Recovery from the dip results from the LDO increasing its sourcing current, and leads
to output voltage regulation.
C
LDO responding to transient
At high load currents the LDO takes some time to heat up. During this time the output
voltage changes slightly.
D
E
F
Reaching thermal equilibrium
Regulation
Regulation
Initial voltage rise results from the LDO sourcing a large current, and leads to the
output capacitor charge to increase.
Output current ramping
Recovery from the rise results from the LDO decreasing its sourcing current in
combination with the load discharging the output capacitor.
G
H
LDO responding to transient
Regulation
Regulation
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The transient response peaks (VOUTx(max) and VOUTx(min)) are improved by using more output capacitance;
however, doing so slows down the recovery time (Wrise and Wfall). 图 51 shows these parameters during a load
transient, with a given pulse duration (PW) and current levels (IOUTx(LO) and IOUTx(HI)).
VOUTx(max)
Wrise
VOUTx
Wfall
VOUTx(min)
IOUTx(HI)
PW
IOUTx
IOUTx(LO)
IOUTx(LO)
trise
tfall
图 51. Simplified Load Transient Waveform
8.1.4 DC Performance
8.1.4.1 Output Voltage Accuracy (VOUTx
)
The device features an output voltage accuracy of 1% maximum that includes the errors introduced by the
internal reference, load regulation, line regulation, and operating temperature as specified by the Electrical
Characteristics table. Output voltage accuracy specifies minimum and maximum output voltage error, relative to
the expected nominal output voltage stated as a percent.
8.1.4.2 Dropout Voltage (VDO
)
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (VDO = VINx – VOUTx) that is required for regulation. When VINx drops below the required VDO for
the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is proportional to the output current because the device is operating as a resistive switch, as shown in 图
52.
VDO
IOUTx
图 52. Dropout Voltage versus Output Current
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect
to VINx on this device because of the internal charge pump. Dropout voltage increases exponentially when the
input voltage nears its maximum operating voltage because the charge pump multiplies the input voltage by a
factor of 4 and then is internally clamped to 8.0 V.
8.1.4.2.1 Behavior when Transitioning from Dropout into Regulation
Some applications can have transients that place the LDO into dropout, such as slower ramps on VINX for start-
up or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.
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A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in
the right range, as shown in 图 53. This condition is easily avoided through either the use of an enable signal, or
by increasing the soft-start time with CSS/NRx
.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VINx = VOUTx(nom) + VDO
Output Voltage
Dropout
VOUTx = VINx - VDO
Output Voltage in
normal regulation.
Time
图 53. Start-Up Into Dropout
8.1.5 Reverse Current Protection
As with most LDOs, this device can be damaged by excessive reverse current.
Reverse current is current that flows through the body diode on the pass element instead of the normal
conducting channel. This current flow, at high enough magnitudes, degrades long-term reliability of the device
resulting from risks of electromigration and excess heat being dissipated across the device. If the current flow
gets high enough, a latch-up condition can be entered.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the
absolute maximum rating of VOUTx > VINx + 0.3 V:
•
•
•
If the device has a large COUTx and the input supply collapses quickly with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If excessive reverse current flow is expected in the application, then external protection must be used to protect
the device. 图 54 shows one approach of protecting the device.
Schottky Diode
Internal Body Diode
INx
OUTx
TI Device
COUTx
CINx
GND
Copyright © 2016, Texas Instruments Incorporated
图 54. Example Circuit for Reverse Current Protection Using a Schottky Diode
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ZHCSF74A –MARCH 2016–REVISED JULY 2016
8.1.6 Power Dissipation (PD)
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must
be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. PD can be approximated using 公式 8:
PD = (VOUTx – VINx) × IOUTx
(8)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to
be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output
voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to 公式 9.
The equation is rearranged for output current in 公式 10.
TJ = TA + θJA × PD
(9)
IOUTx = (TJ – TA) / [θJA × (VINx – VOUTx)]
(10)
Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The θJA recorded in the table is determined by the JEDEC standard, PCB, and copper-spreading area,
and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal
layout, θJA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (θJCbot) plus the
thermal resistance contribution by the PCB copper.
8.1.6.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the table and are used in accordance with 公式 11.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in 公式 8
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(11)
版权 © 2016, Texas Instruments Incorporated
29
TPS7A87
ZHCSF74A –MARCH 2016–REVISED JULY 2016
www.ti.com.cn
8.1.6.2 Recommended Area for Continuous Operation (RACO)
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator can be separated into the
following parts, and is shown in 图 55:
•
•
•
Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output
(VINx – VOUTx) at a given output current level; see the Dropout Voltage (VDO) section for more details.
Limited by rated output current: The rated output current limits the maximum recommended output current
level. Exceeding this rating causes the device to fall out of specification.
Limited by thermals: The shape of the slope is given by 公式 10. The slope is nonlinear because the junction
temperature of the LDO is controlled by the power dissipation across the LDO; therefore, when VINx – VOUTx
increases, the output current must decrease in order to ensure that the rated junction temperature of the
device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and reduces
long-term reliability.
•
Limited by VINx range: The rated input voltage range governs both the minimum and maximum of VINx
VOUTx
–
.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited by Thermals
Limited by
Minimum VINx
Limited by
Maximum VINx
VINx œ VOUTx (V)
图 55. Continuous Operation Slope Region Description
30
版权 © 2016, Texas Instruments Incorporated
TPS7A87
www.ti.com.cn
ZHCSF74A –MARCH 2016–REVISED JULY 2016
图 56 to 图 61 show the recommended area of operation curves for this device on a JEDEC-standard, high-K
board with a θJA = 35.4°C/W, as given in the table.
0.75
0.6
0.45
0.3
0.15
0
0.75
0.6
0.45
0.3
0.15
0
TA = 55èC
TA = 70èC
TA = 85èC
TA = 105èC
RACO at TA = 105èC
TA = 55èC
TA = 70èC
TA = 85èC
TA = 105èC
RACO at TA = 105èC
0
1.5
3
4.5
6
0
1.5
3
4.5
6
VINx - VOUTx (V)
VINx - VOUTx (V)
图 56. Recommended Area for Continuous Operation for
图 57. Recommended Area for Continuous Operation for
VOUTx = 0.8 V
VOUTx = 1.2 V
0.75
0.75
TA = 55èC
TA = 70èC
TA = 85èC
TA = 105èC
RACO at TA = 105èC
TA = 55èC
TA = 70èC
TA = 85èC
TA = 105èC
RACO at TA = 105èC
0.6
0.45
0.3
0.6
0.45
0.3
0.15
0
0.15
0
0
1.5
3
4.5
6
0
1.5
3
4.5
6
VINx - VOUTx (V)
VIN - VOUT (V)
图 58. Recommended Area for Continuous Operation for
图 59. Recommended Area for Continuous Operation for
VOUTx = 1.8 V
VOUTx = 2.5 V
0.75
0.75
TA = 55èC
TA = 70èC
TA = 85èC
TA = 105èC
RACO at TA = 105èC
TA = 55èC
TA = 70èC
TA = 85èC
TA = 105èC
RACO at TA = 105èC
0.6
0.45
0.3
0.6
0.45
0.3
0.15
0
0.15
0
0
1.5
3
4.5
6
0
0.5
1
1.5
2
VINx - VOUTx (V)
VINx - VOUTx (V)
图 60. Recommended Area for Continuous Operation for
图 61. Recommended Area for Continuous Operation for
VOUTx = 3.3 V
VOUTx = 5.0 V
版权 © 2016, Texas Instruments Incorporated
31
TPS7A87
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www.ti.com.cn
8.2 Typical Application
This section discusses the implementation of the TPS7A87 to regulate from a common input voltage to two
output voltages of the same value. This application is common for when two noise-sensitive loads must have the
same supply voltage but have high channel-to-channel isolation. The schematic for this application circuit is
provided in 图 62.
VINx
INx
VOUTx
COUTx
OUTx
FBx
R1x
CINx
ENx
SS_CTRLx
R2x
NR/SSx
VPULL-UP
RPGx
CNR/SSx
TI Device
VPGx
PGx
GND
Copyright © 2016, Texas Instruments Incorporated
图 62. Application Example (Single Channel)
8.2.1 Design Requirements
For the design example shown in 图 62, use the parameters listed in 表 10 as the input parameters.
表 10. Design Parameters
PARAMETER
DESIGN REQUIREMENT
1.8 V, ±3%, provided by the dc-dc converter switching at 750 kHz
85°C
Input voltages (VIN1 and VIN2
)
Maximum ambient operating temperature
Output voltages (VOUT1 and VOUT2
)
1.2 V, ±1%, output voltages are isolated
400 mA (maximum), 10 mA (minimum)
Isolation greater than 50 dB at 100 kHz
< 5 µVRMS, bandwidth = 10 Hz to 100 kHz
> 40 dB
Output currents (IOUT2 and IOUT2
Channel-to-channel isolation
RMS noise
)
PSRR at 750 kHz
Startup time
< 5 ms
8.2.2 Detailed Design Procedure
The output voltages can be set to 1.2 V by selecting the correct values for R1x and R2x; see 公式 1.
Input and output capacitors are selected in accordance with the External Component Selection section. Ceramic
capacitances of 10 µF for both inputs and outputs are selected.
To minimize noise, a feed-forward capacitance (CFFx) of 10 nF is selected.
Channel-to-channel isolation depends greatly on the layout of the design. To minimize crosstalk between the
outputs, keep the output capacitor grounds on separate sides of the design. See the Layout section for an
example of how to layout the TPS7A87 to achieve best PSRR, channel-to-channel isolation, and noise.
32
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TPS7A87
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ZHCSF74A –MARCH 2016–REVISED JULY 2016
8.2.3 Application Curves
100
50
25
0
2
IOUTx = 10 mA
IOUTx = 50 mA
IOUTx = 100 mA
IOUTx = 250 mA
IOUTx = 500 mA
VOUTx = 5.0 V
VOUTx = 3.3 V
VOUTx = 1.2 V
VOUTx = 0.9 V
IOUTx
80
1.5
1
60
40
20
0
-25
-50
0.5
0
10
100
1k
10k
100k
1M
10M
0
200
400
600
800
1000
Frequency (Hz)
Time (ms)
图 63. Power-Supply Rejection Ratio vs Frequency
图 64. Load Transient Response vs Time and VOUTx
9 Power Supply Recommendations
Both inputs of the TPS7A87 are designed to operate from an input voltage range between 1.4 V and 6.5 V. The
input voltage range must provide adequate headroom in order for the device to have a regulated output. This
input supply must be well regulated. If the input supply is noisy or has a high output impedance, additional input
capacitors with low ESR can help improve the output noise performance.
版权 © 2016, Texas Instruments Incorporated
33
TPS7A87
ZHCSF74A –MARCH 2016–REVISED JULY 2016
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit
board and as near as practical to the respective LDO pin connections. Place ground return connections to the
input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly
discouraged and negatively affects system performance.
10.1.1 Board Layout
To maximize the performance of the device, following the layout example illustrated in 图 65 is recommended.
This layout isolates the analog ground (AGND) from the noisy power ground. Components that must be
connected to the quiet analog ground are the noise-reduction capacitors (CNR/SSx) and the lower feedback
resistors (R2x). These components must have a separate connection back to the thermal pad of the device. To
minimize crosstalk between the two outputs, the output capacitor grounds are positioned on opposite sides of the
layout and only connect back to the device at opposite sides of the thermal pad. Connecting the GND pins
directly to the thermal pad and not to any external plane is recommended.
To maximize the output voltage accuracy, the connection from each output voltage back to the top output divider
resistors (R1x) must be made as close as possible to the load. This method of connecting the feedback trace
eliminates the voltage drop from the device output to the load.
To improve thermal performance, a 3 × 3 thermal via array must connect the thermal pad to internal ground
planes. A larger area for the internal ground planes improves the thermal performance and lowers the operating
temperature of the device.
34
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TPS7A87
www.ti.com.cn
ZHCSF74A –MARCH 2016–REVISED JULY 2016
10.2 Layout Example
Thermal Ground
RPG1
AGND
R21
PG1
R11
CNR/SS1
CFF1
VOUT1 SENSE
on Bottom
Layer
20
19
18
17
16
CIN1
COUT1
1
2
3
4
5
15
14
13
12
11
IN1
IN1
OUT1
VIN1
VOUT1
OUT1
GND
GND
IN2
IN2
OUT2
OUT2
VOUT2
VIN2
CIN2
COUT2
6
7
8
9
10
VOUT2 SENSE
on Bottom
Layer
CFF2
CNR/SS2
R12
PG2
R22
AGND
RPG2
Thermal Ground
Circles denote PCB via connections.
图 65. TPS7A87 Example Layout
版权 © 2016, Texas Instruments Incorporated
35
TPS7A87
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www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
评估模块 (EVM) 可与 TPS7A87 配套使用，帮助评估初始电路性能。有关此固定装置的相关摘要信息，请参见表
11。
表 11. 设计套件与评估模块(1)
名称
部件号
TPS7A88 评估模块
《TPS7A88EVM 用户指南》
(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。
在德州仪器 (TI) 网站 (www.ti.com) 上，可通过 TPS7A87 产品文件夹获取 EVM。
11.1.1.2 SPICE 模型
分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从 TPS7A87 产品
文件夹中的仿真模型下获取 TPS7A87 的 SPICE 模型。
11.1.2 器件命名规则
表 12. 订购信息(1)
产品
说明
XX 表示输出电压。01 为可调输出版本。
YYY 为封装标识符。
TPS7A87XXYYYZ
Z 为封装数量。
(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
•
•
•
数据表《TPS37xx 双通道、低功耗、高精度电压检测器》（文献编号：SBVS250）
用户指南《TPS7A88 评估模块》（文献编号：SBVU027）
应用报告《使用前馈电容器和低压降稳压器的优缺点》（文献编号：SBVA042）
白皮书《如何测量 LDO 噪声》（文献编号：SLYY076）
11.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
36
版权 © 2016, Texas Instruments Incorporated
TPS7A87
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ZHCSF74A –MARCH 2016–REVISED JULY 2016
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A8701RTJR
TPS7A8701RTJT
ACTIVE
ACTIVE
QFN
QFN
RTJ
RTJ
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
TPS7A87
TPS7A87
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A8701RTJR
TPS7A8701RTJT
QFN
QFN
RTJ
RTJ
20
20
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2016
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A8701RTJR
TPS7A8701RTJT
QFN
QFN
RTJ
RTJ
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTJ 20
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224842/A
www.ti.com
DATA BOOK
PACKAGE OUTLINE
LEADFRAME EXAMPLE
4222370
DRAFTSMAN:
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
H. DENG
09/12/2016
09/12/2016
09/12/2016
DESIGNER:
CHECKER:
ENGINEER:
APPROVED:
RELEASED:
CODE IDENTITY
NUMBER
H. DENG
01295
SEMICONDUCTOR OPERATIONS
V. PAKU & T. LEQUANG
T. TANG
ePOD, RTJ0020D / WQFN,
20 PIN, 0.5 MM PITCH
09/12/2016
10/06/2016
10/24/2016
E. REY & D. CHIN
WDM
SCALE
SIZE
REV
PAGE
OF
TEMPLATE INFO:
4219125
A
15X
04/07/2016
A
EDGE# 4218519
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RTJ0020D
A
4.1
3.9
B
PIN 1 INDEX AREA
4.1
3.9
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
16X 0.5
(A) TYP
6
10
EXPOSED
THERMAL PAD
5
11
SYMM
ꢀꢁꢂꢃꢁꢄ
4X 2
21
15
1
0.5
0.3
20X
PIN 1 ID
(OPTIONAL)
20
16
SYMM
0.29
0.19
0.1
20X
C A B
C
0.05
4219125 / A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
2.7)
SYMM
20
16
20X (0.6)
1
20X (0.24)
15
(1.1)
TYP
21
SYMM
(3.8)
(0.5)
TYP
ꢅꢃꢁꢀꢆꢇ7<3
VIA
5
11
(R0.05)
TYP
6
10
(3.8)
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219125 / A 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.69)
TYP
20
16
20X (0.6)
1
20X (0.24)
15
(0.69)
TYP
SYMM
(3.8)
(0.5)
TYP
5
11
(R0.05)
TYP
21
6
10
4X ( 1.19)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219125 / A 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
R E V I S I O N S
REV
A
DESCRIPTION
ECR
DATE
ENGINEER / DRAFTSMAN
T. TANG / H. DENG
RELEASE NEW DRAWING
2160736
10/24/2016
SCALE
SIZE
REV
PAGE
4219125
5 OF 5
A
NTS
A
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