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TPS7A85

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

TPS7A85

高电流 (4A)、高效 (1%)、低噪声 (4.4 µV_RMS) LDO 稳压器

1 特性

3 说明

1

•

低压降：4A 电流时为 150mV（典型值）

TPS7A85 是一款低噪声 (4.4 µV_RMS)、低压降 (LDO)

线性稳压器，具备 4A 的拉电流能力，其最高压降仅为

240mV。该器件的输出电压可通过引脚在 0.8V 至

3.95V 的范围内进行编程并可通过外部电阻分压器在

0.8V 至 5.0V 范围内进行调节。

线路、负载和温度精度为 1%（最大值）

输出电压噪声：

–

4.4 µV_RMS（输出为 0.8V）

8.4 µV_RMS（输出为 5.0V）

•

输入电压范围：

TPS7A85 将低噪声 (4.4 µV_RMS)、高电源抑制比

(PSRR) 和高输出电流性能相结合，非常适合为高速通

信、视频、医疗或测试和测量最高可驱动 1A 负载电

流。TPS7A85 的高性能可限制电源生成的相位噪声和

时钟抖动，非常适合为高性能串行器和解串器

(SerDes)、模数转换器 (ADC)、数模转换器 (DAC) 以

及射频 (RF) 组件供电。RF 放大器尤其受益于该器件

的高性能和 5.0V 输出性能。

–

无偏置：1.4V 至 6.5V

有偏置：1.1V 至 6.5V

•

ANY-OUT™运行：

输出电压范围：0.8V 至 3.95V

可调节运行：

输出电压范围：0.8V 至 5.0V

电源纹波抑制：

500kHz 时为 40dB

–

对于需要以低输入电压、低输出 (LILO) 电压运行的数

字负载 [如特定用途集成电路 (ASIC)、现场可编程门阵

列 (FPGA) 以及数字信号处理器 (DSP)]，TPS7A85 优

异的精度特性（负载和温度范围内的精度为

0.75%）、远程感测、出色的瞬态性能以及软启动功能

可确保最优系统性能。

•

出色的负载瞬态响应

可调节软启动浪涌电流控制

开漏电源正常 (PG) 输出

与 47µF 或更大的陶瓷输出电容一起工作时保持稳

定

•

工作温度范围：

–40°C 至 +125°C

TPS7A85 的多种用途使其成为许多高要求应用会考虑

的选择。

20 引脚 3.5mm × 3.5mm 超薄型四方扁平无引线

(VQFN) 封装

器件信息⁽¹⁾

2 应用

器件型号

TPS7A85

封装

封装尺寸（标称值）

超薄四方扁平无引线

封装 (VQFN) (20)

•

数字负载：串行解串器、现场可编程门阵列

3.50mm x 3.50mm

(FPGA) 和数字信号处理器 (DSP)

仪器仪表、医疗和音频

高速模拟电路：

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

•

–

压控振荡器 (VCO)、模数转换器 (ADC)、数模

转换器 (DAC) 以及低压差分信令 (LVDS)

•

成像：互补金属氧化物半导体 (CMOS) 传感器和视

频专用集成电路 (ASIC)

测试和测量

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBVS267

TPS7A85

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

www.ti.com.cn

为 RF 组件供电

为数字负载供电

Bias Supply

BIAS

Input Supply

EN Signal

BIAS

IN

Input Supply

IN

TPS7A85

OUT

TPS7A85

OUT

EN

EN Signal

PG

EN

PG

V_DD

DSP,

ASIC,

FPGA

ADC

DAC

GPIO

ADS54J40

ADS54J66

ACD31JB68

DAC38J82

DAC39J84

DAC5670

C6000

2

TPS7A85

www.ti.com.cn

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

7.4 Device Functional Modes........................................ 20

Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Applications ................................................ 36

Power-Supply Recommendations...................... 38

1

2

3

4

5

6

特性.......................................................................... 1

8

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 3

Pin Configurations and Functions....................... 4

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 8

Detailed Description ............................................ 16

7.1 Overview ................................................................. 16

7.2 Functional Block Diagram ....................................... 17

7.3 Feature Description................................................. 18

10 Layout................................................................... 39

10.1 Layout Guidelines ................................................. 39

10.2 Layout Example .................................................... 39

11 器件和文档支持 ..................................................... 40

11.1 器件支持................................................................ 40

11.2 文档支持................................................................ 40

11.3 社区资源................................................................ 40

11.4 商标....................................................................... 41

11.5 静电放电警告......................................................... 41

11.6 Glossary................................................................ 41

12 机械、封装和可订购信息....................................... 41

7

4 修订历史记录

Changes from Original (January 2016) to Revision A

Page

•

已发布为量产数据................................................................................................................................................................... 1

3

TPS7A85

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

www.ti.com.cn

5 Pin Configurations and Functions

RGR Package

3.5-mm × 3.5-mm, 20-Pin VQFN

Top View

OUT

SNS

FB

1

2

3

4

5

15 IN

14 EN

13 NR/SS

12 BIAS

11 1.6V

Thermal Pad

PG

50mV

Pin Functions

NAME

50mV

NO.

5

I/O

DESCRIPTION

100mV

200mV

400mV

800mV

1.6V

6

ANY-OUT voltage setting pins. Connect these pins to ground, SNS, or leave floating. Connecting these pins to ground

increases the output voltage, whereas connecting these pins to SNS increases the resolution of the ANY-OUT network

but decreases the range of the network; multiple pins can be simultaneously connected to GND or SNS to select the

desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output

Voltage section for additional details.

7

I

9

10

11

BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, V_IN

1.2 V, V_OUT= 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac

performance for V_IN≤ 2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used,

=

BIAS

EN

12

14

3

I

this pin must be left floating or tied to ground.

Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable

functionality is not required, this pin must be connected to IN. If enable functionality is required, V_ENmust always be high

after V_INis established when a BIAS supply is used. See the Sequencing Requirements section for more details.

Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT

(as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor

can disrupt PG (power good) functionality. See the ANY-OUT Programmable Output Voltage and Adjustable Operation

sections for more details.

FB

Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance

connection.

GND

IN

8, 18

—

I

Input supply voltage pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from IN to

ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as

possible. See the Input and Output Capacitor Requirements section for more details.

15-17

Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference

voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended

to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. See the Noise-

Reduction and Soft-Start Capacitor section for more details.

NR/SS

13

—

Regulated output pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from OUT to

ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the

OUT pin to the load. See the Input and Output Capacitor Requirements section for more details.

OUT

PG

1, 19, 20

O

Active-high, power-good pin. An open-drain output indicates when the output voltage reaches 89.3% of the target. The

use of a feed-forward capacitor can disrupt PG (power good) functionality. See the Power-Good (PG) Function section

for more details.

4

2

Output voltage sense input pin. This pin connects the internal R₁resistor to the output. Connect this pin to the load side

of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin floating. See

the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.

SNS

I

Thermal pad

—

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

4

TPS7A85

www.ti.com.cn

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

7.0

UNIT

IN, BIAS, PG, EN

IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs)

SNS, OUT

7.5

V_IN+ 0.3⁽²⁾

Voltage

Current

V

NR/SS, FB

3.6

50mV, 100mV, 200mV, 400mV, 800mV, 1.6V

OUT

V_OUT+ 0.3

Internally limited

A

PG (sink current into device)

5

mA

°C

Operating junction temperature, T_J

Storage temperature, T_stg

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_IN+ 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

MIN

1.1

3.0

0.8

0

NOM

MAX

UNIT

V_IN

Input supply voltage range

Bias supply voltage range⁽¹⁾

Output voltage range⁽²⁾

Enable voltage range

Output current

6.5

5

V

V_BIAS

V_OUT

V_EN

V

V_IN

4

V

I_OUT

C_IN

0

A

Input capacitor

10

47

10

47

µF

kΩ

nF

C_OUT

R_PG

Output capacitor

47 || 10 || 10⁽³⁾

Power-good pullup resistance

NR/SS capacitor

100

C_NR/SS

C_FF

10

Feed-forward capacitor

Top resistor value in feedback network for

adjustable operation

R₁

12.1⁽⁴⁾

kΩ

Bottom resistor value in feedback network for

adjustable operation

R₂

T_J

160⁽⁵⁾

125

kΩ

Operating junction temperature

–40

°C

(1) BIAS supply is required when the V_INsupply is below 1.4 V. Conversely, no BIAS supply is required when the V_INsupply is higher than

or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for V_IN≤ 2.2 V.

(2) This output voltage range does not include device accuracy or accuracy of the feedback resistors.

(3) The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency

range is a typical value for dc-dc supplies.

(4) The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R₁value.

(5) The upper limit for the R₂resistor is to ensure accuracy by making the current through the feedback network much larger than the

leakage current into the feedback node.

5

TPS7A85

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

www.ti.com.cn

6.4 Thermal Information

TPS7A85

RGR (VQFN)

20 PINS

35.4

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

47.6

12.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

12.4

R_θJC(bot)

1.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over operating junction temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.5 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 μF, C_OUT= 47 μF, C_NR/SS

without C_FF, and PG pin pulled up to V_INwith 100 kΩ, unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input supply voltage range⁽³⁾

Bias supply voltage range⁽³⁾

Feedback voltage

1.1

6.5

V

V_BIAS

V_IN= 1.1 V

3.0

6.5

V

V_FB

0.8

V

V_NR/SS

NR/SS pin voltage

V

V_UVLO1(IN)

V_HYS1(IN)

V_UVLO2(IN)

V_HYS2(IN)

V_UVLO(BIAS)

V_HYS(BIAS)

Input supply UVLO with BIAS

V_UVLO1(IN)hysteresis

V_INrising with V_BIAS= 3.0 V

V_BIAS= 3.0 V

1.02

320

1.31

253

2.83

290

1.085

1.39

2.9

V

mV

V

Input supply UVLO without BIAS

V_UVLO2(IN)hysteresis

V_INrising

mV

V

Bias supply UVLO

V_BIASrising, V_IN= 1.1 V

V_UVLO(BIAS)hysteresis

V_IN= 1.1 V

mV

Using the ANY-OUT pins

Using external resistors⁽⁴⁾

0.8 V ≤ V_OUT≤ 5 V, 5 mA ≤ I_OUT≤ 4 A, over V_IN

0.8 – 1.0%

–1.0%

3.95 + 1.0%

5.0 + 1.0%

1.0%

Range

V

Accuracy⁽⁴⁾⁽⁵⁾

Output voltage

V_OUT

Accuracy with

BIAS

V_IN= 1.1 V, 5 mA ≤ I_OUT≤ 4 A,

3.0 V ≤ V_BIAS≤ 6.5 V

–0.75%

0.75%

ΔV_OUT

ΔV_IN

/

Line regulation

Load regulation

I_OUT= 5 mA, 1.4 V ≤ V_IN≤ 6.5 V

0.0035

0.07

mV/V

mV/A

5 mA ≤ I_OUT≤ 4 A, 3.0 V ≤ V_BIAS≤ 6.5 V,

V_IN= 1.1 V

ΔV_OUT

ΔI_OUT

5 mA ≤ I_OUT≤ 4 A

0.08

0.4

5 mA ≤ I_OUT≤ 4 A, V_OUT= 5.0 V

V_IN= 1.4 V, I_OUT= 4 A, V_FB= 0.8 V – 3%

V_IN= 5.5 V, I_OUT= 4 A, V_FB= 0.8 V – 3%

215

325

320

500

V_DO

Dropout voltage

mV

V_IN= 1.1 V, V_BIAS= 5.0 V,

I_OUT= 4 A, V_FB= 0.8 V – 3%

150

5.2

240

5.7

V_OUTforced at 0.9 × V_OUT(nom)

V_IN= V_OUT(nom)+ 0.4 V

,

I_LIM

I_SC

Output current limit

4.7

A

Short-circuit current limit

R_LOAD= 20 mΩ

1.0

2.8

4.8

V_IN= 6.5 V, I_OUT= 5 mA

V_IN= 1.4 V, I_OUT= 4 A

4.0

6.0

25

mA

µA

I_GND

GND pin current

Shutdown, PG = open, V_IN= 6.5 V, V_EN= 0.5 V

(1) V_OUT(nom)is the calculated V_OUTtarget value from the ANY-OUT in a fixed configuration. In an adjustable configuration, V_OUT(nom)is the

expected V_OUTvalue set by the external feedback resistors.

(2) This 50-Ω load is disconnected when the test conditions specify an I_OUTvalue.

(3) BIAS supply is required when the V_INsupply is below 1.4 V. Conversely, no BIAS supply is required when the V_INsupply is higher than

or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for V_IN≤ 2.2 V.

(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(5) The device is not tested under conditions where V_IN> V_OUT+ 1.25 V and I_OUT= 4 A, because the power dissipation is higher than the

maximum rating of the package.

6

TPS7A85

www.ti.com.cn

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

Electrical Characteristics (continued)

Over operating junction temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.5 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 μF, C_OUT= 47 μF, C_NR/SS

without C_FF, and PG pin pulled up to V_INwith 100 kΩ, unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_EN

EN pin current

V_IN= 6.5 V, V_EN= 0 V and 6.5 V

–0.1

0.1

µA

V_IN= 1.1 V, V_BIAS= 6.5 V,

V_OUT(nom)= 0.8 V, I_OUT= 4 A

I_BIAS

BIAS pin current

2.3

3.5

0.5

mA

V

EN pin high-level input voltage

(enable device)

V_IL(EN)

V_IH(EN)

0

1.1

EN pin low-level input voltage

(disable device)

6.5

V

88.3% ×

V_OUT

V_IT(PG)

PG pin threshold

For falling V_OUT

For rising V_OUT

82% × V_OUT

93% × V_OUT

V

V_HYS(PG)

V_OL(PG)

PG pin hysteresis

1% × V_OUT

V_OUT< V_IT(PG), I_PG= –1 mA

(current sunk into pin)

PG pin low-level output voltage

0.4

I_lkg(PG)

I_NR/SS

I_FB

PG pin leakage current

NR/SS pin charging current

FB pin leakage current

V_OUT> V_IT(PG), V_PG= 6.5 V

V_NR/SS= GND, V_IN= 6.5 V

V_IN= 6.5 V

1

9.0

µA

nA

4.0

6.2

–100

100

f = 10 kHz,

V_OUT= 0.8 V,

V_BIAS= 5.0 V

42

39

f = 500 kHz,

V_OUT= 0.8 V,

V_BIAS= 5.0 V

V_IN– V_OUT= 0.5 V,

I_OUT= 4 A, C_NR/SS= 100 nF,

PSRR

Power-supply ripple rejection

dB

C_FF= 10 nF, C_OUT

=

47 μF || 10 μF || 10 μF

f = 10 kHz,

V_OUT= 3.3 V

40

25

f = 500 kHz,

V_OUT= 3.3 V

BW = 10 Hz to 100 kHz, V_IN= 1.2 V,

V_OUT= 0.8 V, V_BIAS= 5.0 V, I_OUT= 4 A,

C_NR/SS= 100 nF, C_FF= 10 nF,

4.4

8.4

C_OUT= 47 μF || 10 μF || 10 μF

V_n

Output noise voltage

μV_RMS

BW = 10 Hz to 100 kHz,

V_OUT= 5.0 V, I_OUT= 4 A, C_NR/SS= 100 nF,

C_FF= 10 nF, C_OUT= 47 μF || 10 μF || 10 μF

Shutdown, temperature increasing

Reset, temperature decreasing

160

140

T_sd

T_J

Thermal shutdown temperature

Operating junction temperature

°C

–40

125

7

TPS7A85

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

www.ti.com.cn

6.6 Typical Characteristics

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

100

80

60

40

20

0

100

80

60

40

20

0

I_OUT= 0.1 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 3.5 A

I_OUT= 4.0 A

V_IN= 1.10 V

V_IN= 1.15 V

V_IN= 1.20 V

V_IN= 1.25 V

V_IN= 1.30 V

V_IN= 1.35 V

V_IN= 1.40 V

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= 1.2 V, V_BIAS= 5 V,

I_OUT= 4 A, V_BIAS= 5 V,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

图 1. PSRR vs Frequency and I_OUT

图 2. PSRR vs Frequency and V_INwith Bias

100

V_BIAS= 0 V

V_BIAS= 3.0 V

V_BIAS= 5.0 V

V_BIAS= 6.5 V

80

60

40

60

40

20

0

V_IN= 1.1 V, V_BIAS= 5 V

V_IN= 1.2 V, V_BIAS= 5 V

V_IN= 1.4 V, V_BIAS= 0 V

20

V_IN= 2.5 V, V_BIAS= 0 V

V_IN= 5.0 V, V_BIAS= 0 V

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= 1.4 V, I_OUT= 1 A,

I_OUT= 1 A,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

图 3. PSRR vs Frequency and V_BIAS

图 4. PSRR vs Frequency and V_IN

100

V_OUT= 0.8 V

V_OUT= 0.9 V

V_IN= 3.60 V

V_IN= 3.65 V

V_OUT= 1.1 V

V_IN= 3.70 V

80

V_OUT= 1.2 V

V_OUT= 1.5 V

V_OUT= 1.8 V

V_IN= 3.75 V

V_IN= 3.80 V

V_IN= 3.85 V

60

V_OUT= 2.5 V

V_IN= 3.90 V

40

20

0

40

20

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= V_OUT+ 0.4 V, V_BIAS= 5.0 V, I_OUT= 4 A,

I_OUT= 4 A, C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

C_FF= 10 nF

图 5. PSRR vs Frequency and V_OUTwith Bias

图 6. PSRR vs Frequency and V_INfor V_OUT= 3.3 V

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

100

80

60

40

20

0

100

80

60

40

20

0

C_OUT= 47 mF||10 mF||10 mF

C_OUT= 47 mF

I_OUT= 0.1 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 4.0 A

C_OUT= 100 mF

C_OUT= 200 mF

C_OUT= 500 mF

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= 5.6 V, C_OUT= 47 μF || 10 μF || 10 μF,

V_IN= V_OUT+ 0.4 V, V_OUT= 1 V, I_OUT= 4 A,

C_NR/SS= 10 nF, C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

图 7. PSRR vs Frequency and C_OUT

图 8. PSRR vs Frequency and I_OUTfor V_OUT= 5.0 V

100

80

60

40

20

0

100

V_IN= 5.35 V

V_IN= 5.4 V

V_IN= 5.45 V

V_IN= 5.5 V

V_IN= 5.55 V

V_IN= 5.60 V

V_IN= 5.65 V

80

60

40

20

V_BIAS= 3.0 V

V_BIAS= 5.0 V

V_BIAS= 6.5 V

0

10

100

1k

10k

100k

1M

10M

100 1k

10k

100k

1M

10M

Frequency (Hz)

I_OUT= 4 A, C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF,

V_IN= V_OUT+ 0.4 V, V_OUT= 1 V, I_OUT= 4 A,

C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

图 9. PSRR vs Frequency and V_INfor V_OUT= 5.0 V

图 10. V_BIASPSRR vs Frequency

15

2

I_OUT= 1.0 A

V_OUT= 0.8 V, 4.5 mV_RMS

1

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 4.0 A

V_OUT= 1.5 V, 5.4 mV_RMS

13.5

12

10.5

9

V_OUT= 3.3 V, 8.5 mV_RMS

V_OUT= 5.0 V, 12.4 mV_RMS

0.5

0.2

0.1

0.05

0.02

0.01

7.5

6

0.005

4.5

3

0.002

0.001

0.6

1.2

1.8

2.4

3

3.6

4.2

4.8

5.4

10

100

1k

10k

100k

1M

Output Voltage (V)

Frequency (Hz)

V_IN= V_OUT+ 0.4 V and V_BIAS= 5 V for V_OUT≤ 2.2 V,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

V_IN= V_OUT+ 0.4 V and V_BIAS= 5 V for V_OUT≤ 2.2 V, I_OUT= 4 A,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

图 12. Output Noise vs Frequency and V_OUT

图 11. Output Voltage Noise vs Output Voltage

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

2

V_IN= 1.4 V, V_BIAS= 5.0 V, 4.5 mV_RMS

V_IN= 1.4 V, 6.0 mV_RMS

C_NR/SS= 0 nF, 6.2 mV_RMS

C_NR/SS= 1 nF, 4.9 mV_RMS

C_NR/SS= 10 nF, 4.5 mV_RMS

C_NR/SS= 100 nF, 4.4 mV_RMS

1

V_IN= 1.5 V, 4.5 mV_RMS

0.5

V_IN= 1.8 V, 4.5 mV_RMS

V_IN= 2.5 V, 4.6 mV_RMS

0.2

0.1

0.2

0.1

V_IN= 5.0 V, 5.15 mV_RMS

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

Frequency (Hz)

I_OUT= 1 A, C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF,

V_IN= V_OUT+ 0.4 V, V_BIAS= 5 V, I_OUT= 4 A,

C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF, C_FF= 10 nF

图 13. Output Noise vs Frequency and V_IN

图 14. Output Noise vs Frequency and C_NR/SS

2

C_FF= 0 nF, 6.2 mV_RMS

C_NR/SS= 10 nF, 12.3 mV_RMS

1

C_FF= 0.1 nF, 5.8 mV_RMS

C_NR/SS= 100 nF, 8.4 mV_RMS

C_FF= 1 nF, 4.9 mV_RMS

C_FF= 10 nF, 4.5mV_RMS

C_FF= 100 nF, 4.4 mV_RMS

C_FF= C_NR/SS= 100 nF, 6.6 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

Frequency (Hz)

V_IN= V_OUT+ 0.4 V, V_BIAS= 5 V, I_OUT= 4 A,

V_IN= 5.6 V, I_OUT= 4 A, C_OUT= 47 μF || 10 μF || 10 μF,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF

C_FF= 10 nF

图 15. Output Noise vs Frequency and C_FF

图 16. Output Noise at 5.0-V Output vs C_NR/SSand C_FF

1.2

10

7.5

5

50

25

0

Output Current

V_OUT= 0.9 V

V_OUT= 1.2 V

V_OUT= 1.8 V

1

0.8

0.6

0.4

0.2

0

V_EN

2.5

0

-25

-50

V_OUT, C_NR/SS= 0 nF

V_OUT, C_NR/SS= 10 nF

V_OUT, C_NR/SS= 47 nF

V_OUT, C_NR/SS= 100 nF

-0.2

0

5

10

15

20

25

30

35

40

45

50

0

0.5

1

1.5

2

Time (ms)

V_IN= 1.2 V, V_OUT= 0.9 V, V_BIAS= 5.0 V, I_OUT= 4 A,

V_IN= V_OUT+ 0.3 V, V_BIAS= 5 V, I_{OUT, DC}= 100 mA, slew rate =

1 A/μs, C_NR/SS= C_FF= 10 nF, C_OUT= 47 μF || 10 μF || 10 μF

C_OUT= 47 μF || 10 μF || 10 μF, C_FF= 10 nF

图 18. Load Transient Waveform vs Time and

图 17. Start-Up Waveform vs Time and C_NR/SS

V_OUTwith Bias

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

50

25

0

10

7.5

5

50

25

0

Slew Rate = 2 A/ms

Slew Rate = 1 A/ms

Slew Rate = 0.5 A/ms

Output Current

V_OUT= 3.3 V

V_OUT= 5.0 V

2.5

0

-25

-50

-25

-50

0

0.4

0.8

1.2

1.6

2

0

0.4

0.8

1.2

1.6

2

Time (ms)

I_{OUT, DC}= 100 mA, C_OUT= 47 μF || 10 μF || 10 μF,

C_NR/SS= C_FF= 10 nF, slew rate = 1 A/μs

V_OUT= 5 V, I_{OUT, DC}= 100 mA, I_OUT= 100 mA to 4 A,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= C_FF= 10 nF

图 19. Load Transient Waveform vs Time and

图 20. Load Transient Waveform vs Time and

V_OUTwithout Bias

Slew Rate

50

25

0

50

I_OUT= 100 mA to 4 A

I_OUT= 500 mA to 4 A

I_OUT= 1 A to 4 A

25

0

-25

-50

C_OUT= 100 mF

C_OUT= 200 mF

C_OUT= 500 mF

C_OUT= 500 mF || 1 mF Oscon

-50

0

0.4

0.8

1.2

1.6

2

0

0.4

0.8

1.2

1.6

2

Time (ms)

V_IN= 1.2 V, V_BIAS= 5.0 V, I_OUT= 100 mA to 4 A,

V_IN= 1.2 V, V_BIAS= 5.0 V, C_OUT= 47 μF || 10 μF || 10 μF,

C_NR/SS= C_FF= 10 nF, slew rate = 1 A/μs

图 21. Load Transient Waveform vs Time and C_OUT

图 22. Load Transient Waveform vs Time and DC Load

(V_OUT= 0.9 V)

450

-40°C

0°C

450

-40°C

0°C

400

350

300

250

200

150

400

350

300

250

200

150

25°C

85°C

125°C

25°C

85°C

125°C

1

2

3

4

5

6

1

2

3

4

5

6

Input Voltage (V)

I_OUT= 4 A, V_BIAS= 0 V

I_OUT= 4 A, V_BIAS= 6.5 V

图 23. Dropout Voltage vs Input Voltage without Bias

图 24. Dropout Voltage vs Input Voltage with Bias

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

300

250

200

150

100

50

0.2

0.175

0.15

0.125

0.1

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

0.075

0.05

0.025

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Output Current (A)

V_IN= 1.4 V, V_BIAS= 0 V

V_IN= 1.1 V, V_BIAS= 3 V

图 26. Dropout Voltage vs Output Current with Bias

图 25. Dropout Voltage vs Output Current without Bias

350

0.2

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

300

0.15

0.1

250

200

150

100

50

0.05

0

-0.05

-0.1

0

0.5

1

1.5

2

2.5

3

3.5

4

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Output Current (A)

Output Voltage (V)

V_IN= 5.5 V

I_OUT= 100 mA to 4 A

图 27. Dropout Voltage vs Output Current (High V_IN

)

图 28. Load Regulation vs Output Voltage

0.15

0.025

0

-40°C

0°C

25°C

85°C

125°C

0.1

0.05

0

-0.025

-0.05

-0.075

-0.1

-40°C

0°C

25°C

85°C

125°C

-0.05

-0.1

0

0.8

1.6

2.4

3.2

4

0

0.8

1.6

2.4

3.2

4

Output Current (A)

图 29. Load Regulation (0.8-V Output)

图 30. Load Regulation (3.3-V Output)

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

0.025

0

-0.025

-0.05

0

-0.025

-0.05

-0.075

-0.1

-0.075

-0.1

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

-0.125

0

0.8

1.6

2.4

3.2

4

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

Output Current (A)

Input Voltage (V)

I_OUT= 5 mA

图 31. Load Regulation (5-V Output)

图 32. Line Regulation without Bias

25

0

-20

-40

-60

-25

-50

-75

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

-100

3

3.5

4

4.5

5

5.5

6

6.5

5.25

5.5

5.75

6

6.25

6.5

Bias Voltage (V)

Input Voltage (V)

V_IN= 1.1 V, I_OUT= 5 mA

图 33. Line Regulation vs Bias Voltage

I_OUT= 5 mA

图 34. Line Regulation (5-V Output)

3.3

3

2.4

2

1.6

1.2

0.8

2.7

2.4

2.1

1.8

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

1.5

1

2

3

4

5

6

7

3

3.5

4

4.5

5

5.5

6

6.5

Input Voltage (V)

Bias Voltage (V)

I_OUT= 5 mA

V_IN= 1.1 V, I_OUT= 5 mA

图 36. Bias Pin Current vs Bias Voltage

图 35. Ground Pin Current vs Input Voltage

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

5

4

3

2

1

0

6

5

4

3

2

1

0

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

3

3.5

4

4.5

5

5.5

6

6.5

Input Voltage (V)

Bias Voltage (V)

V_IN= 1.1 V

图 37. Shutdown Current vs Input Voltage

图 38. Shutdown Current vs Bias Voltage

7.5

7

1.4

1.2

1

6.5

6

0.8

0.6

0.4

0.2

5.5

5

-40°C

0°C

25°C

85°C

125°C

V_UVLO2(IN), Rising

V_UVLO2(IN), Falling

V_UVLO1(IN), Rising

V_UVLO1(IN), Falling

4.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

-40

-20

0

20

40

60

80

100 120 140

Input Voltage (V)

Temperature (°C)

图 39. NR/SS Charging Current vs Input Voltage

图 40. V_INUVLO vs Temperature

0.85

0.8

3

2.9

2.8

2.7

2.6

2.5

V_UVLO(BIAS), Rising

V_UVLO(BIAS), Falling

0.75

0.7

0.65

0.6

V_IH(EN), V_IN= 1.4 V

V_IH(EN), V_IN= 6.5 V

V_IL(EN), V_IN= 1.4 V

V_IL(EN), V_IN= 6.5 V

0.55

-60

-30

0

30

60

90

120

150

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

V_IN= 1.1 V

图 41. V_BIASUVLO vs Temperature

图 42. Enable Threshold vs Temperature

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

0.75

0.6

0.45

0.3

0.15

0

0.4

0.32

0.24

0.16

0.08

0

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

0

0.5

1

1.5

2

2.5

3

0

0.5

1

1.5

2

2.5

3

PG Current Sink (mA)

V_IN= 6.5 V

图 43. PG Voltage vs PG Current Sink

图 44. PG Voltage vs PG Current Sink

90.25

V_IT(PG)Rising, V_IN= 1.4 V

V_IT(PG)Rising, V_IN= 6.5 V

V_IT(PG)Falling, V_IN= 1.4V

V_IT(PG)Falling, V_IN= 6.5 V

90

89.75

89.5

89.25

89

88.75

88.5

88.25

88

87.75

-50

-25

0

25

50

75

100

125

Temperature (°C)

图 45. PG Threshold vs Temperature

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7 Detailed Description

7.1 Overview

The TPS7A85 is a high-current (4 A), low-noise (4.4 µV_RMS), high accuracy (1%) low-dropout linear voltage

regulator (LDO). These features make the device a robust solution to solve many challenging problems in

generating a clean, accurate power supply.

The TPS7A85 has several features that make the device useful in a variety of applications. As detailed in the

Functional Block Diagram section, these features include:

•

Low-noise, high-PSRR output

ANY-OUT resistor network

Optional bias rail

Power-good (PG) output

Programmable soft-start

Foldback current limit

Enable circuitry

Active discharge

Thermal protection

Overall, these features make the TPS7A85 the component of choice because of its versatility and ability to

generate a supply for most applications.

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7.2 Functional Block Diagram

PSRR

Boost

Current

Limit

IN

OUT

Charge

Pump

BIAS

Active

R_NR/SS= 250 kW

Discharge

0.8-V

V_REF

+

Error

Amp

œ

I_NR/SS

SNS

NR/SS

200 pF

R₁= 2×R = 12.1 kW

FB

1×R = 6.05 kW

1.6V

2×R = 12.1 kW

Internal

800mV

Controller

UVLO

4×R = 24.2 kW

400mV

Circuits

8×R = 48.4 kW

200mV

16×R = 96.8 kW

100mV

32×R = 193.6 kW

50mV

ANY-OUT Network

Thermal

Shutdown

PG

œ

0.893 x V_REF

+

EN

GND

NOTE: For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual

resistance can vary significantly from the values listed.

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7.3 Feature Description

7.3.1 Low-Noise, High-PSRR Output

The TPS7A85 includes a low-noise reference and error amplifier ensuring minimal noise during operation. The

NR/SS capacitor (C_NR/SS) and feed-forward capacitor (C_FF) are the most effective way to reduce device noise.

C_NR/SSfilters the noise from the reference and C_FFfilters the noise from the error amplifier. The noise contribution

from the charge pump is minimal. The overall noise of the system at low output voltages can be reduced by

using a bias rail because this rail provides more headroom for internal circuitry.

The high power-supply rejection ratio (PSRR) of the TPS7A85 ensures minimal coupling of input supply noise to

the output. The PSRR performance primarily results from a high-bandwidth, high-gain error amplifier and an

innovative circuit to boost the PSRR between 200 kHz and 1 MHz.

The combination of a low noise floor and high PSRR ensure that the device provides a clean supply to the

application; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR

performance.

7.3.2 Integrated Resistance Network (ANY-OUT)

An internal feedback resistance network is provided, allowing the TPS7A85 output voltage to be programmed

easily between 0.8 V to 3.95 V with a 50-mV step by tying the ANY-OUT pins to ground. Tying the ANY-OUT

pins to SNS increases the resolution but limits the range of the output voltage because the effective value of R₁

is decreased. The ANY-OUT network provides excellent accuracy across output voltage and temperature; see

the Application and Implementation section for more details.

7.3.3 Bias Rail

The device features a bias rail to enable low-input voltage, low-output (LILO) voltage operation by providing

power to the internal circuitry of the device. The bias rail is required for operation with V_IN< 1.4 V.

An internal power MUX supplies the greater of either the input voltage or the bias voltage to an internal charge

pump to power the internal circuitry. Unlike other LDOs that have a bias supply, the TPS7A85 does not have a

minimum bias voltage with respect to the input supply because an internal charge pump is used instead.

The internal charge pump multiples the output voltage of the power MUX by a factor of 4 to a maximum of

typically 8 V; therefore, using a bias supply with V_IN≤ 2.2 V is recommended for optimal dc and ac performance.

Sequencing requirements exist for when the bias rail is used; see the Sequencing Requirements section for more

details.

7.3.4 Power-Good (PG) Function

The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.

When the feedback pin voltage falls below the PG threshold voltage (V_IT(PG)+ V_HYS(PG), typically 89.3%), the PG

pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the

V_IT(PG)threshold by an amount greater than V_HYS(PG)(typically 91.3%), the PG pin becomes high impedance. By

connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic

signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic

signal for the receiving device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using

an external voltage detector device such as the TPS3702 is also recommended in applications where more

accurate voltage monitoring or overvoltage monitoring is required.

The use of a feed-forward capacitor (C_FF) can cause glitches on start-up, and the power-good circuit may not

function normally below the minimum input supply range. For more details on the use of the power-good circuitry,

see the Power-Good (PG) Operation section.

7.3.5 Programmable Soft-Start

Soft-start refers to the ramp-up time of the output voltage during LDO turn-on after EN and UVLO exceed the

respective threshold voltages. The noise-reduction capacitor (C_NR/SS) serves a dual purpose of both governing

output noise reduction and programming the soft-start ramp time during turn-on. The start-up ramp is monotonic.

The majority of the ramp is linear; however, there is an offset voltage in the error amplifier that can cause a small

initial jump in output voltage; see the Application and Implementation section on implementing a soft-start.

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Feature Description (接下页)

7.3.6 Internal Current Limit (I_LIM

)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events.

During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased

load impedance. Thermal shutdown can activate during a current limit event because of the high power

dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the

inductances to the input and load. Continuous operation in current limit is not recommended.

The foldback current limit crosses 0 A when V_OUT< 0 V and prevents the device from turning on into a

negatively-biased output. See the Negatively-Biased Output section for additional ways to ensure start-up when

the TPS7A85 output is pulled below ground.

If V_OUT> V_IN+ 0.3 V, then reverse current can flow from the output to the input. The reverse current can cause

damage to the device; therefore, limit this reverse current to 10% of the rated output current of the device. See

the Reverse Current Protection section for more details.

7.3.7 Enable

The enable pin for the TPS7A85 is active high. The output of the TPS7A85 is turned on when the enable pin

voltage is greater than its rising voltage threshold (1.1 V, max), and the output of the TPS7A85 is turned off when

the enable pin voltage is less than its falling voltage threshold (0.5 V, min). A voltage less than 0.5 V on the

enable pin disables all internal circuits. At the next turn-on this voltage ensures a normal start-up waveform with

in-rush control, provided there is enough time to discharge the output capacitance.

When the enable functionality is not desired, EN must be tied to V_IN. However, when the enable functionality is

desired, the enable voltage must come after V_INis above V_UVLO1(IN)when a BIAS rail is used; see the Application

and Implementation section for further details.

7.3.8 Active Discharge Circuit

The TPS7A85 has an internal pulldown MOSFET that connects a resistance of several hundred ohms to ground

when the device is disabled to actively discharge the output voltage when the device is disabled.

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current

flow can cause damage to the device. Limit reverse current to no more than 10% of the device rated current for a

short period of time; see the Reverse Current Protection section for more details.

7.3.9 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit monitors the input and bias voltage (V_INand V_BIAS, respectively) to

prevent the device from turning on before V_INand V_BIASrise above the lockout voltage. The UVLO circuit also

disables the output of the device when V_INor V_BIASfall below the lockout voltage.

The UVLO circuit responds quickly to glitches on V_INor V_BIASand attempts to disable the output of the device if

either of these rails collapse. As a result of the fast response time of the input supply UVLO circuit, fast slew rate

and short duration line transients well below the input supply UVLO falling threshold can cause momentary

glitches during the edges of the transient; see the Application and Implementation section for more details.

7.3.10 Thermal Protection

The TPS7A85 contains a thermal shutdown protection circuit to disable the device when thermal junction

temperature (T_J) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the

LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the

semiconductor die is fairly short, and thus the device may cycle on and off when thermal shutdown is reached

until the power dissipation is reduced.

For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the

device to exceed its operational specifications. Although the internal protection circuitry of the TPS7A85 is

designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat

sinking. Continuously running the TPS7A85 into thermal shutdown or above a junction temperature of 125°C

reduces long-term reliability.

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7.4 Device Functional Modes

7.4.1 Operation with 1.1 V ≤ V_IN< 1.4 V

The TPS7A85 requires a bias voltage on the BIAS pin greater than or equal to 3.0 V if the high-current input

supply voltage is between 1.1 V to 1.4 V. The bias voltage pin consumes 2.3 mA, typically.

7.4.2 Operation with 1.4 V ≤ V_IN≤ 6.5 V

If the input voltage is equal to or exceeds 1.4 V, no BIAS voltage is required. The TPS7A85 is powered from

either the input supply or the BIAS supply, whichever is greater. For higher performance, a BIAS rail is

recommended for V_IN≤ 2.2 V.

7.4.3 Shutdown

Shutting down the device reduces the ground current of the device to a maximum of 25 µA.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7A85 is a linear voltage regulator with an input voltage range of 1.1 V to 6.5 V and an output voltage

range of 0.8 V to 5.0 V with a 1% accuracy and a 4-A maximum output current. The TPS7A85 has an integrated

charge pump for ease of use and an external bias rail to allow for the lowest dropout across the entire output

voltage range.

8.1.1 Recommended Capacitor Types

The TPS7A85 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry

standard for these types of applications and are recommended, but must be used with good judgment. Ceramic

capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability

across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in

capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors

recommended herein account for a effective capacitance derating of approximately 50%, but at high V_INand

V_OUTconditions (that is, V_IN= 5.5 V to V_OUT= 5.0 V) the derating can be greater than 50% and must be taken

into consideration.

8.1.2 Input and Output Capacitor Requirements (C_INand C_OUT

)

The TPS7A85 is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or

greater of effective capacitance) at the output and 10 µF or greater (5 μF or greater of effective capacitance) at

the input. Using at least a 47-µF capacitor is highly recommended at the input to minimize input impedance.

Place the input and output capacitors as near as practical to the respective input and output pins to minimize

trace parasitics. If the trace inductance from the input supply to the TPS7A85 is high, a fast current transient can

cause V_INto ring above the absolute maximum voltage rating and damage the device. This situation can be

mitigated by additional input capacitors to dampen the ringing and to keep the ringing below the device absolute

maximum ratings.

A combination of multiple output capacitors boosts the high-frequency PSRR, as illustrated in several of the

PSRR curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized,

10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes

PSRR for the frequency range of 400 kHz to 700 kHz (which is a typical range for dc-dc supply switching

frequency). This 47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output

voltage configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors

have a voltage derating of approximately 60% to 75% at 5.0 V, so the addition of the two 10-µF capacitors

ensures that the capacitance is at or above 22 µF.

8.1.3 Noise-Reduction and Soft-Start Capacitor (C_NR/SS

)

The TPS7A85 features a programmable, monotonic, voltage-controlled soft-start that is set with an external

capacitor (C_NR/SS).The use of an external C_NR/SSis highly recommended, especially to minimize in-rush current

into the output capacitors. This soft-start eliminates power-up initialization problems when powering field-

programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled

voltage ramp of the output also reduces peak in-rush current during start-up, minimizing start-up transients to the

input power bus.

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Application Information (接下页)

To achieve a monotonic start-up, the TPS7A85 error amplifier tracks the voltage ramp of the external soft-start

capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start

charging current (I_NR/SS), the soft-start capacitance (C_NR/SS), and the internal reference (V_NR/SS). Soft-start ramp

time can be calculated with 公式 1:

t_SS= (V_NR/SS× C_NR/SS) / I_NR/SS

(1)

Note that I_NR/SSis provided in the Electrical Characteristics table and has a typical value of 6.2 µA.

The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that

filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the

device noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with 公式 2. The

typical value of R_NRis 250 kΩ. Increasing the C_NR/SScapacitor has a greater affect because the output voltage

increases when the noise from the reference is gained up even more at higher output voltages. For low-noise

applications, a 10-nF to 1-µF C_NR/SSis recommended.

f_cutoff= 1/ (2 × π × R_NR× C_NR/SS

)

(2)

8.1.4 Feed-Forward Capacitor (C_FF)

Although a feed-forward capacitor (C_FF) from the FB pin to the OUT pin is not required to achieve stability, a

10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher

capacitance C_FFcan be used; however, the start-up time is longer and the power-good signal can incorrectly

indicate that the output voltage is settled. To ensure proper PG functionality the time constant defined by C_NR/SS

must be greater than or equal to the time constant from the C_FF. For a detailed description, see application report

Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042.

8.1.5 Soft-Start and In-Rush Current

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and both UVLOs

exceed their threshold voltages. The noise-reduction capacitor serves a dual purpose of both governing output

noise reduction and programming the soft-start ramp during turn-on.

The soft-start ramp is not fully linear as the error amplifier has a several millivolt offset voltage. The output

voltage starts to ramp only after the voltage created by the soft-start circuit increases above this offset voltage, at

which point the output rises quickly to the voltage on the NR/SS pin. After this initial jump, the voltage rises at the

ramp rate determined by the soft-start function. This jump typically does not cause a problem in applications

because the quick rise in the output voltage has a very small amplitude.

In-rush current is defined as the current into the LDO at the IN pin during start-up. In-rush current then consists

primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to

measure because the input capacitor must be removed, which is not recommended. However, this soft-start

current can be estimated by 公式 3:

C

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

=

+

dt

where:

•

V_OUT(t) is the instantaneous output voltage of the turn-on ramp

dV_OUT(t) / dt is the slope of the V_OUTramp

R_LOADis the resistive load impedance

(3)

8.1.6 Optimizing Noise and PSRR

The ultra-low noise floor and PSRR of the device can be improved by careful selection of:

•

C_NR/SSfor the low-frequency range

C_FFfor the mid-band frequency range

C_OUTfor the high-frequency range

V_IN– V_OUTfor all frequencies, and

V_BIASat lower input voltages

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Application Information (接下页)

The noise-reduction capacitor filters out low-frequency noise from the reference and the feed-forward capacitor

reduces output voltage noise by filtering out the mid-band frequency noise. However, a large feed-forward

capacitor can create some new issues that are discussed in application report Pros and Cons of Using a Feed-

Forward Capacitor with a Low Dropout Regulator, SBVA042.

Note that a large output capacitor reduces high-frequency output voltage noise. Additionally, a bias rail or higher

input voltage improves the noise because greater headroom is provided for the internal circuits. A high power

dissipation across the die increases the output noise because of the increase in junction temperature.

A larger noise-reduction capacitor improves low-frequency PSRR by filtering any noise coupling from the input

into the reference. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the

loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR. Larger output capacitors

and various output capacitors can be used to improve high-frequency PSRR; see 图 7 for more details.

A higher input voltage improves PSRR by providing the device more headroom to respond to noise on the input;

see 图 2. A bias rail also improves the PSRR at lower input voltages because greater headroom is provided for

the internal circuits. 表 1 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5.0-V output for a

variety of conditions with an input voltage of 5.6 V, an R₁of 12.1 kΩ, and a load current of 4 A. The 5.0-V output

is chosen because this output is the worst-case condition for output voltage noise. Note that the input voltage is

5.6 V, not 5.5 V as provided in the Electrical Characteristics table. The higher input voltage limits the maximum

ambient temperature to below 40°C on a standard-JEDEC high-K board; see the Power Dissipation (P_D) section

for more information.

表 1. Output Noise Voltage at a 5.0-V Output with a 5.6-V Input

OUTPUT VOLTAGE NOISE

C_NR/SS(nF)

C_FF(nF)

C_OUT(µF)

(µV_RMS

12.3

8.4

)

10

47 || 10 || 10

1000

100

6.6

6.4

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8.1.6.1 Charge Pump Noise

The device internal charge pump generates a minimal amount of noise, as shown in 图 46.

Using a bias rail minimizes the internal charge pump noise when the internal voltage is clamped, thereby

reducing the overall output noise floor.

The high-frequency components of the output voltage noise density curve are filtered out in most applications by

using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the

load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.

0.5

V_IN= 1.5 V, 4.5 mV_RMS

V_IN= 1.4 V, V_BIAS= 5.0 V, 4.5 mV_RMS

0.3

0.2

0.1

0.07

0.05

0.03

0.02

0.01

0.007

0.005

0.003

0.002

0.001

1000000

2000000

3000000

4000000

5000000

6000000

7000000

8000000

9000000

1E+7

Frequency (Hz)

图 46. Charge Pump Noise

8.1.7 ANY-OUT Programmable Output Voltage

The TPS7A85 can either use external resistors or the internally-matched ANY-OUT feedback resistor network to

set the output voltage. The ANY-OUT resistors are accessible via pins 2 and 5 to 11 and are used to program

the regulated output voltage. Each pin can be connected to ground (active) or left open (floating), or connected to

SNS. ANY-OUT programming is set by 公式 4 as the sum of the internal reference voltage (V_NR/SS= 0.8 V) plus

the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin

6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). 表 2 summarizes these voltage values

associated with each active pin setting for reference. By leaving all program pins open or floating, the output is

thereby programmed to the minimum possible output voltage equal to V_FB

.

V_OUT= V_NR/SS+ (Σ ANY-OUT Pins to Ground)

(4)

表 2. ANY-OUT Programmable Output Voltage

ANY-OUT PROGRAM PINS (Active Low)

ADDITIVE OUTPUT VOLTAGE LEVEL

Pin 5 (50mV)

Pin 6 (100mV)

Pin 7 (200mV)

Pin 9 (400mV)

Pin 10 (800mV)

Pin 11 (1.6V)

50 mV

100 mV

200 mV

400 mV

800 mV

1.6 V

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表 3 provides a full list of target output voltages and corresponding pin settings when the ANY-OUT pins are only

tied to ground or left floating. The voltage setting pins have a binary weight; therefore, the output voltage can be

programmed to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground. There are

several alternative ways to set the output voltage. The program pins can be driven by using external general-

purpose input/output pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired by the

given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable operation, the

output voltage is set according to 公式 5 except that R₁and R₂are internally integrated and matched for higher

accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback network

by lowering the value of R₁; see the Increasing ANY-OUT Resolution for LILO Conditions section for additional

information.

V_OUT= V_NR/SS× (1 + R₁/ R₂)

(5)

注

For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the

Adjustable Operation section).

表 3. User-Configurable Output Voltage Settings

V_OUT(NOM)

(V)

V_OUT(NOM)

50mV

100mV 200mV 400mV 800mV

1.6V

50mV 100mV 200mV 400mV 800mV

1.6V

(V)

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

3.65

3.70

3.75

3.80

3.85

3.90

3.95

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

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8.1.8 ANY-OUT Operation

Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ) the

output voltage is set by grounding the appropriate control pins, as shown in 图 47. When grounded, all control

pins add a specific voltage on top of the internal reference voltage (V_NR/SS= 0.8 V). The output voltage can be

calculated by 公式 6 and 公式 7. 图 47 and 图 48 show a 3.3-V and a 0.9-V output voltage, respectively, that

provides an example of the circuit usage with and without bias voltage.

BIAS

EN

IN

PG

OUT

SNS

FB

R_PG

Input

Supply

To Load

C_OUT

C_IN

Device

C_FF

NR/SS

C_NR/SS

GND 50mV 100mV 200mV 400mV 800mV 1.6V

图 47. ANY-OUT Configuration Circuit

(3.3-V Output, No External Bias)

V_OUT(nom)= V_NR/SS+ 1.6 V + 0.8 V + 0.1 V = 0.8 V + 1.6 V + 0.8 V + 0.1 V = 3.3 V

(6)

C_BIAS

Bias

Supply

BIAS

EN

IN

PG

OUT

SNS

FB

R_PG

Input

Supply

To Load

C_OUT

C_IN

Device

C_FF

NR/SS

C_NR/SS

GND 50mV 100mV 200mV 400mV 800mV 1.6V

图 48. ANY-OUT Configuration Circuit

(0.9-V Output with Bias)

V_OUT(nom)= V_NR/SS+ 0.1 V = 0.8 V + 0.1 V = 0.9 V

(7)

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8.1.9 Increasing ANY-OUT Resolution for LILO Conditions

As with the adjustable operation, the output voltage is set according to 公式 5, except that R₁and R₂are

internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the

resolution of the internal feedback network by lowering the value of R₁. One of the more useful pin combinations

is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range. The new

ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. The new additive output voltage levels are listed in

表 4.

表 4. ANY-OUT Programmable Output Voltage with 800mV Tied to SNS

ANY-OUT PROGRAM PINS (Active Low)

Pin 5 (50mV)

ADDITIVE OUTPUT VOLTAGE LEVEL

25 mV

50 mV

Pin 6 (100mV)

Pin 7 (200mV)

100 mV

200 mV

800 mV

Pin 9 (400mV)

Pin 11 (1.6V)

8.1.10 Current Sharing

Current sharing is possible through the use of external operational amplifiers. For more details, see the reference

design 6A Current-Sharing Dual LDO, TIDU421.

8.1.11 Adjustable Operation

The TPS7A85 can either be used with the internal ANY-OUT network or by using external resistors. Using the

ANY-OUT network allows the TPS7A85 to be programmed from 0.8 V to 3.95 V. To extend this output voltage

range to 5.0 V, external resistors must be used. This configuration is referred to as the adjustable configuration

of the TPS7A85 throughout this document. Regardless whether the internal resistor network or external resistors

are used, the output voltage is set by two resistors, as shown in 图 49. Using the internal resistor ensures a 1%

accurate output voltage and minimizes the number of external components.

Optional Bias

C_BIAS

Supply

BIAS

EN

IN

PG

OUT

SNS

FB

R_PG

Input

Supply

To Load

C_IN

C_OUT

Device

C_FF

R₁

R₂

NR/SS

C_NR/SS

GND 50mV 100mV 200mV 400mV 800mV 1.6V

图 49. Adjustable Operation

R₁and R₂can be calculated for any output voltage range using 公式 8. This resistive network must provide a

current equal to or greater than 5 μA for dc accuracy. Using an R₁of 12.1 kΩ is recommended to optimize the

noise and PSRR.

V_OUT= V_NR/SS× (1 + R₁/ R₂)

(8)

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表 5 shows the resistor combinations required to achieve several common rails using standard 1%-tolerance

resistors.

表 5. Recommended Feedback-Resistor Values⁽¹⁾

TARGETED OUTPUT

FEEDBACK RESISTOR VALUES

CALCULATED OUTPUT

VOLTAGE

(V)

VOLTAGE

(V)

R₁(kΩ)

R₂(kΩ)

0.9

12.4

12.1

12.4

12.1

11.8

12.1

11.8

12.4

100

66.5

49.9

33.2

24.9

14.3

10

0.899

0.949

0.999

1.099

1.198

1.494

1.798

1.89

0.95

1.00

1.10

1.20

1.50

1.80

1.90

2.50

2.85

3.00

3.30

3.60

4.5

8.87

5.9

2.48

4.75

4.42

3.74

3.48

2.55

2.37

2.838

2.990

3.324

3.582

4.502

4.985

5.00

(1) R₁is connected from OUT to FB; R₂is connected from FB to GND.

8.1.12 Sequencing Requirements

Supply and enable sequencing is only required when the bias rail is present. The start-up is always monotonic,

independent of the sequencing requirements. Under these conditions the following requirements apply:

•

V_BIASand V_INcan be sequenced in any order, as long as V_ENis tied to V_INor established after V_IN, as shown

in 图 50.

tt₀≥ 0t

V_UVLO1(IN)

V_IN

V_IH(EN)

V_EN

图 50. Sequencing Diagram

Two typical application circuits for implementing the sequencing requirements are detailed in the Sequencing

with a Power-Good DC-DC Converter Pin and Sequencing with a Microcontroller (MCU) sections.

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8.1.12.1 Sequencing with a Power-Good DC-DC Converter Pin

When a dc-dc converter is used to power the device and the PG of the dc-dc converter is used to enable the

device, pull PG up to V_IN, as shown in 图 51.

From Input Supply

BIAS

OUT

PG

IN

DC-DC

R_PU

Device

IN

EN

图 51. Sequencing with a DC-DC Converter and PG

8.1.12.2 Sequencing with a Microcontroller (MCU)

If a push-pull output stage is used to provide the enable signal to the device and the enable signal can possibly

come before V_INwhen a bias is present (such as with an MCU), convert the enable signal to an open-drain signal

as shown in 图 52. Using an open-drain signal ensures that if the signal arrives before V_IN, then the enable

voltage does not violate the sequencing requirement.

Bias Supply

Input Supply

R_PU

BIAS

IN

Device

EN

Enable Signal

MCU

图 52. Push-Pull Enable to Open-Drain Enable

8.1.13 Power-Good (PG) Operation

To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and

100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and

the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor

is outside of this range, then the power-good signal may not read a valid digital logic level.

Using a large C_FFwith a small C_NR/SScauses the power-good signal to incorrectly indicate that the output voltage

has settled during turn-on. The C_FFtime constant must be greater than the soft-start time constant to ensure

proper operation of the PG during start-up. For a detailed description, see application report Pros and Cons of

Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042.

The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO

events and at light loads, power-good does not assert because the output voltage is sustained by the output

capacitance.

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8.1.14 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input or bias supplies reach the minimum

operational voltage range, and ensures that the device shuts down when the input supply or bias supply

collapse.

The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a

downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the

UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device.

When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled.

The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall

time of the input supply when operating near the minimum V_IN, or by using a bias rail.

图 53 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the

following parts:

•

Region A: The device does not turn on until the input reaches the UVLO rising threshold.

Region B: Normal operation with a regulated output

Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

output may fall out of regulation but the device is still enabled.

•

Region D: Normal operation with a regulated output

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up then follows.

•

Region F: Normal operation followed by the input falling to the UVLO falling threshold.

Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

C

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

图 53. Typical UVLO Operation

8.1.15 Dropout Voltage (V_DO

)

Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and

output voltage (V_DO= V_IN– V_OUT) that is required for regulation. When V_INdrops below the required V_DOfor the

given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout

voltage is proportional to the output current because the device is operating as a resistive switch; see 图 25, 图

26, and 图 27.

Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect

to V_INon this device because of the internal charge pump. The charge pump causes a higher dropout voltage at

lower input voltages when a bias rail is not used, as illustrated in 图 23.

For this device, dropout voltage increases exponentially when the input voltage nears its maximum operating

voltage because the charge pump is internally clamped to 8.0 V; see 图 23 and 图 24.

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8.1.16 Behavior when Transitioning from Dropout into Regulation

Some applications may have transients that place the device into dropout, especially because this device is a

high-current linear regulator. A typical application with these conditions requires setting V_IN≤ V_DOin order to

keep the device junction temperature within its specified operating range. A load transient or line transient in

these conditions can place the device into dropout, such as a load transient from 1 A to 4 A at 1A/µs when

operating with a V_INof 5.4- V and a V_OUTof 5.0 V.

The load transient saturates the error amplifier output stage when the pass element is fully driven on, thus

making the pass element function like a resistor from V_INto V_OUT. The error amplifier response time to this load

transient (I_OUT= 4 A to 1 A at 1 A/µs) is limited because the error amplifier must first recover from saturation and

then place the pass element back into active mode. During the recovery from the load transient, V_OUTovershoots

because the pass element is functioning as a resistor from V_INto V_OUT. If operating under these conditions, apply

a higher dc load or increase the output capacitance to reduce the overshoot because these solutions provide a

path to dissipate the excess charge.

8.1.17 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained; see 图 18. There are two key transitions during a load transient

response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions

shown in 图 54 are broken down in this section. Regions A, E, and H are where the output voltage is in steady-

state.

During transitions from a light load to a heavy load, the:

•

Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B).

•

Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C).

During transitions from a heavy load to a light load, the:

•

Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F).

•

Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G).

Transitions between current levels changes the internal power dissipation because the TPS7A85 is a high-

current device (region D). The change in power dissipation changes the die temperature during these transitions,

and leads to a slightly different voltage level. This different output voltage level shows up in the various load

transient responses; see 图 18.

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor; see 图 20.

tAt

tCt

tDt

tEt

tGt

tHt

B

F

图 54. Load Transient Waveform

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8.1.18 Negatively-Biased Output

The device does not start or operate as expected if the output voltage is pulled below ground. This issue

commonly occurs when powering a split-rail system where the negative rail is established before the device is

enabled. Several application solutions are possible, such as:

•

Enable the device before the negative regulator and disable the device after the negative regulator.

Delaying the EN voltage with respect to the IN voltage allows the internal pulldown resistor to discharge any

voltage at OUT. If the discharge circuit is not strong enough to keep the output voltage at ground, then use an

external pulldown resistor.

•

Place a zener diode from IN to OUT to provide a small positive dc bias on the output when the input is

supplied to the device, as shown in 图 55.

IN

V_IN

OUT

To Load

C_OUT

GND

图 55. Zener Diode Placed from IN to OUT

•

Use a PMOSFET to isolate the output of the device from the load causing the negative bias when the device

is off, as shown in 图 56.

To All Other Loads

To Loads with

Negative Bias

IN

V_IN

OUT

C_OUT

GND

图 56. PMOSFET to Isolate the Output from the Load

8.1.19 Reverse Current Protection

As with most LDOs, this device can be damaged by excessive reverse current.

Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the

absolute maximum rating of V_OUT> V_IN+ 0.3 V:

•

If the device has a large C_OUT, then the input supply collapses quickly and the load current becomes very

small

•

The output is biased when the input supply is not established

The output is biased above the input supply

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If an excessive reverse current flow is expected in the application, then external protection must be used to

protect the device. 图 57 shows one approach of protecting the device.

Schottky Diode

Internal Body Diode

IN

OUT

Device

C_OUT

C_IN

GND

图 57. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.20 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. P_Dcan be approximated using 公式 9:

P_D= (V_OUT- V_IN) ´ I_OUT

(9)

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper

selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to

be obtained. The low dropout of the TPS7A85 allows for maximum efficiency across a wide range of output

voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance

(θ_JA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to 公式

10. The equation is rearranged for output current in 公式 11.

T_J= T_A+ (q_JA´ P_D)

(10)

I_OUT= (T_J– T_A) / [θ_JA× (V_IN– V_OUT)]

(11)

Unfortunately, this thermal resistance (θ_JA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The θ_JArecorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and

copper-spreading area, and is only used as a relative measure of package thermal performance. Note that for a

well-designed thermal layout, θ_JAis actually the sum of the VQFN package junction-to-case (bottom) thermal

resistance (θ_JCbot) plus the thermal resistance contribution by the PCB copper.

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8.1.20.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are given in the Electrical Characteristics table and are used in accordance with 公式 12.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

where:

•

P_Dis the power dissipated as explained in 公式 9

T_Tis the temperature at the center-top of the device package, and

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(12)

8.1.20.2 Recommended Area for Continuous Operation (RACO)

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator can be separated into the

following parts, and is shown in 图 58:

•

Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output

(V_IN– V_OUT) at a given output current level; see the Dropout Voltage (V_DO) section for more details.

Limited by rated output current: The rated output current limits the maximum recommended output current

level. Exceeding this rating causes the device to fall out of specification.

Limited by thermals: The shape of the slope is given by 公式 11. The slope is nonlinear because the junction

temperature of the LDO is controlled by the power dissipation across the LDO; therefore, when V_IN– V_OUT

increases, the output current must decrease in order to ensure that the rated junction temperature of the

device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and reduces

long-term reliability.

•

Limited by V_INrange: The rated input voltage range governs both the minimum and maximum of V_IN– V_OUT.

Output Current Limited

by Dropout

Rated Output

Current

Output Current Limited

by Thermals

Limited by

Minimum V_IN

Maximum V_IN

V_INœ V_OUT(V)

图 58. Continuous Operation Slope Region Description

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图 59 to 图 64 show the recommended area of operation curves for this device on a JEDEC-standard high-K

board with a θ_JA= 35.4°C/W, as given in the Electrical Characteristics table.

5

4.5

4

5

4.5

4

T_A= 40èC

T_A= 55èC

T_A= 70èC

T_A= 85èC

RACO at T_A= 85èC

T_A= 70èC

T_A= 85èC

RACO at T_A= 85èC

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

0.25

0.5

0.75

1

1.25

1.5

0

0.25

0.5

0.75

1

1.25

1.5

V_IN- V_OUT(V)

图 59. Recommended Area for Continuous Operation for

图 60. Recommended Area for Continuous Operation for

V_OUT= 0.9 V with Bias

V_OUT= 1.2 V with Bias

5

T_A= 40èC

4.5

T_A= 55èC

T_A= 70èC

T_A= 85èC

RACO at T_A= 85èC

T_A= 70èC

T_A= 85èC

RACO at T_A= 85èC

4

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

0.25

0.5

0.75

1

1.25

1.5

0

0.25

0.5

0.75

1

1.25

1.5

V_IN- V_OUT(V)

图 61. Recommended Area for Continuous Operation for

图 62. Recommended Area for Continuous Operation for

V_OUT= 1.8 V

V_OUT= 2.5 V

5

T_A= 40èC

4.5

T_A= 55èC

T_A= 70èC

T_A= 85èC

RACO at T_A= 85èC

T_A= 70èC

T_A= 85èC

RACO at T_A= 85èC

4

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

0.25

0.5

0.75

1

1.25

1.5

0

0.25

0.5

0.75

1

1.25

1.5

V_IN- V_OUT(V)

图 63. Recommended Area for Continuous Operation for

图 64. Recommended Area for Continuous Operation for

V_OUT= 3.3 V

V_OUT= 5.0 V

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8.2 Typical Applications

8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions

This section discusses the implementation of the TPS7A85 using the ANY-OUT configuration to regulate a 4.0-A

load requiring good PSRR at high frequency with low noise at 0.9 V using a 1.3-V input voltage and a 5.0-V bias

supply. The schematic for this typical application circuit is provided in 图 65.

C_BIAS

Bias

Supply

BIAS

EN

IN

PG

OUT

SNS

FB

R_PG

Input

Supply

To Load

C_OUT

C_IN

Device

C_FF

NR/SS

C_NR/SS

GND 50mV 100mV 200mV 400mV 800mV 1.6V

图 65. Typical Application

8.2.1.1 Design Requirements

For this design example, use the parameters listed in 表 6 as the input parameters.

表 6. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

1.4 V, ±3%, provided by the dc-dc converter switching at 500 kHz

Output voltage

0.9 V, ±1%

Output current

4.0 A (maximum), 100 mA (minimum)

RMS noise, 10 Hz to 100 kHz

PSRR at 500 kHz

Start-up time

< 10 µV_RMS

> 40 dB

< 25 ms

8.2.1.2 Detailed Design Procedure

For these conditions, the maximum dropout of the TPS7A85 is approximately 240 mV, thus a 400-mV headroom

is sufficient for operation over both input and output voltage accuracy. The bias rail is provided for better

performance for the LILO conditions. PSRR is greater than 40 dB in these conditions, as per 图 2. Noise is less

than 10 µV_RMS, as per 图 11.

The ANY-OUT internal resistor network is also used for maximum accuracy.

To achieve 0.9 V on the output, the 100mV pin is grounded. The voltage value of 100 mV is added to the 0.8-V

internal reference voltage for V_OUT(nom)equal to 0.9 V, as described in 公式 13.

V_OUT(nom)= V_NR/SS+ 0.1 V = 0.8 V + 0.1 V = 0.9 V

(13)

Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.

Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the

output are selected.

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To satisfy the required start-up time and still maintain low-noise performance, a 100-nF C_NR/SSis selected. This

value is calculated with 公式 14. To further minimize noise, a feed-forward capacitance (C_FF) of 10 nF is

selected.

t_SS= (V_NR/SS× C_NR/SS) / I_NR/SS

(14)

The maximum ambient temperature for this application is 40°C based on 图 59 and given the 3% accuracy of the

input supply.

8.2.1.3 Application Curves

100

80

60

40

20

0

15

13.5

12

V_IN= 1.10 V

V_IN= 1.15 V

V_IN= 1.20 V

V_IN= 1.25 V

V_IN= 1.30 V

V_IN= 1.35 V

V_IN= 1.40 V

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 4.0 A

10.5

9

7.5

6

4.5

3

10

100

1k

10k

100k

1M

10M

0.6

1.2

1.8

2.4

3

3.6

4.2

4.8

5.4

Frequency (Hz)

Output Voltage (V)

图 66. Output PSRR

图 67. Output Noise Level

8.2.2 Typical Application for a 5.0-V Rail

This section discusses the implementation of the TPS7A85 using an adjustable feedback network to regulate a

4-A load requiring good PSRR at high frequency with low noise at an output voltage of 5.0 V. The schematic for

this typical application circuit is provided in 图 68.

Optional Bias

C_BIAS

Supply

BIAS

EN

IN

PG

OUT

SNS

FB

R_PG

Input

Supply

To Load

C_IN

C_OUT

Device

C_FF

R₁

R₂

NR/SS

C_NR/SS

GND 50mV 100mV 200mV 400mV 800mV 1.6V

图 68. Typical Application

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8.2.2.1 Design Requirements

For this design example, use the parameters listed in 表 6 as the input parameters.

表 7. Design Parameters

PARAMETER

Input voltage

Output voltage

Output current

Start-up time

DESIGN REQUIREMENT

5.60 V, ±1%, provided by the dc-dc converter switching at 500 kHz

5.0 V, ±1%

4.0 A (maximum), 10 mA (minimum)

< 25 ms

8.2.2.2 Detailed Design Procedure

For these conditions, the maximum dropout of the TPS7A85 is approximately 500 mV, thus a 600-mV headroom

is sufficient for operation over both input and output voltage accuracy. At full load and high temperature on some

devices, the TPS7A85 can enter dropout if both the input and output supply are beyond the edges of their

accuracy specification.

For a 5.0-V output, use external adjustable resistors. See the resistor values in listed 表 5 for choosing resistors

for a 5.0-V output.

Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.

Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the

output are selected. To further minimize noise, a feed-forward capacitance (C_FF) of 10 nF is selected.

To satisfy the required start-up time and still maintain low-noise performance, a 100-nF C_NR/SSis selected. This

value is calculated with 公式 14.

t_SS= (V_NR/SS× C_NR/SS) / I_NR/SS

(15)

The maximum ambient temperature for this application is 40°C based on 图 64 and given the 1% accuracy of the

input supply. This temperature can still exceed the maximum junction temperature, but the 4.0-A load is a short

pulse requirement and not a dc load so the thermal effects are minimal.

8.2.2.3 Application Curves

100

80

60

40

20

0

100

80

60

40

20

0

I_OUT= 0.1 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 4.0 A

V_IN= 5.35 V

V_IN= 5.4 V

V_IN= 5.45 V

V_IN= 5.5 V

V_IN= 5.55 V

V_IN= 5.60 V

V_IN= 5.65 V

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

图 69. PSRR vs Frequency and I_OUTfor V_OUT= 5.0 V with

图 70. PSRR vs Frequency and V_INfor V_OUT= 5.0 V at I_OUT

V_IN= 5.6 V

= 4.0 A

9 Power-Supply Recommendations

The TPS7A85 is designed to operate from an input voltage supply range between 1.1 V and 6.5 V. If the input

supply is less than 1.4 V, then a bias rail of at least 3.0 V must be used. The input voltage range provides

adequate headroom in order for the device to have a regulated output. This input supply must be well regulated.

If the input supply is noisy, additional input capacitors with low ESR can help improve output noise performance.

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10 Layout

10.1 Layout Guidelines

10.1.1 Board Layout

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,

copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and

negatively affects system performance. The grounding and layout scheme shown in 图 71 minimizes inductive

parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability.

A ground reference plane is also recommended and is either embedded in the PCB itself or located on the

bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output

voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when

connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.

10.2 Layout Example

Ground Plane for Thermal Relief and Signal

Ground

10

9

8

7

6

To PG Pullup Supply

PG Output

1.6V 11

BIAS

5

50mV

PG

C_BIAS

R_PG

To Bias Supply

To Signal Ground

Enable Signal

12

4

3

Thermal Pad

R₂

NR/SS 13

EN 14

FB

To Signal Ground

To Load

C_NR/SS

2

1

SNS

OUT

C_FFR₁

15

IN

16

18 19 20

17

Input Power Plane

Output Power Plane

C_IN

C_OUT

Power Ground Plane

Vias used for application purposes.

图 71. Example Layout

39

TPS7A85

ZHCSEP4A –JANUARY 2016–REVISED FEBRUARY 2016

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

评估模块 (EVM) 可与 TPS7A85 配套使用，帮助评估初始电路性能。有关此固定装置的相关摘要信息，请参见表

8。

表 8. 设计套件与评估模块

名称

文献编号

SLVU919

SBVU021

TPS7A8300EVM-209 评估模块

TPS7A8300EVM-579 评估模块

您可以在德州仪器 (TI) 网站上的 TPS7A85 产品文件夹中获取 EVM。

11.1.1.2 Spice 模型

分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从 TPS7A85 产品

文件夹中的仿真模型下获取 TPS7A85 的 SPICE 模型。

11.1.2 器件命名规则

表 9. 订购信息⁽¹⁾

产品

说明

YY 为封装标识符。

Z 为封装数量。

TPS7A85YYZ

(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。

11.2 文档支持

11.2.1 相关文档ꢀ


型号：	TPS7A8500RGRT
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示功能的 4A、低输入电压、低噪声、高精度、超低压降稳压器 \| RGR \| 20 \| -40 to 125 输出元件稳压器调节器
文件：	总48页 (文件大小：2934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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