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TPS7A85A

SBVS313 –JUNE 2017

TPS7A85A 4-A, High-Accuracy (0.75%), Low-Noise (4.4 μVRMS), LDO Regulator

1 Features

3 Description

The TPS7A85A is a low-noise (4.4 μV_RMS), low

dropout linear regulator (LDO) capable of sourcing 4

A with only 240 mV of maximum dropout. The device

output voltage is pin-programmable from 0.8 V to

3.95 V and adjustable from 0.8 V to 5.1 V using an

external resistor divider.

1

•

Low Dropout: 150 mV (Typical) at 4 A

•

0.75% (Maximum) Accuracy Over Line, Load, and

Temperature With BIAS

•

Output Voltage Noise:

–

4.4 μV_RMSat 0.8-V Output

7.7 μV_RMSat 5.1-V Output

The combination of low-noise (4.4 μV_RMS), high-

PSRR, and high output current capability makes the

•

Input Voltage Range:

TPS7A85A

ideal

to

power

noise-sensitive

–

Without BIAS: 1.4 V to 6.5 V

With BIAS: 1.1 V to 6.5 V

components such as those found in high-speed

communications, video, medical, or test and

measurement applications. The high performance of

the TPS7A85A limits power-supply-generated phase

noise and clock jitter, making this device ideal for

powering high-performance serializer and deserializer

(SerDes), analog-to-digital converters (ADCs), digital-

to-analog converters (DACs), and RF components.

Specifically, RF amplifiers benefit from the high-

performance and 5.1-V output capability of the

device.

•

ANY-OUT™ Operation:

Output Voltage Range: 0.8 V to 3.95 V

Adjustable Operation:

Output Voltage Range: 0.8 V to 5.1 V

Power-Supply Ripple Rejection:

40 dB at 500 kHz

–

•

Excellent Load Transient Response

Adjustable Soft-Start In-Rush Control

Open-Drain Power-Good (PG) Output

For digital loads (such as application-specific

integrated circuits (ASICs), field-programmable gate

arrays (FPGAs), and digital signal processors

(DSPs)) requiring low-input voltage, low-output (LILO)

voltage operation, the exceptional accuracy (0.75%

over load and temperature), remote sensing,

excellent transient performance, and soft-start

capabilities of the TPS7A85A ensure optimal system

performance.

Stable with a 47-μF or Larger Ceramic Output

Capacitor

•

θ_JC= 3.4°C/W

3.5-mm × 3.5-mm, 20-Pin VQFN

2 Applications

The versatility of the TPS7A8500A makes the device

•

Digital Loads: SerDes, FPGAs, and DSPs

Instrumentation, Medical, and Audio

High-Speed Analog Circuits:

a

component of choice for many demanding

applications.

Device Information⁽¹⁾

–

VCO, ADC, DAC, and LVDS

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Imaging: CMOS Sensors and Video ASICs

Test and Measurement

TPS7A85A

VQFN (20)

3.50 mm × 3.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Powering RF Components

Powering Digital Loads

TPS7A85A

C_BIAS

Bias

Supply

Input Supply

OUT

IN

PG

1.4 V_IN

IN

BIAS

C_IN

EN

PG

OUT

SNS

FB

VCC

R_PG

0.9 V_OUT

To Digital

Load

NR/SS

EN

C_OUT

C_NR/SS

IQ Modulators

IQ Demodulators

TPS7A85A

1.6 V

TRF372017

TRF3722

TRF371125

TRF371135

C_FF

800 mV

400 mV

200 mV

100 mV

50 mV

ANYOUT

Used to set

voltage

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS7A85A

SBVS313 –JUNE 2017

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Table of Contents

1

2

3

4

5

6

Features.................................................................. 1

7

Detailed Description ............................................ 16

7.1 Overview ................................................................. 16

7.2 Functional Block Diagram ....................................... 16

7.3 Feature Description................................................. 17

7.4 Device Functional Modes........................................ 20

Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Applications ................................................ 38

Power-Supply Recommendations...................... 39

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information ................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 8

8

9

10 Layout................................................................... 39

10.1 Layout Guidelines ................................................. 39

10.2 Layout Example .................................................... 40

4 Revision History

DATE

REVISION

NOTES

June 2017

*

Initial release.

2

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5 Pin Configuration and Functions

RGR Package

20-Pin VQFN

Top View

20 1ꢁ 18 17 16

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C.

1

2

3

4

5

15 Lb

9b

14

13

12

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6

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10

Pin Functions

I/O

DESCRIPTION

NAME

50mV

NO.

5

100mV

200mV

400mV

800mV

1.6V

6

ANY-OUT voltage setting pins. These pins connect to an internal feedback network. Connect these pins to ground,

SNS, or leave floating. Connecting these pins to ground increases the output voltage, whereas connecting these pins

to SNS increases the resolution of the ANY-OUT network but decreases the range of the network; multiple pins may

be simultaneously connected to GND or SNS to select the desired output voltage. Leave these pins floating (open)

when not in use. See ANY-OUT Programmable Output Voltage for additional details.

7

I

9

10

11

BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, V_IN

1.2 V, V_OUT= 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac

performance for V_IN≤ 2.2 V. A 10-µF capacitor (5-µF capacitance) or larger must be connected between this pin and

ground if BIAS pin is used. If not used, this pin must be left floating or tied to ground and a capacitor is not required.

=

BIAS

EN

12

14

3

I

Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable

functionality is not required, this pin must be connected to IN or BIAS.

Feedback pin connected to the error amplifier. Although not required, TI recommends a 10-nF feed-forward capacitor

from FB to OUT (as close to the device as possible) to maximize ac performance. The use of a feed-forward

capacitor may disrupt power-good (PG) functionality. See ANY-OUT Programmable Output Voltage and Adjustable

Operation for more details.

FB

Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance

connection.

GND

IN

8, 18

—

I

Input supply voltage pin. A 10-μF or larger ceramic capacitor (5 μF of capacitance or greater) from IN to ground is

required to reduce the impedance of the input supply. Place the input capacitor as close as possible to the input. See

Input and Output Capacitor Requirements (C_INand C_OUT) for more details.

15, 16, 17

Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference

voltage noise and enables the soft-start function. Although not required, TI recommends a 10-nF or larger capacitor

be connected from NR/SS to GND (as close as possible to the pin) to maximize ac performance. See Input and

Output Capacitor Requirements (C_INand C_OUT) for more details.

NR/SS

13

—

Regulated output pin. A 47-μF or larger ceramic capacitor (25 μF of capacitance or greater) from OUT to ground is

required for stability and must be placed as close as possible to the output. Minimize the impedance from the OUT

pin to the load. See Input and Output Capacitor Requirements (C_INand C_OUT) for more details.

OUT

PG

1, 19, 20

O

Active-high, PG pin. An open-drain output indicates when the output voltage reaches V_IT(PG)of the target. The use of

a feed-forward capacitor may disrupt PG functionality. See Input and Output Capacitor Requirements (C_INand C_OUT)

for more details.

4

2

Output voltage sense input pin. This pin connects the internal R₁resistor to the output. Connect this pin to the load

side of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin

floating. See ANY-OUT Programmable Output Voltage and Adjustable Operation for more details.

SNS

I

Thermal pad

—

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

IN, BIAS, PG, EN

–0.3

7

V

IN, BIAS, PG, EN (5% duty cycle, pulse

duration = 200 μs)

–0.3

7.5

V

Voltage

Current

SNS, OUT

–0.3

V_IN+ 0.3

3.6

V

NR/SS, FB

50mV, 100mV, 200mV, 400mV, 800mV, 1.6V

V_OUT+ 0.3

Internally

limited

Internally

limited

OUT

A

PG (sink current into device)

5

mA

°C

Operating junction temperature, T_J

Storage temperature, T_stg

–55

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.

4

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6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

MIN

1.1

3

NOM

MAX

6.5

5.1

V_IN

4

UNIT

V

V_IN

Input supply voltage range

Bias supply voltage range⁽¹⁾

Output voltage range⁽²⁾

Enable voltage range

Output current

V_BIAS

V_OUT

V_EN

I_OUT

C_IN

V

0.8

0

V

0

A

Input capacitor

10

47

μF

47 || 10 || 10

C_OUT

Output capacitor

47

μF

(3)

C_BIAS

R_PG

BIAS Capacitor

10

μF

kΩ

nF

Power-good pullup resistance

NR/SS capacitor

100

C_NR/SS

C_FF

10

Feed-forward capacitor

Top resistor value in feedback network for adjustable

operation

(4)

R₁

12.1

kΩ

Bottom resistor value in feedback network for

adjustable operation

(5)

R₂

T_J

160

kΩ

Operating junction temperature

–40

125

°C

(1) BIAS supply is required when the V_INsupply is below 1.4 V. Conversely, no BIAS supply is required when the V_INsupply is higher than

or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for V_IN≤ 2.2 V.

(2) This output voltage range does not include device accuracy or accuracy of the feedback resistors.

(3) The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency

range is a typical value for dc-dc supplies.

(4) The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R₁value.

(5) The upper limit for the R₂resistor is to ensure accuracy by making the current through the feedback network much larger than the

leakage current into the feedback node.

6.4 Thermal Information

TPS7A85A

THERMAL METRIC⁽¹⁾

RGR (VQFN)

20 PINS

43.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

36.8

17.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

ψ_JB

17.6

R_θJC(bot)

3.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

over operating junction temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.5 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 μF, C_OUT= 47 μF, C_NR/SS

= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

1.1

3

TYP

MAX

UNIT

V_IN

Input supply voltage range⁽³⁾

Bias supply voltage range⁽³⁾

Feedback voltage

6.5

V

V_BIAS

V_IN= 1.1 V

6.5

V_FB

0.8

V_NR/SS

V_UVLO1(IN)

V_HYS1(IN)

V_UVLO2(IN)

V_HYS2(IN)

NR/SS pin voltage

V

Input supply UVLO with BIAS

V_UVLO1(IN)hysteresis

V_INrising with V_BIAS= 3 V

V_BIAS= 3 V

1.02

320

1.31

253

1.085

1.39

mV

V

Input supply UVLO without BIAS V_INrising

V_UVLO2(IN)hysteresis

mV

V_BIASrising

Bias supply UVLO

V_UVLO(BIAS)

V_HYS(BIAS)

2.83

290

2.9

V

V_IN= 1.1 V

V_UVLO(BIAS)hysteresis

Range

V_IN= 1.1 V

mV

Using the ANY-OUT pins

Using external resistors⁽⁴⁾

0.8 – 1%

3.95 + 1%

5.1 + 1%

V

(6)

0.8 V ≤ V_OUT≤ 5.1 V

(5)

Accuracy⁽⁴⁾

5 mA ≤ I_OUT≤ 4 A

1.4 V ≤ V_IN≤ 6.5 V

–1%

1%

Output

voltage

V_OUT

1.1V ≤ V_IN≤ 2.2 V

0.8 V ≤ V_OUT≤ 1.9 V

5 mA ≤ I_OUT≤ 4 A

Accuracy with

BIAS

–0.75%

0.75%

3 V ≤ V_BIAS≤ 6.5 V

I_OUT= 5 mA

1.4 V ≤ V_IN≤ 6.5 V

ΔV_OUT/ ΔV_IN

Line regulation

0.0035

0.07

mV/V

mV/A

5 mA ≤ I_OUT≤ 4 A

3 V ≤ V_BIAS≤ 6.5 V

V_IN= 1.1 V

ΔV_OUT/ ΔI_OUT

Load regulation

5 mA ≤ I_OUT≤ 4 A

0.08

0.4

5 mA ≤ I_OUT≤ 4 A

V_OUT= 5.1 V

V_IN= 1.4 V

I_OUT= 4 A

V_FB= 0.8 V – 3%

215

325

320

500

V_IN= 5.5 V

I_OUT= 4 A

V_FB= 0.8 V – 3%

V_DO

Dropout voltage

mV

V_IN= 1.1 V

V_BIAS= 5 V

I_OUT= 4 A

150

240

V_FB= 0.8 V – 3%

V_IN= 5.7 V

I_OUT= 4 A

V_FB= 0.8 V – 3%

600

5.7

V_OUTforced at 0.9 × V_OUT(nom)

V_IN= V_OUT(nom)+ 0.4 V

,

I_LIM

I_SC

Output current limit

4.7

5.2

1

A

Short-circuit current limit

R_LOAD= 20 mΩ

(1) V_OUT(nom)is the calculated V_OUTtarget value from the ANY-OUT in a fixed configuration. In an adjustable configuration, V_OUT(nom)is the

expected V_OUTvalue set by the external feedback resistors.

(2) This 50-Ω load is disconnected when the test conditions specify an I_OUTvalue.

(3) BIAS supply is required when the V_INsupply is below 1.4 V. Conversely, no BIAS supply is required when the V_INsupply is higher than

or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for V_IN≤ 2.2 V.

(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(5) The device is not tested under conditions where V_IN> V_OUT+ 1.25 V and I_OUT= 4 A because the power dissipation is higher than the

maximum rating of the package.

(6) For V_OUT≤ 5 V, V_IN= V_OUT+ 0.5 V. For V_OUT> 5 V, V_IN= V_OUT+ 0.6 V.

6

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Electrical Characteristics (continued)

over operating junction temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.5 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 μF, C_OUT= 47 μF, C_NR/SS

= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN= 6.5 V

I_OUT= 5 mA

2.8

4

mA

V_IN= 1.4 V

I_OUT= 4 A

I_GND

GND pin current

4.8

6

25

Shutdown, PG = open, V_IN= 6.5 V

V_EN= 0.5 V

µA

V_IN= 6.5 V

V_EN= 0 V and 6.5 V

I_EN

EN pin current

–0.1

0.1

V_IN= 1.1 V

V_BIAS= 6.5 V

V_OUT(nom)= 0.8 V

I_OUT= 4 A

I_BIAS

BIAS pin current

2.3

3.5

mA

EN pin low-level input voltage

(disable device)

V_IL(EN)

V_IH(EN)

0

1.1

0.5

6.5

V

EN pin high-level input voltage

(enable device)

88.3% ×

V_OUT

V_IT(PG)

PG pin threshold

For falling V_OUT

For rising V_OUT

82% × V_OUT

93% × V_OUT

V

V_HYS(PG)

V_OL(PG)

PG pin hysteresis

1% × V_OUT

V_OUT< V_IT(PG)

I_PG= –1 mA (current into device)

PG pin low-level output voltage

0.4

1

V_OUT> V_IT(PG)

V_PG= 6.5 V

I_lkg(PG)

PG pin leakage current

µA

V_NR/SS= GND

V_IN= 6.5 V

I_NR/SS

I_FB

NR/SS pin charging current

FB pin leakage current

4

6.2

9

µA

nA

V_IN= 6.5 V

–100

100

f = 10 kHz

V_OUT= 0.8 V

V_BIAS= 5 V

42

39

V_IN– V_{O UT}= 0.5 V

I_OUT= 4 A

C_NR/SS= 100 nF

C_FF= 10 nF

f = 500 kHz

V_OUT= 0.8 V

V_BIAS= 5 V

PSRR

Power-supply ripple rejection

dB

C_OUT

=

f = 10 kHz

V_OUT= 5 V

40

25

47 μF || 10 μF || 10 μF

f = 500 kHz

V_OUT= 5 V

Bandwidth = 10 Hz to 100 kHz, V_IN= 1.1 V

V_OUT= 0.8 V

V_BIAS= 5 V

I_OUT= 4 A

4.4

C_NR/SS= 100 nF

C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF

V_n

Output noise voltage

μV_RMS

Bandwidth = 10 Hz to 100 kHz

V_OUT= 5 V

I_OUT= 4 A

C_NR/SS= 100 nF

8.4

C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF

Shutdown, temperature increasing

Reset, temperature decreasing

160

140

T_sd

T_J

Thermal shutdown temperature

Operating junction temperature

°C

–40

125

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6.6 Typical Characteristics

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

100

80

60

40

20

0

100

80

60

40

20

0

I_OUT= 0.1 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 3.5 A

I_OUT= 4.0 A

V_IN= 1.10 V

V_IN= 1.15 V

V_IN= 1.20 V

V_IN= 1.25 V

V_IN= 1.30 V

V_IN= 1.35 V

V_IN= 1.40 V

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= 1.2 V, V_BIAS= 5 V,

I_OUT= 4 A, V_BIAS= 5 V,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 1. PSRR vs Frequency and I_OUT

Figure 2. PSRR vs Frequency and V_INWith Bias

100

V_BIAS= 0 V

V_BIAS= 3.0 V

V_BIAS= 5.0 V

V_BIAS= 6.5 V

80

60

40

60

40

20

0

V_IN= 1.1 V, V_BIAS= 5 V

V_IN= 1.2 V, V_BIAS= 5 V

V_IN= 1.4 V, V_BIAS= 0 V

20

V_IN= 2.5 V, V_BIAS= 0 V

V_IN= 5.0 V, V_BIAS= 0 V

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= 1.4 V, I_OUT= 1 A,

I_OUT= 1 A,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 3. PSRR vs Frequency and V_BIAS

Figure 4. PSRR vs Frequency and V_IN

100

V_OUT= 0.8 V

V_OUT= 0.9 V

V_IN= 3.60 V

V_IN= 3.65 V

V_OUT= 1.1 V

V_IN= 3.70 V

80

V_OUT= 1.2 V

V_OUT= 1.5 V

V_OUT= 1.8 V

V_IN= 3.75 V

V_IN= 3.80 V

V_IN= 3.85 V

60

V_OUT= 2.5 V

V_IN= 3.90 V

40

20

0

40

20

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= V_OUT+ 0.4 V, V_BIAS= 5.0 V, I_OUT= 4 A,

I_OUT= 4 A, C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

C_FF= 10 nF

Figure 5. PSRR vs Frequency and V_OUTWith Bias

Figure 6. PSRR vs Frequency and V_INfor V_OUT= 3.3 V

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Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

100

80

60

40

20

0

100

80

60

40

20

0

C_OUT= 47 mF||10 mF||10 mF

C_OUT= 47 mF

I_OUT= 0.1 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 4.0 A

C_OUT= 100 mF

C_OUT= 200 mF

C_OUT= 500 mF

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_IN= 5.6 V, C_OUT= 47 μF || 10 μF || 10 μF,

V_IN= V_OUT+ 0.6 V, I_OUT= 4 A,

C_NR/SS= 10 nF, C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 7. PSRR vs Frequency and C_OUT

Figure 8. PSRR vs Frequency and I_OUTfor V_OUT= 5 V

100

80

60

40

20

0

100

V_IN= 5.35 V

V_IN= 5.4 V

V_IN= 5.45 V

V_IN= 5.5 V

V_IN= 5.55 V

V_IN= 5.60 V

V_IN= 5.65 V

80

60

40

20

V_BIAS= 3.0 V

V_BIAS= 5.0 V

V_BIAS= 6.5 V

0

10

100

1k

10k

100k

1M

10M

100 1k

10k

100k

1M

10M

Frequency (Hz)

I_OUT= 4 A, C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF,

V_IN= V_OUT+ 0.4 V, V_OUT= 1 V, I_OUT= 4 A,

C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 9. PSRR vs Frequency and V_INfor V_OUT= 5 V

Figure 10. V_BIASPSRR vs Frequency

15

2

I_OUT= 1.0 A

V_OUT= 0.8 V, 4.5 mV_RMS

1

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 4.0 A

V_OUT= 1.5 V, 5.4 mV_RMS

13.5

12

10.5

9

V_OUT= 3.3 V, 8.5 mV_RMS

V_OUT= 5.0 V, 12.4 mV_RMS

0.5

0.2

0.1

0.05

0.02

0.01

7.5

6

0.005

4.5

3

0.002

0.001

0.6

1.2

1.8

2.4

3

3.6

4.2

4.8

5.4

10

100

1k

10k

100k

1M

Output Voltage (V)

Frequency (Hz)

V_IN= V_OUT+ 0.4 V and V_BIAS= 5 V for V_OUT≤ 2.2 V,

V_IN= V_OUT+ 0.4 V and V_BIAS= 5 V for V_OUT≤ 2.2 V, I_OUT= 4 A,

RMS Noise BW = 10 Hz to 100 kHz,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 12. Output Noise vs Frequency and V_OUT

Figure 11. Output Voltage Noise vs Output Voltage

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Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

2

V_IN= 1.4 V, V_BIAS= 5.0 V, 4.5 mV_RMS

V_IN= 1.4 V, 6.0 mV_RMS

C_NR/SS= 0 nF, 6.2 mV_RMS

C_NR/SS= 1 nF, 4.9 mV_RMS

C_NR/SS= 10 nF, 4.5 mV_RMS

C_NR/SS= 100 nF, 4.4 mV_RMS

1

V_IN= 1.5 V, 4.5 mV_RMS

0.5

V_IN= 1.8 V, 4.5 mV_RMS

V_IN= 2.5 V, 4.6 mV_RMS

0.2

0.1

0.2

0.1

V_IN= 5.0 V, 5.15 mV_RMS

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

Frequency (Hz)

I_OUT= 1 A, RMS Noise BW = 10 Hz to 100 kHz,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

V_IN= V_OUT+ 0.4 V, V_BIAS= 5 V, I_OUT= 4 A,

RMS Noise BW = 10 Hz to 100 kHz,

C_OUT= 47 μF || 10 μF || 10 μF, C_FF= 10 nF

Figure 14. Output Noise vs Frequency and C_NR/SS

Figure 13. Output Noise vs Frequency and V_IN

2

C_FF= 0 nF, 6.2 mV_RMS

C_NR/SS= 10 nF, 12.3 mV_RMS

1

C_FF= 0.1 nF, 5.8 mV_RMS

C_NR/SS= 100 nF, 8.4 mV_RMS

C_FF= 1 nF, 4.9 mV_RMS

C_FF= 10 nF, 4.5mV_RMS

C_FF= 100 nF, 4.4 mV_RMS

C_FF= C_NR/SS= 100 nF, 6.6 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

Frequency (Hz)

V_IN= V_OUT+ 0.4 V, V_BIAS= 5 V, I_OUT= 4 A,

RMS Noise BW = 10 Hz to 100 kHz,

V_IN= 5.6 V, I_OUT= 4 A, RMS Noise BW = 10 Hz to 100 kHz,

C_OUT= 47 μF || 10 μF || 10 μF, C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF

Figure 15. Output Noise vs Frequency and C_FF

Figure 16. Output Noise at 5.0-V Output vs C_NR/SSand C_FF

1.2

10

7.5

5

50

25

0

Output Current

V_OUT= 0.9 V

V_OUT= 1.2 V

V_OUT= 1.8 V

1

0.8

0.6

0.4

0.2

0

V_EN

2.5

0

-25

-50

V_OUT, C_NR/SS= 0 nF

V_OUT, C_NR/SS= 10 nF

V_OUT, C_NR/SS= 47 nF

V_OUT, C_NR/SS= 100 nF

-0.2

0

5

10

15

20

25

30

35

40

45

50

0

0.5

1

1.5

2

Time (ms)

V_IN= 1.2 V, V_OUT= 0.9 V, V_BIAS= 5.0 V, I_OUT= 4 A,

V_IN= V_OUT+ 0.3 V, V_BIAS= 5 V, I_{OUT, DC}= 100 mA, slew rate =

1 A/μs, C_NR/SS= C_FF= 10 nF, C_OUT= 47 μF || 10 μF || 10 μF

C_OUT= 47 μF || 10 μF || 10 μF, C_FF= 10 nF

Figure 18. Load Transient Waveform vs Time and

V_OUTWith Bias

Figure 17. Start-Up Waveform vs Time and C_NR/SS

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Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

50

25

0

10

7.5

5

50

25

0

Slew Rate = 2 A/ms

Slew Rate = 1 A/ms

Slew Rate = 0.5 A/ms

Output Current

V_OUT= 3.3 V

V_OUT= 5.0 V

2.5

0

-25

-50

-25

-50

0

0.4

0.8

1.2

1.6

2

0

0.4

0.8

1.2

1.6

2

Time (ms)

I_{OUT, DC}= 100 mA, C_OUT= 47 μF || 10 μF || 10 μF,

C_NR/SS= C_FF= 10 nF, slew rate = 1 A/μs

V_OUT= 5 V, I_{OUT, DC}= 100 mA, I_OUT= 100 mA to 4 A,

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= C_FF= 10 nF

Figure 19. Load Transient Waveform vs

Time and V_OUTWithout Bias

Figure 20. Load Transient Waveform vs

Time and Slew Rate

50

25

0

50

I_OUT= 100 mA to 4 A

I_OUT= 500 mA to 4 A

I_OUT= 1 A to 4 A

25

0

-25

-50

C_OUT= 100 mF

C_OUT= 200 mF

C_OUT= 500 mF

C_OUT= 500 mF || 1 mF Oscon

-50

0

0.4

0.8

1.2

1.6

2

0

0.4

0.8

1.2

1.6

2

Time (ms)

V_IN= 1.2 V, V_BIAS= 5.0 V, I_OUT= 100 mA to 4 A,

V_IN= 1.2 V, V_BIAS= 5.0 V, C_OUT= 47 μF || 10 μF || 10 μF,

C_NR/SS= C_FF= 10 nF, slew rate = 1 A/μs

Figure 21. Load Transient Waveform vs Time and C_OUT

(V_OUT= 0.9 V)

Figure 22. Load Transient Waveform vs Time and DC Load

(V_OUT= 0.9 V)

450

-40°C

0°C

450

-40°C

0°C

400

350

300

250

200

150

400

350

300

250

200

150

25°C

85°C

125°C

25°C

85°C

125°C

1

2

3

4

5

6

1

2

3

4

5

6

Input Voltage (V)

I_OUT= 4 A, V_BIAS= 0 V

I_OUT= 4 A, V_BIAS= 6.5 V

Figure 23. Dropout Voltage vs Input Voltage Without Bias

Figure 24. Dropout Voltage vs Input Voltage With Bias

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Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

300

250

200

150

100

50

0.2

0.175

0.15

0.125

0.1

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

0.075

0.05

0.025

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Output Current (A)

V_IN= 1.4 V, V_BIAS= 0 V

V_IN= 1.1 V, V_BIAS= 3 V

Figure 25. Dropout Voltage vs Output Current Without Bias

Figure 26. Dropout Voltage vs Output Current With Bias

350

0.2

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

300

0.15

0.1

250

200

150

100

50

0.05

0

-0.05

-0.1

0

0.5

1

1.5

2

2.5

3

3.5

4

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Output Current (A)

Output Voltage (V)

V_IN= 5.5 V

I_OUT= 100 mA to 4 A

Figure 27. Dropout Voltage vs Output Current (High V_IN

)

Figure 28. Load Regulation vs Output Voltage

0.15

-40°C

0°C

0.025

0

25°C

0.1

85°C

125°C

0.05

0

-0.025

-0.05

-0.075

-0.1

-40°C

0°C

25°C

85°C

125°C

-0.05

-0.1

0

0.8

1.6

2.4

3.2

4

0

0.8

1.6

2.4

3.2

4

Output Current (A)

Figure 29. Load Regulation (0.8-V Output)

Figure 30. Load Regulation (3.3-V Output)

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Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

0.025

0

-0.025

-0.05

0

-0.025

-0.05

-0.075

-0.1

-0.075

-0.1

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

-0.125

0

0.8

1.6

2.4

3.2

4

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

Output Current (A)

Input Voltage (V)

I_OUT= 5 mA

Figure 31. Load Regulation (5-V Output)

Figure 32. Line Regulation Without Bias

25

0

-20

-40

-60

-25

-50

-75

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

-100

3

3.5

4

4.5

5

5.5

6

6.5

5.25

5.5

5.75

6

6.25

6.5

Bias Voltage (V)

Input Voltage (V)

V_IN= 1.1 V, I_OUT= 5 mA

Figure 33. Line Regulation vs Bias Voltage

I_OUT= 5 mA

Figure 34. Line Regulation (5-V Output)

3.3

3

2.4

2

1.6

1.2

0.8

2.7

2.4

2.1

1.8

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

1.5

1

2

3

4

5

6

7

3

3.5

4

4.5

5

5.5

6

6.5

Input Voltage (V)

Bias Voltage (V)

I_OUT= 5 mA

V_IN= 1.1 V, I_OUT= 5 mA

Figure 35. Ground Pin Current vs Input Voltage

Figure 36. Bias Pin Current vs Bias Voltage

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Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

5

4

3

2

1

0

6

5

4

3

2

1

0

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

3

3.5

4

4.5

5

5.5

6

6.5

Input Voltage (V)

Bias Voltage (V)

V_IN= 1.1 V

Figure 37. Shutdown Current vs Input Voltage

Figure 38. Shutdown Current vs Bias Voltage

7.5

7

1.4

1.2

1

6.5

6

0.8

0.6

0.4

0.2

5.5

5

-40°C

0°C

25°C

85°C

125°C

V_UVLO2(IN), Rising

V_UVLO2(IN), Falling

V_UVLO1(IN), Rising

V_UVLO1(IN), Falling

4.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

-40

-20

0

20

40

60

80

100 120 140

Input Voltage (V)

Temperature (°C)

Figure 39. NR/SS Charging Current vs Input Voltage

Figure 40. V_INUVLO vs Temperature

0.85

0.8

3

V_UVLO(BIAS), Rising

V_UVLO(BIAS), Falling

2.9

2.8

2.7

2.6

2.5

0.75

0.7

0.65

0.6

V_IH(EN), V_IN= 1.4 V

V_IH(EN), V_IN= 6.5 V

V_IL(EN), V_IN= 1.4 V

V_IL(EN), V_IN= 6.5 V

0.55

-60

-30

0

30

60

90

120

150

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

V_IN= 1.1 V

Figure 41. V_BIASUVLO vs Temperature

Figure 42. Enable Threshold vs Temperature

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Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.5 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

0.75

0.6

0.45

0.3

0.15

0

0.4

0.32

0.24

0.16

0.08

0

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

0

0.5

1

1.5

2

2.5

3

0

0.5

1

1.5

2

2.5

3

PG Current Sink (mA)

V_IN= 6.5 V

Figure 43. PG Voltage vs PG Current Sink

Figure 44. PG Voltage vs PG Current Sink

90.25

V_IT(PG)Rising, V_IN= 1.4 V

V_IT(PG)Rising, V_IN= 6.5 V

V_IT(PG)Falling, V_IN= 1.4V

V_IT(PG)Falling, V_IN= 6.5 V

90

89.75

89.5

89.25

89

88.75

88.5

88.25

88

87.75

-50

-25

0

25

50

75

100

125

Temperature (°C)

Figure 45. PG Threshold vs Temperature

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7 Detailed Description

7.1 Overview

The TPS7A85A is a high-current (4 A), low-noise (4.4 µV_RMS), high accuracy (0.75%) low-dropout linear voltage

regulator (LDO). These features make the device a robust solution to solve many challenging problems in

generating a clean, accurate power supply.

The TPS7A85A has several features that makes the device useful in a variety of applications. See Table 1 for a

categorization of the functions shown in the Functional Block Diagram.

Table 1. Features

VOLTAGE REGULATION

SYSTEM START-UP

INTERNAL PROTECTION

High accuracy

Programmable soft-start

Foldback current limit

No sequencing requirement between BIAS,

IN and EN

Low-noise, high-PSRR output

Fast transient response

Thermal shutdown

Power-good output

Start-up with negative bias on OUT

Overall, these features make the TPS7A85A the component of choice due to its versatility and ability to generate

a supply for most applications.

7.2 Functional Block Diagram

PSRR

Boost

Current

Limit

IN

OUT

Charge

Pump

BIAS

Active

R_NR/SS= 250 kW

Discharge

0.8-V

V_REF

+

Error

Amp

œ

I_NR/SS

SNS

FB

NR/SS

200 pF

R₁= 2×R = 12.1 kW

1×R = 6.05 kW

2×R = 12.1 kW

4×R = 24.2 kW

8×R = 48.4 kW

16×R = 96.8 kW

32×R = 193.6 kW

1.6 V

Internal

Controller

800 mV

400 mV

200 mV

100 mV

50 mV

UVLO

Circuits

ANY-OUT Network

Thermal

Shutdown

PG

œ

0.88 x V_REF

+

EN

GND

NOTE: For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual

resistance may vary significantly from the numbers listed.

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7.3 Feature Description

7.3.1 Voltage Regulation Features

7.3.1.1 DC Regulation

An LDO functions as a class-B amplifier in which the input signal is the internal reference voltage (V_REF), as

shown in Figure 46. V_REFis designed to have a very low bandwidth at the input to the error amplifier through the

use of a low-pass filter (V_NR/SS).

As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes

from the combination of the output capacitor and pass element. The pass element presents a high input

impedance to the source voltage when operating as a current source. A positive LDO can only source current

because of the class-B architecture.

This device achieves a maximum of 0.75% output voltage accuracy primarily because of the high-precision band-

gap voltage (V_BG) that creates V_REF. The low dropout voltage (V_DO) reduces the thermal power dissipation

required by the device to regulate the output voltage at a given current level, which improves system efficiency.

These features combine to make this device a good approximation of an ideal voltage source.

V_IN

To Load

R₁

V_REF

R₂

GND

NOTE: V_OUT= V_REF× (1 + R₁/ R₂).

Figure 46. Simplified Regulation Circuit

7.3.1.2 AC and Transient Response

The LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the output

current (load transient) resulting from the LDO high-input impedance and low output-impedance across

frequency. This same capability also means that the LDO has a high power-supply rejection ratio (PSRR) and,

when coupled with a low internal noise-floor (V_n), the LDO approximates an ideal power supply in ac (small-

signal) and large-signal conditions.

The choice of external component values optimizes the small- and large-signal response. The NR/SS capacitor

(C_NR/SS) and feed-forward capacitor (C_FF) reduce the device noise floor and improve PSRR; see Optimizing

Noise and PSRR for more information on optimizing the noise and PSRR performance.

7.3.2 System Start-Up Features

In many different applications, the power-supply output must turn on within a specific window of time to either

ensure proper operation of the load or to minimize the loading on the input supply or other sequencing

requirements. The LDO start-up is well-controlled and user-adjustable, solving the demanding requirements

faced by many power-supply design engineers in a simple fashion.

7.3.2.1 Programmable Soft Start (NR/SS)

Soft start directly controls the output start-up time and indirectly controls the output current during start-up (inrush

current).

The external capacitor at the NR/SS pin (C_NR/SS) sets the output start-up time by setting the rise time of the

internal reference (V_NR/SS), as shown in Figure 47.

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Feature Description (continued)

SW

I_NR/SS

R_NR

V_REF

+

C_NR/SS

GND

œ

V_FB

Figure 47. Simplified Soft-Start Circuit

7.3.2.2 Internal Sequencing

Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of

the high power levels inherent in a PDN, and the variations between all of the supplies. The LDO turnon and

turnoff time is set by the enable circuit (EN) and undervoltage lockout circuits (UVLO_1,2(IN)and UVLO_BIAS), as

shown in Figure 48 and Table 2.

EN

Internal Enable

UVLO_BIAS

Control

UVLO_1,2(IN)

Figure 48. Simplified Turnon Control

Table 2. Internal Sequencing Functionality Table

ENABLE

STATUS

ACTIVE

DISCHARGE

INPUT VOLTAGE

BIAS VOLTAGE

_BIAS≥ V_UVLO(BIAS)

LDO STATUS

POWER GOOD

EN = 1

EN = 0

On

Off

On

PG = 1 when V_OUT≥ V_IT(PG)

V

V_IN≥ V_{UVLO_1,2(IN)}

V_BIAS< V_UVLO(BIAS)

V_HYS(BIAS)

+

Off

PG = 0

EN = don't

care

(1)

V_IN< V_{UVLO_1,2(IN)}

V_HYS1,2(IN)

–

On

BIAS = don't care

Off

IN = don't care

V_BIAS≥ V_UVLO(BIAS)

(1) The active discharge remains on as long as V_INor V_BIASprovides enough headroom for the discharge circuit to function.

7.3.2.2.1 Enable (EN)

The enable signal (V_EN) is an active-high digital control that enables the LDO when the enable voltage is past the

rising threshold (V_EN≥ V_IH(EN)) and disables the LDO when the enable voltage is below the falling threshold (V_EN

≤ V_IL(EN)). The exact enable threshold is between V_IH(EN)and V_IL(EN)because EN is a digital control. Connect EN

to V_INif enable functionality is not desired.

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7.3.2.2.2 Undervoltage Lockout (UVLO) Control

The UVLO circuits respond quickly to glitches on IN or BIAS and attempts to disable the output of the device if

either of these rails collapse.

The local input capacitance prevents severe brownouts in most applications; see Undervoltage Lockout (UVLO)

for more details.

7.3.2.2.3 Active Discharge

When EN or UVLO is low, the device connects a resistor of several hundred ohms from V_OUTto GND,

discharging the output capacitance.

Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops

below the targeted output voltage. Current flows from the output to the input (reverse current) when V_OUT> V_IN,

which can cause damage to the device (when V_OUT> V_IN+ 0.3 V); see Reverse Current for more details.

7.3.2.3 Power-Good Output (PG)

The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals

when the output nears its nominal value. PG can be used to signal other devices in a system when the output

voltage is near, at, or above the set output voltage (V_OUT(nom)). A simplified schematic is shown in Figure 49.

The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high.

The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.

Using a large feed-forward capacitor (C_FF) delays the output voltage and, because the PG circuit monitors the FB

pin, the PG signal can indicate a false positive. A simple solution to this scenario is to use an external voltage

detector device, such as the TPS3890; see Feed-Forward Capacitor (C_FF) for more information.

V_PG

V_BG

V_IN

œ

+

V_FB

GND

UVLO_BIAS

UVLO_IN

EN

GND

Figure 49. Simplified PG Circuit

7.3.3 Internal Protection Features

In many applications, fault events can occur that damage devices in the system. Short circuits and excessive

heat are the most common fault events for power supplies. The TPS7A85A implements circuitry to protect the

device and the load during these events. Continuously operating in these fault conditions or above a junction

temperature of 125°C is not recommended because the long-term reliability of the device is reduced.

7.3.3.1 Foldback Current Limit (I_CL

)

The internal current limit circuit protects the LDO against high load-current faults or shorting events. During a

current-limit event, the LDO sources constant current. As a result, the output voltage falls with decreased load

impedance. Thermal shutdown can activate during a current limit event because of the high power dissipation

typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to

the input and load. Continuous operation in current limit is not recommended.

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7.3.3.2 Thermal Protection (T_sd)

The thermal shutdown circuit protects the LDO against excessive heat in the system, resulting from current limit

or high ambient temperature.

The output of the LDO turns off when the LDO temperature (junction temperature, T_J) exceeds the rising thermal

shutdown temperature. The output turns on again after T_Jdecreases below the falling thermal shutdown

temperature.

A high power dissipation across the device, combined with a high ambient temperature (T_A), can cause T_Jto be

greater than or equal to T_sd, which triggers the thermal shutdown and causing the output to fall to 0 V. The LDO

can cycle on and off when thermal shutdown is reached under these conditions.

7.4 Device Functional Modes

Table 3 lists a comparison between the regulation and disabled operation.

Table 3. Device Functional Modes Comparison

PARAMETER

EN

OPERATING

MODE

V_IN

V_BIAS

I_OUT

T_J

V_IN> V_OUT(nom)

V_DO

+

Regulation⁽¹⁾

Disabled⁽³⁾

V

_BIAS≥ V_UVLO(BIAS)

V_EN> V_IH(EN)

V_EN< V_IL(EN)

I_OUT< I_CL

T_J≤ T_J(maximum)

T_J> T_sd

(2)

V_IN< V_{UVLO_1,2(IN)}

V_BIAS< V_UVLO(BIAS)

Current limit

operation

I_OUT≥ I_CL

(1) All table conditions must be met.

(2) V_BIASonly required for V_IN< 1.4 V.

(3) The device is disabled when any condition is met.

7.4.1 Regulation

The device regulates the output to the nominal output voltage when all the conditions in Table 3 are met.

7.4.2 Disabled

When disabled, the pass device is turned off, the internal circuits are shut down, and the output voltage is

actively discharged to ground by an internal resistor from the output to ground. See Active Discharge for

additional information.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

8.1.1 External Component Selection

8.1.1.1 Adjustable Operation

The TPS7A85A can be used with the internal ANY-OUT network or by using external resistors. Using the ANY-

OUT network allows the TPS7A85A to be programmed from 0.8 V to 3.95 V. For output voltage range greater

than 3.95 V and up to 5.1 V, external resistors must be used. This configuration is referred to as the adjustable

configuration of the TPS7A85A throughout the data sheet. The output voltage is set by two resistors, as shown in

Figure 50. 0.75% accuracy can be achieved with an external BIAS for V_INlower than 2.2 V.

C_BIAS

Optional

Bias

Supply

Input

Supply

BIAS

IN

C_IN

PG

OUT

SNS

FB

EN

R_PG

NR/SS

To Load

C_OUT

C_NR/SS

TPS7A85A

1.6 V

C_FF

R₁

800 mV

400 mV

200 mV

100 mV

50 mV

R₂

GND

Figure 50. Adjustable Operation

R₁and R₂can be calculated for any output voltage range using . This resistive network must provide a current

equal to or greater than 5 μA for dc accuracy. TI recommends using an R₁approximately 12 kΩ to optimize the

noise and PSRR.

V_OUT= V_NR/SS´(1+ R₁/ R₂)

(1)

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Application Information (continued)

Table 4 lists the resistor combinations required to achieve several common rails using standard 1%-tolerance

resistors.

Table 4. Recommended Feedback-Resistor Values⁽¹⁾

TARGETED OUTPUT

FEEDBACK RESISTOR VALUES

CALCULATED OUTPUT

VOLTAGE

(V)

VOLTAGE

(V)

R₁(kΩ)

R₂(kΩ)

0.9

0.95

1

12.4

12.1

12.4

12.1

11.8

12.1

11.8

12.4

100

66.5

49.9

33.2

24.9

14.3

10

0.899

0.949

0.999

1.099

1.198

1.494

1.798

1.89

1.1

1.2

1.5

1.8

1.9

2.5

2.85

3

8.87

5.9

2.48

4.75

4.42

3.74

3.48

2.55

2.37

2.838

2.990

3.324

3.582

4.502

4.985

3.3

3.6

4.5

5

(1) R₁is connected from OUT to FB; R₂is connected from FB to GND.

8.1.1.2 ANY-OUT Programmable Output Voltage

The TPS7A85A can use external resistors or the internally-matched ANY-OUT feedback resistor network to set

output voltage. The ANY-OUT resistors are accessible through pin 2 and pins 5 to 11 and program the regulated

output voltage. Each pin can be connected to ground (active), left open (floating), or connected to SNS. ANY-

OUT programming is set by as the sum of the internal reference voltage (V_NR/SS= 0.8 V) plus the accumulated

sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7),

400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 5 lists the voltage values associated with each active pin

setting for reference. By leaving all program pins open or floating, the output is programmed to the minimum

possible output voltage equal to V_FB

.

V_OUT= V_NR/SS+ (å ANY - OUT Pins to Ground)

(2)

Table 5. ANY-OUT Programmable Output Voltage (RGR Package)

ANY-OUT PROGRAM PINS (ACTIVE LOW)

Pin 5 (50mV)

ADDITIVE OUTPUT VOLTAGE LEVEL

50 mV

100 mV

200 mV

400 mV

800 mV

1.6 V

Pin 6 (100mV)

Pin 7 (200mV)

Pin 9 (400mV)

Pin 10 (800mV)

Pin 11 (1.6V)

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Table 6 lists target output voltages and corresponding pin settings when the ANY-OUT pins are only tied to

ground or left floating. The voltage setting pins have a binary weight, so the output voltage can be programmed

to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground. There are several alternative

ways to set the output voltage. The program pins can be driven using external general-purpose input or output

pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired by the given layout of the

printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable operation, the output voltage is

set according to except that R₁and R₂are internally integrated and matched for higher accuracy. Tying any of

the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by decreasing the value

of R₁. See Increasing ANY-OUT Resolution for LILO Conditions for additional information.

V_OUT= V_NR/SS´(1+ R₁/ R₂)

(3)

NOTE

For output voltages greater than 3.95 V, use a traditional adjustable configuration (see

Adjustable Operation).

Table 6. User-Configurable Output Voltage Settings

V_OUT(NOM)

(V)

V_OUT(NOM)

(V)

50 mV 100 mV 200 mV 400 mV 800 mV

1.6 V

50 mV 100 mV 200 mV 400 mV 800 mV 1.6 V

0.8

0.85

0.9

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

2.4

2.45

2.5

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

0.95

1

2.55

2.6

1.05

1.1

2.65

2.7

1.15

1.2

2.75

2.8

1.25

1.3

2.85

2.9

1.35

1.4

2.95

3

1.45

1.5

3.05

3.1

1.55

1.6

3.15

3.2

1.65

1.7

3.25

3.3

1.75

1.8

3.35

3.4

1.85

1.9

3.45

3.5

1.95

2

3.55

3.6

2.05

2.10

2.15

2.2

3.65

3.7

3.75

3.8

2.25

2.3

3.85

3.9

2.35

3.95

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8.1.1.3 ANY-OUT Operation

Considering the use of the ANY-OUT internal network where the unit resistance of 1R, as shown in () is equal to

6.05 kΩ, the output voltage is set by grounding the appropriate control pins as shown in Figure 51. When

grounded, all control pins add a specific voltage on top of the internal reference voltage (V_NR/SS= 0.8 V). The

output voltage can be calculated by and . Figure 51 and Figure 52 show a 0.9-V output voltage (respectively) that

show an example of the circuit usage with and without bias voltage.

C_BIAS

Bias

Supply

EN

V_IN

BIAS

IN

C_IN

PG

OUT

SNS

FB

R_PG

3.3 V_OUT

To Load

NR/SS

C_OUT

C_NR/SS

TPS7A85A

1.6 V

C_FF

800 mV

400 mV

200 mV

100 mV

50 mV

GND

Figure 51. ANY-OUT Configuration Circuit

(3.3-V Output, No External Bias)

V_OUT(nom)= V_NR/SS+1.6 V + 0.8 V + 0.1 V = 0.8 V +1.6 V + 0.8 V + 0.1 V = 3.3 V

(4)

C_BIAS

Bias

Supply

1.4 V_IN

BIAS

IN

C_IN

PG

OUT

SNS

FB

EN

R_PG

0.9 V_OUT

To Digital

Load

NR/SS

C_OUT

C_NR/SS

TPS7A85A

1.6 V

C_FF

800 mV

400 mV

200 mV

100 mV

50 mV

ANYOUT

Used to set

voltage

GND

Figure 52. ANY-OUT Configuration Circuit

(0.9-V Output with Bias)

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V_OUT(nom)= V_NR/SS+ 0.1 V = 0.8 V + 0.1 V = 0.9 V

(5)

8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions

As with the adjustable operation, the output voltage is set according to Equation 5. However, R₁and R₂are

internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the

resolution of the internal feedback network by decreasing the value of R₁. One of the more useful pin

combinations is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range.

The new ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. Table 7 lists the new additive output

voltage levels.

Table 7. ANY-OUT Programmable Output Voltage With 800 mV Tied to SNS (RGR Package)

ANY-OUT PROGRAM PINS (ACTIVE LOW)

Pin 5 (50mV)

ADDITIVE OUTPUT VOLTAGE LEVEL

25 mV

50 mV

100 mV

200 mV

800 V

Pin 6 (100mV)

Pin 7 (200mV)

Pin 9 (400mV)

Pin 11 (1.6V)

8.1.1.5 Current Sharing

Current sharing is possible through the use of external operational amplifiers. For more details, see 6A Current-

Sharing Dual LDO.

8.1.1.6 Recommended Capacitor Types

The TPS7A85A is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

input, output, and noise-reduction pin (NR/SS). Multilayer ceramic capacitors are the industry standard for these

types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that use

X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature,

whereas the use of Y5V-rated capacitors is not recommended because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature; derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein

account for a capacitance derating of approximately 50%, but at high V_INand V_OUTconditions (for example, V_IN

5.6 V to V_OUT= 5.1 V) the derating can be greater than 50% and must be taken into consideration.

=

8.1.1.7 Input and Output Capacitor Requirements (C_INand C_OUT

)

The TPS7A85A is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or

greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. TI

recommends using a capacitor with a value of at least 47 µF at the input to minimize input impedance. Place the

input and output capacitors as close as possible to the respective input and output pins to minimize trace

parasitic. If the trace inductance from the input supply to the TPS7A85A is high, a fast current transient can

cause V_INto ring above the absolute maximum voltage rating and damage the device. This situation can be

mitigated by additional input capacitors to dampen the ringing and to keep it below the device absolute maximum

ratings.

A combination of multiple output capacitors boosts the high-frequency PSRR as shown in several of the PSRR

curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized,

10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes

PSRR for the frequency range of 400 kHz to 700 kHz, a typical range for dc-dc supply switching frequency. This

47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage

configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a

voltage derating of approximately 60% to 80% at 5.15 V, so the addition of the two 10-µF capacitors ensures that

the capacitance is at or above 25 µF.

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8.1.1.8 Feed-Forward Capacitor (C_FF)

Although a feed-forward capacitor (C_FF) from the FB pin to the OUT pin is not required to achieve stability, a

10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher

capacitance C_FFcan be used; however, the start-up time is longer, and the PG signal can incorrectly indicate that

the output voltage is settled. For a detailed description, see Pros and Cons of Using a Feed-Forward Capacitor

with a Low Dropout Regulator.

8.1.1.9 Noise-Reduction and Soft-Start Capacitor (C_NR/SS

)

The TPS7A85A features a programmable, monotonic, voltage-controlled soft-start that is set with an external

capacitor (C_NR/SS).The use of an external C_NR/SSis highly recommended, especially to minimize inrush current

into the output capacitors. This soft-start eliminates power-up initialization problems when powering field-

programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled

voltage ramp of the output reduces peak inrush current during start-up, which minimizes start-up transients to the

input power bus.

To achieve a monotonic start-up, the TPS7A85A error amplifier tracks the voltage ramp of the external soft-start

capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start

charging current (I_NR/SS), the soft-start capacitance (C_NR/SS), and the internal reference (V_NR/SS). Soft-start ramp

time can be calculated with Equation 6:

t_SS= (V_NR/SS´C_NR/SS) / I_NR/SS

(6)

I_NR/SSis shown in Electrical Characteristics.

The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that

minimizes the noise from the reference. The reference and noise are amplified by the error amplifier and so the

C_NR/SSreduces the overall noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated

with Equation 7. The typical value of R_NR/SSis 250 kΩ. Increasing the C_NR/SScapacitor has a dominant effect on

the output noise at higher output voltages because of the larger gain that is present on the error amplifier. For

low-noise applications, TI recommends using a 10-nF to 1-µF C_NR/SS. A larger C_NR/SShas a higher leakage

current and as a result, the start-up time may be higher than the expected soft-start time calculated with

Equation 6.

f_cutoff= 1/ (2´ p´R_NR/SS´C_NR/SS

8.1.2 Start-Up

8.1.2.1 Circuit Soft-Start Control (NR/SS)

)

(7)

Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an

external capacitor (C_NR/SS). This soft-start eliminates power-up initialization problems when powering field-

programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled

voltage ramp of the output reduces peak inrush current during start-up, which minimizes start-up transients to the

input power bus.

The output voltage (V_OUT) rises proportionally to V_NR/SSduring start-up as the LDO regulates so that the feedback

voltage equals the NR/SS voltage (V_FB= V_NR/SS). The time required for V_NR/SSto reach the nominal value

determines the rise time of V_OUT(start-up time).

Not using a noise-reduction capacitor on the NR/SS pin may result in an output voltage overshoot of

approximately 10%. Using a capacitor on the NR/SS pin minimizes the overshoot.

lists the soft-start charging current values.

8.1.2.1.1 Inrush Current

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current consists of the

sum of load current and the current that charges the output capacitor. This current is difficult to measure because

the input capacitor must be removed, which is not recommended. This soft-start current can be estimated by

Equation 8:

≈

∆

«

’

÷

◊

C

ì dV_OUT(t)

dt

V_OUT(t)

R_LOAD

≈

’

OUT

I_OUT(t) =

+

∆

«

÷

◊

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where:

•

V_OUT(t) is the instantaneous output voltage of the turnon ramp

dV_OUT(t) / dt is the slope of the V_OUTramp

R_LOADis the resistive load impedance

(8)

8.1.2.2 Undervoltage Lockout (UVLO)

The UVLO circuits ensure that the device stays disabled before the input or bias supplies reach the minimum

operational voltage range, and ensures that the device properly shuts down when the input or bias supply

collapses.

Figure 53 and Table 8 show one of the UVLO circuits triggered by various input voltage events, assuming that

V_EN≥ V_IH(EN).

UVLO Rising Threshold

UVLO Hysteresis

V_IN

C

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

Figure 53. Typical UVLO Operation

Table 8. Typical UVLO Operation Description

REGION

EVENT

V_OUTSTATUS

COMMENT

Turnon, V_IN≥ V_{UVLO_1, 2(IN)}and

A

B

Off

On

Start-up

V_BIAS≥ V_UVLO(BIAS)

Regulation

Regulates to target V_OUT

Brownout, V_IN≥ V_{UVLO_1, 2(IN)}

–

C

D

V_{HYS_1, 2(IN)}

or V_BIAS≥ V_UVLO(BIAS)– V_HYS(BIAS)

On

The output can fall out of regulation but the device is still enabled.

Regulation

Regulates to target V_OUT

The device is disabled and the output falls because of the load and

active discharge circuit. The device is reenabled when the UVLO

fault is removed when either the IN or BIAS UVLO rising threshold

is reached by the input or bias voltage and a normal start-up then

follows.

Brownout, V_IN< V_{UVLO_1, 2(IN)}

V_{HYS_1, 2(IN)}

or V_BIAS≥ V_UVLO(BIAS)– V_HYS(BIAS)

–

E

Off

F

Regulation

On

Off

Regulates to target V_OUT

Turnoff, V_IN< V_{UVLO_1, 2(IN)}

V_{HYS_1, 2(IN)}

–

G

The output falls because of the load and active discharge circuit.

or V_BIAS< V_UVLO(BIAS)– V_HYS(BIAS)

Similar to many other LDOs with this feature, the UVLO circuits take a few microseconds to fully assert. During

this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time;

however, the UVLO circuits do not have enough stored energy to fully discharge the internal circuits inside of the

device. When the UVLO circuits are not given enough time to fully discharge the internal nodes, the outputs are

not fully disabled.

The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall

time of the input supply when operating near the minimum V_IN.

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8.1.2.3 Power-Good (PG) Function

The PG circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The PG

circuit asserts whenever FB, V_IN, or EN are below the thresholds. The PG operation versus the output voltage is

shown in Figure 54, which is listed in Table 9.

PG Rising Threshold

PG Falling Threshold

V_OUT

E

C

PG

tAt

tBt

tDt

tFt

tGt

Figure 54. Typical PG Operation

Table 9. Typical PG Operation Description

REGION

EVENT

Turnon

PG STATUS

FB VOLTAGE

A

B

C

D

E

F

0

V_FB< V_IT(PG)+ V_HYS(PG)

Regulation

Hi-Z

0

Output voltage dip

Regulation

V_FB≥ V_IT(PG)

Output voltage dip

Regulation

V_FB< V_IT(PG)

_FB≥ V_IT(PG)

V_FB< V_IT(PG)

Hi-Z

0

V

G

Turnoff

The PG pin is open-drain and connects a pullup resistor to an external supply, enabling other devices to receive

power good as a logic signal that can be used for sequencing. Take care to ensure that the external pullup

supply voltage results in a valid logic signal for the receiving device or devices.

To ensure proper operation of the PG circuit, the pullup resistor value must be from 10 kΩ and 100 kΩ. The

lower limit of 10 kΩ results from the maximum pulldown strength of the PG transistor, and the upper limit of 100

kΩ results from the maximum leakage current at the PG node. If the pullup resistor is outside of this range, then

the PG signal may not read a valid digital logic level.

Using a large C_FFwith a small C_NR/SScauses the PG signal to incorrectly indicate that the output voltage has

settled during turnon. The C_FFtime constant must be greater than the soft-start time constant to ensure proper

operation of the PG during start-up. For a detailed description, see Pros and Cons of Using a Feed-Forward

Capacitor with a Low Dropout Regulator.

The state of PG is only valid when the device operates above the minimum supply voltage. During short

brownout events and at light loads, PG does not assert because the output voltage (and as a result, V_FB) is

sustained by the output capacitance.

8.1.3 AC and Transient Performance

LDO ac performance includes power-supply-rejection ratio, output-current transient response, and output noise.

These metrics are primarily a function of open-loop gain, bandwidth, and phase margin that control the closed-

loop input and output impedance of the LDO. The output noise is primarily a result of the reference and error

amplifier noise.

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8.1.3.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control loop rejects signals from V_INto V_OUTacross the frequency

spectrum (usually 10 Hz to 10 MHz). Equation 9 gives the PSRR calculation as a function of frequency for the

input signal (V_IN(f)) and output signal (V_OUT(f)).

≈

’

V

ƒ

_IN( )

PSRR dB = 20Log

(

)

∆

÷

10

V_OUT

ƒ

( )

«

◊

(9)

Although PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.

A simplified diagram of PSRR versus frequency is shown in Figure 55.

PSRR Boost Circuit Improves PSRR in This Region

Band-Gap

RC Filter

Error Amplifier,

Flat-Gain Region

Error Amplifier,

Gain Roll-Off

Output Capacitor

|Z_COUT| Decreasing

Output Capacitor

|Z_COUT| Increasing

Band Gap

Sub 10 Hz

10 Hzœ1 MHz

100 kHz +

Frequency (Hz)

Figure 55. Power-Supply Rejection Ratio Diagram

An LDO is often employed not only as a dc-dc regulator, but provides exceptionally clean power-supply voltages

that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for the

TPS7A85A.

The TPS7A85A features an innovative circuit to boost the PSRR from 200 kHz to 1 MHz; see . To achieve the

maximum benefit of this PSRR boost circuit, TI recommends using a capacitor with a minimum impedance in the

100-kHz to 1-MHz band.

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8.1.3.2 Output Voltage Noise

The TPS7A85A is designed for system applications where minimizing noise on the power-supply rail is critical to

system performance. For example, the TPS7A85A can be used in a phase-locked loop (PLL)-based clocking

circuit can be used for minimum phase noise, or in test and measurement systems where small power-supply

noise fluctuations reduce system dynamic range.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This

noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,

thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower

frequencies as a function of 1/f). Figure 56 shows a simplified output voltage noise density plot versus frequency.

Charge Pump Spurs

Wide-Band Noise

Integrated Noise

From Band-Gap and Error Amplifier

Measurement Noise Floor

Frequency (Hz)

Figure 56. Output Voltage Noise Diagram

For further details, see the How to Measure LDO Noise white paper.

8.1.3.3 Optimizing Noise and PSRR

The ultra-low noise floor and PSRR of the device can be improved in several ways, as listed in Table 10.

Table 10. Effect of Various Parameters on AC Performance⁽¹⁾⁽²⁾

NOISE

PSRR

PARAMETER

LOW-

MID-

HIGH-

LOW-

MID-

HIGH-

FREQUENCY

FREQUENCY FREQUENCY

C_NR/SS

C_FF

+++

No effect

+++

++

+

No effect

+

++

No effect

+

+++

+

+++

+

+++

+

C_OUT

No effect

+++

++

V_IN– V_OUT

PCB layout

+

+++

++

+

+++

(1) The number of + symbols indicate the improvement in noise or PSRR performance by increasing the parameter value.

(2) Shaded cells indicate the simplest improvement to noise or PSRR performance.

The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that

filters out the noise from the reference before being gained up with the error amplifier, which minimizes the

output voltage noise floor. The LPF is a single-pole filter, and the cutoff frequency can be calculated with

Equation 10. The typical value of R_NR/SSis 250 kΩ. The effect of the C_NR/SScapacitor increases when V_OUT(nom)

increases because the noise from the reference is gained up when the output voltage increases. For low-noise

applications, TI recommends a 10-nF to 10-µF C_NR/SS

.

f_cutoff= 1/ (2´ p´R_NR/SS´C_NR/SS

)

(10)

The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-

forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing

out the loop bandwidth, which improves mid-band PSRR.

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A larger C_OUTor multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing

the high-frequency output impedance of the power supply.

Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the

internal circuits. However, a high power dissipation across the die increases the output noise because of the

increase in junction temperature.

Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and

isolating V_OUTat high frequencies.

Table 11 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions

with an input voltage of 5.5 V and a load current of 4 A. The 5-V output is selected as a worst-case nominal

operation for output voltage noise.

Table 11. Output Noise Voltage at a 5-V Output

OUTPUT VOLTAGE NOISE

C_NR/SS(nF)

C_FF(nF)

C_OUT(µF)

(µV_RMS

11.7

7.7

)

10

47 || 10 || 10

1000

100

6

100

10

7.4

5.8

100

1000

8.1.3.3.1 Charge Pump Noise

The device internal charge pump generates a minimal amount of noise, as shown in Figure 57.

Using a bias rail minimizes the internal charge-pump noise when the internal voltage is clamped, which reduces

the overall output noise floor.

The high-frequency components of the output voltage noise density curve are filtered out in most applications by

using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the

load input capacitors forms a pi-filter, which further reduces the high-frequency noise contribution.

0.5

V_IN= 1.5 V, 4.5 mV_RMS

V_IN= 1.4 V, V_BIAS= 5.0 V, 4.5 mV_RMS

0.3

0.2

0.1

0.07

0.05

0.03

0.02

0.01

0.007

0.005

0.003

0.002

0.001

1000000

2000000

3000000

4000000

5000000

6000000

7000000

8000000

9000000

1E+7

Frequency (Hz)

Figure 57. Charge Pump Noise

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8.1.3.4 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, where

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in

Figure 58 are further described in this section and are listed in Table 12. Regions A, E, and H are where the

output voltage is in steady-state.

V_OUTx

B

F

A

C

D

E

G

H

I_OUTx

Figure 58. Load Transient Waveform

Table 12. Load Transient Waveform Description

REGION

DESCRIPTION

COMMENT

A

B

Regulation

Output current ramping

Initial voltage dip is a result of the depletion of the output capacitor charge.

Recovery from the dip results from the LDO increasing its sourcing current, and leads

to output voltage regulation.

C

LDO responding to transient

At high load currents the LDO takes some time to heat up. During this time the output

voltage changes slightly.

D

E

F

Reaching thermal equilibrium

Regulation

Initial voltage rise results from the LDO sourcing a large current, and leads to the

output capacitor charge to increase.

Output current ramping

Recovery from the rise results from the LDO decreasing its sourcing current in

combination with the load discharging the output capacitor.

G

H

LDO responding to transient

Regulation

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The transient response peaks (V_OUT(max)and V_OUT(min)) are improved by using more output capacitance; however,

using more output capacitance slows down the recovery time (W_riseand W_fall). Figure 59 shows these parameters

during a load transient with a given pulse duration (PW) and current levels (I_OUT(LO)and I_OUT(HI)).

V_OUT(max)

W_rise

V_OUT

W_fall

V_OUT(min)

I_OUT(HI)

PW

I_OUT

I_OUT(LO)

t_rise

t_fall

Figure 59. Simplified Load Transient Waveform

8.1.4 DC Performance

8.1.4.1 Output Voltage Accuracy (V_OUT

)

The device features an output voltage accuracy of 0.75% maximum with BIAS that includes the errors introduced

by the internal reference, load regulation, line regulation, and operating temperature as shown in the . Output

voltage accuracy specifies minimum and maximum output voltage error relative to the expected nominal output

voltage stated as a percent.

8.1.4.2 Dropout Voltage (V_DO

)

Generally, the dropout voltage refers to the minimum voltage difference between the input and output voltage

(V_DO= V_IN– V_OUT) that is required for regulation. When V_INdrops below the required V_DOfor the given load

current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is

proportional to the output current because the device is operating as a resistive switch, as shown in Figure 60.

V_DO

I_OUT

Figure 60. Dropout Voltage versus Output Current

Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect

to V_INon this device because of the internal charge pump. Dropout voltage increases exponentially when the

input voltage approaches the maximum operating voltage.

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8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation

Some applications can have transients that place the LDO into dropout, such as slower ramps on V_INfor start-up

or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.

A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in

the right range, as shown in Figure 61. This condition is simply avoided by using an enable signal or by

increasing the soft-start time with C_SS/NR

.

Input Voltage

Response time for

LDO to get back into

regulation.

Load current discharges

output voltage.

V_IN= V_OUT(nom)+ V_DO

Output Voltage

Dropout

V_OUT= V_IN- V_DO

Output Voltage in

normal regulation.

Time

Figure 61. Start-Up Into Dropout

8.1.5 Sequencing Requirements

There is no sequencing requirement between the BIAS, IN, and EN pins in the TPS7A85A.

8.1.6 Negatively Biased Output

The TPS7A85A output can be negatively biased to the absolute maximum rating without effecting start-up

condition.

8.1.7 Reverse Current

As with most LDOs, excessive reverse current can damage this device.

Reverse current is current that flows through the body diode on the pass element instead of the normal

conducting channel. This current flow, at high enough magnitudes, degrades long-term reliability of the device

resulting from risks of electromigration and excess heat being dissipated across the device. If the current flow

gets high enough, a latch-up condition can be entered.

This section outlines conditions where excessive current can occur, all of which can exceed the absolute

maximum rating of V_OUT> V_IN+ 0.3 V:

•

If the device has a large C_OUTand the input supply collapses quickly with little or no load current,

The output is biased when the input supply is not established, or

The output is biased above the input supply.

If excessive reverse current flow is expected in the application, then external protection must be used to protect

the device. Figure 62 shows one approach of protecting the device.

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Schottky Diode

Internal Body Diode

IN

OUT

TI Device

C_OUT

C_IN

GND

Figure 62. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.8 Power Dissipation (P_D)

Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on

the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must

be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. P_Dcan be approximated using Equation 11:

P_D= (V – V_OUT)´I_OUT

IN

(11)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. The minimum input to output voltage differential is obtained by properly selecting the system

voltage rails. The low dropout of the device allows for maximum efficiency across a wide range of output

voltages.

The main heat conduction path for the device is through the thermal pad on the package. As a result, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance

(R_θJA) of the combined PCB, device package, and the temperature of the ambient air (T_A), according to

Equation 12. The equation is rearranged for output current in Equation 13.

T_J= T_A+ R_qJA´P_D

(12)

I

_OUT= (T_J- T_A) / R_qJA´(V – V_OUT)

IN

(13)

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, which varies according to the total copper area, copper weight, and location of the planes.

The R_θJArecorded in the v table is determined by the JEDEC standard, PCB, and copper-spreading area, and is

only used as a relative measure of package thermal performance. For a well-designed thermal layout, R_θJAis the

sum of the VQFN package junction-to-case (bottom) thermal resistance (R_θJCbot) plus the thermal resistance

contribution by the PCB copper.

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8.1.8.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not referencing thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are shown in and are used in accordance with Equation 14.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

where:

•

P_Dis the power dissipated as explained in

T_Tis the temperature at the center-top of the device package, and

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(14)

8.1.8.2 Recommended Area for Continuous Operation (RACO)

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator can be separated into the

following parts, as shown in Figure 63:

•

Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output

(V_IN– V_OUT) at a given output current level; see Dropout Voltage (V_DO) for more details.

Limited by rated output current: The rated output current limits the maximum recommended output current

level. Exceeding this rating causes the device to fall out of specification.

Limited by thermals: The shape of the slope is calculated by Equation 14. The slope is nonlinear because the

junction temperature of the LDO is controlled by the power dissipation across the LDO. As a result, when

V_IN– V_OUTincreases, the output current must decrease to ensure that the rated junction temperature of the

device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and reduces

long-term reliability.

•

Limited by V_INrange: The rated input voltage range governs both the minimum and maximum of V_IN– V_OUT.

Output Current Limited

by Dropout

Rated Output

Current

Output Current Limited by Thermals

Limited by

Minimum V_IN

Limited by

Maximum V_IN

V_INœ V_OUT(V)

Figure 63. Continuous Operation Slope Region Description

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Figure 64 to Figure 69 show the recommended area of operation curves for this device on a JEDEC-standard,

high-K board with a R_θJA= 43.4°C/W, as shown in .

6

5

4

3

2

1

0

6

5

4

3

2

1

0

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

V_IN- V_OUT(V)

D0fi0g15

D0fi0g16

Figure 64. Recommended Area for Continuous Operation

for V_OUT= 0.9 V

Figure 65. Recommended Area for Continuous Operation

for V_OUT= 1.2 V

6

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

5

4

3

2

1

0

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

V_IN- V_OUT(V)

D0fi0g16

Figure 66. Recommended Area for Continuous Operation

for V_OUT= 1.8 V

Figure 67. Recommended Area for Continuous Operation

for V_OUT= 2.5 V

6

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

5

4

3

2

1

0

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

V_IN- V_OUT(V)

D0fi0g16

Figure 68. Recommended Area for Continuous Operation

for V_OUT= 3.3 V

Figure 69. Recommended Area for Continuous Operation

for V_OUT= 5 V

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8.2 Typical Applications

8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions

The TPS7A85A device uses the ANY-OUT configuration to regulate a 4-A load requiring good PSRR at high

frequency with low-noise at 0.9 V using a 1.2-V input voltage and a 5-V bias supply. The schematic for this

typical application circuit is shown in Figure 70.

C_BIAS

Bias

Supply

1.4 V_IN

BIAS

IN

C_IN

PG

OUT

SNS

FB

EN

R_PG

0.9 V_OUT

To Digital

Load

NR/SS

C_OUT

C_NR/SS

TPS7A85A

1.6 V

C_FF

800 mV

400 mV

200 mV

100 mV

50 mV

ANYOUT

Used to set

voltage

GND

Figure 70. TPS7A85A Typical Application

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 13 as the input parameters.

Table 13. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

1.4 V, ±3%, provided by the dc-dc converter switching at 500 kHz

Bias voltage

5 V, ±5%

Output voltage

0.9 V, ±1%

Output current

4 A (maximum), 100 mA (minimum)

RMS noise, 10 Hz to 100 kHz

PSRR at 500 kHz

Start-up time

< 10 µV_RMS

> 40 dB

< 25 ms

8.2.1.2 Detailed Design Procedure

At 4 A, the dropout of the TPS7A85A has 240-mV maximum dropout over temperature, and a result, a 400-mV

headroom is sufficient for operation over input and output voltage accuracy. The bias rail is provided for better

performance for the LILO conditions. The PSRR is greater than 40 dB in these conditions, and noise is less than

10 µV_RMS, as listed in Table 13.

The ANY-OUT internal resistor network is used for maximum accuracy.

The 100mV pin is grounded to achieve 0.9 V on the output. The voltage value of 100 mV is added to the 0.8-V

internal reference voltage for V_OUT(nom)equal to 0.9 V, as shown in Equation 15.

V_OUT(nom)= V_NR/SS+ 0.1 V = 0.8 V + 0.1 V = 0.9 V

(15)

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Input and output capacitors are selected in accordance with External Component Selection. Ceramic

capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the output

are selected.

To satisfy the required start-up time and still maintain low-noise performance, a 100-nF C_NR/SSis selected. This

value is calculated with Equation 16.

t_SS= (V_NR/SS´ C_NR/SS) / I_NR/SS

(16)

At the 4-A maximum load, the internal power dissipation is 2 W and corresponds to a 7°C junction temperature

rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient temperature, the

junction temperature is at 62°C. To further minimize noise, a feed-forward capacitance (C_FF) of 10 nF is selected.

8.2.1.3 Application Curves

1.2

1

10

7.5

5

50

25

0

Output Current

V_OUT= 0.9 V

V_OUT= 1.2 V

V_OUT= 1.8 V

0.8

0.6

0.4

0.2

0

V_EN

2.5

0

-25

-50

V_OUT, C_NR/SS= 0 nF

V_OUT, C_NR/SS= 10 nF

V_OUT, C_NR/SS= 47 nF

V_OUT, C_NR/SS= 100 nF

-0.2

0

0.5

1

1.5

2

0

5

10

15

20

25

30

35

40

45

50

Time (ms)

Figure 71. Output Load Transient Response

Figure 72. Output Start-Up Response

9 Power-Supply Recommendations

The TPS7A85A device is designed to operate from an input voltage supply range from 1.1 V to 6.5 V. If the input

supply is less than 1.4 V, then a bias rail of at least 3 V must be used. The input voltage range provides

adequate headroom for the device to have a regulated output. This input supply must be well-regulated. If the

input supply is noisy, additional input capacitors with low ESR may help improve output noise performance.

10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,

copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and

negatively affects system performance. The grounding and layout scheme shown in Figure 73 minimizes

inductive parasitics, and as a result, reduces load-current transients, minimizes noise, and increases circuit

stability.

TI recommends a ground reference plane embedded in the PCB itself or located on the bottom side of the PCB

opposite the components. This reference plane serves to ensure accuracy of the output voltage, shield noise,

and behaves similarly to a thermal plane to spread (or sink) heat from the LDO device when connected to the

thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.

Submit Documentation Feedback

39

Product Folder Links: TPS7A85A

TPS7A85A

SBVS313 –JUNE 2017

www.ti.com

10.2 Layout Example

Ground Plane for Thermal Relief and Signal

Ground

10

9

8

7

6

To PG Pullup Supply

PG Output

1.6V 11

BIAS

5

50mV

PG

C_BIAS

R_PG

To Bias Supply

To Signal Ground

Enable Signal

12

4

3

Thermal Pad

R₂

NR/SS 13

EN 14

FB

To Signal Ground

To Load

C_NR/SS

2

1

SNS

OUT

C_FFR₁

15

IN

16

18 19 20

17

Input Power Plane

Output Power Plane

C_IN

C_OUT

Power Ground Plane

Vias used for application purposes.

Figure 73. Example Layout

40

Submit Documentation Feedback

Product Folder Links: TPS7A85A

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jun-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A8500ARGRR

TPS7A8500ARGRT

VQFN

RGR

20

3000

250

330.0

180.0

12.4

3.75

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jun-2017

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A8500ARGRR

TPS7A8500ARGRT

VQFN

RGR

20

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGR 20

3.5 x 3.5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4228482/A

www.ti.com

PACKAGE OUTLINE

RGR0020A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.65

3.35

A

B

PIN 1 INDEX AREA

3.65

3.35

SIDE WALL

METAL THICKNESS

DIM A

1.0

0.8

OPTION 1

0.1

OPTION 2

0.2

C

SEATING PLANE

0.08 C

0.05

0.00

2X 2

(DIM A) TYP

SYMM

6

10

EXPOSED

THERMAL PAD

11

5

SYMM

21

2X 2

2.05 0.1

16X 0.5

1

15

0.30

20X

PIN 1 ID

20

16

0.18

0.5

0.3

0.1

C A B

20X

0.05

4219031/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGR0020A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.05)

SYMM

16

SEE SOLDER MASK

DETAIL

20

20X (0.6)

15

20X (0.24)

16X (0.5)

1

(2.05)

SYMM

21

(3.3)

(0.775)

5

11

(R0.05) TYP

(

0.2) TYP

VIA

6

10

(0.775)

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219031/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGR0020A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.56) TYP

16

20

20X (0.6)

1

20X (0.24)

16X (0.5)

15

(0.56) TYP

(3.3)

21

SYMM

4X (0.92)

11

(R0.05) TYP

5

6

10

4X (0.92)

SYMM

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 21

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4219031/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS7A85A
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示功能的 4A、低输入电压 (1.1V)、低噪声、高精度、超低压降稳压器稳压器
文件：	总49页 (文件大小：3362K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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