TPS7B4250QDBVQ1 [TI]
汽车类 50mA、电池供电运行 (40V)、可调节电压跟踪低压降稳压器 | DBV | 5 | -40 to 125;
| 型号： | TPS7B4250QDBVQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 50mA、电池供电运行 (40V)、可调节电压跟踪低压降稳压器 | DBV | 5 | -40 to 125 电池 稳压器 |
| 文件： | 总23页 (文件大小：1430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
TPS7B4250-Q1 低压降电压跟踪 LDO
1 特性
2 应用
1
•
•
适用于汽车电子 应用
符合 AEC-Q100 标准的下列结果
•
•
电路板外传感器电源
高精度电压跟踪
–
–
–
器件温度等级 1：环境运行温度范围为 -40°C
至 125°C
3 说明
TPS7B4250-Q1 器件是一款单片、集成型低压降跟踪
器。此器件采用 SOT-23 封装。TPS7B4250-Q1 器件
被设计用来为汽车环境中的电路板外传感器供电。此集
成电路 (IC) 具有针对过载、过热、反向极性和电池与
接地输出短路的集成保护功能。
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
3A
器件带电器件模型 (CDM） ESD 分类等级 C6
•
•
•
-20V 至 45V 宽范围、最大输入电压范围
输出电流，50mA
极低输出跟踪容限，
5mV（最大值）
调节输入引脚 ADJ 上施加的基准电压用于对高达 VIN
= 45V 的电源电压进行稳压，负载电流高达 50mA。
•
•
•
•
当 IOUT = 10mA 时，低压降电压为 150mV
组合基准和使能输入
通过将调节/使能输入引脚 (ADJ/EN) 置为低电
平，TPS7B4250-Q1 器件可切换至待机模式，从而最
大限度地降低静态电流。
轻负载时，40µA 的低静态电流
极端、宽 ESD 范围。
–
与 1µF 至 50µF 陶瓷输出电容器，1mΩ 至 20Ω
等效串联电阻 (ESR) 一同使用时保持稳定
器件信息(1)
器件型号
封装
SOT-23 (5)
封装尺寸（标称值）
•
•
•
•
反极性保护
TPS7B4250-Q1
2.90mm x 1.60mm
过热保护
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
对接地和电源的输出短路保护
SOT-23 封装
输出等于基准电压
输出低于基准电压
TPS7B4250-Q1
VIN
VOUT
2.2 µF
Vreg
Vbat
TPS7B4250-Q1
VOUT
2.2 µF
VIN
1 µF
Vreg
Vbat
1 µF
Vref
ADJ/EN
Vref
GND
ADJ/EN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCA0
TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 13
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
8
9
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
10.3 Power Dissipation and Thermal Considerations... 15
11 器件和文档支持 ..................................................... 16
11.1 文档支持................................................................ 16
11.2 社区资源................................................................ 16
11.3 商标....................................................................... 16
11.4 静电放电警告......................................................... 16
11.5 Glossary................................................................ 16
12 机械、封装和可订购信息....................................... 16
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2013) to Revision B
Page
•
•
•
已更改 HBM ESD 分类等级，从 2 改为 3A ........................................................................................................................... 1
已更改 CDM ESD 分类等级，从 C4 改为 C6......................................................................................................................... 1
已添加 引脚配置和功能部分，ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部
分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分 ................................................................................ 1
•
•
Deleted the transient current and 107-pF capacitor for HBM table notes from the ESD Ratings table ................................ 5
Changed input voltage symbol from VIN to VI for the ΔVO(ΔVI) and Vdropout parameters and the output voltage symbol
from VOUT to VO for the IL parameter in the Electrical Characteristics table ........................................................................... 6
•
•
•
•
•
•
Added IO and CO to the PSRR test condition in the Electrical Characteristics table ............................................................. 6
Changed the max value for Vdropout where IO = 10 mA from 250 to 265 in the Electrical Characteristics table ..................... 6
Deleted the VADJ = 5 V condition for the Ground current vs Temperature graph and changed the legend........................... 7
Changed the y axis units from mV to mA in the Current-limit vs Temperature graph .......................................................... 7
Added the VADJ condition statement to the Input Voltage vs Output Voltage graph and changed the y-axis from IO to VO .. 7
Changed the title of Figure 8 from Input Voltage vs Output Voltage to Reference Voltage vs Output Voltage, and
changed the y-axis from IO to VO. Also added the VI condition statement to the graph......................................................... 7
•
•
•
•
Changed the second y axis from IO to VI and removed the units in the Line Transient......................................................... 7
Deleted the units from the second y axis in the Load Transient ............................................................................................ 7
Added the VADJ condition statement to the Power-supply Rejection Ratio vs Frequency graph ........................................... 8
Added resistor-divider values to the Tracking LDO With Enable Circuit figure.................................................................... 11
2
版权 © 2013–2015, Texas Instruments Incorporated
TPS7B4250-Q1
www.ti.com.cn
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
Changes from Original (October 2013) to Revision A
Page
•
•
•
•
•
•
•
•
•
已更改 CDM ESD 分类等级，通篇从 C3B 改为 C4 ............................................................................................................... 1
Changed VOUT min value from –0.3 to –1 in the Absolute Maximum Ratings table............................................................... 5
Added transient current flow to ESD rating in the Absolute Maximum Ratings table ............................................................ 5
Changed HBM absolute maximum rating from 2 kV to 4 kV.................................................................................................. 5
Deleted relevant ESR value from Recommended Operating Conditions table...................................................................... 5
Added grater-than-or-equal-to (≥) value to VADJ/EN in condition statement of the Electrical Characteristics table ................ 6
Added VADJ = 1.5 V to both test conditions for VUVLO parameter in the Electrical Characteristics table ................................ 6
Changed max value for load regulation parameter from 3 to 4 in the Electrical Characteristics table .................................. 6
Changed max value for the current consumption test condition where IO = 0.5 mA from 80 to 90 in the Electrical
Characteristics table ............................................................................................................................................................... 6
•
•
Added the Detailed Description section.................................................................................................................................. 9
Added the TPS7B4250 block diagram ................................................................................................................................... 9
Copyright © 2013–2015, Texas Instruments Incorporated
3
TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
www.ti.com.cn
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
1
ADJ/EN
GND
5
GND
2
3
V
IN
4
V
OUT
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
This pin connects to the reference voltage. A low signal disables the IC and a high signal
enables the IC. Connected the voltage reference directly or with a voltage divider for lower
output voltages. To compensate for line influences, TI recommends to place a capacitor
close to the IC pins.
ADJ/EN
1
I
2
5
Internally connected to pin 5
Internally connected to pin 2
GND
G
This pin is the IC supply. To compensate for line influences, TI recommends to place a
capacitor close to the IC pins.
VIN
3
4
I
VOUT is an external capacitor that is required between VOUT and GND with respect to the
capacitance and ESR requirements given in the Recommended Operating Conditions.
VOUT
O
4
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7B4250-Q1
www.ti.com.cn
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–20
–1
MAX
45
UNIT
V
(2)(3)
Input voltage, unregulated input, VIN
Output voltage, regulated output, VOUT
Adjust input and enable input voltage, ADJ/EN(2)(3)
ADJ Voltage minus input voltage (ADJ–VIN), VIN > 0 V
Operating junction temperature, TJ
22
V
–0.3
22
V
7
V
–40
–65
150
150
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, GND.
(3) Absolute maximum voltage.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
4
MAX
UNIT
V
VIN
Unregulated input
40
18
18
5
VOUT
regulated output
1.5
1.5
V
ADJ/EN
ADJ–VIN
COUT
Adjust input and enable input voltage
ADJ voltage minus input voltage
Output capacitor requirements(2)
Output ESR requirements
Operating junction temperature
V
V
1
0.001
–40
50
20
150
µF
Ω
ESRCOUT
TJ
°C
(1) Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified within the
conditions given in the related electrical characteristics table.
(2) The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%.
6.4 Thermal Information
TPS7B4250-Q1
THERMAL METRIC(1)(2)
DBV (SOT-23)
5 PINS
171.7
81.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
31.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.5
ψJB
31.2
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The thermal data is based on the JEDEC standard high K profile, JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.
The copper pad is soldered to the thermal land pattern. Also, correct attachment procedure must be incorporated.
Copyright © 2013–2015, Texas Instruments Incorporated
5
TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
www.ti.com.cn
MAX UNIT
6.5 Electrical Characteristics
VI = 13.5 V, 18 V ≥ VADJ/EN ≥ 1.5 V, TJ = –40ºC to 150ºC unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
Ramp up VI until the output turns on, VADJ = 1.5 V
Ramp down VI until the output turns off, VADJ = 1.5 V
3.65
VUVLO
VIN undervoltage detection
V
3
IO = 100 µA to 1 mA, VI = 4 V to 40 V, 1.5 V < VADJ
VI – 0.3 V
<
–4
–5
4
ΔVO
Output-voltage tracking accuracy
Load regulation steady-state
mV
5
IO = 1 mA to 50 mA, VI = 4 V to 40 V, 1.5 V < VADJ
VI – 1.5 V
<
ΔVO(ΔIL)
IO = 1 mA to 30 mA
4
3
mV
mV
ΔVO(ΔVI) Line regulation steady-state
IO = 10 mA, VI = 6 V to 40 V
Frequency = 100 Hz, Vrip = 0.5 VPP, IO = 5 mA, CO
2.2 µF
=
60
PSRR
Power-supply ripple rejection
dB
IO = 10 mA, VI ≥ 4 V(1)
IO = 50 mA, VI ≥ 4 V(1)
150
550
265
1000
500
0
Vdropout
Dropout voltage, Vdropout = VI – VQ
mV
IL
Output-current limitation
Reverse current at VIN
VO short to GND
100
–5
mA
µA
IR
VI = 0 V, VO = 20 V, VADJ = 5 V
VI = –20 V, VO = 0 V, VADJ = 5 V
VI = –20 V, VO = 20 V, VADJ = 5 V
IRN1
IRN2
–5
0
Reverse current at negative input
voltage
µA
°C
–5
0
TJ increasing because of power dissipation
generated by the IC
175
7.5
TSD
Thermal shutdown temperature
VADJ < 0.8 V, TA ≤ 85°C(2)
VADJ < 0.8 V, TA ≤ 125°C
IO = 0.5 mA, VADJ = 5 V
IO = 30 mA, VADJ = 5 V
VADJ = 5 V
15
20
90
350
1
IQ
Current consumption
µA
µA
40
150
Adjust-input and enable-input
current
IADJ
VADJ,low
Adjust and enable low signal valid
VO = 0 V
0.8
18
V
V
VADJ,high Adjust and enable high signal valid
|VO – VADJ| < 5 mV
1.5
(1) Measured when the output voltage VQ has dropped 10 mV from the typical value.
(2) Ensured by design.
6
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7B4250-Q1
www.ti.com.cn
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
6.6 Typical Characteristics
400
350
300
250
200
150
100
50
1000
900
800
700
600
500
400
300
200
100
0
œ40°C
0°C
25°C
75°C
125°C
0
0
5
10
15
20
25
30
35
40
45
50
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
Temperature (°C)
C002
C001
I
(mA)
O
VI = VADJ = 4 V
IO = 10 mA
VI = VADJ = 4 V
Figure 1. Dropout Voltage vs Temperature
Figure 2. Dropout Voltage vs Output Current
250
200
150
100
50
200
175
150
125
100
75
VADJ < 0.8 V
IO = 0.5 mA
IO = 30mA
50
œ40°C
25°C
25
125°C
0
0
0
10
20
30
40
50
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
Temperature (°C)
C003
C004
I
(mA)
O
VI = 13.5 V
VI = 13.5 V
VADJ = 5 V
Figure 4. Ground Current vs Temperature
Figure 3. Ground Current vs Output Current
500
450
400
350
300
250
200
150
100
50
5
4
3
2
1
0
œ1
œ2
œ3
œ4
œ5
1 mA
50 mA
0
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
C005
C006
VI = 13.5 V
VADJ = 5 V
VI = 13.5 V
VADJ = 5 V
IO = 1 mA, 50 mA
Figure 5. Current-limit vs Temperature
Figure 6. Tracking Error vs Temperature
Copyright © 2013–2015, Texas Instruments Incorporated
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TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
www.ti.com.cn
Typical Characteristics (continued)
6
6
5
4
3
2
1
0
5
4
3
2
1
0
œ40°C
25°C
œ40°C
25°C
125°C
125°C
0
5
10
15
20
25
30
35
40
0
1
2
3
4
5
C007
C008
V (V)
I
V
(V)
ADJ
VADJ = 5 V
VI = 13.5 V
Figure 7. Input Voltage vs Output Voltage
Figure 8. Reference Voltage vs Output Voltage
5.10
5.06
5.02
4.98
4.94
4.90
0.05
0.04
0.03
0.02
0.01
0.00
5.03
5.02
5.01
5.00
4.99
4.98
4.97
20
V
V
I
O
O
V
18
16
14
12
10
8
I
30 mA
16 V
9 V
5 mA
0
0.0003
0.0006
0.0009
0.0012
0.0015
0
0.0003
0.0006
0.0009
0.0012
0.0015
Time (seconds)
Time (seconds)
C009
C010
VI = 9 to 16 V
2.2-µF ceramic output capacitor
IO = 5 to 30 mA
2.2-µF ceramic output capacitor
Figure 9. Line Transient
Figure 10. Load Transient
120
50
50
100
80
60
40
20
0
40
40
30
30
Stable Region
20
20
10
10
1
0
0.001
5
10
15
20
100
1000 10000
100000 1000000 10000000
0000
Frequency (Hz)
ESR of C (ꢀ)
C011
C012
O
VI = 13.5 V
VADJ = 5 V
CO = 2.2 µF
ILOAD = 25 mA
Figure 11. Power-Supply Rejection Ratio vs Frequency
Figure 12. ESR Stability vs Load Capacitance
8
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7B4250-Q1
www.ti.com.cn
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
7 Detailed Description
7.1 Overview
The TPS7B4250-Q1 device is a monolithic integrated low-dropout voltage tracker with ultra-low tracking
tolerance. Several types of protection circuits are also integrated in the device such as output current limitation,
reverse polarity protection, and thermal shutdown in case of over temperature.
7.2 Functional Block Diagram
O
V
V
reg
bat
2.2 µF
Logic
Control
Internal
Supply
Thermal
Shutdown
ADJ/EN
V
ref
GND
7.3 Feature Description
7.3.1 Regulated Output (VOUT
)
VOUT is the regulated output based on the reference voltage. The output has current limitation. During initial
power up, the regulator has an incorporated soft start to control the initial current through the pass element.
7.3.2 Undervoltage Shutdown
The device has an internally-fixed undervoltage shutdown threshold. Undervoltage shutdown activates when the
input voltage on VIN drops below UVLO. This activation ensures the regulator is not latched into an unknown
state during low input supply voltage. If the input voltage has a negative transient that drops below the UVLO
threshold and recovers, the regulator shuts down and powers up similar to a standard power-up sequence when
the input voltage is above the required levels.
Copyright © 2013–2015, Texas Instruments Incorporated
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Feature Description (continued)
7.3.3 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 175°C which allows
the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator and protects it from damage as a result of
overheating.
The internal protection circuitry of the TPS7B4250-Q1 device has been designed to protect against overload
conditions. The circuitry was not intended to replace proper heat-sinking. Continuously running the TPS7B4250-
Q1 device into thermal shutdown degrades device reliability.
7.3.4 VOUT Short to Battery
The TPS7B4250-Q1 device survives a short to battery when the output is shorted to the battery as shown in
Figure 13. No damage occurs to the device. A short to the battery can also occur when the device is powered by
an isolated supply at a lower voltage as shown in Figure 14. In this case the TPS7B4250-Q1 supply input voltage
is set at 7 V when a short to battery (14 V typical) occurs on VOUT which typically runs at 5 V. The continuous
reverse current flows out through VIN is less than 5 µA.
Automotive Battery,
14 V (typically)
Switch
Switch
V
bat
Automotive Battery,
14 V (typically)
TPS7B4250-Q1
V
OUT
V
IN
V
V
reg
bat
TPS7B4250-Q1
V
OUT
V
IN
V
1 µF
reg
7-V V
2.2 µF
I
1 µF
2.2 µF
5-V V
ref
5-V V
ref
ADJ/EN
GND
ADJ/EN
GND
Figure 13. Output-Voltage Short to Battery
Figure 14. Output Voltage Higher than Input
7.3.5 Tracking Regulator with ENABLE Circuit
By pulling the reference voltage of the device below 0.8 V, the IC disables and enters a sleep state where the
device draws 7.5 µA (typical) from the power supply. In a real application, the reference voltage is generally
sourced from another LDO voltage rail. A case where the device must be disabled without a shutdown of the
reference voltage can occur. In such case, the device can be configured as shown in Figure 15. The
TPS7A6650-Q1 device is a 150-mA LDO with ultra-low quiescent current that is used as a reference voltage to
the TPS7B4250-Q1 device and also as a power supply to the ADC. In a configuration as shown in Figure 15, the
status of the device is controlled by an MCU I/O.
10
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7B4250-Q1
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ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
Feature Description (continued)
TPS7A6650-Q1
V
O
V
ADC
bat
22 µF
EN
10k
PG
10 µF
V
IN
GND
10 µF
TPS7B4250-Q1
47k
CT
GND
ADJ
V
OUT
Sensor
2.2 µF
100k
MCU I/O
47k
Figure 15. Tracking LDO With Enable Circuit
7.4 Device Functional Modes
7.4.1 Operation With VI < 4 V
The device operates with input voltages above 4 V. The maximum UVLO voltage is 3 V and operates at input
voltage above 4 V. The device can also operate at lower input voltages; no minimum UVLO voltage is specified.
At input voltages below the actual UVLO voltage, the device does not operate.
7.4.2 Operation With ADJ/EN Control
The rising-edge threshold voltage of the ADJ/EN pin is 1.5 V (maximum). When the EN pin is held above that
voltage and the input voltage is above the 4 V, the device becomes active. The enable falling edge is 0.8 V
(minimum). When the EN pin is held below that voltage the device is disabled, the IC quiescent current is
reduced in this state.
Copyright © 2013–2015, Texas Instruments Incorporated
11
TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Based on the end-application, different values of external components can be used. An application can require a
larger output capacitor during fast load steps to prevent a reset from occurring. TI recommends a low ESR
ceramic capacitor with a dielectric of type X5R or X7R for better load transient response.
8.2 Typical Application
Figure 16 show typical application circuit for the TPS7B4250-Q1 device.
TPS7B4250-Q1
VOUT
2.2 µF
VIN
1 µF
Vreg
Vbat
ADJ/EN
GND
Vref
0.1 µF
Figure 16. Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUES
4 to 40 V
ADJ reference voltage
Output voltage
1.5 to 18 V
1.5 to 18 V
Output current rating
Output capacitor range
Output capacitor ESR range
50 mA
1 µF to 50 µF
1 mΩ to 20 Ω
12
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7B4250-Q1
www.ti.com.cn
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
•
•
•
Input voltage range
Reference voltage
Output voltage
Output current rating
Input capacitor
Output capacitor
8.2.2.1 External Capacitors
An input capacitor, CI, is recommended to buffer line influences. Connect the capacitors close to the IC pins.
The output capacitor for the TPS7B4250-Q1 device is required for stability. Without the output capacitor, the
regulator oscillates. The actual size and type of the output capacitor can vary based on the application load and
temperature range. The effective series resistance (ESR) of the capacitor is also a factor in the IC stability. The
worst case is determined at the minimum ambient temperature and maximum load expected. To ensure stability
of TPS7B4250-Q1 device, the device requires an output capacitor between 1 µF and 50 µF with an ESR range
between 0.001 Ω and 20 Ω that can cover most types of capacitor ESR variation under the recommend operating
conditions. As a result, the output capacitor selection is flexible.
The capacitor must also be rated at all ambient temperature expected in the system. To maintain regulator
stability down to –40°C, use a capacitor rated at that temperature.
8.2.3 Application Curves
VI = 12 V
VADJ = 5 V
VI = 12 V
VADJ = 5 V
Figure 17. Power Up
Figure 18. Power Down
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4 V and 40 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the TPS7B4250-Q1 device,
adding an electrolytic capacitor with a value of 10-µF and a ceramic bypass capacitor at the input is
recommended.
Copyright © 2013–2015, Texas Instruments Incorporated
13
TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
10.1.1 Package Mounting
Solder-pad footprint recommendations for the TPS7B4250-Q1 device are available in the 机械、封装和可订购信
息 section and at www.ti.com.
10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve AC performance such as PSRR, output noise, and transient response, TI recommends to design the
board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of
the device.
Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure
stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as
the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because of the negative impact on system performance. Vias and
long traces can also cause instability.
If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout
pattern used for TPS7B4250 evaluation board, available at www.ti.com.
10.2 Layout Example
ADJ/EN
GND
1
5
TPS7B4250-Q1
Bypass
Capacitor
Power
Ground
GND
VIN
2
3
Input
Capacitor
Output
Capacitor
VOUT
4
Figure 19. TPS7B4250-Q1 Layout Example
14
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7B4250-Q1
www.ti.com.cn
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
10.3 Power Dissipation and Thermal Considerations
Device power dissipation is calculated with Equation 1.
PD = IO ´ V - V + I ´ V
I
(
)
I
O
Q
where
•
•
•
•
•
PD = continuous power dissipation
IO = output current
VI = input voltage
VO = output voltage
IQ = quiescent current
(1)
As IQ « IO, the term IQ × VI in Equation 1 can be ignored.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) with
Equation 2.
T = T + q ´ PD
(
)
J
A
JA
where
•
θJA = junction-to-junction-ambient air thermal impedance
(2)
(3)
A rise in junction temperature because of power dissipation can be calculated with Equation 3.
DT = T - T = q ´ PD
(
)
J
A
JA
For a given maximum junction temperature (TJM), the maximum ambient air temperature (TAM) at which the
device can operate can be calculated with Equation 4.
TAM = TJM - (qJA ´ PD )
(4)
版权 © 2013–2015, Texas Instruments Incorporated
15
TPS7B4250-Q1
ZHCSBU7B –OCTOBER 2013–REVISED JULY 2015
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档请参见以下部分：
《TPS7B4250 评估模块》，SLVU975
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
16
版权 © 2013–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B4250QDBVQ1
TPS7B4250QDBVRQ1
PREVIEW
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000
TBD
Call TI
NIPDAU
Call TI
-40 to 125
-40 to 125
3000 RoHS & Green
Level-3-260C-168 HR
PA3Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B4250QDBVRQ1 SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
190.0 190.0 30.0
TPS7B4250QDBVRQ1
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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