TPS7B7050QPWPRQ1 [TI]
具有复位延迟功能的汽车类 300mA、电池供电运行 (40V)、低 IQ、低压降稳压器 | PWP | 16 | -40 to 125;
| 型号： | TPS7B7050QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有复位延迟功能的汽车类 300mA、电池供电运行 (40V)、低 IQ、低压降稳压器 | PWP | 16 | -40 to 125 电池 稳压器 |
| 文件： | 总26页 (文件大小：1918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7B70-Q1
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
具有电源正常指示功能的 TPS7B70-Q1 汽车类 300mA 40V 低 IQ LDO
1 特性
3 说明
1
•
符合汽车类应用的 应用
TPS7B70-Q1 是一款通过汽车电池供电的 300mA 低
压降线性稳压器 (LDO)。该器件在轻负载条件下的静
态电流仅有 19µA。因此，TPS7B70-Q1 是用于为微控
制器 (MCU) 和控制器局域网 (CAN) 收发器等常开式组
件供电的绝佳选择。
•
具有符合 AEC-Q100 标准的下列结果：
–
器件温度 1 级：–40°C 至 125°C 的环境工作温
度范围
–
–
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级 C4B
TPS7B70-Q1 的输入电压范围扩展到了 40V。该电压
可帮助该器件承受瞬态条件，例如负载突降。该器件还
具有电源正常 (PG) 引脚，可在输出电压实现稳压后通
知系统。要实现必要的操作，您可以调整 PG 阈值电
压和延迟。PG 信号的阈值电压通过外部电阻器进行调
整。请使用外部电容器来调整延迟。
•
器件结温范围：
–40°C 至 +150°C
•
•
最大输出电流：300mA
4V 至 40V 宽 VIN 输入电压范围，瞬态电压高达
45V
•
•
•
3.3V 和 5V 两种固定输出电压
最大压降电压：400mV（电流为 300mA）
此器件可在 –40°C 至 +125°C 的环境温度下运行，且
结温范围为 –40°C 至 +150°C。此外，此器件还采用
了热传导封装，即使整个器件散热较多，也能实现持久
运行，这是一种典型的脱离电池供电运行的特征。这些
特性以及所包含的电流限制和热关断保护使得
在宽电容（4.7µF 至 500µF）和 ESR（0.001Ω 至
20Ω）范围内，与输出电容器搭配使用时可保持稳
定
•
低静态电流 (I(Q))
–
–
EN 为低电平（关断模式）时 < 4µA
TPS7B70-Q1 成为为汽车系统组件供电的绝佳选择。
轻负载（VINT 为高电平）时为 19µA（典型
值）
器件信息(1)
器件编号
输出电压
3.3V 或 5V
封装
•
•
•
完全可调的电源正常阈值和电源正常延迟计时
针对欠压闭锁 (UVLO) 的低输入电压跟踪功能
集成故障保护
TPS7B70-Q1
HTSSOP (16)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
–
–
过载限流保护
热关断
典型应用
TPS7B7033-Q1
TPS7B7050-Q1
•
16 引脚 HTSSOP PowerPAD™封装
热阻 (RθJA)：39.7°C/W
VIN
VOUT
–
IN
OUT
Vreg
Vbat
2 应用
PGADJ
•
•
•
•
•
车身控制模块 (BCM)
EV 和 HEV 电池管理系统
变速器控制单元 (TCU)
音响主机
EN
PG
VINT
电动助力转向 (EPS)
DELAY
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEK5
TPS7B70-Q1
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
Power Supply Recommendations...................... 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 器件和文档支持 ..................................................... 17
11.1 文档支持................................................................ 17
11.2 接收文档更新通知 ................................................. 17
11.3 社区资源................................................................ 17
11.4 商标....................................................................... 17
11.5 静电放电警告......................................................... 17
11.6 术语表 ................................................................... 17
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (August 2018) to Revision A
Page
•
已更改 将器件状态从高级信息 更改为生产数据 ..................................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
TPS7B70-Q1
www.ti.com.cn
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With PowerPAD
Top View
IN
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT
PGADJ
PG
GND
GND
GND
GND
GND
DELAY
GND
GND
VINT
GND
GND
PowerPAD™
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
DELAY
NO.
Power-good delay adjustment pin. Connect this pin through a capacitor to ground to adjust
the power-good delay time.
8
O
I
Device enable pin. Pull this pin down to low-level voltage to disable the device. Pull this pin
up to high-level voltage to enable the device.
EN
2
3, 4, 5, 6, 7,
9, 10, 12, 13
GND
—
Ground reference
IN
1
I
Device input power supply pin
OUT
16
O
Device 3.3-V or 5-V regulated output-voltage pin
Power-good pin. Open-drain output pin. Pull this pin up to VOUT or to a reference through a
resistor. When the output voltage is not ready, this pin is pulled down to ground.
PG
14
O
Power-good threshold-adjustment pin. Connect a resistor divider between the PGADJ and
OUT pins to set the power-good threshold. Connect this pin to ground to set the threshold to
PGADJ
15
O
91.6% of output voltage VOUT
Internal voltage rail. Tie this pin above 2 V for lowest IGND
Solder thermal pad to board to improve the thermal performance.
.
VINT
11
—
I
.
PowerPAD
—
Copyright © 2018, Texas Instruments Incorporated
3
TPS7B70-Q1
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
45
7
UNIT
V
Unregulated input
IN, EN
DELAY
OUT
Power-good delay-timer output
Regulated output
V
7
V
Power-good output voltage
V-internal
PG
7
V
VINT
7
V
Power-good threshold-adjustment voltage
Operating junction temperature
Storage temperature
PGADJ
7
V
TJ
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
All pins
V
Corner pins (1, 14, 15, and 28)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4
NOM
MAX
40
UNIT
V
Unregulated input
40-V pins
IN
EN
0
VIN
5.5
V
Regulated output
Power good
OUT
0
V
PG
0
5.5
V
Low voltage pins
Output current
PGADJ, DELAY
0
5.5
V
IOUT
TA
0
300
125
150
mA
°C
°C
Ambient temperature
Junction temperature
–40
–40
TJ
6.4 Thermal Information
TPS7B70-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
39.7
28.9
23.8
1.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
23.7
3.1
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
TPS7B70-Q1
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ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 14 V, COUT ≥ 4.7 µF, and 1 mΩ < ESR < 20 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
I(SLEEP)
Input sleep current
EN = off
4.5
29.6
2.6
µA
µA
VIN = VOUT + 1 V to 40 V, EN = on, VINT >
2 V, IOUT < 1 mA, –40°C ≤ TJ ≤ 85°C
I(GND)
Input quiescent current
Undervoltage lockout, falling
19
V(UVLO)
Ramp VIN down until output is turned off
V
V
V(UVLO_HYST) UVLO hysteresis
0.5
ENABLE INPUT (EN)
VIL
Low-level input voltage
0.7
V
V
VIH
Vhys
High-level input voltage
Hysteresis
2
150
mV
REGULATED OUTPUT (OUT)
VIN = VOUT + 1 V to 40 V, IOUT = 0 mA to
300 mA, –40°C ≤ TJ ≤ 125°C
–2%
2%
VOUT
Regulated output
Line regulation
VIN = VOUT + 1 V to 40 V, IOUT = 0 mA to
300 mA
–2.5%
2.5%
ΔVOUT(ΔVIN)
VIN = VOUT + 1 V to 40 V, IOUT = 1 mA
IOUT = 1 mA to 300 mA
IOUT = 300 mA
10
20
mV
mV
ΔVOUT(ΔIOUT) Load regulation
V(dropout) Dropout voltage (VIN – VOUT
I(LIM) Output current limit
300
170
680
400
325
1000
(1)(2)
)
mV
mA
IOUT = 200 mA
VOUT shorted to ground, VIN = 5.6 V
301
IOUT = 100 mA, COUT = 10 µF,
frequency (f) = 100 Hz
60
40
PSRR
Power-supply ripple rejection(3)
dB
IOUT = 100 mA, COUT = 10 µF,
frequency (f) = 100 kHz
POWER GOOD (PG, PGADJ)
VOL(PG) PG output, low voltage
Ilkg(PG)
IOL = 5 mA, PG pulled low
0.4
1
V
PG pin leakage current
PG pulled to VOUT through a 10‑kΩ resistor
µA
VOUT powered above the internally set
tolerance, PGADJ pin shorted to ground
% of
VOUT
V(PG_TH)
Default power-good threshold
88.6
91.6
2
93.6
VOUT falling below the internally set
tolerance hysteresis
% of
VOUT
V(PG_HYST)
Power-good hysteresis
(1) This test is done with VOUT in regulation, measuring the VIN – VOUT when VOUT drops by 100 mV from the rated output voltage at the
specified load.
(2) Dropout is not measured for VOUT = 3.3 V in this test because VIN must be 4 V or greater for proper operation.
(3) Design information—not tested, determined by characterization.
Copyright © 2018, Texas Instruments Incorporated
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 14 V, COUT ≥ 4.7 µF, and 1 mΩ < ESR < 20 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PGADJ
Switching voltage for the power-
good adjust pin
V(PGADJ_TH)
VOUT is falling
1.067
1.1
1.133
V
POWER-GOOD DELAY
DELAY capacitor charging
current
I(DLY_CHG)
V(DLY_TH)
I(DLY_DIS)
3
0.95
0.5
5
1
10
µA
V
DELAY pin threshold to release
PG high
Voltage at DELAY pin is ramped up
VDELAY = 1 V
1.05
DELAY capacitor discharging
current
mA
TEMPERATURE
T(SD)
Junction shutdown temperature
Hysteresis of thermal shutdown
175
25
°C
°C
T(HYST)
6.6 Switching Characteristics
TJ = –40°C to 150°C, VI = 14 V, CO ≥ 4.7 µF, and 1 mΩ < ESR < 20 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-GOOD DELAY (DELAY)
t(DEGLITCH)
t(DLY_FIX)
t(DLY)
Power-good deglitch time
180
248
20
250
900
µs
µs
Fixed power-good delay
Power-good delay
No capacitor connect at DELAY pin
Delay capacitor value: C(DELAY) = 100 nF
ms
6
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TPS7B70-Q1
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ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
6.7 Typical Characteristics
TJ = –40ºC to 150ºC, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
80
70
60
50
40
30
20
10
0
400
350
300
250
200
150
100
50
-40 °C
25 °C
125 °C
IOUT = 1 mA
IOUT = 100 mA
IOUT = 200 mA
0
0
50
100
150
200
250
300
0
5
10
15
20
25
30
35
40
Output Current (mA)
Input Voltage (V)
D001
D002
图 1. Ground Current vs Output Current
图 2. Ground Current vs Input Voltage
35
30
25
20
15
10
5
4
3
2
1
0
IOUT = 1 mA
IOUT = 100 mA
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
Ambient Temperature (èC)
D003
D004
EN = 0 V
图 3. Shutdown Current vs Ambient Temperature
图 4. Ground Current vs Ambient Temperature
350
300
250
200
150
100
50
300
250
200
150
100
50
-40 °C
25 °C
125 °C
0
0
0
50
100
150
200
250
300
350
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
Output Current (mA)
D005
D006
IOUT = 200 mA
图 6. Dropout Voltage vs Ambient Temperature
图 5. Dropout Voltage vs Output Current
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Typical Characteristics (接下页)
TJ = –40ºC to 150ºC, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
5.06
5.03
5
6
5
4
3
2
1
0
4.97
-40èC
25èC
125èC
4.94
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
0
5
10
15
20
25
30
35
40
Input Voltage (V)
D007
D008
VOUT = 5 V
图 7. Output Voltage vs Ambient Temperature
VOUT = 5 V
图 8. Output Voltage vs Input Voltage
900
800
700
600
500
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-40 °C
25 °C
125 °C
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
0
50
100
150
200
250
300
350
Output Current (mA)
D009
D010
VIN = 5.6 V
图 9. Output Current Limit (ILIM) vs Ambient Temperature
图 10. Load Regulation
1
120
100
80
60
40
20
0
-40èC
0.8
25èC
125èC
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
5
10
15
20
25
30
35
40
10
100
1k
10k
100k
1M
10M
Input Voltage (V)
Frequency (Hz)
D011
D012
COUT = 10 µF
IOUT = 1 mA
图 12. PSRR vs Frequency
TA = 25°C
图 11. Line Regulation
8
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Typical Characteristics (接下页)
TJ = –40ºC to 150ºC, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
120
100
80
60
40
20
0
1k
Unstable Region
Stable Region
500
100
10
4.7
Unstable Region
1
0.001
10
100
1k
10k
100k
1M
10M
0.01
0.1
ESR (W)
1
10 20
Frequency (Hz)
D013
D014
COUT = 10 µF
IOUT = 100 mA
图 13. PSRR vs Frequency
TA = 25°C
图 14. ESR Stability vs Output Capacitance
VIN (10 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VIN (10 V/div)
VOUT(AC) (100 mV/div)
IOUT (10 mA/div)
VOUT(AC) (100 mV/div)
IOUT (10 mA/div)
VIN = 6 V to 40 V
IOUT = 1 mA
VOUT = 5 V
COUT = 10 µF
VIN = 40 V to 6 V
IOUT = 1 mA
VOUT = 5 V
COUT = 10 µF
图 15. Line Transient
图 16. Line Transient
VIN (5 V/div)
VIN (5 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VOUT(AC) (50 mV/div)
IOUT (200 mA/div)
VOUT(AC) (50 mV/div)
IOUT (200 mA/div)
VIN = 6 V to 40 V
IOUT = 200 mA
VOUT = 5 V
COUT = 10 µF
VIN = 40 V to 6 V
IOUT = 200 mA
VOUT = 5 V
COUT = 10 µF
图 17. Line Transient
图 18. Line Transient
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Typical Characteristics (接下页)
TJ = –40ºC to 150ºC, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
VIN (5 V/div)
VIN (5 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VOUT(AC) (500 mV/div)
VOUT(AC) (500 mV/div)
IOUT (200 mA/div)
IOUT (200 mA/div)
VOUT = 5 V
COUT = 10 µF
IOUT = 1 mA to 200 mA
VOUT = 5 V
COUT = 10 µF
IOUT = 200 mA to 1 mA
图 19. Load Transient
图 20. Load Transient
10
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www.ti.com.cn
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
7 Detailed Description
7.1 Overview
The TPS7B70-Q1 is a 300-mA, 40-V monolithic low-dropout linear voltage regulator with adjustable power-good
threshold functionality. This voltage regulator consumes only 19-µA quiescent current in light-load applications.
Because of the adjustable power-good delay (also called power-on-reset delay) and the adjustable power-good
threshold, this device is an excellent choice as a power supply for microprocessors and microcontrollers in
automotive applications.
7.2 Functional Block Diagram
IN
OUT
VINT
PG
Undervoltage
Lockout
Overcurrent
Protection
Band Gap Filter
Regulator Control
Thermal Shutdown
+
EN
Error
Amp
VREF
œ
Power Good
Control With
Delay
DELAY
V(PG_REF)
GND
œ
GND
Amp
+
PGADJ
7.3 Feature Description
7.3.1 Device Enable (EN)
The EN pin is a high-voltage-tolerant pin. A high input activates the device and turns the regulator on. Connect
this input pin to an external microcontroller or a digital control circuit to enable and disable the device, or connect
to the IN pin for self-bias applications.
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Feature Description (接下页)
7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
The PG pin is an open-drain output with an external pullup resistor to the regulated supply, and the PGADJ pin is
a power-good threshold adjustment pin. Connecting the PGADJ pin to GND sets the power-good threshold value
to the default, V(PG_TH). When VOUT exceeds the default power-good threshold, the PG output turns high after the
power-good delay has expired. When VOUT falls below V(PG_TH) – V(PG_HYST), the PG output turns low after a short
deglitch time.
The power-good threshold is also adjustable from 1.1 V to 5 V by using an external resistor divider between
PGADJ and OUT. 公式 1 calculates the threshold:
R1+ R2
R2
V PG_ ADJ falling = V PGADJ_ TH falling
ì
(
)
(
)
R1+ R2
R2
»
ÿ
⁄
V PG_ ADJ risng = V PGADJ_ TH falling + 26 mV typ
ì
(
)
(
)
(
)
where:
•
•
V(PG_ADJ) is the adjustable power-good threshold
V(PG_REF) is the internal comparator reference voltage of the PGADJ pin, 1.1 V typical, 2% accuracy specified
under all conditions (1)
By setting the power-good threshold V(PG_ADJ) when VOUT exceeds this threshold, the PG output turns high after
the power-good delay has expired. When VOUT falls below V(PG_ADJ) – V(PG_HYST), the PG output turns low after a
short deglitch time. 图 21 shows a block diagram of this threshold.
OUT
VREG
Adjustable
Power-Good
Threshold
R1
PG
DELAY
Power-Good
Control
R2
V(PG_REF)
PGADJ
Amp
图 21. Adjustable Power-Good Threshold
7.3.3 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay, t(DLY), is the time from when PGADJ is greater than V(PG,REF) until the PG pin goes high.
The power-good delay is a function of the value of the external capacitor that is connected to the DELAY pin
(CDELAY). Connecting an external capacitor from this pin to GND sets the power-good delay. The constant current
charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator, and 公式 2
determines the power-good delay. 图 22 illustrates a timing diagram for power-good power-up conditions.
C
DELAY ´ 1 V
t(DLY)
=
5 mA
where
•
•
t(DLY) is the adjustable power-good delay
CDELAY is the value of the power-good delay capacitor
(2)
12
版权 © 2018, Texas Instruments Incorporated
TPS7B70-Q1
www.ti.com.cn
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
Feature Description (接下页)
VIN
V
(UVLO)
t < t(DEGLITCH)
V(PG_HYST)
V(PG_TH) rising
V(PG_TH) falling
V(PG_ADJ) falling
V(PG_ADJ) rising
VOUT
V
(DLY_TH)
DELAY
t(DEGLITCH)
t(DEGLITCH)
t
t
(DLY)
(DLY)
PG
Power Up
Input Voltage Drop
Undervoltage
Power Down
图 22. Power-Up and Conditions for Activation of Power Good
If the DELAY pin is open, the default delay time is t(DLY_FIX)
7.3.4 Undervoltage Shutdown
.
This device has an integrated undervoltage lockout (UVLO) circuit that shuts down the output if the input voltage
falls below an internal UVLO threshold, V(UVLO). The UVLO circuit makes sure that the regulator does not latch
into an unknown state during low-input-voltage conditions. If the input voltage has a negative transient that drops
below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up
sequence after the input voltage rises above the required level.
7.3.5 Current Limit
The TPS7B70-Q1 has current-limit protection to keep the device in a safe operating area when an overload or
output short-to-ground condition occurs. This feature protects the device from excessive power dissipation. For
example, during a short-circuit condition on the output, fault protection limits the current through the pass
element to I(LIM) to protect the device from excessive power dissipation.
7.3.6 Thermal Shutdown
This device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature must not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature falls below T(SD) – T(HYST), the
output turns on again.
7.4 Device Functional Modes
7.4.1 Operation With Input Voltage Less Than 4 V
The device normally operates with input voltages above 4 V. The device can also operate at lower input
voltages; the maximum UVLO voltage is 2.6 V. At input voltages below the actual UVLO voltage, the device does
not operate.
7.4.2 Operation With Input Voltage Greater Than 4 V
If the input voltage is greater than the output set value plus the device dropout voltage when the input voltage is
greater than 4 V, then the output voltage is equal to the set value. Otherwise, the output voltage is equal to the
input voltage minus the dropout voltage.
版权 © 2018, Texas Instruments Incorporated
13
TPS7B70-Q1
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B70-Q1 is a 300-mA low-dropout linear regulator with ultra-low quiescent current. The PSpice transient
model is available for download on the product folder and can be used to evaluate the basic function of the
device.
8.2 Typical Application
图 23 shows a typical application circuit for the TPS7B70-Q1. Different values of external components can be
used, depending on the end application. An application may require a larger output capacitor during fast load
steps to prevent a large drop on the output voltage. Use a low-ESR ceramic capacitor with a dielectric of type
X7R.
CAN
OUT
VIN
I/O
IN
10 …F
10 …F
MCU
10 kꢀ
31.6 kꢀ
TPS7B70-Q1
PG
PGADJ
EN
10 kꢀ
VINT
GND
DELAY
100 nF
图 23. Supply Power to an MCU
14
版权 © 2018, Texas Instruments Incorporated
TPS7B70-Q1
www.ti.com.cn
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
Typical Application (接下页)
8.2.1 Design Requirements
For this design, the TPS7B70-Q1 must be able to supply a CAN transceiver and an MCU from a 12-V automotive
battery. To provide good MCU operation, the PG pin must trip when the output is at 95% of the nominal value.
The PG pin must have a 20-ms delay in order to avoid shutting down as a result of temporary glitches.
8.2.2 Detailed Design Procedure
8.2.2.1 Input Capacitor
A 10-µF capacitor in parallel with a 0.1-µF ceramic bypass capacitor is placed at the input in order to keep the
input voltage stable. The input can tolerate transients up to 40 V, so the input capacitors have a 50-V voltage
rating.
8.2.2.2 Output Capacitor
For this application, a 10-µF X7R ceramic capacitor is used to provide good output transient performance and
good loop stability.
8.2.2.3 Power-Good Threshold
The power-good threshold is set by connecting PGADJ to GND, or by connecting PGADJ to a resistor divider
from OUT to GND. The Adjustable Power-Good Threshold (PG, PGADJ) section provides the method to setup
the power-good threshold. Rearranging 公式 1 yields 公式 3, and solves the values of R1 and R2 that are
needed to get the 95% falling threshold. In this design, R2 is a 10-kΩ resistor. Solving 公式 3 for R1 gives a
value of 33.18 kΩ. This value is not a standard 1% resistor value, so a 31.6-kΩ resistor is chosen for R1.
≈
’
V
(PGADJ)falling
(PTGADJ_ TH)falling
R1= R2
∆
∆
«
÷
÷
◊
V
(3)
8.2.2.4 Power-Good Delay, t(DLY)
Set the power-good delay with an external capacitor (CDELAY) to ground. Calculate the correct capacitance with
公式 2. This application requires a delay of 20 ms, so solve for the correct capacitance required to get this delay.
As shown in 公式 4, rearrange 公式 2 to solve for CDELAY
.
CDELAY = tDLY ×5ꢀA
(4)
8.2.3 Application Curve
VIN (5 V/div)
VOUT (2 V/div)
VPG (2 V/div)
IOUT (10 mA/div)
图 24. Power-Up Waveform
版权 © 2018, Texas Instruments Incorporated
15
TPS7B70-Q1
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
www.ti.com.cn
9 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range from 4 V to 40 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the TPS7B70-Q1, add a capacitor
with a value of ≥ 10 µF with a 0.1-µF ceramic bypass capacitor in parallel at the input.
10 Layout
10.1 Layout Guidelines
For LDO power supplies, especially high-voltage and high-current supplies, layout is an important step. If the
layout is not carefully designed, the regulator cannot deliver enough output current because of thermal
limitations. To improve the thermal performance of the device and maximize the current output at high ambient
temperature, spread out the thermal pad as much as possible, and put enough thermal vias on the thermal pad.
图 25 shows an example layout.
10.2 Layout Example
1
IN
EN
20
OUT
PGADJ
PG
19
18
2
3
GND
GND
GND
17
16
15
4
5
6
7
8
GND
GND
VINT
GND
GND
GND
GND
14
13
DELAY
Denotes a via
图 25. Layout Example
16
版权 © 2018, Texas Instruments Incorporated
TPS7B70-Q1
www.ti.com.cn
ZHCSIQ1A –AUGUST 2018–REVISED OCTOBER 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
德州仪器 (TI)，《TPS7B70EVM-008 评估模块》用户指南
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航面板。
版权 © 2018, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B7033QPWPRQ1
TPS7B7050QPWPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
16
16
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
7B7033Q
7B7050Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B7033QPWPRQ1 HTSSOP PWP
TPS7B7050QPWPRQ1 HTSSOP PWP
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B7033QPWPRQ1
TPS7B7050QPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
16
16
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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