TPS7H3301HKR/EM [TI]

Radiation-hardened QMLV, 2.3-V to 3.5-V input, 3-A sink and source DDR termination LDO regulator | HKR | 16 | 25 to 25;


型号：	TPS7H3301HKR/EM
厂家：	TEXAS INSTRUMENTS
描述：	Radiation-hardened QMLV, 2.3-V to 3.5-V input, 3-A sink and source DDR termination LDO regulator \| HKR \| 16 \| 25 to 25 双倍数据速率
文件：	总31页 (文件大小：2138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7H3301-SP

ZHCSEJ1 –DECEMBER 2015

TPS7H3301-SP 内置 VREF 的灌电流/拉电流抗辐射加固型 3A DDR 终端

稳压器

1 特性

3 说明

•

QML V 类符合 5962-14228⁽¹⁾⁽²⁾

TPS7H3301-SP 是一款内置 VREF 的 TID 和单粒子效

应 (SEE) 抗辐射加固型双倍数据速率 (DDR) 3A 终端

稳压器。该稳压器专门用于为空间 DDR 终端应用

（如单电路板计算机、固态记录器和载荷处理应用）

提供一套完整的紧凑型、低噪声解决方案。

–

总电离剂量为 100krad (Si)

–

高剂量率 (HDR) (50-100 rad(Si)/s)

低剂量率 (LDR) (0.01 rad(Si)/s)

–

单粒子锁定 (SEL)、单粒子栅穿 (SEGR)、单粒

子烧毁 (SEB) 对于线性能量传输 (LET) 的抗扰

度 = 65MeV-cm²/mg

TPS7H3301-SP 支持并兼容 DDR、DDR2、DDR3、

DDR4 以及相关的低功耗 JEDEC 规范。凭借快速瞬态

响应，TPS7H3301-SP VTT 稳压器可在读取/写入状态

下提供稳定性较高的电源。TPS7H3301-SP 还包含一

个内置的 VREF 电源。该电源可跟踪 VTT 以进一步缩

减解决方案尺寸。在瞬态变化过程中，VREF 电源的快

速跟踪功能能够最大限度地降低 VTT 和 VREF 之间的

电压偏移。请参见说明（续）。

单粒子瞬变 (SET)、单粒子功能中断 (SEFI)、

单粒子翻转 (SEU) 的抗扰度为 65MeV-cm²/mg

（详细信息请参见辐射报告）

•

支持 DDR、DDR2、DDR3、DDR3LP 和 DDR4 终

端应用并兼容 JEDEC 标准

输入电压：支持 2.5V 和 3.3V 电源轨⁽³⁾

•

独立低电压输入 (VLDOIN) 降至

0.9V 以改善电源效率⁽³⁾

器件信息⁽¹⁾⁽²⁾

封装

•

具有压降补偿功能的 3A 灌电流/拉电流终端稳压器

用于电源排序的使能输入和电源正常输出

VTT 终端稳压器

器件型号

封装尺寸（标称值）

TPS7H3301-SP

CFP (16)

9.60mm x 11.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

–

输出电压范围：0.5V 至 1.75V

3A 灌电流和拉电流

(2) 抗辐射加固保障 (RHA) 当前可达 100krad；详细信息请联系制

造商。

(3) 适用于 DDR2、DDR3、DDR3L 和 DDR4 DDR 的标称输入电

压 = 3.3V。V_{INDDR1 的}为 2.95V 至 3.5V，所有 DDR 的 V_LDOIN

精度为 ±20mV

•

具有感测输入的精密集成分压器网络

远程感测 (VOSNS)

> V_TT

。

DDR2 3A 负载条件下的 Vin 为 2.45V 至 3.5V。

Vin 余量：V_{in_min}≥ V_TT+ 1.5V

VTTREF 缓冲参考输出

(4) 这些部件仅用于工程评估。以非合规性流程对其进行了处理

（即未进行老化处理等操作）并且仅在 25°C 的额定温度下进

行了测试。这些部件不适用于质检、生产、辐射测试或飞行。

这些零部件无法在 –55°C 至 125°C 的完整 MIL 额定温度范围

内或运行寿命中保证其性能。

–

精度为 VDDQ/2 ± 1%

±10mA 灌/拉电流

•

集成了内置软启动 (SS)、欠压锁定 (UVLO) 以及过

流限制 (OCL) 功能

标准 DDR 应用

TPS7H3301

VTTREF = VDDQSNS / 2

2 应用

VTTSNS

VTTREF

VDDQ

SNS

AGND

•

采用 DDR、DDR2、DDR3 和低功耗 DDR3 和

VTT / Vo = VDDQ / 2

AGND

VDDQ

VTT/Vo

VLDOIN

DDR4 存储器的单电路板计算机、固态记录器和载

荷应用

DDR œ 2.5 V

VTT/Vo

DDR2 œ 1.8 V

DDR3 œ 1.5 V

DDR3L œ 1.35 V

DDR4 œ 1.2 V

VLDOIN

•

超快速瞬态电源应用

POWER GOOD

PGOOD

PGND

支持军用温度范围（-55°C 至 125°C）

提供工程评估 (/EM) 组件⁽⁴⁾

3.3-V or 2.5-V

Supply

VDD/

Vin

ENABLE

PGND

AGND

PGND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCJ5

TPS7H3301-SP

ZHCSEJ1 –DECEMBER 2015

www.ti.com.cn

8.4 Device Functional Modes........................................ 14

Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Application ................................................. 15

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ..................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 8

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 12

8.3 Feature Description................................................. 12

10 Power Supply Recommendations ..................... 23

11 Layout................................................................... 24

11.1 Layout Guidelines ................................................. 24

11.2 Layout Example .................................................... 24

11.3 Thermal Considerations........................................ 25

12 器件和文档支持 ..................................................... 26

12.1 器件支持................................................................ 26

12.2 社区资源................................................................ 26

12.3 商标....................................................................... 26

12.4 静电放电警告......................................................... 26

12.5 Glossary................................................................ 26

13 机械、封装和可订购信息....................................... 26

4 修订历史记录

日期

2015 年 12 月

修订版本

注释

最初发布版本

TPS7H3301-SP

www.ti.com.cn

ZHCSEJ1 –DECEMBER 2015

5 说明（续）

为了简单的启用电源排序，使能输入和电源正常输出 (PGOOD) 已在 TPS7H3301-SP 中集成。PGOOD 输出是开

漏输出，因此可在所有电源进入稳压状态时将其与多个开漏输出相连来进行监控。使能信号还可用于在挂起至

RAM (S3) 断电模式时使 VTT 放电。

TPS7H3301-SP 采用 TI 常用的 16 引脚耐热增强型双陶瓷扁平封装 (HKR)，TPS7H1101-SP 同样采用这种封装。

TPS7H3301-SP

ZHCSEJ1 –DECEMBER 2015

www.ti.com.cn

6 Pin Configuration and Functions

HKR Package

16-Pin CFP

Top View - Live Bug

VTTREF

VTTSNS

VDDQSNS

VLDOIN

AGND

VTT/V_O

VLDOIN

VTT/V_O

Thermal Pad

(Bottom Side)

VLDOIN

PGND

PGOOD

VDD/

Pin Functions

I/O

DESCRIPTION

NAME

NO.

VTTREF

Reference output. Connect to GND through 0.1-µF ceramic capacitor.

VDDQ sense input. Reference input for VTTREF.

VDDQSNS

VLDOIN

Supply voltage for the LDO. Connect to VDDQ voltage or an alternate voltage source.

Power ground. Connect output for the VTT/ V _OLDO to negative pin of the output capacitor.

PGND

—

Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the

device.

2.5- or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1 and 10 µF is

required.

VDD/V_IN

PGOOD

PGOOD output pin. PGOOD pin is an open drain output to indicate the output voltage is within

specification.

VTT/V_O

Power output for VTT LDO

AGND

—

Signal ground. Connect to negative pin of output capacitors.⁽¹⁾

VDDQ sense input, reference input for VTTREF. Voltage sense for VTT/ V _O. Connect to positive pin of

the output capacitor or the load.

VTTSNS

(1) Thermal pad must be connected to GND.

TPS7H3301-SP

www.ti.com.cn

ZHCSEJ1 –DECEMBER 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature, unless otherwise noted⁽¹⁾

MIN

–0.36

–0.3

MAX

3.6

6.5

0.3

3.6

UNIT

V_IN/VDD, VLDOIN, VTTSNS, VDDQSNS

(2)

Input voltage

PGND to AGND

V_O/VTT, VTTREF

PGOOD

(2)

Output voltage

Peak output current

PG pin sink current

Internally limited

°C

T_J

Maximum operating junction temperature

Storage temperature

–55

150

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground pin unless otherwise noted.

7.2 ESD Ratings

VALUE

±4000

±750

UNIT

(1)

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

Electrostatic

discharge

V_(ESD)

(2)

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

2.375

0.9

NOM

MAX

3.5

1.8

0.1

125

UNIT

Supply voltage

V_IN/ VDD

VLDOIN

EN, VTTSNS

VDDQSNS

–0.1

1.0

Voltage

V_O/ VTT, PGOOD

VTTREF

–0.1

–55

PGND

T _J

Operating junction temperature

°C

7.4 Thermal Information

TPS7H3301-SP

HKR (CFP)

16 PINS

(1) (2) (3)

THERMAL METRIC

UNIT

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

0.6

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Do not allow package body temperature to exceed 265°C at any time or permanent damage may result.

(3) Maximum power dissipation may be limited by overcurrent protection.

TPS7H3301-SP

ZHCSEJ1 –DECEMBER 2015

www.ti.com.cn

7.5 Electrical Characteristics

Over full temperature range, –55°C to 125°C, V_IN/VDD= 3.3 V and 2.375V,V_VLDOIN= 1.8 V, V_VDDQSNS= 1.8 V,

V_VOSNS/VTTSNS= 0.9 V, V_EN= V_VIN/VDD, 标准 DDR 应用 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY CURRENT

I_IN/I_VDD

Supply current

V _EN= 3.3 V, No Load

V _EN= 0 V, VDDQSNS = 0, No Load

V _EN= 0 V, VDDQSNS > 0.78 V, No Load

V _EN= 3.3 V, No Load

I_VDD(SDN)

Shutdown current

6.5

575

I_LDOIN

Supply current of VLDOIN

1200

μA

Shutdown current of

VLDOIN

I_LDOIN(SDN)

V _EN= 0 V, No Load

100

INPUT CURRENT

I_VDDQsns

Input current, VDDQsns

V _EN= 3.3 V

1.25

0.9

μA

V_O/ V_TTOUTPUT

V _LDOIN= 2.5 V, V_VTTREF= 1.25 V (DDR1), I _O= 0 A

V _LDOIN= 1.8 V, V_VTTREF= 0.9 V (DDR2), I _O= 0 A

V _LDOIN= 1.5 V, V_VTTREF= 0.75 V (DDR3), I _O= 0 A

V _LDOIN= 1.35 V, V_VTTREF= 0.675 V (DDR3L), I _O= 0 A

V _LDOIN= 1.20 V, V_VTTREF= 0.60 V (DDR4), I _O= 0 A

–6

0.75

0.675

0.60

V_VOSNS/VTTSNS

Output DC voltage, VO

V_IN/ V_DD= 2.95 V, V_VDDQSNS= 2.50 V, V _TT= V_VTTREF– 50 mV

(DDR1), I _O= 0.5 A

101

209

230

V_IN/ V_DD= 2.95 V, V_VDDQSNS= 2.50 V, V _TT= V_VTTREF– 50 mV

(DDR1), I _O= 1 A

300

400

230

300

400

230

300

400

230

300

400

230

300

400

V_IN/ V_DD= 2.95 V, V_VDDQSNS= 2.50 V, V _TT= V_VTTREF– 50 mV

(DDR1), I _O= 2.0 A⁽²⁾

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.80 V, V _TT= V_VTTREF– 50 mV

(DDR2), I _O= 0.5 A⁽²⁾

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.80 V, V _TT= V_VTTREF– 50 mV

(DDR2), I _O= 1 A⁽²⁾

108

228

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.80 V, V _TT= V_VTTREF– 50 mV

(DDR2), I _O= 2.0 A⁽²⁾

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.50 V, V _TT= V_VTTREF– 50 mV

(DDR3), I _O= 0.5 A

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.50 V, V _TT= V_VTTREF– 50 mV

(DDR3), I _O= 1 A

(1)

V_LODIN– V_TT

V_LODIN> V_TT

104

216

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.50 V, V _TT= V_VTTREF– 50 mV

(DDR3), I _O= 2.0 A⁽²⁾

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.35 V, V _TT= V_VTTREF– 50 mV

(DDR3L), I _O= 0.5 A

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.35 V, V _TT= V_VTTREF– 50 mV

(DDR3L), I _O= 1 A

102

212

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.35 V, V _TT= V_VTTREF– 50 mV

(DDR3L), I _O= 2.0 A⁽²⁾

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.20 V, V _TT= V_VTTREF– 50 mV

(DDR4), I _O= 0.5 A

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.20 V, V _TT= V_VTTREF– 50 mV

(DDR4), I _O= 1 A

102

210

V_IN/ V_DD= 2.375 V, V_VDDQSNS= 1.20 V, V _TT= V_VTTREF– 50 mV

(DDR4), I _O= 2.0 A⁽²⁾

I _VO= –3 A, across V_INvoltage range⁽²⁾

I _VO= 3 A, across V_INvoltage range⁽²⁾

-34

-12

Output voltage tolerance to

V_VTTREF

V_VOTOL/VTTTOL

I_VOSRCL

–25

VO/VTT source current limit With reference to V _VTTREF, V_VTTSNS= 90% × V _VTTREF

3.25

(1) Dropout / Headroom information provided to help designer in optimizing system efficiency

(2) Specified by characterization and not production tested

TPS7H3301-SP

www.ti.com.cn

ZHCSEJ1 –DECEMBER 2015

Electrical Characteristics (continued)

Over full temperature range, –55°C to 125°C, V_IN/VDD= 3.3 V and 2.375V,V_VLDOIN= 1.8 V, V_VDDQSNS= 1.8 V,

V_VOSNS/VTTSNS= 0.9 V, V_EN= V_VIN/VDD, 标准 DDR 应用 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_VOSNCL

VO/VTT sink current limit

Discharge impedance, Ω

With reference to V _VTTREF, V_VTTSNS= 110% × V _VTTREF

V _DDQSNS= 0 V, V_VO= 0.3 V, V _EN= 0 V, T_A= 25°C

3.5

5.5

R_DSCHRG

Ω

POWERGOOD COMPARATOR

PGOOD window lower threshold with respect to V_VTTREF

PGOOD window upper threshold with respect to V_VTTREF

PGOOD hysteresis

–23.5%

17.5%

–20% –17.5%

V_TH(PG)

VO/VTT PGOOD threshold

20%

23.5%

T_PGSTUPDLY

V_PGOODLOW

T_PBADDLY

PGOOD startup delay

Output low voltage

PGOOD bad delay

Startup rising edge, VOSNS within 15% of V_VTTREF

I _SINK= 4 mA

0.4

V _OSNSis outside of the ±20% PGOOD window

μs

V _OSNS= V_REFIN(PGOOD high impedance),

PGOOD = V_IN+ 0.2 V

I_PGOODLK

Leakage current

μA

V_DDQSNSAND V_VTTREFOUTPUT

V_DDQSNS

V_DDQSNSvoltage range

1.0

2.80

V_DDQSNSundervoltage

lockout

V_{DDQSNS_UVLO}

V _DDQSNSrising

780

V_DDQSNSundervoltage

lockout hysteresis

V_DDQSNSUVHYS

V _VTTREF

V_VTTREFvoltage

V_DDQSNS/ 2

–10 mA < I _VTTREF<10 mA, V_VDDQSNS= 2.5 V

–10 mA <I _VTTREF<10 mA, V_VDDQSNS= 1.8 V

–10 mA <I _VTTREF<10 mA, V_VDDQSNS= 1.5 V

–10 mA <I _VTTREF<10 mA, V_VDDQSNS= 1.35 V

–10 mA <I _VTTREF<10 mA, V_VDDQSNS= 1.2 V

–15

V _VTTREFvoltage tolerance to

V_VDDQSNS

V _VTTREF

I _VTTREFSRCL

I _VTTREFSNCCL

I _VTTREFDIS

V _VTTREFsource current limit VTTREF = 0 V

V _VTTREFsink current limit

V_{VTTREF discharge current}

VTTREF = 0 V

EN = 0 V, V _DDQSNS= 0 V, V_VTTREF= 0.5 V

1.3

UVLO/EN LOGIC THRESHOLD

Wake up, T _A= 25°C

Hysteresis

Enable

2.18

2.25

V_VINUVVIN

UVLO threshold

V_ENIH

High-level input voltage

Low-level input voltage

Hysteresis voltage

1.7

–1

V_ENIL

Enable

0.3

V_ENYST

I_ENLEAK

Enable

0.5

Logic input leakage current

EN, T _A= 25°C

μA

THERMAL SHUTDOWN

Thermal shutdown threshold

Shutdown temperature

Hysteresis

210

T_SON

°C

(3)

(3) Ensured by design, not production tested

TPS7H3301-SP

ZHCSEJ1 –DECEMBER 2015

www.ti.com.cn

7.6 Typical Characteristics

For Figure 1 through Figure 15, (3 × 150 µF T530D157M010ATE005 tantalum + 4 × 4.7 µF MLCC) or equivalent

capacitance/ESR are used on the output.

1.29

1.28

1.27

1.26

1.25

1.24

1.23

1.22

0.94

0.93

0.92

0.91

0.9

25°C

125°C

œ55°C

25°C

125°C

œ55°C

0.89

0.88

0.87

-3

-2

-1

-3

-2

-1

Output Current (A)

D001

D002

V_VIN= 3.3 V

VDDQSNS = 2.5 V

V_VIN= 3.3 V

VDDQSNS = 1.8 V

Figure 1. Output Voltage vs Output Current

Figure 2. Output Voltage vs Output Current

0.79

0.78

0.77

0.76

0.75

0.74

0.73

0.72

0.71

0.7

25°C

125°C

œ55°C

25°C

125°C

œ55°C

0.69

0.68

0.67

0.66

0.65

-3

-2

-1

-3

-2

-1

Output Current (A)

D003

D004

V_VIN= 3.3 V

VDDQSNS = 1.5 V

V_VIN= 3.3 V

VDDQSNS = 1.35 V

Figure 3. Output Voltage vs Output Current

Figure 4. Output Voltage vs Output Current

0.66

0.65

0.64

0.63

0.62

0.61

0.6

1.29

1.28

1.27

1.26

1.25

1.24

1.23

1.22

25°C

125°C

œ55°C

25°C

125°C

œ55°C

0.59

0.58

0.57

-3

-2

-1

-3

-2

-1

Output Current (A)

D005

D006

V_VIN= 3.3 V

VDDQSNS = 1.2 V

V_VIN= 2.95 V

VDDQSNS = 2.5 V

Figure 5. Output Voltage vs Output Current

Figure 6. Output Voltage vs Output Current

TPS7H3301-SP

www.ti.com.cn

ZHCSEJ1 –DECEMBER 2015

Typical Characteristics (continued)

For Figure 1 through Figure 15, (3 × 150 µF T530D157M010ATE005 tantalum + 4 × 4.7 µF MLCC) or equivalent

capacitance/ESR are used on the output.

0.94

0.93

0.92

0.91

0.9

0.79

0.78

0.77

0.76

0.75

0.74

0.73

0.72

25°C

125°C

œ55°C

25°C

125°C

œ55°C

0.89

0.88

0.87

-3

-2

-1

-3

-2

-1

Output Current (A)

D007

D008

V_VIN= 2.95 V

VDDQSNS = 1.8 V

V_VIN= 2.375 V

VDDQSNS = 1.5 V

Figure 7. Output Voltage vs Output Current

Figure 8. Output Voltage vs Output Current

0.72

0.71

0.7

0.66

0.65

0.64

0.63

0.62

0.61

0.6

25°C

125°C

œ55°C

25°C

125°C

œ55°C

0.69

0.68

0.67

0.66

0.65

0.59

0.58

0.57

-3

-2

-1

-3

-2

-1

Output Current (A)

D009

D010

V_VIN= 2.375 V

VDDQSNS = 1.35 V

V_VIN= 2.375 V

VDDQSNS = 1.2 V

Figure 9. Output Voltage vs Output Current

Figure 10. Output Voltage vs Output Current

1.26

1.259

1.258

1.257

1.256

1.255

1.254

1.253

1.252

1.251

1.25

0.91

0.909

0.908

0.907

0.906

0.905

0.904

0.903

0.902

0.901

0.9

25°C

125°C

œ55°C

25°C

125°C

œ55°C

-15

-10

-5

-15

-10

-5

VTTREF Current (mA)

D011

D012

VDDQSNS = 2.5 V

VDDQSNS = 1.8 V

Figure 11. RF Voltage vs REFOUT Current

Figure 12. RF Voltage vs REFOUT Current

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Typical Characteristics (continued)

For Figure 1 through Figure 15, (3 × 150 µF T530D157M010ATE005 tantalum + 4 × 4.7 µF MLCC) or equivalent

capacitance/ESR are used on the output.

0.76

0.759

0.758

0.757

0.756

0.755

0.754

0.753

0.752

0.751

0.75

0.686

0.685

0.684

0.683

0.682

0.681

0.68

25°C

125°C

œ55°C

25°C

125°C

œ55°C

0.679

0.678

0.677

0.676

-15

-10

-5

-15

-10

-5

VTTREF Output Current (mA)

D013

D014

VDDQSNS = 1.5 V

VDDQSNS = 1.35 V

Figure 13. RF Voltage vs REFOUT Current

Figure 14. RF Voltage vs REFOUT Current

0.275

0.25

0.225

0.2

0.61

0.609

0.608

0.607

0.606

0.605

0.604

0.603

0.602

0.601

0.6

25°C

125°C

œ55°C

0.175

0.15

0.125

0.1

0.6 V

0.075

0.05

0.025

0.675 V

0.75 V

0.9 V

1.25 V

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

-15

-10

-5

Output Current (A)

VTTREF Output Current (mA)

D016

D015

V_VIN= 3.6 V

VDDQSNS = 1.2 V

Figure 16. Dropout Voltage vs Output Current

Figure 15. RF Voltage vs REFOUT Current

1.5

1.4

1.3

1.2

1.1

1.5

1.4

1.3

1.2

1.1

25èC

125èC

œ55èC

125èC

œ55èC

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

-8 -7 -6 -5 -4 -3 -2 -1

Output Current (A)

D017

D018

V_IN= 2.375 V

VDDQSNS = 1.5 V

V_IN= 3.5 V

VDDQSNS = 1.5 V

Figure 17. Output Voltage vs Output Current, DDR3

Figure 18. Output Voltage vs Output Current, DDR3

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Typical Characteristics (continued)

For Figure 1 through Figure 15, (3 × 150 µF T530D157M010ATE005 tantalum + 4 × 4.7 µF MLCC) or equivalent

capacitance/ESR are used on the output.

1.8

1.6

1.4

1.2

1.8

1.6

1.4

1.2

25èC

125èC

œ55èC

125èC

œ55èC

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

-8 -7 -6 -5 -4 -3 -2 -1

Output Current (A)

D019

D020

V_IN= 2.375 V

VDDQSNS = 1.8 V

V_IN= 3.5 V

VDDQSNS = 1.8 V

Figure 19. Output Voltage vs Output Current, DDR2

Figure 20. Output Voltage vs Output Current, DDR2

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8 Detailed Description

8.1 Overview

The TPS7H3301-SP device is a sink and source double data rate (DDR) termination regulator specifically

designed for low input voltage, low-cost, low-noise systems where space and weight is a key consideration.

8.2 Functional Block Diagram

VDDQSNS

3,4,5 VLDOIN

VTTREF

2.25 V

UVLO

VDD/V_IN

DchgREF

DchgVTT

12,13,14

VOSNS/VTTSNS

VO/VTT

ENVTT

6,7,8 PGND

REFINOK

PGND 15

PGOOD

Startup

Delay

8.3 Feature Description

8.3.1 VO Sink/Source Regulator

The TPS7H3301-SP is a 3A sink/source tracking termination regulator specifically designed for low input voltage,

low-cost, and low external component count systems where space is a key application parameter. The

TPS7H3301-SP integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both

sourcing and sinking current. The LDO regulator employs a fast feedback loop so that ceramic capacitors can be

used to support the fast load transient response. To achieve tight regulation with minimum effect of trace

resistance, a remote sensing pin, VOSNS/VTTSNS, should be connected to the positive pin of the output

capacitor(s) as a separate trace from the high current path from Vo/VTT.

The TPS7H3301-SP has a dedicated pin VLDOIN, for VTT power supply to minimize the LDO power dissipation

on user application. The minimum VLDOIN voltage is 400mV above the 1/2 VDDQSNS voltage or as highlighted

in electrical table VLDOIN to VTT headroom for various load conditions.

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Feature Description (continued)

8.3.2 Reference Input (VDDQSNS)

The output voltage, Vo/VTT, is regulated to VTTREF. VDDQSNS incorporates integrated resistor divider network.

VDDQSNS can be connected to memory supply bus (VDDQ). VDDQSNS should be connected to the memory

supply bus (VDDQ). The TPS7H3301-SP supports VDDQSNS voltage from 1.0 V to 3.5 V, making it versatile

and ideal for many types of low-power LDO applications.

8.3.3 Reference Output (VTTREF)

When it is configured for DDR termination applications, VTTREF generates the DDR VTT reference voltage for

the memory application. VTTREF block consists of an on-chip 1/2 divider and a low-pass filter (LPF). VTTREF

tracks 1/2 of VDDQSNS with 1% accuracy. It is capable of supporting both a sourcing and sinking load of 10 mA.

VTTREF becomes active when VDDQSNS voltage rises to 0.78 V and Vin/VDD is above the UVLO threshold.

When VTTREF is less than 0.375 V, VTTREF is disabled and subsequently discharges to GND through an

internal MOSFET. VO/ VTT is also dicharged following discharge of VTTREF. VTTREF is independent of the EN

pin state. To meet stability criteria, a capacitor of 0.1 µF min must be installed close to VTTREF (pin1). Capacitor

value at VTTREF (pin 1) must not exceed 2.2 µF.

8.3.4 EN ControL (EN)

When EN is driven high, the TPS7H3301-SP Vo/ VTT regulator begins normal operation. When EN is driven low,

Vo/VTT is discharges to GND through an internal 18-Ω MOSFET. VTTREF remains on when EN is driven low.

EN is not tied high internally to prevent power sequencing issues with an external signal that may be controlling

the enable. EN is floating input and not internally tied, thus the user can have complete control over where and

when the EN signal is generated. EN feeds directly into PowerGood (PGOOD). When enable is low Pgood is

low.

8.3.5 PowerGood Function (PGOOD)

The TPS7H3301-SP provides an open-drain PGOOD output that goes high when the Vo/VTT output is within

20% of VTTREF (typ). PGOOD deasserts within 1 μs after the output exceeds the size of the powergood

window. During initial Vo/VTT startup, PGOOD asserts high 2 ms (typ) after the Vo/ VTT enters power good

window. Because PGOOD is an open-drain output, a 100-kΩ, pullup resistor between PGOOD and a stable

active supply voltage rail is required.

8.3.6 VO Current Protection

The LDO has a constant OCL.

8.3.7 VIN UVLO Protection

For VIN/ VDD undervoltage lockout (UVLO) protection, the TPS7H3301-SP monitors VIN/ VDD voltage. When

the VIN/ VDD voltage is lower than the UVLO threshold voltage, both the VTT nd VTTREF regulators are

powered off. This shutdown is a non-latch protection.

8.3.8 Thermal Shutdown

The TPS7H3301-SP monitors its junction temperature. If the device junction temperature exceeds its threshold

value, (typically 210°C), the VO/VTT and VTTREF regulators are both shut off, discharged by the internal

discharge MOSFETs. This shutdown is a non-latch protection.

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8.4 Device Functional Modes

TPS7H3301-SP a 3-A source-sink LDO provides low output noise to meet system needs. In order to improve

efficiency in the LDO, TPS7H3301-SP LDO can operate from low VLDOIN voltage rail, thus using dual voltage

source one for the VLDOIN that supports high current and an alternate voltage source that provides voltage for

VDDQSNS pin.

Typcically VLDOIN and VDDQSNS pins are tied together. In the memory system VDDQ is a high-current supply

that powers the core, the I/O, and the logic of the memory, VTTREF is a low-current, precision reference voltage

that provides a threshold between a logic high (one) and a logic low (zero) that adapts to changes in the I/O

supply voltage. By providing a precision threshold that adapts to the supply voltage, VTTREF realizes wider

noise margins than those possible with a fixed threshold and normal variations in termination and drive

impedance. Specifications vary from device manufacturer to manufacturer, but the most common specification is

0.49 to 0.51 times VDDQ and draws only tens to hundreds of microamps. For TPS7H3301-SP VTTREF is

desinged to source / sink 10 mA.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS7H3301-SP device is a highly-integrated source sink LDO. The device is targeted to support VTT

voltage for DDR memory applications and is capable of sourcing and sinking 3-A load current. The TPS7H3301-

SP user’s guide is available on www.ti.com, SLVUAK2. The guide highlights standard EVM test results,

schematic, and bill of materials (BOM) for reference.

9.2 Typical Application

The design example describes a 2.5-V Vin, DDR3 configuration.

TPS7H3301

VTTREF = VDDQSNS / 2

VTTSNS

VTTREF

VDDQ

SNS

AGND

VTT / Vo = 0.75 V

AGND

VTT/Vo

VLDOIN

VDDQ

C11

DDR3 œ 1.5 V

C10

VTT/Vo

VLDOIN

POWER GOOD

PGOOD

PGND

2.5-V Supply

VDD/

Vin

ENABLE

C12

PGND

AGND

PGND

Figure 21. Typical Application Circuit

9.2.1 Design Requirements

See the Recommended Operating Conditions for recommended limits.

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Typical Application (continued)

9.2.2 Detailed Design Procedure

Table 1. Design Example 1 List of Materials

REFERENCE

DESIGNATOR

DESCRIPTION

SPECIFICATION

PART NUMBER

MANUFACTURER

392 Ω

100 kΩ

CRCW0603392RFKEA

CRCW0603100KJNEA

T530D157M010ATE005

GRM188R71H102KA01D

08053C104KAT2A

Resistor

C3, C5, C6, C7

150 µF, 10 V

1000 pF

Kemet

MuRata

AVX

C4, C8, C9, C10, C11

C12

Capacitor

0.1 µF

4.7 µF, 10 V

10 µF, 10 V

1210ZC475KAT2A

Murata

GRM21BR71A106KE51L

9.2.2.1 VIN/VDD Capacitor

Add a ceramic capacitor, with a value between 1- and 10-μF, placed close to the VIN/VDD pin, to stabilize the

bias supply (2.5-V rail or 3.3-V rail) from any parasitic impedance from the supply.

9.2.2.2 VLDO Input Capacitor

Depending on the trace impedance between the VLDOIN/ VDDQ bulk power supply to the device, a transient

increase of source current is supplied mostly by the charge from the VLDOIN/ VDDQ input capacitor. Use a 150-

μF (or greater) tantalum capacitor in parallel with 4.7uf ceramic capacitor to supply this transient charge. Provide

more input capacitance as more output capacitance is used at VO. In general, use one-half of the C_OUTvalue for

input. One can also determine the input capacitance based upon headroom between VLDOIN and VTT/ Vo

voltage differential in the application.

9.2.2.3 VTT Output Capacitor

For stable operation, the total capacitance of the VTT/ Vo output pin must be greater than 470 μF. Attach three,

3 x 150-μF low esr tantalum capacitors in parallel with ceramic capacitors to minimize the effect of equivalent

series resistance (ESR) and equivalent series inductance (ESL). If the ESR is greater than 2 mΩ, insert an R-C

filter between the output and the VTTSNS input to achieve loop stability. The R-C filter time constant should be

almost the same as or slightly lower than the time constant of the output capacitor and its ESR.

9.2.2.4 VTTSNS Connection

To achieve tight regulation with minimum effect of trace resistance, a remote sensing pin, the VTTSNS pin

should be connected to the positive pin of the VTT pin output capacitor or capacitors as a separate trace from

the high-current path from VTT. Consider adding a low-pass R-C filter at the VTTSNS pin in case the ESR of the

VTT output capacitor or capacitors is larger than 2 mΩ. The R-C filter time constant should be approximately the

same or slightly lower than the time constant of the VTT output capacitance and ESR.

132

VTT

TPS7H3301-SP

VTT

R_C

VTTSNS

C_C

470 µF

PGND

Figure 22. R-C Filter for VTTSNS

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9.2.2.5 Low VIN Applications

TPS7H3301-SP can be used in an application system where either a 2.5-V rail or a 3.3-V rail is available. The

TPS7H3301-SP minimum input voltage requirement is 2.375 V. If a 2.5-V rail is used, ensure that the absolute

minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a

2.5-V rail input is between –5% and 5% accuracy, or better.

9.2.2.6 S3 and Pseudo-S5 Support

The TPS7H3301-SP provides S3 support by an EN function. The EN pin could be connected to an SLP_S3

signal in the end application. Both VTTREF and Vo/VTT are on when EN = high (S0 state). VTTREF is

maintained while Vo/ VTT is turned off and discharged via an internal discharge MOSFET when EN = low (S3

state). When EN = low and the VDDQSNS voltage is less than 0.780 V, TPS7H3301-SP enters pseudo-S5 state.

Both VTTREF and VTTREF outputs are turned off and discharged to GND through internal MOSFETs when

pseudo-S5 support is engaged (S4/S5 state). Figure 23 shows a typical startup and shutdown timing diagram for

an application that uses S3 and pseudo-S5 support.

9.2.2.7 Tracking Startup and Shutdown

The TPS7H3301-SP also supports tracking startup and shutdown when EN is tied directly to the system bus and

not used to turn on or turn off the device. During tracking startup, VO/VTT follows VTTREF once VDDQSNS

voltage is greater than 0.78 V. VDDQSNS incorporates the resistor divider network. The typical soft-start time for

the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The SS time

of the VO/VTT output no longer depends on the OCL setting, but it is a function of the SS time of the VDDQ rail.

PGOOD is asserted 2 ms after VO/VTT is within ±20% of VTTREF. During tracking shutdown, VO/VTT falls

following VTTREF until VTTREF reaches 0.37 V. Once VTTREF falls below 0.37 V, the internal discharge

MOSFETs are turned on and quickly discharge both VTTREF and VO/VTT to GND. PGOOD is deasserted once

VO/VTT is beyond the ±20% range of VTTREF. Figure 24 shows the typical timing diagram for an application

that uses tracking startup and shutdown.

There are no sequencing requirements between Vin/VDD and VLDOIN. If VLDOIN is applied first followed by

VDD/Vin there is no issue. Vin UVLO protection monitors Vin/VDD voltage, when Vin/Vdd is lower than UVLO

threshold both VTT and VTTREF regulators are powered off.

3.3VIN

= 1.5 V

VDDQ

0.780 V

VLDOIN

0.370 V

VDDQSNS

VTTREF

(S3_SLP)

= 0.75 V

OOCL

PGOOD

2 ms

Figure 23. Typical Timing Diagram for S3 and Pseudo-S5 Support

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3.3VIN

VLDOIN

VDDQSNS

VTTREF

determined

by the SS time

of VLDOIN

= 0.75 V

PGOOD

2ms

Figure 24. Typical Timing Diagram of Tracking Startup and Shutdown

9.2.2.8 Output Tolerance Consideration for VTT DIMM Applications

The TPS7H3301-SP is specifically designed to power up the memory termination rail (as shown in Figure 25).

The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to

sink and source current while maintaining acceptable VTT tolerance. See Figure 26 for typical characteristics for

a single memory cell.

DDR3 240-Pin Socket

TPS7H3301-SP

150 µF

Figure 25. Typical Application Diagram for DDR3 VTT DIMM using TPS7H3301-SP

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ZHCSEJ1 –DECEMBER 2015

DDQ

25 W

20 W

Receiver

Ouput

Buffer

(Driver)

OUT

UDG-08023

Figure 26. DDR Physical Signal System Bidirectional SSTL Signaling

In Figure 26, when Q1 is on and Q2 is off:

•

Current flows from VDDQ via the termination resistor to VTT

VTT sinks current

In Figure 26, when Q2 is on and Q1 is off:

•

Current flows from VTT via the termination resistor to GND

VTT sources current

Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the

tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR

JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).

VTTREF – 40 mV <VTT <VTTREF + 40 mV, for both dc and ac conditions

The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.

The TPS7H3301-SP ensures the regulator output voltage to be:

VTTREF –34 mV <VTT <VTTREF + 34mV, for both DC and AC conditions and –3 A <I_VTT<3 A

The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to

DDR, DDR2, DDR3 and Low Power DDR3/DDR4 applications (see Table 2 for detailed information). To meet the

stability requirement, a minimum output capacitance of 470 μF is needed, combination of both Tantalum and

ceramic capacitors. Considering the actual tolerance on the MLCC capacitors, four or higher 4.7-μF ceramic

capacitors in parallel with 3 × 150 µF low esr tantalum capacitor are sufficient to meet the above requirement.

For higher esr tantalum capacitors it will require multiple tantalum capacitors in parallel with ceramic capacitors to

meet system needs.

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Table 2. DDR, DDR2, DDR3, and LP DDR3 Termination Technology and Their Differences

LOW POWER DDR3

(DDR3L)

DDR

DDR2

DDR3

FSB Data Rates 200, 266, 333 and 400 MHz 400, 533, 677 and 800 MHz

On-die termination for data

800, 1066, 1330 and 1600 MHz

Same as DDR3

On-die termination for data

group. VTT termination for

Motherboard termination to group. VTT termination for

Termination

Same as DDR3

VTT for all signals

address, command and control address, command and control

signals

Not as demanding

•

Only 34 signals (address,

command, control) tied to

VTT

•

Only 34 signals (address,

command, control) tied to

VTT

Max source/sink transient

currents of up to 2.6 A to

2.9 A

Termination

Current Demand

Same as DDR3

•

ODT handles data signals

•

ODT handles data signals

Less than 1 A of burst current

2.5-V Core and I/O 1.25-V

VTT

1.35-V Core and I/O

0.68-V VTT

Voltage Level

1.8-V Core and I/O 0.9-V VTT

1.5-V Core and I/O 0.75-V VTT

The TPS7H3301-SP is designed as a Gm driven LDO. The voltage droop between the reference input and the

output regulator is determined by the transconductance and output current of the device. The typical Gm is 250 S

at 3 A and changes with respect to the load in order to conserve the quiescent current (that is, the Gm is very

low at no load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage

loop is only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see

Equation 1).

UGBW

2´ p´ C

OUT

where

•

F_UGBWis the unity gain bandwidth

Gm is transconductance

C_OUTis the output capacitance

(1)

There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement. To

maintain stability, the zero location contributed by the ESR of the output capacitors should be greater than the

–3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the

design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to

prevent the gain peaking effect around the Gm –3-dB point because of the large ESL, the output capacitor and

parasitic inductance of the VO trace.

Figure 27 shows the bode plot simulation for a typical DDR3 configuration of the TPS7H3301-SP, where:

•

V_IN= 2.4 V

V_VLDOIN= 1.5 V

V_VO= 0.75 V

I_IO= 2 A

3 × 150-μF low-ESR tantalum capacitors (T530D157M010ATE005) in parallel with 4 × 4.7-µF ceramic

capacitor include

•

ESR = 1.66 mΩ

ESL = 800 pH

The unity-gain bandwidth is approximately 87.3 kHz and the phase margin is 82°. The 0-dB level is crossed, the

gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.

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Figure 27. Bode Plot for a Typical DDR3 Configuration

Figure 8 shows the load regulation and Figure 28 shows the transient response for a typical DDR3 configuration.

When the regulator is subjected to ±1.5-A load step and release, the output voltage measurement shows no

difference between the DC and AC conditions.

Figure 28. Transient Plot

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9.2.2.9 LDO Design Guidelines

The minimum input (VLDOIN) to output voltage (V_O/V_tt) difference (headroom) decides the lowest usable supply

voltage Gm-driven to drive a certain load. For TPS7H3301-SP, a minimum of 300 mV (VLDOIN_MIN– VO_MAX) is

needed in order to support a Gm driven sourcing current of 3 A based on a design of V_IN= 3.3 V and C

OUT

470 μF. Because the TPS7H3301-SP is essentially a Gm driven LDO, its impedance characteristics are both a

function of the 1/Gm and R_DS(on)of the sourcing MOSFET (see Figure 29). The current inflection point of the

design is between 3 A and 4 A. When I

is less than the inflection point, the LDO is considered to be

SRC

operating in the Gm region; when I_SRCis greater than the inflection point but less than the overcurrent limit point,

the LDO is operating in the R_DS(on)region. The typical sourcing R_DS(on)is 154 mΩ with V

= 3.0 V and T_J=

125°C.

1/Gm

Inflection

Point

1/R

DS(on)

(between

32AA and 34 AA))

Overcurrent

Limit

- Source Current - A

SRC

UDG-08026

Figure 29. TPS7H3301-SP Impedance Characteristics

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9.2.3 Application Curve

Figure 30. DDR2 2-A Load Vin 2.4 V 0.9 Vtt

10 Power Supply Recommendations

TPS7H3301-SP is designed to support DDR, DDR2, DDR3, DDR3L, and DDR4 VTT applications. TPS7H3301-

SP VLDOIN supports voltage range from 0.9 V to 3.5 V. The supply must be well regulated. Having a separate

VLDOIN and VDDQSNS allows designer to optimize system efficiency. Vin/VDD is used to bias the TPS7H3301-

SP IC and its voltage range is from 2.375 V to 3.5 V. This supply must be well regulated and bypassed with a

ceramic capacitor with a value of 1 µF and 10 µF. TI recommends that VLDOIN and VDDQSNS be isolated from

each other. If this is not possible then an RC filter must be used to isolated VLDOIN and VDDQNSS. However, in

so doing the dynamic tracking of VTT and VTTREF will be lost. See the user's guide SLVUAK2 for additional

details.

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11 Layout

11.1 Layout Guidelines

Consider the following points before starting the TPS7H3301-SP layout design.

•

The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide

connections.

The output capacitor for VO/VTT should be placed close to the pin with short and wide connection in order to

avoid additional ESR and/or ESL trace inductance.

VOSNS should be connected to the positive node of VO/VTT output capacitors as a separate trace from the

high current power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. If

sensing the voltage at the point of the load is required, it is recommended to attach the output capacitor or

capacitors at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace

between the GND pin and the output capacitor or capacitors.

•

Consider adding low-pass filter at VOSNS if the ESR of the VO/VTT output capacitor or capacitors is larger

than 2 mΩ.

VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference

voltage of VTTREF. Avoid any noise-generating lines.

The negative node of the VO/VTT output capacitor or capacitors and the VTTREF capacitor should be tied

together by avoiding common impedance to the high current path of the VO/VTT source/sink current.

The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias

connecting to the internal system ground planes (for better result, use at least two internal ground planes).

Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane.

Also, place bulk caps close to the DIMM load point, route the VOSNS to the DIMM load sense point.

•

In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly

to the package’s thermal pad. The wide traces of the component and the side copper connected to the

thermal land pad help to dissipate heat. Numerous vias 0.33 mm in diameter connected from the thermal land

to the internal/solder side ground plane or planes should also be used to help dissipation.

11.2 Layout Example

TPS7H3301

VTTREF = VDDQSNS / 2

VTTSNS

VTTREF

Cref

VDDQ

SNS

AGND

VTT / Vo

AGND

VTT/Vo

VLDOIN

VDDQ = VLDOIN

COUT

VTT/Vo 13

VLDOIN

C1N

VTT/Vo

POWER GOOD

PGOOD

VDD/Vin

PGND

3.3-V or 2.5-V Supply

ENABLE

CVin

PGND

AGND

Power Ground Plane

PGND

Figure 31. Layout Recommendation

TPS7H3301-SP

www.ti.com.cn

ZHCSEJ1 –DECEMBER 2015

11.3 Thermal Considerations

Because the TPS7H3301-SP is a linear regulator, the VO current flows in both source and sink directions,

thereby dissipating power from the device. When the device is sourcing current, the voltage difference between

VLDOIN and VO times IO (I_IO) current becomes the power dissipation as shown in Equation 2.

(

- V

x I

O _SRC

)

DISS _SRC

VLDOIN

(2)

In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power

loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power

dissipation, P_{DISS_SNK}can be calculated by Equation 3.

= V ´ I

VO O _SNK

DISS _SNK

(3)

Because the device does not sink and source current at the same time and the IO current may vary rapidly with

time, the actual power dissipation should be the time average of the above dissipations over the thermal

relaxation duration of the system. Another source of power consumption is the current used for the internal

current control circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less

during normal operating conditions. This power must be effectively dissipated from the package.

The thermal performance of an LDO depends on the printed circuit board (PCB) layout. Because the

TPS7H3301-SP device is shipped unformed, only the recommended heat pad pattern is shown. Lead pad

placement depends on final form factor.

To further improve the thermal performance of this device, using a larger than recommended thermal land as

well as increasing the number of vias helps lower the thermal resistance from junction to heat slug. TI

recommends that up to 48 (0.01 inch) thermal vias can be located under the device package.

TPS7H3301-SP

ZHCSEJ1 –DECEMBER 2015

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

5962-1422801VXC

5962R1422801VXC

TPS7H3301HKR/EM

ACTIVE

CFP

HKR

RoHS-Exempt

& Green

NIAU

N / A for Pkg Type

-55 to 125

25 to 25

5962-1422801VXC

TPS7H3301-SP

Samples

ACTIVE

HKR

RoHS-Exempt

& Green

NIAU

5962R1422801VXC

TPS7H3301-RHA

HKR

RoHS-Exempt

& Green

TPS7H3301HKREM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2022

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

HKR0016A

CFP - 2.416 mm max height

CERAMIC DUAL FLATPACK

9.88

9.38

METAL LID

PIN 1 ID

14X 1.27

11.26

10.76

(10.41)

2X 8.89

0.482

16X

0.382

(9.14)

0.2

C A B

METAL LID

2.416

1.850

0.177

0.097

(6.59)

1.04

0.84

25.142

24.642

HEATSINK

8.95

8.65

6.74

6.44

PIN 1 ID

4226020/C 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermetically sealed with a metal lid. Lid is connected to Heatsink.

4. The terminals are gold plated.

5. Falls within MIL-STD-1835 CDFP-F11A.

www.ti.com

EXAMPLE BOARD LAYOUT

HKR0016A

CFP - 2.416 mm max height

CERAMIC DUAL FLATPACK

(6.59)

(1.2) TYP

(0.6)

(1.2) TYP

(0.6)

(8.8)

PKG

(

0.2) TYP

(R0.05) TYP

PKG

HEATSINK LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

4226020/C 08/2022

www.ti.com

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TPS7H3301HKR/EM [TI]

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