TPS8802DCPR [TI]
民用烟雾报警器模拟前端 | DCP | 38 | -40 to 85;
| 型号： | TPS8802DCPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 民用烟雾报警器模拟前端 | DCP | 38 | -40 to 85 |
| 文件： | 总78页 (文件大小：2721K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS8802
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
TPS8802 烟雾报警器AFE
1 特性
2 应用
• 照相室AFE
• 烟雾和一氧化碳报警器
3 说明
– 双8 位可编程电流LED 驱动器
– LED 电流温度补偿
TPS8802 集成了双波光电烟雾报警器和一氧化碳(CO)
探测系统所需的所有调节器、放大器和驱动器。它的高
度灵活性非常适合精度和功耗至关重要的烟雾报警系
统。
– 用于光电二极管的超低失调电压运算放大器
– 可编程和可旁路增益级
• 一氧化碳传感器AFE
– 超低失调电压增益级
– 可编程增益和基准
• 喇叭驱动器
宽输入电压范围与低待机功耗和省电功能相结合，支持
使用单个锂原电池运行 10 年的电池寿命。TPS8802
还支持备用电池烟雾报警器，在主电源掉电或电池断开
连接时以无缝方式保持供电状态。
– 三端压电的自谐振驱动器
– PWM 支持两端压电语音
• 电源管理
器件信息(1)
– 用于外部微控制器的可编程LDO
– 用于喇叭、互连的升压转换器
• 多报警通信互连总线
• 超低功耗
封装尺寸（标称值）
器件型号
封装
TSSOP (38)
9.7mm x 4.4mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• I2C 串行接口
• 可编程电池测试负载
TPS8802
VLX
COO
CON
VBST
VCC
CO
Sensor
COP
VBAT
3-V Battery
PLDO
VINT
REF0P3
LEDLDO
PREF
VMCU
VBAT
Photo
Chamber
MCUSEL
PDP
PDN
PDO
Blue IR
VIN
ADC
AMUX
LEDEN
GPIO
GPIO
DINA
DINB
CSA
CSB
MCU
SCL
I2C
SDA
CSEL
HBEN
HORNFB
HORNSL
HORNBR
GPIO
Piezo Horn
GND
DGND AGND PGND
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
Table of Contents
8.4 Device Functional Modes..........................................40
8.5 Programming............................................................ 42
8.6 Register Maps...........................................................43
9 Application and Implementation..................................54
9.1 Application Information............................................. 54
9.2 Typical Application.................................................... 54
10 Power Supply Recommendations..............................62
11 Layout...........................................................................63
11.1 Layout Guidelines................................................... 63
11.2 Layout Example...................................................... 64
12 Device and Documentation Support..........................68
12.1 接收文档更新通知................................................... 68
12.2 支持资源..................................................................68
12.3 Trademarks.............................................................68
12.4 静电放电警告.......................................................... 68
12.5 术语表..................................................................... 68
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics..............................................21
7 Typical Characteristics................................................. 22
8 Detailed Description......................................................23
8.1 Overview...................................................................23
8.2 Functional Block Diagram.........................................24
8.3 Feature Description...................................................25
Information.................................................................... 69
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (March 2021) to Revision C (August 2021)
Page
• 更新了图 3-1 ......................................................................................................................................................1
• Updated 图8-4 ................................................................................................................................................ 29
• Added Connect a capacitor with a value between 1 µF and 100 µF to the LEDLDO. to 节8.3.4.2 ................ 30
• Updated VCCLOW description in 节8.6.2 .......................................................................................................44
• Updated 图9-1 ................................................................................................................................................ 54
• Updated 图9-10 .............................................................................................................................................. 59
Changes from Revision A (March 2020) to Revision B (March 2021)
Page
• Changed typical IMCULDO,Q based on measurement data...................................................................................6
• Changed typical ICO,Q based on measurement data.......................................................................................... 6
• Added requirement when enabling the boost converter and disabling the photo input amplifier......................33
Changes from Revision * (October 2019) to Revision A (March 2020)
Page
• 将文档状态从预告信息 更改为量产数据 ............................................................................................................ 1
• Added typical value to VPDIN,OFS ....................................................................................................................... 6
• Added typical value to VOFFS,CO ........................................................................................................................ 6
• Added typical value to VMUX,OFFS ...................................................................................................................... 6
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
2
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
5 Pin Configuration and Functions
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RESERVED
RESERVED
RESERVED
LEDLDO
AGND
REF0P3
PREF
COP
2
3
4
CON
5
COO
6
PDP
AMUX
DGND
LEDEN
HBEN
CSEL
SDA
7
PDN
8
PDO
9
CSA
10
11
12
13
14
15
16
17
18
DINA
CSB
DINB
SCL
Thermal
Pad
MCUSEL
HORNBR
HORNSL
HORNFB
PGND
GPIO
INT_MCU
INT_UNIT
VMCU
VINT
VLX
PLDO
VCC
VBST
19
20
图5-1. DCP Package 38-Pin TSSOP Top View
Pin Functions
PIN
NAME
AGND
AMUX
CON
I/O
DESCRIPTION
Analog ground. Connect to ground plane.
NO.
5
I
O
I
33
35
34
36
9
Analog multiplexer output.
Negative terminal of CO operational amplifier. Connect to GND if unused.
Output of CO operational amplifier. Connect to GND if unused.
Positive terminal of CO operational amplifier. Connect to GND if unused.
LED driver A current sense.
COO
O
I
COP
CSA
I
CSB
11
I
LED driver B current sense. Connect to GND if unused.
Device address select pin for I2C serial interface. Pull to GND for I2C address 0x3F. Pull to
VMCU for I2C address 0x2A. Do not leave floating.
CSEL
29
I
DGND
DINA
32
10
12
26
30
14
I
I
Digital ground. Connect to AGND.
LED driver A current sink. Connect to cathode of LED.
LED driver B current sink. Connect to cathode of LED. Connect to GND if unused.
Multi-purpose digital input and output.
DINB
I
GPIO
I/O
I
HBEN
HORNBR
Horn block enable. Do not leave floating while device is powered.
Brass terminal of piezo horn.
O
Feedback terminal of a three-terminal piezo horn. Do not leave floating while device is
powered.
HORNFB
16
I
HORNSL
INT_MCU
INT_UNIT
LEDEN
15
25
24
31
4
O
I/O
I/O
I
Silver terminal of piezo horn.
Interconnect and interrupt signal to microcontroller.
Interconnect bus to connect other smoke alarms.
LED driver enable. Do not leave floating while device is powered.
LDO output for charging LED supply capacitor. Connect to GND if unused.
LEDLDO
O
Default MCULDO and VBST voltage selection input. Leave floating for VMCU = 3.3 V, VBST
= 4.7 V. Tie to VINT for VMCU = 2.5 V, VBST = 3.8 V. Tie to GND for VMCU = 1.8 V, VBST =
2.7 V. Connect to GND with a 620-Ωresistor for VMCU = 1.5 V, VBST = 2.7 V.
MCUSEL
13
I
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
PIN
I/O
DESCRIPTION
NAME
PDN
NO.
7
I
O
I
Photo input amplifier negative input. Connect to cathode of photodiode.
Photo input amplifier output pin.
PDO
8
PDP
6
Photo input amplifier positive Input. Connect to anode of photodiode.
PGND
PLDO
PREF
REF0P3
RESERVED
SCL
17
21
37
38
1, 2, 3
27
28
19
20
22
18
23
39
I
Power ground connection to boost converter and horn driver. Connect to AGND.
Capacitor connection to PLDO regulator.
O
O
O
N/A
I
Photo reference voltage and output for testing CO sensor connectivity.
300mV reference. Connect to GND if unused.
Connect to GND.
Clock input for I2C serial interface.
SDA
I/O
I
Data line for I2C serial interface.
VBST
VCC
Boost converter feedback and power input.
Input supply pin.
I
VINT
O
I
Capacitor connection to internal supply LDO.
Boost converter switch node.
VLX
VMCU
Thermal Pad
I/O
N/A
LDO supply for external microcontroller and internal IO buffers.
Metal connection for thermal dissipation. Connect to ground plane.
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
–0.3
–0.3
–3
MAX
16.5
12
UNIT
Power IO
Analog IO
HORNSL, HORNBR, VBST, VCC
DINA, DINB, LEDLDO
V
V
V
V
Horn feedback HORNFB
6.5
Boost switch
VLX
16.5
–0.3
VINT + 0.3 or
3.6, whichever
is lower
Analog
connections
AMUX, CON, COO, COP, PREF, MCUSEL, PDO, REF0P3
V
V
V
V
–0.3
–0.3
–0.3
–0.3
PLDO + 0.3 or
3.6, whichever
is lower
LDO outputs
VINT, VMCU
CSA
DINA + 0.3 or
3.6, whichever
is lower
LED current
sense
DINB + 0.3 or
3.6, whichever
is lower
LED current
sense
CSB
Photo amplifier
inputs
PDN, PDP
PLDO
3.6
7.0
18
V
V
V
–0.3
–0.3
–0.3
PLDO voltage
Interconnect
bus
INT_UNIT
VMCU + 0.3 or
3.6, whichever
is lower
Digital IO
CSEL, GPIO, HBEN, INT_MCU, LEDEN, SCL, SDA
V
–0.3
-40
Max operating
ambient
temperature
TA
TJ
125
125
°C
°C
Max operating
junction
-40
temperature
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
Value
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 1
±3000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 2
±1500
1
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
2
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
3 V battery
VBAT
2.0
3.3
V
voltage
9 V battery
VBAT
6.0
10
V
voltage
Power supply
LED driver
VCC, VBST
DINA, DINB
2.6(1)
0
15.6
11.5
6
V
V
V
Horn feedback HORNFB
–2
Interconnect
INT_UNIT
bus
0
0
17
VMCU
3.6
V
V
V
Digital IO
INT_MCU, SCL, SDA, CSEL, LEDEN, HBEN, GPIO
Digital IO
supply
VMCU
TA
1.425
Ambient
temperature
85
85
°C
°C
–40
–40
Junction
temperature
TJ
(1) Device powers up with VCC < 2.6 V but is not parametrically guaranteed
6.4 Thermal Information
TPS8802
THERMAL METRIC(1)
DCP
38 PINS
29.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
20.0
10.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
10.0
ΨJB
RθJC(bot)
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
INPUT VOLTAGE AND CURRENTS
Power up threshold. Note:
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPWRUP
Device enters active state
when MCU_PG=1.
VCC rising
1.2
1.55
2.0
V
VPWRDOWN
VPWR, HYS
Power down threshold
VCC falling
0.932
6.4
1.15
400
2.0
V
VCC power up to power down
hysteresis
580
mV
PLDO voltage rising
Deglitch time
2.35
110
2.54
141
2.42
141
2.7
172
2.6
V
µs
V
VCC low warning reset
threshold
VVCCLOW, RISE
PLDO voltage falling
Deglitch time
2.15
110
VCC low warning assert
threshold
VVCCLOW, FALL
172
µs
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
6
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All blocks that can be
disabled are off, TJ=27C,
VCC=3V, VMCU=1.8V
3.8
4.4
µA
ISTANDBY
Standby Supply Current
All blocks that can be
disabled are off, TJ=27C,
VCC=9V, VMCU=3.3V
7.7
9.1
µA
POWER LDO
VCC = 2.0 V, IPLDO = 10 mA
VCC = 2.0 V, IPLDO = 30 mA
VCC = 3.3 V, IPLDO = 30 mA
VCC = 9 V, IPLDO = 30 mA
VCC = 11.5 V, IPLDO = 30 mA
1.93
1.8
3.1
4.1
4.1
1.96
1.89
3.22
4.9
1.99
1.95
3.3
V
V
V
V
V
VPLDO
Output Voltage
6.7
5
6.7
PLDO capacitor required for
stability
CPLDO
INTERNAL LDO
Output Voltage
0.7
1
1.3
µF
IVINT < 10 mA
2.25
2.25
2.3
2.3
2.35
2.40
V
V
IVINT < 10 uA, T>80C
No external/internal load,
VCC = 2.6 V - 11.5 V
DC Output Voltage Accuacy
Line Regulation
2
2
2
8
5
%
%
%
%
%
dB
–2
–2
–2
–8
–5
50
VCC = 2.6 V-11.5 V, IOUT =
10 mA
IVINT = 0 mA - 10 mA, VCC =
3 V
VINTLDO
Load Regulation
IVINT stepped from 0 mA to 10
mA in 1us
Transient regulation
PSRR
IVINT stepped from 10 mA to 0
mA in 1us
VIN = 3.0 V, IOUT = 10 mA, f =
60 Hz (200 mVpp)
IINTLDO, OUT
IINTLDO, SC
Output current range
0
10
mA
mA
Short Circuit Current Limit
30
280
52
1
500
From PLDO to VINT, IVINT
10 mA, PLDO = 2.2 V
=
VINTLDO, DO
Dropout Voltage
66
mV
Output Capacitor
0.7
1.3
µF
CINTLDO, OUT
Ceramic
ESR of Output Capacitor
100
mΩ
MCU LDO
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IMCULDO < 30 mA, VCC > 2.2
V, VMCUSET = 00 (T < 80°C
for no load)
1.425
1.5
1.575
V
IMCULDO < 10 uA, VCC > 2.2 V,
VMCUSET = 00, T > 80°C
1.425
1.71
1.71
2.38
2.38
3.13
1.5
1.8
1.8
2.5
2.5
3.3
1.65
1.89
1.98
2.63
2.75
3.47
V
V
V
V
V
V
IMCULDO < 30 mA, VCC > 2.6
V, VMCUSET = 01 (T < 80°C
for no load)
IMCULDO < 10 uA, VCC > 2.6 V,
VMCUSET = 01, T > 80°C
IMCULDO < 30 mA, VCC > 3.65
V, VMCUSET = 10 (T < 80°C
for no load)
Output Voltage(1)
VMCULDO
IMCULDO < 10 uA, VCC > 3.65
V, VMCUSET = 10, T > 80°C
IMCULDO < 10 mA, VCC > 3.65
V, VMCUSET = 11 (T < 80°C
for no load)
IMCULDO < 10 uA, VCC > 4.5 V,
VMCUSET = 11, T > 80°C
3.13
3.13
3.3
3.3
3.60
3.47
V
V
IMCULDO < 50 mA, VCC > 5.5
V, VMCUSET = 11
DC Output Voltage Accuracy T < 80°C
5
95
85
30
30
%
%
–5
75
65
0
VMCU rising
82
78
MCULDO power good
threshold
VMCULDO,PG
VMCU falling
%
VCC > 2.2 V, VMCUSET = 00
VCC > 2.6 V, VMCUSET = 01
mA
mA
0
IMCULDO
Output Current Range
VCC > 3.65 V, VMCUSET =
10
0
0
30
50
7
mA
mA
%
VCC > 4.5 V, VMCUSET = 11
IMCULDO stepped from 0 mA
to 10 mA in 1us, T < 80°C
–7
IMCULDO stepped from 0 mA
to 10 mA in 1us, T > 80°C
8
5
%
%
–8
–5
MCULDO load transient
regulation
VMCULDO, TR
IMCULDO stepped from 10 mA
to 0 mA in 1us, T < 80°C
IMCULDO stepped from 10 mA
to 0 mA in 1us, T > 80°C
8
%
–8
IMCULDO, SC
Short Circuit current limit
72
162
600
253
mA
CMCULDO = 1µF, time from
VMCU=0V to 90% of target
voltage
tMCULDO, PWR Power Up Time
1100
158
µs
µs
MCULDO power good
deglitch time
TMCULDO, PG
92
125
10
MCULDO low voltage error
mask time. MCULDO_ERR is
masked for
T_MCULDO,MASK after
VMCUSET or MCU_DIS is
changed.
TMCULDO,
ms
MASK
IMCULDO, Q
CMCULDO
Quiescent Current
Output Capacitor
IMCULDO = 0µA
Ceramic
2.04
1
3
10
µA
µF
0.7
ESR of Output Capacitor
100
mΩ
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
8
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pull-down resistance to set
VMCUSET[1:0]=00 on
powerup
558
620
682
Ω
Pull-down resistance to set
VMCUSET[1:0]=01 on
powerup
0
0
10
10
Ω
Ω
pF
MCUSEL component
requirements. Not tested in
production
RMCUSEL
Pull-up resistance to VINT to
set VMCUSET[1:0]=10 on
powerup
Capacitance to set
VMCUSET[1:0]=11 on
powerup
300
1000
DCDC BOOST REGULATOR
IBST < 50 mA, 2.0 V < VBAT <
2.5 V, VBST =
0000, BST_CLIM[3:0] = 1111
2.45
3.55
4.40
5.60
8.64
9.6
2.7
3.8
4.7
6
2.808
3.952
4.888
6.24
V
V
V
V
V
V
V
V
V
IBST < 50 mA, 2.0 V < VBAT <
3.5 V, VBST =
0001, BST_CLIM[3:0] = 1111
IBST < 50 mA, 2.0 V < VBAT <
4.0 V, VBST =
0010, BST_CLIM[3:0] = 1111
IBST < 50 mA, 2.0 V < VBAT <
5.2 V, VBST =
0011, BST_CLIM[3:0] = 1111
Boost minimum output
voltage. Load applied after
IBST < 30 mA, 2.0 V < VBAT <
voltage settles. Note: average 8.0 V, VBST =
VBST
9
9.36
output voltage depends on
ripple.
0100, BST_CLIM[3:0] = 1111
IBST < 30 mA, 2.0 V < VBAT <
9.0 V, VBST =
0101, BST_CLIM[3:0] = 1111
10
10.4
IBST < 30 mA, 2.0 V < VBAT <
9.5 V, VBST =
0110, BST_CLIM[3:0] = 1111
10.08
10.56
10.96
10.5
11
10.92
11.44
11.96
IBST < 30 mA, 2.0 V < VBAT <
10.0 V, VBST =
0111, BST_CLIM[3:0] = 1111
IBST < 30 mA, 2.0 V < VBAT <
10.5 V, VBST =
11.5
1000, BST_CLIM[3:0] = 1111
Boost minimum output
voltage. Load applied after
IBST < 20 mA, 2.0 V < VBAT <
VBST
voltage settles. Note: average 13.5 V, VBST =
14.4
15
15.6
V
output voltage depends on
ripple.
1001, BST_CLIM[3:0] = 1111
VBST rising
VBST falling
96
85
VBST, PG
Power good threshold
%
Output current when boost is VBST = 0000, VCC = VBST <
5
5
mA
mA
powering up. The boost
output current is limited when
VBST is below the specified
voltage.
2.7 V
IBST, PWRUP
VBST = 0001:1000, VCC =
VBST < 3.0 V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BST_CLIM[3:0] = 0000,
VCC=2.6 V
4
30
70
mA
BST_CLIM[3:0] = 0001,
VCC=2.6 V
18
18
40
50
75
90
mA
mA
BST_CLIM[3:0] = 0010, 2.6 V
< VCC < 3.65 V
BST_CLIM[3:0] = 0011
BST_CLIM[3:0] = 0100
BST_CLIM[3:0] = 0101
BST_CLIM[3:0] = 0110
BST_CLIM[3:0] = 0111
BST_CLIM[3:0] = 1000
BST_CLIM[3:0] = 1001
BST_CLIM[3:0] = 1010
BST_CLIM[3:0] = 1011
BST_CLIM[3:0] = 1100
BST_CLIM[3:0] = 1101
BST_CLIM[3:0] = 1110
BST_CLIM[3:0] = 1111
18
43
60
80
105
130
150
190
220
275
324
384
444
504
566
640
720
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
69
100
130
160
200
240
280
320
360
400
450
500
102
133
168
198
230
262
291
324
360
398
IBST, PEAK
Inductor peak current setting
Low-side MOSFET on
resistance
RDS, BST
VCC = 3.3 V
0
0.9
1.18
150
Ω
Standby current. Current
does not include bias block or IBST = 0, BST_EN=1.
8 MHz oscillator.
IBST,STANDBY
100
µA
Recommended external
capacitance
CBST
4.7
33
µF
µH
Recommended external
inductance
LBST
Recommended inductor DC
resistance
RIND, BST
TBST, PG
0.5
141
0.8
Ω
Boost power good deglitch
time
110
172
µs
Boost activity monitor delay
time—BST_nACT is set to 1
when the boost converter has
not switched for T_BST,ACT
while BST_EN=1. Not tested
in production.
T_BSTACT[1:0] = 00
T_BSTACT[1:0] = 01
T_BSTACT[1:0] = 10
0.1
0.9
9.4
0.156
1
0.2
1.1
TBST, ACT
ms
10
10.6
T_BSTACT[1:0] = 11
94
100
10
106
Boost converter BST_ERR
mask time. BST_ERR is
masked for TBST,MASK after
VBST or BST_EN is
changed.
TBST, MASK
ms
V
PHOTO CHAMBER INPUT STAGE AMPLIFIER
PAMP_EN=1, Feedback
network: 1.5M Ω, 10pF
VPDO
Output voltage range
0
0.5
fPDIN, BW
Unity Gain Bandwidth
Input Offset Voltage
1
5
MHz
µV
VPDIN, OFS
-530
-195
240
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
10
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50mV applied to PDP with
1.5MΩ series resistor. 1.5MΩ
resistor connects PDN to
PDO. Voltage measured
between 50mV and PDO.
VPDO, OFS
Output Offset Voltage
Chop Frequency
-10
10
mV
fPDIN, CHOP
2
MHz
µs
Feedback network: 1.5M Ω,
10pF. 1 nA to 10 nA applied
from PDN to PDP. 0V
reference
0
0
30
40
Input amplifier settling time.
Time between stepping the
current and measuring 90%
of the final value + 10% of the
initial value at PDO
TPDIN, SET
Feedback network: 1.5MΩ,
5pF. 1.5MΩ connected from
PDP to PREF. 1 nA to 10 nA
applied from PDN to PDP.
PREF_SEL=1
20
40
µs
Active current. Current does
not include bias block or 8
MHz oscillator.
IPDIN, ACT
175
210
µA
PHOTO CHAMBER GAIN STAGE AMPLIFIER
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
00
4.75
10.67
19.4
4.9
11
5.05
11.33
20.6
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
Closed Loop Gain
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
01
Slope (VAOUT_PH2
-
VAOUT_PH1)/(VSIG2-VSIG1).
Apply VSIG1 from PREF to
PDO and measure
AOUT_PH. Apply VSIG2 from
COTEST to PDO and
measure AOUT_PH
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
10
20
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
11
33.95
4.61
35
36.05
4.89
GPGAIN
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
00
4.75
10.4
18.5
Closed Loop Gain
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
01
Slope (VAOUT_PH2
-
10.09
17.94
31.28
10.71
19.06
33.22
VAOUT_PH1)/(VSIG2-VSIG1).
Apply VSIG1 from PREF to
PDO and measure
AOUT_PH. Apply VSIG2 from
PREF to PDO and measure
AOUT_PH
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
10
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
11
32.25
5
FPGAIN, BW
VPGAIN, OFS
Unity Gain Bandwidth
Input offset Voltage
1
8
5
MHz
mV
-6
Gain amplifier settling time.
Time between stepping the
PGAIN[1:0]=00. PDO
TPGAIN, SET
voltage and measuring 90% stepped from 3mV to 30mV.
of the final value + 10% of the PREF_SEL=0
initial value at AOUT_PH
1.8
40
2.522
70
µs
µA
V
1.0 V input voltage,
Active current. Current does
PGAIN[1:0] = 00, PGAIN_EN
not include bias block.
IPGAIN, ACT
= 1
LED LDO
LEDLDO output voltage
range
VLEDLDO
7.5
10
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
%
VLEDLDO,ACC LDO output accuracy
VLEDLDO, RES LED LDO output step size
I_LEDLDO = 0uA to 100uA
-5
5
0.5
3
V
ILEDLDO, OUT
ILEDLDO, Q
LDO output current limit
1
6
mA
Quiescent current. Current
does not include bias block.
31
60
µA
VBST=7V,
VBST=7V,
VLEDLDO, DROP LED LDO dropout voltage
ILEDLDO=100u ILEDLDO=100u
565
1000
mV
A
A
LED DRIVER A
NPDACA, RES
Resolution
8
Bits
mV
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
274
567
252
546
164
458
54
299
323
619
301
597
213
510
104
403
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
593
277
572
188
484
79
mV
mV
mV
mV
mV
mV
mV
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
VCSA
CSA output voltage
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
350
376
DAC step size
VPDACA, STEP INL
DNL
Settling Time
1.18
mV
LSB
LSB
µs
-10
10
1.5
5
-1.5
tPDACA, SET
1
TEMPCOA[1:0] = 00,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
0.174
0.208
0.346
0.520
0.347
0.521
0.624
1.039
1.560
mV/°C
mV/°C
mV/°C
mV/°C
TEMPCOA[1:0] = 01,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
0.416
0.693
1.040
CSA temperature
compensation coefficient
KPDACA, COMP
TEMPCOA[1:0] = 10,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
TEMPCOA[1:0] = 11,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
12
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=11,
PDAC_A[7:0]=0x28, TJ=27°C
(I_LED≈158mA, 0.8% temp
coefficient)
300
mV
Dropout voltage. Voltage
required between DINA and
CSA for current regulation.
VDINA, DROP
PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=01,
PDAC_A[7:0]=0x79, TJ=27°C
(I_LED≈507mA, 0.1% temp
coefficient)
500
550
mV
mA
IDINA
LED current
Resolution
0
LED DRIVER B
NPDACB, RES
8
Bits
mV
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
271
562
250
541
163
456
55
299
327
626
305
604
216
516
108
408
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
594
277
572
189
486
81
mV
mV
mV
mV
mV
mV
mV
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
VCSB
CSB output voltage
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
350
379
DAC step size
VPDACB, STEP INL
DNL
Settling time
1.18
mV
LSB
LSB
µs
-10
10
1.5
5
-1.5
tPDACB, SET
1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPCOB[1:0] = 00,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.174
0.347
0.521
mV/°C
TEMPCOB[1:0] = 01,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.208
0.346
0.520
0.416
0.693
1.040
0.624
1.039
1.560
mV/°C
mV/°C
mV/°C
CSB temperature
compensation coefficient
KPDACB, COMP
TEMPCOB[1:0] = 10,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
TEMPCOB[1:0] = 11,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=11,
PDAC[7:0]=0x28, TJ=27°C
(I_LED≈158mA, 0.8% temp
coefficient)
300
mV
Dropout voltage. Voltage
required between DINB and
CSB for current regulation.
VDINB, DROP
PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=01,
PDAC[7:0]=0x79, TJ=27°C
(I_LED≈507mA, 0.1% temp
coefficient)
500
550
mV
mA
IDINB
LED current
0
CO TRANSIMPEDANCE AMPLIFIER
RI, CO
CO input resistance
COSWRI = 1
0.7
1
1.5
kΩ
kΩ
COGAIN[1:0] = 00,
COSWRG = 1
770
1100
1430
COGAIN[1:0] = 01,
COSWRG = 1
210
350
560
0
300
500
800
390
650
1040
0.6
kΩ
kΩ
kΩ
V
RF, CO
CO feedback resistance
COGAIN[1:0] = 10,
COSWRG = 1
COGAIN[1:0] = 11, COSWRG
= 1
CO amplifier input voltage
(COP pin)
VIN, COP
VIN, CON
VOFFS, CO
VOUT, COO
ICO, Q
CO amplifier input voltage
(CON pin)
0
0.6
V
CO amplifier input offset
voltage
-130
0.1
94
300
2
µV
V
CO amplifier output voltage
(COO pin)
CO amplifier quiescent
current
0.63
2.1
µA
CO amplifier unity gain
bandwidth
fCO, BW
fCO, CHOP
RCOO
5
3.8
70
12
4
20
4.2
kHz
kHz
kΩ
CO amplifier chop frequency
CO amplifier output
resistance
COSWRO = 1
95
130
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
14
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COSWREF=1, COREF[1:0] =
00, TJ = 27°C
0.89
1.14
1.47
COSWREF=1, COREF[1:0] =
00, TJ = -40°C to 85°C
0.86
1.75
1.7
1.14
2.23
2.23
3.23
3.23
4.43
4.43
0.76
0.37
1.66
2.7
COSWREF=1, COREF[1:0] =
01, TJ = 27°C
COSWREF=1, COREF[1:0] =
01, TJ = -40°C to 85°C
2.95
4
CO amplifier reference
voltage
VCOPREF
mV
COSWREF=1, COREF[1:0] =
10, TJ = 27°C
2.6
COSWREF=1, COREF[1:0] =
10, TJ = -40°C to 85°C
2.55
3.45
3.4
4.24
5.38
5.48
1.1
COSWREF=1, COREF[1:0] =
11, TJ = 27°C
COSWREF=1, COREF[1:0] =
11, TJ = -40°C to 85°C
COTEST pull up FET
resistance
RCOTEST, PU
RCOTEST, PD
0.36
0.25
kΩ
kΩ
COTEST pull-down FET
resistance
0.82
INTERCONNECT
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 0.8 V
4
5
9
9
4
4
4
1
7.35
14.7
19.4
19.0
7.6
15
30
30
30
15
15
13
4
mA
mA
mA
mA
mA
mA
mA
mA
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 2.0 V
ISNK, INT_UNIT Interconnect sink current
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 6.0 V
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 10 V
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 0.8 V
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 2.0 V
7.6
ISRC, INT_UNIT Interconnect source current
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 6.0 V
7.0
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 10 V
1.6
INT_DIR = 0, INT_DEG[1:0] =
00
0
0.090
0.9
0
0.125
1
0.065
0.160
1.1
INT_DIR = 0, INT_DEG[1:0] =
01
tINT, DEG
Interconnect deglitch time
ms
uA
INT_DIR = 0, INT_DEG[1:0] =
10
INT_DIR = 0, INT_DEG[1:0] =
11
19.4
20
20.6
0.5
IINT, Q
Interconnect standby current INT_DIR = 0
0.25
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Interconnect input high
threshold voltage
VINT_UNIT, IHI
VINT_UNIT, IHI
VINT_UNIT, ILO
VINT_UNIT, ILO
INT_HYS = 0
1.3
2.0
2.7
V
Interconnect input high
threshold voltage
INT_HYS = 1
INT_HYS = 0
INT_HYS = 1
1.3
0.5
1.2
2.0
0.8
1.8
2.7
1.1
2.7
V
V
V
Interconnect low threshold
voltage
Interconnect low threshold
voltage
INT_HYS = 0
INT_HYS = 1
INT_PD=1
0.7
0.01
65
1.2
0.2
107
41
1.7
0.3
165
56
V
V
VINT_UNIT, HYS Interconnect input hysteresis
kΩ
MΩ
Interconnect input pulldown
RINT_UNIT, PD
resistance
INT_PD=0
3.5
HORN DRIVER
VBST = 11.5 V, IHORNSL = –
16 mA
VOH, HORNSL
VOL, HORNSL
HORNSL output high voltage
HORNSL output low voltage
11
11
11.3
0.1
V
V
V
V
VBST = 11.5 V, IHORNSL = 16
mA
0.5
VBST = 11.5 V, IHORNBR = –
16 mA
VOH, HORNBR HORNBR output high voltage
11.3
0.1
VBST = 11.5 V, IHORNBR = 16
mA
VOL, HORNBR
HORNBR output low voltage
0.5
20
VBST=11.5V, no load,
HORNSEL=0, HORNFB from
HORNSL rise time, 2 terminal 0 to VMCU. Time from
VHORNSL=1.15V to
tR, HORNSL2
10
10
10
10
ns
ns
ns
ns
VHORNSL=10.35V
VBST=11.5V, no load,
HORNSEL=0, HORNFB from
HORNSL fall time, 2 terminal VMCU to 0. Time from
VHORNSL=10.35V to
tF, HORNSL2
tR, HORNBR2
tF, HORNBR2
20
20
20
VHORNSL=1.15V
VBST=11.5V, no load,
HORNSEL=0, HBEN from 0
HORNBR rise time, 2
to VMCU. Time from
terminal
VHORNBR=1.15V to
VHORNBR=10.35V
VBST=11.5V, no load,
HORNSEL=0, HBEN from
HORNBR fall time, 2 terminal VMCU to 0. Time from
VHORNBR=10.35V to
VHORNBR=1.15V
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
from 0V to 3V. Time from
VHORNSL=1.15V to
VHORNSL=10.35V
tR, HORNSL3
HORNSL rise time, 3 terminal
2.9
2.3
5
5
µs
µs
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
tF, HORNSL3
HORNSL fall time, 3 terminal
from 3V to 0V. Time from
VHORNSL=10.35V to
VHORNSL=1.15V
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
16
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
from 3V to 0V. Time from
VHORNBR=1.15V to
HORNBR rise time, 3
terminal
tR, HORNBR3
3.1
5
µs
VHORNBR=10.35V
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
from 0V to 3V. Time from
VHORNBR=10.35V to
tF, HORNBR3
HORNBR fall time, 3 terminal
2.5
5
µs
VHORNBR=1.15V
Horn driver input high
voltage. HBEN and HORNFB
VBST = 11.5 V, HORNSEL =
0
VIH2, HORNFB
VIL2, HORNFB
0.35×VMCU
0.25×VMCU
0.7× VMCU
0.65×VMCU
V
V
Horn driver input low voltage. VBST = 11.5 V, HORNSEL =
HBEN and HORNFB
0
Horn driver output high delay
mismatch. Difference in
output delay between
HORNFB to HORNSL and
HBEN to HORNBR
HORNSEL=0, VBST=11.5V,
HORNFB and HBEN switch
from 0 to VMCU.
tSKEW,HIGH
0
0
1
2
10
10
ns
ns
Horn driver output low delay
mismatch. Difference in
output delay between
HORNFB to HORNSL and
HBEN to HORNBR
HORNSEL=0, VBST=11.5V,
HORNFB and HBEN switch
from VMCU to 0.
tSKEW,LOW
HORNSEL=0, VBST=11.5V,
HORNFB, HBEN=0,
HORN_EN=1. Current from
VBST, VCC pins measured
0
0
80.1
65
150
150
uA
uA
Horn driver quiescent
current. Current does not
include bias block.
IHORN,Q
HORNSEL=1, VBST=11.5V,
HORNFB=0, HBEN=1,
HORN_EN=1. Current from
VBST, VCC pins measured
ANALOG MULTIPLEXER
Multiplexer buffer input signal
voltage range
VMUX
AMUX_BYP=0
0.05
0.99
-8
2
1.01
8
V
GMUX, GAIN
VMUX, OFFS
Multiplexer bufffer output gain AMUX_BYP=0
1
V/V
mV
Multiplexer buffer offset
AMUX_BYP=0
voltage
-0.5
AMUX_BYP=0, AMUX_SEL
stepped from 000 to 011 with
PDO=2V, PAMP_EN=0. Time
until AMUX reaches 99% of
its final value
Multiplexer buffer enable
settling time
tMUX, EN
0
0
10
15
15
us
us
AMUX_BYP=0,
AMUX_SEL=011, PDO
stepped from 50mV to 2V,
PAMP_EN=0. Time until
AMUX reaches 99% of its
final value
Multiplexer buffer input step
settling time
tMUX, STEP
10
1
fMUX, BW
Multiplexer bandwidth
AMUX_BYP=0
AMUX_BYP=0
0.5
25
10
MHz
uA
IMUX, OUT
Multiplexer output current
–10
Multiplexer quiescent
current. Current does not
include bias block.
IMUX, Q
AMUX_BYP=0
8.3
50
uA
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Multiplexer buffer output
capacitor required for stability
CMUX
AMUX_BYP=0
150
1000
pF
BATTERY TEST
VBST = 4.5 V to 11.5
V, IBATTEST = 000
9.15
11.13
12.94
14.65
16.3
10
12
14
16
18
20
10.76
12.64
14.89
17.29
19.63
22.06
mA
mA
mA
mA
mA
mA
VBST = 4.5 V to 11.5
V, IBATTEST = 001
VBST = 4.5 V to 11.5
V, IBATTEST = 010
IBATTEST
Battery test load current.
VBST = 4.5 V to 11.5
V, IBATTEST = 011
VBST = 4.5 V to 11.5
V, IBATTEST = 100
VBST = 4.5 V to 11.5
V, IBATTEST = 101
17.96
Battery test rise time. Time
from enabling battery test
until 90% of target current is
reached
tBATTEST,RISE
VBST=10V, IBATTEST=101
VBST=10V, IBATTEST=101
10
10
us
us
Battery test fall time. Time
from disabling battery test
until 10% of initial current is
reached
tBATTEST,FALL
OSCILLATOR, REFERENCE SYSTEM
Oscillator frequency
fOSC8
8
MHz
%
Frequency accuracy
TA = -10°C to 70°C
TA = -10°C to 70°C
3
–3
Low-power Oscillator
32
kHz
frequency
fOSC32
Frequency accuracy
3
%
s
–3
TTIMEOUT
IREF0P3, Q
Error timeout time
0.9
1
1.1
VCC current difference
between REF0P3_EN=0 and
REF0P3=1. IREF0P3=0 µA
REF0P3 buffer quiescent
current
0.38
0.76
1.5
µA
nF
ms
REF0P3 output capacitor
required for stability
CREF0P3
0.7
1
1
From REF0P3 enabled to
99% of final output voltage.
CREF0P3=1nF, IREF0P3=0 µA
TREF0P3, SET
REF0P3 settling time
1.8
IREF0P3 = 10 µA
IREF0P3 = -25 µA
270
270
300
300
330
330
mV
mV
VREF0P3, OUT REF0P3 output voltage
VCC_LOW monitor quiescent
IVCCLOW,Q
current
0.9
2
uA
IO BUFFERS
LEDEN, CSEL, INT_MCU,
GPIO
VIO, ILO
VIO, IHI
IO buffer input low threshold
IO buffer input high threshold
0.3×VMCU
0.3×VMCU
0.7× VMCU
0.7× VMCU
V
V
LEDEN, CSEL, INT_MCU,
GPIO
LEDEN
HBEN
CSEL
100
100
100
nA
nA
nA
IO buffer input leakage
current
IIO, LEAK
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
18
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INT_MCU, GPIO. IIO = 3 mA,
VMCU = 1.8 V
0
0.19
0.6
V
VIO, OL
IO buffer output low-level
INT_MCU, GPIO. IIO = 1 mA,
VMCU = 1.5 V
0
0
0
0.20
0.30
0.37
0.6
0.6
0.6
V
V
V
INT_MCU, GPIO. IIO = -3 mA,
VMCU = 1.8 V
IO buffer output high-level.
Spec is the voltage drop from
VMCU (i.e. VMCU - VOH)
VIO, OH
INT_MCU, GPIO. IIO = -1 mA,
VMCU = 1.5 V
LEDEN, CSEL
HBEN
2
2
2
10
10
10
pF
pF
pF
CIN, IO
Input capacitance
INT_MCU, GPIO
IO buffer input pulldown
resistor
RIO,PD
INT_MCU, GPIO
0.8
10
50
MΩ
THERMAL WARNING
TWARNING
Thermal trip point
110
C
THERMAL SHUTDOWN
Thermal trip point
125
15
TSHTDWN
C
Thermal hysteresis
5
20
Thermal error mask time.
OTS_ERR is masked for
tOTS,MASK after device fully
powers up or OTS_EN set to
1
tOTS,MASK
300
350
us
I2C IO
VI2C,IL
VI2C,IH
Low-level input voltage
High-level input voltage
-0.5
0.3 × VMCU
V
V
0.7 × VMCU
Hysteresis of Schmitt trigger
inputs
VI2C,HYS
0.05 × VMCU
V
V
V
3 mA sink current; VMCU
>2V
0
0
0.4
VI2C,OL
Low-level output voltage
2 mA sink current; VMCU
< 2V
0.2 × VMCU
VOL = 0.4 V
VOL = 0.6 V
2.5
4
mA
mA
µA
pF
II2C,OL
Low-level output current
II2C,IN
Input current to each I/O pin 0.1VMCU < VI < 0.9VMCUmax
Capacitance for each I/O pin
-10
10
10
CI2C,IN
From VIHmin to VILmax
Standard-Mode
,
250
250
ns
ns
tI2C,OF
Output fall time
From VIHmin to VILmax, Fast-
Mode
Pulse width of spikes that
must be suppressed by the
input filter
tI2C,SP
0
50
ns
I2C BUS LINES
SCL clock frequency,
Standard-Mode
0
0
100
400
kHz
kHz
fSCL
SCL clock frequency Fast-
Mode
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
hold time (repeated) START After this period, the first
condition, Standard-Mode clock pulse is generated.
hold time (repeated) START After this period, the first
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
µs
tHD;STA
0.6
4.7
1.3
4
µs
µs
µs
µs
µs
condition, Fast-Mode
clock pulse is generated.
LOW period of the SCL clock,
Standard-Mode
tSCL ,LOW
LOW period of the SCL clock,
Fast-Mode
HIGH period of the SCL
clock, Standard-Mode
tSCL,HIGH
HIGH period of the SCL
clock, Fast-Mode
0.6
set-up time for a repeated
START condition, Standard-
Mode
4.7
0.6
µs
µs
tSU;STA
set-up time for a repeated
START condition, Fast-Mode
tHD;DAT
tHD;DAT
tHD;DAT
tHD;DAT
CBUS compatible masters
I2C-bus devices
5
0
0
0
µs
µs
µs
µs
data hold time, Standard-
Mode
CBUS compatible masters
I2C-bus devices
data hold time, Fast-Mode
data set-up time, Standard-
Mode
250
100
ns
ns
ns
tSU;DAT
data set-up time, Fast-Mode
rise time of both SDA and
SCL signals, Standard-Mode
1000
300
300
300
tI2C,RISE
rise time of both SDA and
SCL signals, Fast-Mode
20
ns
ns
ns
µs
µs
fall time of both SDA and SCL
signals, Standard-Mode
tI2C,FALL
fall time of both SDA and SCL
signals, Fast-Mode
20 × (VMCU /
5.5 V)
set-up time for STOP
condition, Standard-Mode
4
tSU;STO
set-up time for STOP
condition, Fast-Mode
0.6
bus free time between a
STOP and START condition,
Standard-Mode
4.7
1.3
µs
µs
tBUF
bus free time between a
STOP and START condition,
Fast-Mode
data valid time, Standard-
Mode
3.45
0.9
µs
µs
µs
tVD;DAT
data valid time, Fast-Mode
data valid acknowledge time,
Standard-Mode
3.45
tVD;ACK
data valid acknowledge time,
Fast-Mode
0.9
400
250
µs
pF
pF
capacitive load for each bus
line, Standard-Mode
CBUS
capacitive load for each bus
line, Fast-Mode
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
20
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
noise margin at the LOW
level
for each connected device
(including hysteresis)
VNL
VNH
0.1 × VMCU
V
noise margin at the HIGH
level
for each connected device
(including hysteresis)
0.2 × VMCU
V
(1) MCU LDO output voltage on power-up is determined by the MCUSEL pin state.
6.6 Typical Characteristics
TA = 27°C, VCC = 3.65 V
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
32
26
22
16
16
13
10
7
5
5
1
1
1
1
1
1
0
0
Current (µA)
Current (µA)
µ = 63.44 µA
N = 99 Units
σ= 1.13 µA
µ = 175.41 µA
N = 99 Units
σ= 3.25 µA
图6-2. Bias Block Current
图6-1. 8 MHz Oscillator Current
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
7 Typical Characteristics
TA = 27°C, VCC = 3.65 V
40
35
30
25
35
30
25
20
15
10
5
32
26
22
20
16
16
15
13
10
10
7
5
5
5
0
1
1
1
1
1
1
0
Current (µA)
Current (µA)
µ = 63.44 µA
N = 99 Units
σ= 1.13 µA
µ = 175.41 µA
N = 99 Units
σ= 3.25 µA
图7-2. Bias Block Current
图7-1. 8 MHz Oscillator Current
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
22
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8 Detailed Description
8.1 Overview
The TPS8802 integrates a boost converter, analog supply LDO, microcontroller supply LDO, photoelectric
chamber analog front end (AFE), carbon monoxide sensor AFE, interconnect driver, piezo horn driver, analog
multiplexer, and digital core. The high integration greatly reduces component count in smoke alarms and carbon
monoxide alarms. The TPS8802 can be powered from a variety of sources:
• 9-V battery
• 3-V battery
• 2-V to 15-V DC supply
• DC supply with battery backup
The two LED drivers have highly configurable temperature compensation to support IR and blue LEDs over a
wide range of currents. The wide bandwidth of the photo-amplifier saves power due to reduced LED on-time.
The CO amplifier has integrated gain resistors. The horn driver is compatible with two-terminal or three-terminal
piezo horns, and the three-terminal self-resonant mode is tunable to maximize piezo loudness. The wired
interconnection driver allows multiple smoke alarm units to communicate alarm conditions. Each block is highly
configurable with the digital core I2C interface, supporting on-the-fly adjustment of amplifier gains, regulator
voltages, and driver currents. Digital features such as sleep mode, under-voltage boost enabling, and one-time
boost charging are designed to reduce power consumption for the 10-year battery alarms. Configurable status
and interrupt signal registers alert the MCU of fault conditions such as under-voltage, over-temperature, and
interconnection alerts.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.2 Functional Block Diagram
BST_EN
VBST
VLX
VCC
Power LDO
Boost
PGND
Under-Voltage
Monitor
PLDO
To Digital Core
VBST
Horn Driver
PGND
VINT
HORNFB
HORNSL
HORNBR
VBST
Internal LDO
2.3V
HORN_SEL
HORN_EN
Battery Test
Load
VMCU
MCU LDO
1.5V to 3.3V
PGND
MCUSEL
LED Driver A
DINA
Temperature
Compensated
DAC
INT_UNIT
INT_MCU
INT_DIR
+
VBST
VINT
Interconnect
Interface
œ
CSA
PDAC_A
SCL
LED Driver B
DINB
SDA
CSEL
VMCU
I2C Interface
Temperature
Compensated
DAC
+
œ
CSB
PDAC_B
GPIO
HBEN
LEDEN
VINT
Digital Core
COTEST_EN
PREF_SEL
PREF
Photo Reference
and CO Test
DGND
Photo Amplifier
AMUX_SEL
AMUX_BYP
AOUT_PH
PDO
AMUX
AMUX
œ
COO
PDO
+
PDN
PDP
œ
CO Amplifier
COO
+
CON
COP
œ
+
VBST
REF0P3
REF0P3_EN
LEDLDO_EN
LEDLDO
300mV
Reference
LED LDO
AGND
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
24
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3 Feature Description
8.3.1 System Power-up
VCC<VPWRDOWN
Shutdown
Active
VCC>VPWRUP
INTLDO enabled
Registers loaded
Set BST_EN=1
Set VBST[0:3] =1h
Wait for BST_PG=1
BST_PG=1
MCUSEL sense
Write to VBST[0:3] and
VMCUSET[0:1]
Wait for VBST_PG=1
BST_PG=1
MCU_PG=1
Enable MCU LDO
Wait for MCU_PG=1
Power Up
图8-1. Power-up State Diagram
The TPS8802 can power-up from a battery above 2V connected to the input of the boost converter. This is
achieved with an automatic power-up sequence. When the VCC voltage exceeds the VPWRUP threshold, the
device initializes for 6 ms. After the initialization, the boost converter is enabled and set to 3.8V. In a 3V battery
powered system where VCC is connected to VBST, this raises the VCC and VBST voltage to provide power to
the internal digital and analog blocks. The VBST voltage must exceed the power-good threshold for the 3.8V
setting (typically 95% of its target voltage) for the power-up sequence to proceed. The MCUSEL pin is then
sensed for 2 ms to determine the MCULDO voltage and program the VMCUSET and VBST register accordingly.
表 8-1 indicates the VMCU and VBST setting for each MCUSEL configuration. After VBST reaches its power-
good threshold again, the MCULDO is enabled and the system waits for VMCU to reach its power-good
threshold (typically 85% of its target voltage). The device enters its active state after VMCU reaches its power-
good threshold. This sequence of events is outlined in 图8-1 and 图8-2.
If the boost converter is not being used, the same power-up sequence occurs, but the boost converter is not able
to raise the voltage higher than what is supplied. The minimum VCC and VBST voltage depends on the VMCU
voltage. If the MCUSEL pin sets VMCU to 1.5 V, 1.8 V, or 2.5 V, supply over 3.8V on VBST. If the MCUSEL pin
sets VMCU to 3.3 V, supply over 4.7 V on VBST. If VMCU is set to 1.5 V, 1.8 V, or 2.5 V, provide over 2.6 V to
VCC for power-up. If VMCU is set to 3.3 V, provide over 3.6 V to VCC for power-up. Higher VCC voltage may
required depending on the VMCU load current.
表8-1. VMCU and VBST Power-up Voltage
MCUSEL
VMCU (V)
VBST (V)
Connection
620-Ωto GND
Short to GND
Short to VINT
1.5
1.8
2.5
2.7
2.7
3.8
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-1. VMCU and VBST Power-up Voltage
(continued)
VMCU (V)
3.3
MCUSEL
Connection
VBST (V)
330-pF to GND
4.7
VBAT
VPWRUP
VBST_PG
VBST_PG
VBST
tBST_PG
tBST_PG
BST_PG
MCUSEL_EN
ttMCUSEL
t
VMCU
VMCULDO,PG
tMCULDO_PG
MCU_PG
图8-2. Power-up Timing Diagram
8.3.2 LDO Regulators
8.3.2.1 Power LDO Regulator
The power LDO is a voltage clamp that supplies many of the internal blocks in the TPS8802, including the
internal LDO and MCU LDO. Because the power LDO is designed to clamp the VCC voltage, it is not precise
and varies with VCC voltage and load. The power LDO shorts VCC and PLDO when the VCC voltage is below
approximately 5 V, and regulates VCC when VCC is above approximately 5 V. The power LDO has a dropout
voltage of approximately 1 V when it is regulating VCC. When the power LDO transitions from shorting to
regulating, the PLDO voltage drops by approximately 1 V. Connect a 1-µF capacitor to PLDO to stabilize the
PLDO voltage.
The power LDO is designed for use by the device and can be used to supply external circuitry that has a voltage
limit of 7 V. The power LDO can also be used to supply the IR or blue LED anode through a diode.
8.3.2.2 Internal LDO Regulator
The internal LDO (INT LDO) regulator powers the TPS8802 amplifiers and digital core with a stable 2.3 V supply.
Connect a 1-µF capacitor to VINT to stabilize the output. The INT LDO is always enabled when the device is
powered. The INT LDO can be used to supply external circuitry. It is not recommended to power noisy or
switching loads with INT LDO, as any noise on VINT couples to the internal amplifiers and can generate noise.
The INT LDO can be used in the CO connectivity test circuitry and the photo reference circuitry.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
26
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.2.3 Microcontroller LDO Regulator
The microcontroller LDO (MCU LDO) powers the internal digital input and output buffers (IO buffers) and
external MCU that controls and programs the TPS8802. Connect a 1-µF capacitor to VMCU to stabilize the
output. The MCU LDO can be programmed to output 1.5 V, 1.8 V, 2.5 V, and 3.3 V. The default MCU LDO
setting is determined by the configuration on the MCUSEL pin (see 表 8-1). After the device is powered, the
MCU LDO voltage can be changed using the VMCUSET register. The MCU LDO can also be disabled using the
MCU_DIS register.
The MCU LDO output VMCU powers the IO buffers on SCL, SDA, CSEL, INT_MCU, GPIO, LEDEN, HBEN, and
HORNFB. The IO buffers level shift signals from the digital core to a level suitable for the microcontroller and
signals from the microcontroller to a level suitable for the digital core. In general, connect VMCU to the
microcontroller supply voltage to guarantee logic level compatibility. If the MCU LDO is disabled, connect an
external supply to VMCU. This external supply can be a 3-V battery. Connecting a 3-V battery directly to VMCU
allows the MCU LDO to be disabled, saving some power in the system. When a 3-V battery is connected to
VMCU, set the MCU LDO to 1.5 V or 1.8 V on power-up. The battery voltage overrides the MCU LDO without
excess power draw.
The MCU LDO has a power good signal MCU_PG that indicates whether the MCU LDO is above 85% the
regulation voltage. A 125-µs deglitch filter prevents noise from affecting the MCU_PG signal. If MCU_PG is low
after 10 ms of changing the MCU LDO voltage or enabling the MCU LDO, the MCU_ERR flag is set high. If the
MCU_ERR flag is high and MCUERR_DIS is low, the MCU LDO fault state is entered. See 节 8.4.2.1 section for
more information.
8.3.3 Photo Chamber AFE
PDO
To AMUX
10 pF
1.5 Mꢀ
PDN
PDP
VINT
VINT
œ
+
PAMP_EN
+
To AMUX
PGAIN_EN
Photodiode
œ
PGAIN[1:0]
1.5 Mꢀ
10 pF
Photo Reference
5mV
1
0
Connect if
PGAIN set to
01, 10, or 11
+
50mV
œ
PREF_SEL
VINT
470 kꢀ
PGAIN_EN
PAMP_EN
PREF
To CO Amp
Test
图8-3. Photo Amplifier Circuit
The TPS8802 photo amplifier connects to a photoelectric chamber photodiode and has two stages—an input
stage and gain stage. When the photoelectric chamber LED is enabled, light scatters off smoke particles in the
chamber into the photodiode, producing a signal proportional to the smoke concentration. The output of each
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
photo amplifier stage is connected to the AMUX for ADC reading. This configuration provides high bandwidth
and dynamic range for the photodiode signal chain as the gain stage is on-the-fly adjustable.
8.3.3.1 Photo Input Amplifier
The input stage is a wide-bandwidth, low-offset op-amp designed for amplifying photodiode currents. In 图 8-3,
negative feedback causes the photodiode to conduct with zero voltage bias. The photo-current flows through
resistors connected from PDP to a reference (GND or PREF) and PDN to PDO. These two resistors determine
the gain of the input stage. The same value must be used for these two resistors because PDP and PDN
leakage is amplified by these resistors. Capacitors installed in parallel with the resistors compensate the op-amp
feedback loop for optimal response. The optimal compensation capacitance depends on the photodiode's
capacitance. The compensation capacitance should be adjusted to minimize settling time without having
overshoot on the output of the amplifier. Overshoot adds unnecessary noise in the output. The input stage
outputs through the PDO pin, which is internally connected to the integrated photo gain stage and AMUX. When
measuring the photo amplifier output, disable the boost converter to reduce the noise on the photo amplifier's
output.
The input stage has the option of being referenced to GND or PREF. PREF is a reference that is normally pulled
to VINT and is set to 50 mV when PREF_SEL = 1 and either PAMP_EN = 1 or PGAIN_EN = 1. The 50 mV
reference keeps the input amplifier in a linear operating region when no signal is applied, improving the speed
and zero-current sensitivity of the amplifier. It is generally recommended to set PREF_SEL=1 and connect the
external gain resistor and compensation capacitor to PREF. Connect a 100-pF filtering capacitor from PREF to
GND to reduce high frequency noise on PREF.
When measuring the photo amplifier output, it is recommended to take multiple ADC samples. Averaging ADC
samples approximately reduces the noise by the square root of the amount of samples. The power consumed in
a photoelectric smoke measurement is dominated by the LED power consumption, which is proportional to the
LED on-time multiplied by the LED current. To maximize the signal-to-noise ratio for a given power level, set the
LED pulse length to approximately twice the photo amplifier rise time and take multiple ADC samples while the
output is stabilized.
In systems where the compensation capacitor is selected for a slower rise time and lower noise, take multiple
ADC samples around the peak of the photo amplifier output.
8.3.3.2 Photo Gain Amplifier
The high-bandwidth, low noise photo gain amplifier connects to the output of the photo input stage to further
amplify the photodiode signal. The gain amplifier is adjustable on-the-fly using the I2C interface. The gain
amplifier has four settings:
• 5x (4.75x if PREF_SEL=1)
• 11x (10.4x if PREF_SEL=1)
• 20x (18.5x if PREF_SEL=1)
• 35x (32.3x if PREF_SEL=1)
The gain stage has the option of being referenced to GND or PREF with the PREF_SEL bit. When
PREF_SEL=1, a 5 mV reference offset counteracts the gain stage's input offset voltage to keep the gain stage
output above 50 mV. The 5 mV reference offset is amplified by the gain stage, causing the output to change
when the gain is changed, even when there is zero photo-current. It is recommended to connect a 470 kΩ
resistor from PREF to VINT if the gain is set to 11x, 20x, or 35x. This resistor changes the PREF voltage to 70
mV and prevents the output from dropping below 50 mV in worst-case conditions. Referencing the gain stage to
PREF causes the 50 mV reference to change with signal level due to the finite impedance of the reference.
Because the reference is changing with the signal level, the gain is slightly less with PREF_SEL=1.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
28
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.4 LED Driver
VBST
LEDLDO
IR LED
VBAT
Blue LED
LEDLDO
LEDLDO_EN
LEDLDO[0:2]
LED LDO
1 k
DINA
CSA
PLDO
Blue/IR
LED
TEMPCOA[1:0]
PDAC_A[7:0]
LED
DAC
+
–
100
F
GPIO[0:2]
R
CSA
PGND
0.1
To MCU
To MCU
GPIO
GPIO
Logic
IR LED
VBAT
Blue LED
LEDLDO
LEDEN
LEDPIN_EN
LEDSEL=0
1 k
DINB
CSB
Blue/IR
LED
PLDO
TEMPCOB[1:0]
PDAC_B[7:0]
LED
DAC
+
–
100
F
R
CSB
PGND
0.1
图8-4. LED Driver Circuit
8.3.4.1 LED Current Sink
The two LED drivers are current regulated, temperature compensated, and adjustable with an 8-bit DAC. When
the LED driver is enabled, the CSA voltage is regulated, and the current through the CSA resistor also flows
through the LED and the DINA pin. A current sense resistor connects to the CSA pin. The LED driver is enabled
with the LEDEN pin and LEDPIN_EN bit. Both the pin and bit must be high for the LED driver to operate. The
LEDSEL bit switches which driver the LEDEN signal connects to. The GPIO pin can be configured to enable
either LED driver.
The LED driver is temperature compensated to account for reduced LED intensity with increasing temperature.
Four temperature compensation settings are available to support a variety of IR and blue LEDs. Temperature
compensation is implemented by varying the CSA regulated voltage with temperature, thus the temperature
compensation also depends on the CSA resistor. Each temperature compensation setting has a different DAC
output at room temperature. To achieve a specific temperature compensation and current, the PDAC, TEMPCO,
and CSA resistor must all be adjusted according to the 节9.2.2.2 procedure.
The two LED drivers are interchangeable and support both IR and blue LEDs. The only difference between the
two LED drivers is a code CSA_BIN available to improve the LED A driver current accuracy for IR LEDs.
CSA_BIN in register 0x00 categorizes CSA voltage for each unit as close to the minimum, below average, above
average, or close to the maximum (see 节 8.6). Use CSA_BIN to adjust the DAC and compensate for the
variation on the LED A driver's current. After adjusting the DAC, the effective variation is reduced by a factor of 4
for the TEMPCOA = 11, PDAC_A = 00 setting. IR LEDs typically require the TEMPCOA = 11 temperature
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
compensation setting. Therefore, use the LED driver A for powering IR LEDs. If better accuracy is required,
calibrate the LED driver current by connecting the CSA or CSB pin to the microcontroller ADC port, measuring
the CSA or CSB voltage, and adjusting PDAC_A or PDAC_B until the required current is achieved.
Ensure that the LED current remains below 550 mA, the pulse width remains below 1 ms, and the duty cycle
remains below 1%. There is no protection to prevent operation outside these conditions. Ensure the PDAC and
TEMPCO registers are programmed before enabling the LED driver.
8.3.4.2 LED Voltage Supply
Enough voltage must be provided to the LED such that the DINA voltage is at least the dropout voltage
(VDINA,DROP) above the CSA voltage while the LED driver is enabled. Ensure the DINA voltage does not exceed
11.5 V. Because of the high LED drive currents, a large capacitor connected to the LED anode is required to
provide pulsed power to the LED. Any of the internal regulators ( PLDO, LEDLDO) or external supply (VBAT,
VDC) meeting the voltage requirements can be used to charge the LED capacitor. Depending on the LED
forward voltage, the LED anode can be connected to the battery or to the LEDLDO. Do not connect the LED
anode directly to VBST in low-power applications, because the boost converter output voltage can exceed the
DINA absolute maximum.
The LED LDO clamps the VBST voltage and blocks reverse current with an integrated diode. It is current limited
to prevent inrush current caused by charging the large capacitor. The regulation voltage is adjustable in the
LEDLDO register. The LED LDO may be operated with VBST below the regulation voltage. In this case, the
LEDLDO voltage stabilizes to VBST minus a diode voltage drop.
The LED driver current and rise time can vary by a few millivolts and microseconds across the LED anode
supply and VCC voltages. It is recommended to use a consistent LED anode voltage whenever the LED driver is
enabled. If the LEDLDO is used to supply the LED anode, ensure the boost converter is enabled to the same
voltage whenever the LEDLDO is enabled.
Connect a capacitor with a value between 1 µF and 100 µF to the LEDLDO.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
30
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.5 Carbon Monoxide Sensor AFE
To AMUX
COSWRO=1
RO=100 kꢀ
COO
CON
CO Connectivity Test
0.22 …F
COGAIN[1:0]
VINT
COSWRI=1
COSWRG=1
100 kꢀ
VINT
RI=1 kꢀ
œ
COAMP_EN
+
Working
COP
10 kꢀœ
100 kꢀ
CO
Sensor
100 kꢀ
REF0P3
REF0P3_EN
To MCU GPIO
Counter
COSWREF=1
COREF[1:0]
+
+
300 mV
œ
œ
PREF
To Photo Amp Reference
To Photo
Amp
For CO Connectivity Test
Use in place of pull-up resistor and
pull-down FET if PREF_SEL=0
VINT
200 kꢀ
COTEST_EN
COTEST_DIR
图8-5. Carbon Monoxide Detection Circuit Referenced to GND
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
To AMUX
COSWRO=1
RO=100 kꢀ
COO
CON
CO Connectivity Test
VINT
0.22 …F
COGAIN[1:0]
COSWRI=1
COSWRG=1
100 kꢀ
VINT
RI=1 kꢀ
œ
COAMP_EN
+
Working
COP
10 kꢀœ
100 kꢀ
CO
Sensor
100 kꢀ
REF0P3
REF0P3_EN
COSWREF=0
To MCU GPIO
Counter
+
+
COREF[1:0]
300 mV
1 nF
œ
œ
PREF
To Photo Amp Reference
To Photo
Amp
For CO Connectivity Test
Use in place of pull-up resistor and
pull-down FET if PREF_SEL=0
VINT
200 kꢀ
COTEST_EN
COTEST_DIR
图8-6. Carbon Monoxide Detection Circuit Referenced to 300mV
The TPS8802 CO AFE connects to an electrochemical CO sensor. The amplifier converts the microamps of
sensor current into a voltage readable by an ADC. This is achieved with a low-offset, low-power op-amp with
configurable input, gain, and output resistors.
8.3.5.1 CO Transimpedance Amplifier
The CO transimpedance amplifier is a low-offset, low-power op-amp with integrated input, gain, and output
resistors. Each of these resistors can be disconnected using the COSW register bits if using external resistors.
The input resistor limits amplifier current during a CO sensor connectivity test. The gain resistor amplifies the CO
sensor signal. Adjust the gain resistor by changing the COGAIN register bits. Use the output resistor with an
external capacitor to filter the CO amplifier output signal.
The CO amplifier has two integrated references. A programmable 1.25-mV to 5-mV reference COREF is
internally connected to the op-amp positive terminal. A 300-mV reference is connected to the REF0P3 pin. When
the millivolt reference is used, the CO sensor must be connected to GND. The millivolt reference is amplified to
offset the amplifier output above GND. When the 300 mV reference is used, the reference offsets the CO
amplifier output by 300 mV. In general, either reference can be used. The 300-mV reference offers better DC
accuracy at the cost of extra power consumption. The 300 mV reference is generated with a reference and op-
amp buffer for high precision. The REF0P3 pin must connect to a 1 nF capacitor for stability if it is enabled. The
buffer is designed to source and sink small currents as required by the CO amplifier. The 300 mV reference and
the 1.25 mV to 5mV reference cannot be enabled simultaneously.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
32
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
A resistor connected in parallel with the CO sensor prevents charge from accumulating across its terminals. The
output of the CO amplifier is connected to the COO pin for continuous monitoring and the AMUX for periodic
sampling.
8.3.5.2 CO Connectivity Test
The built-in CO connectivity test function connects to the PREF pin and is available when the photo amplifier is
not referenced to PREF. The COTEST_EN and COTEST_DIR register bits program a pull-up and pull-down
switch on PREF. A 200 kΩ pull-up resistor charges the 1 µF capacitor when the CO test is not in use. When
PREF is pulled low, charge is injected into the amplifier and the output pulse shape can be used to determine if
the sensor is connected. An external MOSFET and pull-up resistor achieves the same function as the internal
COTEST circuitry.
8.3.6 Boost Converter
33 ꢀH
VLX
To Battery
VBST_CLIM[3:0]
VBST[3:0]
4.7 ꢀF
DCDC
Boost
BST_EN
BST_CHARGE
BST_PG
Hysteretic
Controller
VBST
PGND
4.7 ꢀF
BST_nACT
To LED LDO, Battery Test,
Horn Driver, Interconnect
图8-7. DC to DC Hysteretic Boost Circuit
The boost converter operates with a wide range of input and output voltages to support multiple battery
configurations and driver voltages. The boost converter output VBST is internally connected to the LED LDO,
interconnect driver, horn driver, and battery test load, and may be externally connected to VCC. The boost
converter has a power-good register bit BST_PG to notify the MCU when the boost converter is above 95% of
the target voltage. The BST_PG signal is deglitched for 200 μs to prevent load transients from causing a false
indication. If the BST_PG signal is low after 10 ms of enabling the boost or changing the VBST setting, the
BST_ERR signal latches high. The BST_PG signal reads low if the boost converter is disabled.
The boost converter is enabled if any of the following conditions are met:
• BST_EN = 1 or BST_CHARGE=1, except if SLP_BST = 1 and SLP_EN = 1
• VCCLOW_BST = 1 and the deglitched VCCLOW comparator trips
• Device is in MCULDO_ERR state
The SLP_BST signal disables the boost while the device is in sleep mode if the boost is enabled with BST_EN.
The BST_CHARGE register bit enables the boost converter until the BST_PG signal is high, at which point
BST_CHARGE resets to 0 and the boost converter is disabled. VCCLOW_BST enables the boost if the
deglitched VCCLOW comparator trips. MCULDO_ERR state also enables the boost converter.
A specific I2C command sequence must be used when enabling the boost converter and disabling the photo
amplifier. Do not enable the boost converter (changing BST_EN from 0 to 1) and disable the photo input
amplifier (changing PAMP_EN from 1 to 0) in the same I2C command. Use either of the following I2C command
sequences to enable the boost converter and disable the photo input amplifier:
• Write BST_EN=1 and PAMP_EN=1, then write BST_EN=1 and PAMP_EN=0
• Write BST_EN=0 and PAMP_EN=0, then write BST_EN=1 and PAMP_EN=0
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.6.1 Boost Hysteretic Control
The hysteretic control guarantees stability across input and output voltages and has a fast transient response.
When the VBST voltage is below its target (as programmed in the VBOOST register), a charging cycle initiates
by enabling the VLX switch until the current through the inductor exceeds the programmable inductor peak
current setting. After the peak current is reached, the VLX switch is disabled and the inductor charges the VBST
output capacitor. The charging cycle completes when the inductor current reaches zero, and a new cycle initiates
when VBST drops again. Because of the hysteretic control scheme, the average output voltage varies
depending on the input voltage, inductor peak current, inductance, output capacitor, output voltage, and output
load.
When the VBST voltage is above the boost regulation voltage, the boost does not switch. In a battery backup
system, the battery draws no power if the DC supply is providing a VBST voltage above the boost regulation
voltage. The boost starts switching if the DC supply drops, drawing power from the battery to regulate VBST. A
timer, BST_nACT, monitors the time that the boost is not switching to notify the MCU if the boost is inactive. This
timer is programmable from 100 µs to 100 ms. This timer can be used to determine if the battery voltage is
higher than the regulation voltage or if an DC supply is connected.
The default inductor peak current is 500 mA. This sets the boost converter to provide maximum output current.
After the TPS8802 is powered, the peak current can be adjusted using the I2C interface to change the boost
switching frequency or to limit the battery current. The switching frequency is inversely proportional to the square
of the current limit. For example, changing the current limit from 500 mA to 50 mA causes the frequency to
increase by a factor of 100. The peak current determines how much current the boost converter can output. 方程
式1 calculates the maximum boost output current.
D × VBAT × IPEAK
IOUT max
:
=
;
2 × VBST
(1)
Typical boost efficiency is shown in 图 9-5. If the boost output current draw exceeds the maximum, the boost
voltage drops until the converter can supply the output current draw.
8.3.6.2 Boost Soft Start
When the boost converter is enabled and the VBST voltage is below 3 V, the peak inductor current is
automatically lowered to reduce inrush current. As a result, the boost converter cannot deliver full output current
while the VBST voltage is low. For the 2.7-V boost setting, the inductor current is released to the register value
when BST_PG = 1. Maintain the VBST load current below 5 mA during the soft-start period.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
34
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.7 Interconnect Driver
VBST
INT_EN
INTDIR
Enable
INT_EN
INT_DIR
INT_UNIT
VINT
INT_MCU
To MCU
Enable
+
Interconnect
Bus
To STATUS1
Register
Digital
Deglitch
INT_UNIT
œ
+
INT_HYS
INT_DEG
œ
INT_UNIT
Interrupt
STATUS_INT
Enable
INT_EN
INTDIR
INT_PD
图8-8. Interconnect Driver and Receiver
In mains-wired smoke alarm systems, the alarms can alert each other of smoke conditions with a wired
interconnect bus. The TPS8802 has a driver and comparator to interface with the interconnect bus. The driver
pulls the bus high when smoke is detected and low when smoke is cleared. The driver is current limited to
handle short circuit conditions, and has a diode on the high side driver to prevent the bus from driving VBST. The
hysteretic comparator senses when the bus is pulled high, filters the signal with a digital deglitch, and outputs
the result to the INT_MCU pin and STATUS1 register. The comparator output is synchronized with the 32 kHz
clock. The hysteresis has two settings and the deglitch is programmable from 0 ms to 20 ms. A 35-MΩ resistor
prevents the INT_UNIT pin from floating, and a switchable 100-kΩ resistor pulls down the bus to prevent
leakage from causing a false alarm. When the comparator outputs a high signal through the deglitch filter, the
INT_UNIT register bit is latched high in the STATUS1 register.
The INT_MCU pin has the additional function to output status interrupt signals. The STATUS_INT bit in the
MASK register enables interrupt signals to output through the INT_MCU pin. When the interconnect driver is
enabled, the interrupt signal output is disconnected to allow the microcontroller to drive the INT_MCU pin.
8.3.8 Piezoelectric Horn Driver
The horn driver is designed to drive two types of piezo horns: three-terminal self-resonant piezos and two-
terminal piezos. The HORN_SEL bit configures the horn driver for the three-terminal or two-terminal operation.
During operation, 120-kΩ pulldown resistors discharge any residual charge on the piezo element. Because
VBST powers the horn driver, the loudness of the horn can be adjusted by changing the VBST voltage with the
VBST register bits.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.8.1 Three-Terminal Piezo
HORNFB
5.6 Mꢀ
2.4 Mꢀ
1nF
0 kꢀ to 500 kꢀ
220 kꢀ (typ)
1 Mꢀ
VBST
0
1
HORNSL
HORN_THR
Horn Driver
Logic
HORN_SEL
1
VBST
HORNBR
HBEN
From MCU
0
3-terminal
enable
HORN_EN
HBEN
Driver
enable
HORN_SEL
HORN_EN
2-terminal
enable
HORN_SEL=0 for 2 Terminal Piezo
HORN_SEL=1 for 3 Terminal Piezo
图8-9. Three-Terminal Piezoelectric Horn Driver Circuit
In the three-terminal mode, the piezo silver and brass terminals connect directly to the HORNSL and HORNBR
pins, and the feedback terminal connects through a resistor-capacitor network to the HORNFB pin. The driver is
enabled and begins oscillating when the HORN_EN register bit and HBEN pin are set high. Adjust the value of
the resistor connected to the piezo feedback terminal to tune the oscillation frequency. Trial and error is required
to select this resistance. After the driver achieves resonant oscillation, the duty cycle of the HORNSL and
HORNBR outputs can be adjusted using the HORN_THR bits to maximize the loudness. It is recommended to
try each HORN_THR value and select the one that operates the horn closest to 50% duty cycle.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
36
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.8.2 Two-Terminal Piezo
HORNFB
From MCU
VBST
0
HORNSL
1 mH
1
HORN_THR
Horn Driver
Logic
HORN_SEL
1
VBST
HORNBR
HBEN
From MCU
0
3-terminal
enable
HORN_EN
HBEN
Driver
enable
HORN_SEL
HORN_EN
2-terminal
enable
HORN_SEL=0 for 2 Terminal Piezo
HORN_SEL=1 for 3 Terminal Piezo
图8-10. Two-Terminal Piezoelectric Horn Driver Circuit
In the two-terminal mode, the piezo connects to the HORNSL and HORNBR terminals through an inductor. The
HORNFB pin directly controls the HORNSL pin, and the HBEN pin directly controls the HORNBR pin. The two
drivers are matched to minimize skew between the two outputs. The MCU sends a digital signal to control the
driving voltage across the piezo. The signal can be a square wave of the oscillation frequency, a pulse width
modulation (PWM) sine wave of the oscillation frequency, or a PWM arbitrary shape for voice applications. The
inductor improves the rise time and fall time of the output and reduces power dissipation.
8.3.9 Battery Test
The battery test load is used to check the integrity of the battery connected to the TPS8802 device. When
enabled, a load is connected to VBST. The load is programmable from 10 mA to 20 mA with the I_BATTEST
register bits. This load emulates the horn driver current draw during an alarm condition. The boost input voltage,
output voltage, and efficiency affect the current drawn from the battery because the battery test load is
connected to VBST. Therefore, the battery current is programmable with the VBST register as well. Ensure
VBST is greater than 4.5 V when enabling the battery test load. The load is enabled with the BATTEST_EN
register bit or with the GPIO register bit and pin.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.10 AMUX
AMUX_BYP
AMUX_SEL[1:0]≠0
Hi-Z
VINT
0
1
To MCU
ADC
COO
10 kꢀ
AMUX
AMUX
AOUT_PH
PDO
2
1 nF
3
AMUX_BYP AMUX_SEL[1:0]
图8-11. Analog Multiplexer Circuit
The AMUX switch and buffer are used to connect the various TPS8802 amplifier outputs to a single ADC. The
unity-gain amplifier improves the drive strength and fidelity of the analog signals when connected to an ADC. A
330 pF to 1 nF capacitor must be connected to the AMUX pin to stabilize its output. The 10-kΩ resistor filters
high-frequency noise in the analog signal. Using a 10-kΩresistor and 1-nF capacitor reduces noise levels in the
photo amplifier signal. The buffer has the option of being bypassed to remove the added offset introduced by the
unity-gain amplifier. Because the AMUX requires the bias block (see 节 8.3.11), bypassing the buffer does not
eliminate the AMUX current consumption.
8.3.11 Analog Bias Block and 8 MHz Oscillator
A central analog bias block connects to many of the amplifiers, drivers, and regulators. This block is enabled
when any of its connected blocks are enabled. Similarly, an internal 8-MHz oscillator is enabled when the boost
converter or photo input amplifier is enabled. 表8-2 lists the conditions when the bias block and 8-MHz oscillator
are enabled. The bias block and 8-MHz oscillator consume current in addition to the connecting blocks whenever
they are enabled. Because the specified current consumption of each block does not include the bias block or
the 8-MHz oscillator, add the bias block and 8-MHz oscillator currents when calculating system power
consumption. Typical values of the bias block and 8-MHz oscillator current are shown in 节6.6.
表8-2. Conditions for Enabling the Bias Block and 8 MHz Oscillator
BLOCK
Photo input amplifier
Boost converter
AMUX buffer
CONDITION
BIAS ENABLED?
8-MHZ OSC ENABLED?
PAMP_EN = 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
BST_EN = 1
AMUX_SEL[0:2] ≠000
HORN_EN = 1
Horn driver
LED LDO
LEDLDO_EN = 1
PGAIN_EN = 1
Photo gain amplifier
Battery test load
LED driver
BATTEST_EN = 1
LEDEN = VMCU and
LEDPIN_EN = 1
Yes
Yes
No
No
Temperature monitor
OTS_EN = 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
38
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.3.12 Interrupt Signal Alerts
SLP_DONE
SLP_DONEM
VCCLOW
VCCLOWM
MCULDO_ERR
MCULDO_ERRM
OTS_ERR
Interrupt
Signal
To GPIO Logic
OTS_ERRM
OTS_WRN
To Interconnect Block
OTS_WRNM
BST_nACT
BST_nACTM
BST_ERR
BST_ERRM
图8-12. Interrupt Signal Alert Logic
Configurable interrupt signals notify the MCU when a system anomaly occurs. The interrupt signal indicates the
STATUS1 register, which has bits that latch high when reaching various condition limits such as temperature or
voltage. Each of the bits in the STATUS1 register can be independently configured to send an interrupt signal by
setting the MASK register bit corresponding to each STATUS1 bit. The GPIO bits must be set to 0x2 to output
interrupt signals through the GPIO pin, and the STATUS_INT bit must be set to 1 to output interrupt signals
through the INT_MCU pin. By connecting the GPIO or INT_MCU pin to the microcontroller, the MCU can be
immediately notified when a STATUS1 bit changes instead of having to repeatedly read the STATUS1 register.
After the device sends the interrupt signal, the signal remains high until the STATUS1 register is read, at which
point the fault clears if the error condition is removed.
Under some conditions the INT_MCU pin has other functions. If INT_EN = 1 and INT_DIR = 0, the INT_MCU pin
also outputs the INT_UNIT pin status. If INT_EN = 1 and INT_DIR = 1, the INT_MCU pin becomes an input to
control the INT_UNIT driver. See 节8.3.7 for more information.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.4 Device Functional Modes
8.4.1 Sleep Mode
Active
SLP_EN=1
Disable MCU LDO if SLP_MCU=1
Disable boost if SLP_BST=1
Disable high-current analog blocks if
SLP_ANALOG=1
Start sleep timer
Timeout
Set SLP_DONE=1
Set SLP_EN=0
Enable MCU LDO and boost
if previously enabled
Sleep Mode
图8-13. Sleep Mode State Diagram
The device integrates a sleep timer to manage critical analog and regulator blocks independent of the external
microcontroller. When sleep mode is enabled, the timer starts and various blocks (MCU LDO, boost, or drivers
and amplifiers) are disabled depending on the CONFIG1 register configuration. After the sleep timer finishes,
SLP_EN is reset and the SLP_DONE bit in STATUS1 register is latched high and can be configured to output
through the GPIO or INT_MCU pins. This notifies the microcontroller that the sleep timer is finished and sleep
mode is exited. Alternatively, sleep mode is exited by writing zero to the SLP_EN bit. Writing zero to SLP_EN
does not trigger the SLP_DONE bit in the STATUS1 register. 图8-14 shows the sleep mode state diagram.
Sleep mode reduces power consumption in three ways:
• by quickly disabling analog blocks
• by powering off the boost and MCU LDO during sleep mode
• by allowing the MCU to enter its lowest power idle state
Every I2C transaction takes time and consumes a small amount of power. The SLP_ANALOG bit configures
sleep mode to disable high-power amplifiers and drivers simultaneously when entering sleep mode. This
functionality can save several I2C transactions and reduces time that the amplifiers and drivers are idly enabled.
The device may require the boost converter and MCU LDO while the microcontroller is performing sensing and
testing operations, but may not require the boost and MCU LDO while the microcontroller is in its idle state.
SLP_BST and SLP_MCU disable the boost converter and MCU LDO during sleep mode. If the boost converter
and MCU LDO were previously enabled, they are re-enabled when sleep mode is exited. This process reduces
system current consumption caused by the MCU LDO and boost converter while preventing a system brown-out
if the MCU loses power, because the exit of sleep mode returns power to the MCU.
During sleep mode operation, the MCU can enter its lowest power idle state and monitor a GPIO pin for the
SLP_DONE interrupt signal. This monitoring allows the MCU clocks to be disabled as the sleep timer signals the
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
40
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
MCU to wake up after a precise programmed time. The amount of time is programmable from 1 ms to 65535 ms
in 1 ms intervals in the SLPTMR1 and SLPTMR2 registers.
The device is nearly fully functional in sleep mode. The microcontroller can access all registers and configure all
blocks. Only three functions are disabled in sleep mode:
• boost converter inactivity timer
• the MCULDO fault state
• over-temperature shutdown fault state
The MCULDO undervoltage and system over-temperature monitors remain enabled if the MCU LDO and OTS
monitors are enabled, so as soon as the device exits sleep mode, the system enters the fault state that
corresponds to any detected fault.
8.4.2 Fault States
Active
MCU_PG=0 after 10 ms
TJ>125°C after 300 µs
of enabling MCU LDO or
of enabling OTS_EN
changing VMCUSET
Set MCULDO_ERR=1
Set OTS_ERR=1
MCUERR_DIS=0
Enable temperature monitor
Disable amplifiers, drivers, boost,
and MCU LDO
Enable boost converter
Enable temperature monitor
Disable amplifiers and drivers
TJ>125°C
Start 1-second timer
Start 1-second timer
MCU_PG=0
Timeout
TJ>110°C
Timeout
Check TJ
Check MCU_PG
TJ<110°C
MCU_PG=1
Enable blocks if previously
enabled
Enable blocks if previously
enabled
No
Yes
Was OTS entered from MCU
LDO fault state?
Over-Temperature Shutdown
MCU LDO Fault
图8-14. Fault States Diagram
The TPS8802 device uses several monitors to alert the MCU when system irregularities occur. In addition to
alerting the MCU, two monitors cause the device to enter protective fault states:
• MCULDO under-voltage
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
• system over-temperature
The fault states reduce risk of damage and brown-outs to the system in the event of short circuits or other power
errors.
8.4.2.1 MCU LDO Fault
The MCU LDO has an undervoltage monitor to notify the MCU if the LDO falls out of regulation. This monitor is
enabled any time the MCU LDO is enabled and its status is in the MCU_PG register bit. A 125-μs deglitch time
rejects load and line transient spikes that may briefly drop the MCU LDO voltage below the under-voltage
threshold. If MCU_PG is low while the MCU LDO is enabled and it has been more than 10 ms since the LDO
was enabled or changed voltage, the MCU_ERR register bit latches high. When the MCU_ERR bit is set high
and the MCUERR_DIS bit is low, the MCU LDO fault state is entered.
Two scenarios can cause the LDO to drop voltage:
• input voltage (PLDO) drops
• load current exceeds the LDO current limit
If the input voltage drops, it can be because the boost converter is disabled. If the load current exceeds the LDO
current limit, the die temperature could exceed safe limits. The MCU fault state automatically enables the boost
converter and temperature monitor (OTS_EN) to handle both of these cases. The device disables all analog
blocks to prevent further issues caused by an underpowered MCU.
There are two methods to exit the fault state. Every second in the fault state, the MCU_PG register bit is
automatically read. If high, the fault state is exited. The MCU_ERR bit remains high until the STATUS1 register is
read. Alternatively, if the STATUS1 register is read and MCU_PG is high, the fault state is exited. When the
device exits the MCU_ERR fault state, the device re-enables all blocks that were enabled before the fault state
occurred.
If an over-temperature fault occurs while in the MCU LDO fault state, the device enters the over-temperature
fault state. The over-temperature fault state disables the MCU LDO and boost converter in addition to the blocks
that are disabled by the MCU LDO fault state. After the device exits the over-temperature fault state, it
immediately re-enters the MCU LDO fault state to confirm the MCU LDO status.
8.4.2.2 Over-Temperature Fault
An over-temperature shutdown (OTS) fault occurs if OTS_EN = 1 and the die temperature exceeds 125°C. The
fault is masked for 300 μs after setting OTS_EN = 1. OTS_EN must be enabled for at least 300 μs in order to
determine if the die has overheated. After the device detects an over-temperature condition, it disables all
drivers, amplifiers, and regulators and sets OTS_ERR to 1. This action prevents additional temperature stress
caused by a short circuit.
Similar to the MCU LDO fault, the device exits the OTS fault state with two methods:
• The device checks the die temperature once every second. If the temperature is below 110°C, the device
exits the fault state.
• Reading the STATUS1 register with the die temperature below 110°C exits the fault state.
When the device exits the OTS fault state, it re-enables all blocks that were enabled before the OTS fault
occurred.
8.5 Programming
The TPS8802 serial interface follows the I2C industry standard. The device supports both standard and fast
mode, and it supports auto-increment for fast reading and writing of sequential registers. A 33-kΩpullup resistor
connecting the SDA and SCL pins to VMCU is recommended for fast mode operation. The VMCU voltage
determines the logic level for I2C communication. The CSEL pin selects the device address. When CSEL is
pulled to GND, the device address is 0x3F. When CSEL is pulled to VMCU, the device address is 0x2A.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
42
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.6 Register Maps
表 8-3 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in 表
8-3 should be considered as reserved locations and the register contents should not be modified.
表8-3. Device Registers
Offset
0h
Acronym
REVID
Register Name
Device Information
Status 1
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
1h
STATUS1
STATUS2
MASK
2h
Status 2
3h
Interrupt Mask
Config 1
4h
CONFIG1
CONFIG2
ENABLE1
ENABLE2
CONTROL
SLPTMR1
SLPTMR2
GPIO_AMUX
CO_BATTEST
CO
5h
Config 2
6h
Enable 1
7h
Enable 2
8h
Control
9h
Sleep Timer 1
Sleep Timer 2
GPIO and AMUX
CO and Battery Test
CO Amplifier
Boost Converter
LED LDO
Ah
Bh
Ch
Dh
Eh
Fh
VBOOST
LEDLDO
10h
11h
12h
PH_CTRL
LED_DAC_A
LED_DAC_B
Photo Amplifier
LED DAC A
LED DAC B
Complex bit access types are encoded to fit into small table cells. 表 8-4 shows the codes that are used for
access types in this section.
表8-4. Device Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
RC
R
C
Read
to Clear
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.6.1 REVID Register (Offset = 0h) [reset = 0h]
REVID is shown in 表8-5.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
Return to Summary Table.
表8-5. REVID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
CSA_BIN
R
0h
CSA voltage bin for TEMPCOA=11, PDAC_A=00 setting
0h = CSA voltage between specified minimum and typical, closer to
minimum
1h = CSA voltage between specified minimum and typical, closer to
typical
2h = CSA voltage between specified maximum and typical, closer to
typical
3h = CSA voltage between specified maximum and typical, closer to
maximum
5-0
RESERVED
R
0h
Reserved
8.6.2 STATUS1 Register (Offset = 1h) [reset = 0h]
STATUS1 is shown in 表8-6.
Return to Summary Table.
表8-6. STATUS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLP_DONE
RC
0h
Sleep timer wakeup flag
0h = device has not transitioned from sleep to active state via timer
1h = device transitioned from sleep to active state via timer
6
5
VCCLOW
RC
RC
0h
0h
VCC low warning
0h = no VCCLOW error has occurred
1h = VCC below V_VCCLOW,FALL threshold and VCCLOW_DIS=1
for VCCLOW deglitch time. VCCLOW is masked for 1 ms after
VCCLOW_DIS is set to 0.
MCULDO_ERR
MCU LDO power good error
0h = no MCULDO error has occurred
1h = MCU_PG=0 and MCU_EN=1 for TMCULDO,PG.
MCULDO_ERR is masked for TMCULDO,MASK after VMCUSET or
MCU_DIS has changed
4
3
2
OTS_ERR
OTS_WRN
BST_nACT
RC
RC
RC
0h
0h
0h
Thermal shutdown error
0h = no thermal shutdown error has occurred
1h = junction temperature has exceeded T_SHUTDOWN
Thermal warning flag
0h = no thermal warning has occurred
1h = junction temperature has exceeded T_WARNING
Boost activity monitor
0h = boost converter is actively switching or BST_EN=0 or
SLP_EN=1
1h = boost converter has not switched for T_BST,ACT, BST_EN=1
and SLP_EN=0
1
0
BST_ERR
INT_UNIT
RC
RC
0h
0h
Boost converter power good error
0h = no boost converter error has occurred
1h = BST_PG=0 and BST_EN=1 for T_BST,PG. BST_ERR is
masked for T_BST,MASK after VBST or BST_EN has changed
INT_UNIT pin value
0h = INT_UNIT is below VINT_UNIT,ILO or INT_DIR=1
1h = INT_UNIT is high and INT_DIR=0
Copyright © 2023 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.6.3 STATUS2 Register (Offset = 2h) [reset = 0h]
STATUS2 is shown in 表8-7.
Return to Summary Table.
表8-7. STATUS2 Register Field Descriptions
Bit
7-2
1
Field
Type
Reset
Description
RESERVED
MCU_PG
R
0h
Reserved
R
0h
MCU LDO power good indicator
0h = MCU LDO is below power good threshold or MCU_DIS=1
1h = MCU LDO is above power good threshold and MCU_DIS=0
0
BST_PG
R
0h
Boost power good indicator
0h = VBST is below power good threshold or BST_EN=0
1h = VBST is above power good threshold and BST_EN=1
8.6.4 MASK Register (Offset = 3h) [reset = 0h]
MASK is shown in 表8-8.
Return to Summary Table.
表8-8. MASK Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLP_DONEM
R/W
0h
Sleep timer wakeup interrupt mask
0h = interrupt on device transition from sleep to active state
1h = no interrupt on device transition from sleep to active state
6
5
4
3
2
1
0
VCCLOWM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
VCC low warning interrupt mask
0h = interrupt on VCC low
1h = no interrupt on VCC low
MCULDO_ERRM
OTS_ERRM
OTS_WRNM
BST_nACTM
BST_ERRM
STATUS_INT
MCU LDO power good error interrupt mask
0h = interrupt on MCULDO power good error
1h = no interrupt on MCULDO power good error
Thermal shutdown error interrupt mask
0h = interrupt on thermal shutdown error
1h = no interrupt on thermal shutdown error
Thermal warning flag interrupt mask
0h = interrupt on thermal warning
1h = no interrupt on thermal warning
Boost activity monitor interrupt mask
0h = interrupt if boost has not switched for T_BSTACT
1h = no interrupt if boost has not switched for T_BSTACT
Boost converter power good error interrupt mask
0h = interrupt on BST_PG transition from 1 to 0 while BST_EN=1
1h = no interrupt on BST_PG transition from 1 to 0 while BST_EN=1
Status interrupt on the INT_MCU pin
0h = disable
1h = INT_MCU outputs high if any unmasked STATUS1 flags
8.6.5 CONFIG1 Register (Offset = 4h) [reset = 20h]
CONFIG1 is shown in 表8-9.
Return to Summary Table.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-9. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
INT_DEG
R/W
0h
INT_UNIT deglitch control
0h = none
1h = 125us
2h = 1ms
3h = 20ms
5
INT_PD
R/W
R/W
1h
0h
INT_UNIT pulldown resistor enable
0h = >1MOhm pulldown resistor on INT_UNIT
1h = 100k pulldown resistor on INT_UNIT
4-3
VMCUSET
MCU LDO voltage. Default value is set by MCUSEL on power-up.
0h = 1.5V
1h = 1.8V
2h = 2.5V
3h = 3.3V
2
1
SLP_BST
R/W
R/W
0h
0h
Disable boost converter in sleep mode
0h = boost converter unchanged in sleep mode
1h = boost converter disabled when SLP_EN is set to 1. Boost re-
enabled upon exiting sleep mode if previously enabled
SLP_ANALOG
Disable analog blocks in sleep mode. Set AMUX_SEL=000,
BATTEST_EN=0, HORN_EN=0, INT_EN=0, LEDLDO_EN=0,
PAMP_EN=0, PGAIN_EN=0 when SLP_EN is set to 1.
0h = analog blocks unchanged in sleep mode
1h = analog blocks shut off in sleep mode
0
SLP_MCU
R/W
0h
Disable MCULDO in sleep mode
0h = MCULDO unchanged in sleep mode
1h = MCULDO disabled in sleep mode. MCULDO re-enabled upon
exiting sleep mode if previously enabled
8.6.6 CONFIG2 Register (Offset = 5h) [reset = 2h]
CONFIG2 is shown in 表8-10.
Return to Summary Table.
表8-10. CONFIG2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
Reserved
RESERVED
RESERVED
INT_HYS
R
0h
6
R
0h
5
R/W
0h
Interconnect comparator hysteresis
0h = 1.2V hysteresis
1h = 0.1V hysteresis
4
HORN_SEL
HORN_THR
R/W
R/W
0h
0h
Horn block piezo select
0h = 2-terminal piezo
1h = 3-terminal piezo
3-2
Horn driver setting for three-terminal piezo duty cycle tuning
0h = -6%
1h = -3%
2h = Nominal
3h = +3%
Copyright © 2023 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-10. CONFIG2 Register Field Descriptions (continued)
Bit
Field
T_BSTACT
Type
Reset
Description
1-0
R/W
2h
Boost activity monitor alert time. BST_nACT flag goes high if the
boost converter has not switched for the set amount of time
0h = 100us
1h = 1ms
2h = 10ms
3h = 100ms
8.6.7 ENABLE1 Register (Offset = 6h) [reset = 10h]
ENABLE1 is shown in 表8-11.
Return to Summary Table.
表8-11. ENABLE1 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
BATTEST_EN
R
0h
Reserved
6
R/W
0h
Battery test enable
0h = disabled
1h = enabled
5
4
INT_EN
BST_EN
R/W
R/W
0h
1h
Control of interconnect interface
0h = disable
1h = enable
Boost converter control. See 节8.3.6 for the required I2C command
sequence when enabling the boost converter and disabling the photo
input amplifier.
0h = disabled
1h = boost converter enabled
3
2
PAMP_EN
PGAIN_EN
R/W
R/W
0h
0h
Photo input amplifier control
0h = amplifier disabled
1h = amplifier enabled
Photo gain amplifier control
0h = amplifier disabled
1h = amplifier enabled
1
0
RESERVED
LEDLDO_EN
R
0h
0h
Reserved
R/W
LED LDO control
0h = disabled
1h = enabled
8.6.8 ENABLE2 Register (Offset = 7h) [reset = 0h]
ENABLE2 is shown in 表8-12.
Return to Summary Table.
表8-12. ENABLE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LEDSEL
R/W
0h
LED input select
0h = LEDENA
1h = LEDENB
6
BST_CHARGE
R/W
0h
Enable boost while BST_CHARGE=1. When BST_PG=1, set
BST_CHARGE=0.
0h = boost controlled by BST_EN
1h = Boost is enabled until BST_PG=1. Boost remains enabled if
BST_EN=1.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-12. ENABLE2 Register Field Descriptions (continued)
Bit
5-4
3
Field
Type
Reset
Description
RESERVED
INT_DIR
R
0h
Reserved
R/W
0h
Interconnect direction control
0h = from INT_UNIT to INT_MCU
1h = from INT_MCU to INT_UNIT
2
1
0
LEDPIN_EN
HORN_EN
SLP_EN
R/W
R/W
R/W
0h
0h
0h
LEDEN pin enable
0h = LEDEN pin does not enable LED block
1h = LEDEN pin enables LED block
Horn block enable
0h = Horn block disabled
1h = HBEN enables horn block
Sleep timer enable
0h = sleep timer disabled, sleep mode is exited
1h = sleep timer initialized - SLP_DONE is set to 1 and SLP_EN is
set to 0 after sleep timer expires
8.6.9 CONTROL Register (Offset = 8h) [reset = 0h]
CONTROL is shown in 表8-13.
Return to Summary Table.
表8-13. CONTROL Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
MCU_DIS
R
0h
Reserved
R/W
0h
MCU LDO disable
0h = MCU LDO enabled
1h = MCU LDO disabled
4
3
2
VCCLOW_DIS
MCUERR_DIS
OTS_EN
R/W
R/W
R/W
0h
0h
0h
VCCLOW brown-out monitor disable
0h = VCCLOW monitor is enabled
1h = VCCLOW monitor is disabled
MCULDO error mode disable
0h = in case of MCULDO error, FAULT mode is entered
1h = disable entering FAULT mode in case of MCULDO error
Over-temperature shutdown mode disable
0h = disable entering over-temperature FAULT mode.
1h = in case of over-temperature, FAULT mode is entered and
OTS_ERR flag is raised.
1
0
SOFTRESET
R/W
R/W
0h
0h
Set registers to the default value
0h = do not reset registers
1h = reset all registers. SOFTRESET is reset. BST_EN,
BST_CHARGE, VBST, VMCUSET bits and STATUS1 register is
unchanged.
VCCLOW_BST
VCCLOW boost control
0h = boost controlled by BST_EN
1h = boost enabled if VCCLOW=1 or BST_EN=1
8.6.10 SLPTMR1 Register (Offset = 9h) [reset = 0h]
SLPTMR1 is shown in 表8-14.
Return to Summary Table.
Copyright © 2023 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-14. SLPTMR1 Register Field Descriptions
Bit
Field
SLPTMR
Type
Reset
Description
7-0
R/W
0h
Sleep timer most significant bits. See SLPTMR2 register for details
8.6.11 SLPTMR2 Register (Offset = Ah) [reset = 0h]
SLPTMR2 is shown in 表8-15.
Return to Summary Table.
表8-15. SLPTMR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SLPTMR
R/W
0h
Sleep timer duration. If SLPTMR is changed while SLP_EN=1, the
new sleep timer setting will apply the next time SLP_EN is enabled.
Sleep timer can be exited early if SLP_EN is written 0.
0000h = Sleep timer is disabled. If SLP_EN=1, then the sleep timer
is enabled when SLPTMR is changed.
0001h to FFFFh = 1 ms to 65535 ms
8.6.12 GPIO_AMUX Register (Offset = Bh) [reset = 0h]
GPIO_AMUX is shown in 表8-16.
Return to Summary Table.
表8-16. GPIO_AMUX Register Field Descriptions
Bit
Field
Type
Reset
Description
7
AMUX_BYP
R/W
0h
Analog multiplexer bypass
0h = analog multiplexer buffer is enabled when AMUX_SEL[1:0] !=
000
1h = analog multiplexer buffer is bypassed with a low-resistance
switch
6
RESERVED
AMUX_SEL
R
0h
0h
Reserved
5-4
R/W
Analog multiplexer input select
0h = AMUX off
1h = COO
2h = AOUT_PH
3h = PDO
3
RESERVED
GPIO
R
0h
0h
Reserved
2-0
R/W
Multi-purpose digital input and output
0h = Hi-Z
1h = TI Reserved
2h = output low if no status errors, high if any unmasked errors
3h = TI Reserved
4h = GPIO or LEDENA enables LED A
5h = GPIO or LEDENB enables LED B
6h = TI Reserved
7h = GPIO or BATTEST_EN enables battery test
8.6.13 CO_BATTEST Register (Offset = Ch) [reset = 0h]
CO_BATTEST is shown in 表8-17.
Return to Summary Table.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-17. CO_BATTEST Register Field Descriptions
Bit
Field
Type
Reset
Description
7
COSWRO
R/W
0h
CO amplifier output resistor (output of amplifier to COO pin) enable
0h = 0 Ohms
1h = 100 kOhms
6
COSWRG
R/W
0h
CO gain resistor (output of amplifier to inverting input of amplifier)
enable
0h = Hi-Z
1h = Resistance set by COGAIN register
5
4
COSWRI
R/W
R/W
0h
0h
CO input resistor (inverting input of amplifier to CON pin) enable
0h = 0 Ohms
1h = 1 kOhms
COSWREF
CO reference switch enable
0h = positive input of amplifier connected to COP
1h = positive input of amplifier connected to 1mV to 5mV COREF
3
RESERVED
I_BATTEST
R
0h
0h
Reserved
2-0
R/W
Battery test current
0h = 10mA
1h = 12mA
2h = 14mA
3h = 16mA
4h = 18mA
5h = 20mA
6h = Reserved
7h = Reserved
8.6.14 CO Register (Offset = Dh) [reset = 0h]
CO is shown in 表8-18.
Return to Summary Table.
表8-18. CO Register Field Descriptions
Bit
Field
Type
Reset
Description
7
REF0P3_EN
R/W
0h
300mV reference enable
0h = Buffer disabled
1h = Buffer enabled
6-5
4-3
COREF
R/W
R/W
0h
0h
Reference voltage for CO amplifier
0h = 1.25mV
1h = 2.5mV
2h = 3.75mV
3h = 5mV
COGAIN
CO amplifier feedback resistance
0h = 1100 kOhm
1h = 300 kOhm
2h = 500 kOhm
3h = 800 kOhm
2
1
COTEST_DIR
COTEST_EN
R/W
R/W
0h
0h
CO test output direction
0h = pull-down
1h = pull-up
Enable COTEST output on PREF
0h = disabled
1h = enabled
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
50
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-18. CO Register Field Descriptions (continued)
Bit
Field
COAMP_EN
Type
Reset
Description
0
R/W
0h
CO amplifier control
0h = disabled
1h = enabled
8.6.15 VBOOST Register (Offset = Eh) [reset = F2h]
VBOOST is shown in 表8-19.
Return to Summary Table.
表8-19. VBOOST Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BST_CLIM
R/W
Fh
Boost converter inductor peak current setting
0h = 30mA
1h = 40mA
2h = 50mA
3h = 60mA
4h = 80mA
5h = 100mA
6h = 130mA
7h = 160mA
8h = 200mA
9h = 240mA
Ah = 280mA
Bh = 320mA
Ch = 360mA
Dh = 400mA
Eh = 450mA
Fh = 500mA
3-0
VBST
R/W
2h
Boost converter output voltage setting. Default value is set during
power-up based on MCUSEL pin.
0h = 2.7V
1h = 3.8V
2h = 4.7V
3h = 6V
4h = 9V
5h = 10V
6h = 10.5V
7h = 11V
8h = 11.5V
9h = 15V
Ah = Reserved
Bh = Reserved
Ch = Reserved
Dh = Reserved
Eh = Reserved
Fh = Reserved
8.6.16 LEDLDO Register (Offset = Fh) [reset = 0h]
LEDLDO is shown in 表8-20.
Return to Summary Table.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
表8-20. LEDLDO Register Field Descriptions
Bit
7-4
3-1
Field
Type
Reset
Description
RESERVED
LEDLDO
R
0h
Reserved
R/W
0h
LED LDO settings
0h = 7.5V
1h = 8.0V
2h = 8.5V
3h = 9.0V
4h = 9.5V
5h = 10V
6h = Reserved
7h = Reserved
0
RESERVED
R
0h
Reserved
8.6.17 PH_CTRL Register (Offset = 10h) [reset = 0h]
PH_CTRL is shown in 表8-21.
Return to Summary Table.
表8-21. PH_CTRL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
TEMPCOB
R
0h
Reserved
6-5
R/W
0h
LED B Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
4-3
TEMPCOA
R/W
0h
LED A Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
2
PREF_SEL
PGAIN
R/W
R/W
0h
0h
Photo Reference setting
0h = Photo gain amplifier referenced to 0mV
1h = Photo gain amplifier and PREF pin connected to 50mV internal
reference
1-0
Photo Gain setting
0h = 5
1h = 11
2h = 20
3h = 35
8.6.18 LED_DAC_A Register (Offset = 11h) [reset = 0h]
LED_DAC_A is shown in 表8-22.
Return to Summary Table.
表8-22. LED_DAC_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PDAC_A
R/W
0h
LED DAC A setting
00h to FFh = 0mV to 300mV
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
52
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
8.6.19 LED_DAC_B Register (Offset = 12h) [reset = 0h]
LED_DAC_B is shown in 表8-23.
Return to Summary Table.
表8-23. LED_DAC_B Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PDAC_B
R/W
0h
LED DAC B setting
00h to FFh = 0mV to 300mV
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS8802 supports a variety of smoke alarm platforms:
• single-wave or dual-wave photoelectric smoke and CO detection
• 3-V battery, 9-V battery, or AC/DC supply with battery backup
• tone or voice alarm
9.2 Typical Application
33 μH
VBST
VLX
VBAT
VCC
0.1 μF
4.7 μF
3V Battery
4.7 μF
PLDO
VINT
PGND
1 μF
2.4 M
5.6 M
1 μF
VBAT
To MCU
HORNFB
HORNSL
1 nF
VMCU
1 μF
MCUSEL
Piezoelectric Horn
HORNBR
VBAT
1 k
INT_UNIT
INT_MCU
To MCU GPIO
VMCU
DINA
CSA
IR LED
47 μF
0.92
SCL
To MCU I²C
To MCU I²C
SDA
CSEL
DINB
CSB
Blue LED
6.8
To MCU GPIO
From MCU GPIO
To MCU GPIO
GPIO
47 μF
HBEN
LEDEN
To MCU
DGND
LEDLDO
PDO
To MCU
ADC Port
10 k
1 nF
AMUX
10 pF
VINT
0.22 µF
PDN
COO
100 k
1 µF
CON
COP
PDP
Photodiode
To MCU
GPIO
CO
Sensor
10 pF
VINT
REF0P3
470 k
PREF
Thermal Pad
AGND
RESERVED
图9-1. Dual-Wave Photoelectric Smoke and CO Alarm with Backup Battery
Copyright © 2023 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
9.2.1 Design Requirements
In this example, a smoke alarm requires the following:
• 100 MΩphotoamplifier transconductance with sub-nanoamp detection
• 100 mA IR LED current with 1-mA/°C temperature compensation
• 50mA blue LED current with 0.1mA/°C temperature compensation
9.2.2 Detailed Design Procedure
9.2.2.1 Photo Amplifier Component Selection
To meet the 100-MΩ photoamplifier transconductance requirement, set the gain stage to 35x with PGAIN = 11.
Because the application requires sub-nanoamp current detection, reference the photo amplifier to PREF and set
PREF_SEL = 1. This reference offsets the input stage output by 50 mV and offsets the gain stage output by 225
mV. Because the application uses PREF, the gain stage amplification reduces to 32.25x. Divide 100 MΩ by
32.25x to get 3.1 MΩ. The gain is distributed across two resistors, therefore use a resistor with a value of
approximately 1.55 MΩ. A 1.5-MΩ resistor is selected. The achieved transconductance is 96.8 MΩ. Use 10-pF
of compensation capacitance in parallel with the 1.5-MΩ resistors. Use an oscilloscope with averaging to verify
the photo amplifier is quickly settling but not overshooting. If the photo amplifier has overshoot, increase the
compensation capacitance. If the photo amplifier is settling slowly, decrease the compensation capacitance.
9.2.2.2 LED Driver Component Selection
The LED current depends on the TEMPCO bits, PDAC register and CSA and CSB resistors. Changing any of
these values affects the LED current and temperature compensation. The following method selects the
TEMPCO, PDAC, and CSA resistor value based on the required LED current and temperature compensation.
The 100-mA LED current and 1 mA/°C temperature compensation is used as an example for LED A. Repeat the
process for LED B.
1. Determine the room temperature current and temperature compensation required by the application.
• 100mA and 1mA/°C is required by the design.
2. Calculate the compensation in percentage per degree by dividing the compensation coefficient by the
current and multiplying by 100.
• 1 mA/°C divided by 100 mA is 1%/°C.
3. Use 表9-1 or 表9-2 to select a TEMPCO setting which contains the required compensation. If the required
compensation is in two ranges, use the range with a higher TEMPCO setting. If the required temperature
coefficient is not in any of the ranges, choose the TEMPCO and PDAC setting closest to the required
temperature coefficient, then go to step 5.
• 1%/°C is between the mimumum and maximum for TEMPCO = 11.
4. Calculate the target CSA voltage. Divide the driver temperature coefficient [mV/°C] by the desired
temperature coefficient [%/°C] and multiply by 100.
• 1.040 mV/°C divided by 1 %/°C is 104 mV.
5. Calculate the CSA resistor by dividing the target CSA voltage by the required current and subtracting 0.1 Ω
for internal resistance.
• 104 mV divided by 100 mA is 1.04 Ω. Subtract 0.1 Ωto get 0.94 Ω.
6. Select the closest available resistor and calculate the final CSA voltage by multiplying the required current by
the total resistance (external and internal).
• Use a 0.92 Ωresistor. Multiply 100 mA and 1.02 Ωto get 102mV CSA voltage.
7. Calculate the PDAC value by subtracting the final CSA voltage by the specified CSA voltage at PDAC =
0x00 and dividing the result by 1.176 mV (the DAC LSB, equal to 300 mV divided by 255).
• 102 mV minus 79 mV is 23 mV, divided by 1.176 mV is 20. Write 0x14 to the PDAC register.
8. Calibrate the PDAC value. If using the LED A driver, read the CSA_BIN register bits and add 0x11 if
CSA_BIN=00b, add 0x06 if CSA_BIN=01b, subtract 0x06 if CSA_BIN=10b, or subtract 0x11 if
CSA_BIN=11b. The CSA_BIN value varies from unit to unit and must be read on each unit calibrated using
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
this method. Alternatively, measure the CSA or CSB voltage using the MCU ADC and adjust PDAC
accordingly.
• The microcontroller reads that a unit has CSA_BIN=01b. 0x20 is written to PDAC_A.
表9-1. Temperature Coefficients for Each TEMPCOA and DAC_A Setting
CSA Voltage [mV],
T = 27°C
Temperature Coefficient Temperature Coefficient
Register Setting
Coefficient Information
Max for TEMPCO = 11b
Min for TEMPCO = 11b
Max for TEMPCO = 10b
Min for TEMPCO = 10b
Max for TEMPCO = 01b
Min for TEMPCO = 01b
Max for TEMPCO = 00b
Min for TEMPCO = 00b
[mV/°C]
[%/°C]
TEMPCOA[1:0] = 11,
PDAC_A = 0x00
79
1.040
1.316%
TEMPCOA[1:0] = 11,
PDAC_A = 0xFF
376
188
484
277
572
299
593
1.040
0.693
0.693
0.416
0.416
0.347
0.347
0.277%
0.369%
0.143%
0.150%
0.073%
0.116%
0.059%
TEMPCOA[1:0] = 10,
PDAC_A = 0x00
TEMPCOA[1:0] = 10,
PDAC_A = 0xFF
TEMPCOA[1:0] = 01,
PDAC_A = 0x00
TEMPCOA[1:0] = 01,
PDAC_A = 0xFF
TEMPCOA[1:0] = 00,
PDAC_A = 0x00
TEMPCOA[1:0] = 00,
PDAC_A = 0xFF
表9-2. Temperature Coefficients for Each TEMPCOB and DAC_B Setting
CSB Voltage [mV], T =
27°C
Temperature Coefficient Temperature Coefficient
[mV/°C] [%/°C]
Register Setting
Coefficient Information
TEMPCOB[1:0] = 11,
PDAC_B = 0x00
81
1.040
1.040
0.693
0.693
0.416
0.416
0.347
0.347
1.284%
0.272%
0.369%
0.143%
0.150%
0.073%
0.116%
0.059%
Max for TEMPCO = 11b
TEMPCOB[1:0] = 11,
PDAC_B = 0xFF
379
189
486
277
572
299
594
Min for TEMPCO = 11b
Max for TEMPCO = 10b
Min for TEMPCO = 10b
Max for TEMPCO = 01b
Min for TEMPCO = 01b
Max for TEMPCO = 00b
Min for TEMPCO = 00b
TEMPCOB[1:0] = 10,
PDAC_B = 0x00
TEMPCOB[1:0] = 10,
PDAC_B = 0xFF
TEMPCOB[1:0] = 01,
PDAC_B = 0x00
TEMPCOB[1:0] = 01,
PDAC_B = 0xFF
TEMPCOB[1:0] = 00,
PDAC_B = 0x00
TEMPCOB[1:0] = 00,
PDAC_B = 0xFF
Use the same procedure for the blue LED, requiring 50 mA and 0.1 mA/°C, to calculate TEMPCOB = 10, RCSB
= 6.8 Ω, VCSB = 345 mV, PDAC_B = 0x85 (before calibration).
The two drivers are identical, except for the CSA_BIN code to improve the accuracy of the LED_A driver for IR
LEDs. Connect the IR LED to the LED A driver and the blue LED to the LED B driver in multi-wave systems.
9.2.2.3 LED Voltage Supply Selection
Each of the LED anodes must have enough voltage to forward bias the LED, regulate the CSA and CSB voltage,
and exceed the driver dropout voltage requirement from DINA to CSA and DINB to CSB. A typical IR LED at 100
mA has 1.5-V forward voltage. The LED driver dropout voltage at 100 mA is 300 mV. With the CSA voltage set
to 100 mV, the dropout voltage of 300 mV, and forward voltage of 1.5 V, at least 1.9 V must be applied to the IR
LED anode for current regulation. Connect the IR LED anode to the LEDLDO. Enable the boost converter set to
Copyright © 2023 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
2.7 V and enable the LED LDO to charge the IR LED anode capacitor. Alternatively, the IR LED anode can be
connected to PLDO through a diode.
A typical blue LED at 50 mA has 4 V forward voltage. For the blue LED, the CSB voltage is 340 mV, the dropout
voltage is 300 mV, and the forward voltage is 4 V. Supply over 4.64 V to the anode for the duration of the LED
pulse. With a 47 µF capacitor derated to 30 µF, 100 µs LED pulse, the anode voltage drops by 170 mV. Thus,
the capacitor must be charged to 4.81 V. Enable the boost converter set to 6 V and enable the LED LDO to
charge the blue LED anode capacitor. The LED LDO has a diode voltage drop between the VBST voltage and
LEDLDO voltage. The LEDLDO prevents the DINA pin from exceeding its recommended operating limit of 11.5
V.
9.2.2.4 Boost Converter Component Selection
A 4.7-μF, 16-V or 25-V, X5R or X7R capacitor is recommended on VBST. This value provides the best tradeoff
between boost ripple and power loss (from charging and discharging VBST).
A 4.7-μF X5R or X7R capacitor rated for the battery voltage is recommended to be connected to the battery.
This capacitor provides a low-impedance supply for the inductor when the boost converter is rapidly switching.
A 33-μH inductor rated for 700 mA of saturation current with less than 800 mΩ of DC resistance (DCR) is
recommended. Smaller DCR improves the efficiency of the boost converter. Comparing 800 mΩ to 400 mΩ,
approximately 3% efficiency improvement is expected.
表9-3. Recommended Inductors for Boost Converter
PART NUMBER
SUPPLIER
VALUE
33 μH
33 μH
ISAT (A)
DIMENSIONS
DCR (Ω)
SDR0503-330KL
Bourns
0.38
0.85
5.0mm × 4.8mm x 3.0mm
4.0mm x 4.0mm x 1.8mm
NRS4018T330MDGJV
Taiyo Yuden
0.552
0.70
A Schottky diode with low forward voltage and low leakage current is recommended. Ensure the leakage is low
enough to prevent battery recharging issues.
表9-4. Recommended Diode for Boost Converter
PART NUMBER
SUPPLIER
SIZE
MBR0520LT1
ON Semiconductor Corp.
SOD-123
9.2.2.5 Regulator Component Selection
To stabilize the output voltage on each regulator, install 1-µF capacitors on VINT, VMCU, and PLDO. Connect
the MCUSEL pin to GND to set the MCU LDO voltage to 1.8V. The MCU LDO can be set to other voltages by
changing the MCUSEL pin connection. Connect the MCUSEL pin to GND through a 1 nF capacitor to set the
MCU LDO voltage to 3.3 V. Connect MCUSEL to VINT to set the MCU LDO to 2.5 V. Connect MCUSEL to GND
with a 620-Ωresistor to set the MCU LDO to 1.5 V.
9.2.3 Application Curves
All curves use the schematics shown in 图 9-1. The photo amplifier curves do not have the 470 kΩ PREF
resistor installed.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
图9-2. Power-up Waveforms
图9-3. Boost Soft-Start
78
76
74
72
70
68
VBAT=2V, 10mA Load
VBAT=3V, 10mA Load
图9-4. 15V AC/DC Supply with Battery Backup
Handoff
2
4
6
8 10
VBST (V)
12
14
16
图9-5. Boost Converter Efficiency
图9-6. LED Driver and Photo Amplifier Waveforms 图9-7. LED Driver and Photo Amplifier Waveforms
with 128 Averages
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
58
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
图9-9. 3-Terminal Horn Driver Waveforms
图9-8. Carbon Monoxide Amplifier Waveforms with
Calibration Gas
9.2.4 3V Battery Smoke and CO Alarm
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
33 μH
4.7 μF
VBST
VLX
VBAT
VCC
0.1 μF
3V Battery
4.7 μF
PLDO
PGND
1 μF
VINT
2.4 M
5.6 M
1 μF
VBAT
HORNFB
HORNSL
1 nF
To MCU
VMCU
1 μF
MCUSEL
Piezoelectric Horn
HORNBR
VBAT
1 k
INT_UNIT
INT_MCU
To MCU GPIO
DINA
CSA
VMCU
IR LED
47 μF
0.92
SCL
To MCU I²C
To MCU I²C
SDA
CSEL
DINB
CSB
Blue LED
6.8
GPIO
To MCU GPIO
From MCU GPIO
To MCU GPIO
47 μF
HBEN
LEDEN
To MCU
DGND
LEDLDO
PDO
To MCU
ADC Port
10 k
1 nF
AMUX
10 pF
VINT
0.22 µF
PDN
COO
100 k
1 µF
CON
COP
PDP
Photodiode
To MCU
GPIO
CO
Sensor
10 pF
VINT
REF0P3
470 k
PREF
Thermal Pad
AGND
RESERVED
图9-10. 3-V Battery Smoke and CO Alarm
9.2.4.1 Design Requirements
In this example, a smoke alarm requires the following:
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
60
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
• 100 MΩphotoamplifier transconductance with sub-nanoamp detection
• 100mA IR LED current with 1mA/°C temperature compensation
• 50mA blue LED current with 0.1mA/°C temperature compensation
• 10-year battery life with 3V lithium primary battery
9.2.4.2 Detailed Design Procedure
In this application, a 3V battery is the only power source. The 3V battery is used to directly power the IR LED
and the MCU, saving power. The MCU LDO can be disabled after power-up. Ensure the MCU and IR LED can
operate over the range of voltages supplied by the battery.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
10 Power Supply Recommendations
These power sources, among others, can power the TPS8802 device:
• 3-V lithium battery
• 9-V battery
• two 1.5-V batteries
• an AC/DC supply
When the boost converter is used, the power supply must be able to supply 650-mA peak current to the boost
converter. Ensure that the power supply voltage does not drop below 2 V during the initial powerup sequence. A
rise time less than 1 ms may cause VBST to overshoot due to LC ringing. Ensure the power supply's rise time is
less than 100ms.
If the boost converter is not used, ensure the power supply can tolerate transient currents caused by the LED
driver or horn driver. A supply capable of 50 mA average current is generally sufficient. The supply voltage must
be high enough to power the horn driver, LED driver and interconnect. Ensure the power supply's rise time is
less than 100ms.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
62
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
11 Layout
11.1 Layout Guidelines
These blocks require careful layout placement:
• Boost converter
• Photo amplifier
• CO amplifier
• Ground plane and traces
11.1.1 Photo Amplifier Layout
The photo amplifier is a very sensitive analog block in the TPS8802 device. Minimal trace lengths must be used
to connect the photodiode and relevant external components to PDP, PDN, PDO, PREF and AGND. It is
recommended to shield the PDP, PDN, PDO, and PREF traces with the AGND plane.
11.1.2 CO Amplifier Layout
Similar to the photo amplifier, the CO amplifier is very sensitive to noise. Connect the CO electrochemical sensor
close to the TPS8802 device and shield the COP, CON, and COO traces with the AGND plane.
11.1.3 Boost Converter Layout
The boost converter components must be positioned close to the VLX, VBST, and PGND pins. To minimize
switching noise, ensure that the VLX trace is as short as possible. A PGND plane can assist with connecting the
PGND connections together, but may not be necessary if the PGND routing is short enough without the PGND
plane. All PGND routing must remain separated from the AGND plane. Connect PGND to AGND at a single
point near the AGND pin.
11.1.4 Ground Plane Layout
Connect AGND and DGND to the ground plane. Ensure there is a short path from AGND to DGND. Route
PGND and its associated blocks (LED driver, boost converter) separately from the ground plane. Connect PGND
to AGND at a single point near the IC.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
11.2 Layout Example
图11-1. Photo Amplifier Layout
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
64
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
图11-2. CO Amplifier Layout
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
图11-3. Boost Converter Layout with PGND Plane
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
66
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
AGND
DGND
AGND Plane
PGND
PGND
PGND
PGND
PGND
PGND Pla ne
图11-4. Ground Layout
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF25
68
Submit Document Feedback
Product Folder Links: TPS8802
TPS8802
www.ti.com.cn
ZHCSL07C –SEPTEMBER 2019 –REVISED AUGUST 2021
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TPS8802
English Data Sheet: SLVSF25
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS8802DCPR
ACTIVE
HTSSOP
DCP
38
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS8802DCP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS8802DCPR
TPS8802DCPR
HTSSOP DCP
HTSSOP DCP
38
38
2000
2000
330.0
330.0
16.4
16.4
6.9
6.9
10.2
10.2
1.8
1.8
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS8802DCPR
TPS8802DCPR
HTSSOP
HTSSOP
DCP
DCP
38
38
2000
2000
367.0
356.0
367.0
356.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DCP 38
4.4 x 9.7, 0.5 mm pitch
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/B
www.ti.com
PACKAGE OUTLINE
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9
9.8
9.6
NOTE 3
19
20
0.27
0.17
0.08
38X
4.5
4.3
B
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
SYMM
38X (1.5)
38X (0.3)
SEE DETAILS
38
1
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
(4.7)
SYMM
39
BASED ON
0.125 THICK
STENCIL
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
0.125
0.15
0.175
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明