TPS92360 [TI]
38V 1.2A 单通道 LED 背光灯驱动器;
| 型号： | TPS92360 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 38V 1.2A 单通道 LED 背光灯驱动器 驱动 驱动器 |
| 文件： | 总23页 (文件大小：1570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS92360
ZHCSN63 –MARCH 2021
TPS92360 38-V 1.2-A 单通道LED 背光灯驱动器
1 特性
3 说明
• 2.7V 至5.5V 输入电压
• 集成40V、1.8A MOSFET
• 驱动高达38V 的LED 灯串
• 最低1.2A 开关电流限值
• 1.2MHz 开关频率
• 204mV 基准电压
• 内部补偿
• PWM 亮度控制
• LED 开路保护
• 欠压保护
TPS92360 配备 40V 额定值的集成开关 FET，是一款
可驱动串联 LED 的升压转换器。该升压转换器内部具
有一个 40V、1.8A MOSFET，最低电流限值为1.2A，
可针对小型至大型面板背光照明驱动单个 LED 或并联
LED 灯串。 简化版原理图通过外部传感器电阻 RSET
设置白色 LED 的默认电流， 反馈电压可调节至
204mV，如简化原理图 所示。运行期间，LED 电流可
通过施加到 CTRL 引脚上的脉宽调制 (PWM) 信号加以
控制，该信号的占空比决定反馈基准电压。TPS92360
不会突发 LED 电流，因此不会在输出电容器上产生可
闻噪声。为提供最佳保护，该器件配备集成的 LED 开
路保护，即在 LED 开路状态下禁用 TPS92360，以防
止输出电压超过器件的最大绝对电压额定值。
• 内置软启动
• 热关断
• 效率高达90%
2 应用
TPS92360 采用节省空间的5 引脚SC70 封装。
器件信息(1)
• 智能手机背光照明
• 平板电脑背光照明
封装尺寸（标称值）
器件型号
TPS92360
封装
• PDA、掌上电脑、GPS 接收器
• 便携式媒体播放器、便携式电视
• 适合小尺寸和中等尺寸显示屏的白色LED 背光照明
• 手持式数据终端(EPOS)
• 手持式医疗设备
SOT (5)
2.00mm × 1.25mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 恒温器显示屏
• 血糖仪
• 闪光灯
• 冰箱和冷冻柜
L
D
VBAT
CIN
TPS92360
COUT
VIN
SW
FB
CTRL
GND
PWM DIMMING
CONTROL
RSET
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBZ5
TPS92360
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Table of Contents
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
9 Power Supply Recommendations................................17
10 Layout...........................................................................17
10.1 Layout Guidelines................................................... 17
10.2 Layout Example...................................................... 17
11 Device and Documentation Support..........................18
11.1 Device Support........................................................18
11.2 接收文档更新通知................................................... 18
11.3 支持资源..................................................................18
11.4 Trademarks............................................................. 18
11.5 静电放电警告...........................................................18
11.6 术语表..................................................................... 18
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description........................................................7
7.1 Overview.....................................................................7
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes..........................................10
Information.................................................................... 18
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2021
*
Initial Release
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5 Pin Configuration and Functions
SW
GND
FB
1
2
3
5
VIN
4
CTRL
图5-1. DCK Package 5-Pin SC70 (Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NUMBER
NAME
SW
1
2
3
4
5
I
O
I
Drain connection of the internal power FET.
GND
FB
Ground.
Feedback pin for current. Connect the sense resistor from FB to GND.
PWM dimming signal input.
CTRL
VIN
I
I
Supply input pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
7
UNIT
VIN, CTRL, PWM, FB
Voltage(2)
V
SW
40
PD
Continuous power dissipation
See Thermal Information
Table
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
–40
–65
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
2.7
VIN
4.7
1
NOM
MAX
5.5
38
UNIT
V
VIN
VOUT
L
Input voltage
Output voltage
V
Inductor
10
µH
µF
µF
kHz
CI
Input capacitor
CO
Output capacitor
1
10
100
FPWM
DPWM
TJ
PWM dimming signal frequency
PWM dimming signal duty cycle
Operating junction temperature
5
1%
–40
100%
125
°C
6.4 Thermal Information
TPS92360
THERMAL METRIC(1)
DCK (SC70)
5 PINS
263.8
76.1
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
°C/W
°C/W
°C/W
°C/W
°C/W
51.4
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
1.1
50.7
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
6.5 Electrical Characteristics
Over operating free-air temperature range, VIN = 3.6 V, CTRL = VIN (unless otherwise specified).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
2.7
5.5
V
VIN falling
VIN rising
2.3
2.6
VVIN_UVLO
Undervoltage lockout threshold
VIN UVLO hysteresis
2
200
0.3
1
V
VVIN_HYS
IQ_VIN
mV
mA
µA
Operating quiescent current into
VIN
Device enable, switching 1.2 MHz
and no load,
0.45
2
ISD
Shutdown current
CTRL = GND
CONTROL LOGIC AND TIMING
VH
CTRL Logic high voltage
CTRL Logic Low voltage
1.2
V
V
VL
0.4
RPD
CTRL pin internal pull-down
resistor
300
204
KΩ
tSD
CTRL logic low time to shutdown CTRL high to low
2.5
ms
VOLTAGE AND CURRENT REGULATION
Voltage feedback regulation
voltage
VREF
188
220
2.5
mV
Duty = 100%, TA ≥25°C
IFB
FB pin bias current
VFB = 204 mV
µA
ms
tREF
VREF filter time constant
1
POWER SWITCH
R DS(ON) N-channel MOSFET on-resistance
ILN_NFET N-channel leakage current
SWITCHING FREQUENCY
0.35
0.7
1
Ω
VSW = 35 V
VIN = 3 V
µA
Switching frequency
0.75
1.2
1.2
1.5
2.4
MHz
ƒSW
PROTECTION AND SOFT START
ILIM
Switching MOSFET current limit
1.8
A
A
D = DMAX , TA ≤85°C
TA ≤85°C
ILIM_Start
Switching MOSFET start-up
current limit
0.72
tHalf_LIM
Time step for half current limit
6.5
ms
V
VOVP_SW
Output voltage overvoltage
threshold
36
37.5
39
THERMAL SHUTDOWN
Tshutdown Thermal shutdown threshold
Thys Thermal shutdown hysteresis
160
15
°C
°C
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6.6 Typical Characteristics
At TA = 25°C, unless otherwise noted.
250
200
150
100
50
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0
0
10
20
30
40
50
60
Dimming Duty Cycle (%)
70
80
90 100
-60
-40
-20
0
20 40
Temperature (°C)
60
80
100 120
D001
D002
图6-1. FB Voltage vs Dimming Duty Cycle
图6-2. Current Limit vs Temperature
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7 Detailed Description
7.1 Overview
The TPS92360 is a high-efficiency, high-output voltage boost converter in small package size. The device
integrates 40-V/1.8-A switch FET and is designed for output voltage up to 39 V with a switch peak current limit of
1.2-A minimum. Its large driving capability can drive single or parallel LED strings for small to large size panel
backlighting.
The TPS92360 operates in a current mode scheme with quasi-constant frequency. It is internally compensated
for maximum flexibility and stability. The switching frequency is 1.2 MHz, and the minimum input voltage is 2.7 V.
During the on-time, the current rises into the inductor. When the current reaches a threshold value set by the
internal GM amplifier, the power switch MOSFET is turned off. The polarity of the inductor changes and forward
biases the schottky diode which lets the current flow towards the output of the boost converter. The off-time is
fixed for a certain VIN and VOUT, and therefore maintains the same frequency when varying these parameters.
However, for different output loads, the frequency slightly changes due to the voltage drop across the RDS(ON)
of the power switch MOSFET, this has an effect on the voltage across the inductor and thus on tON (tOFF remains
fixed). The fixed off-time maintains a quasi-fixed frequency that provides better stability for the system over a
wider range of input and output voltages than conventional boost converters. The TPS92360 topology has also
the benefits of providing very good load and line regulations, and excellent line and load transient responses.
The feedback loop regulates the FB pin to a low reference voltage (204-mV typical), reducing the power
dissipation in the current sense resistor.
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7.2 Functional Block Diagram
L
D
VBAT
VOUT
COUT
CIN
SW
VIN
UVLO
OVP
Current Limit and
Soft Start
TOFF
Generator
Ton
PWM
Generator
Gate Driver of
Power MOSFET
FB
GM Amplifier
VREF
RSET
CTRL
PWM Dimming
Reference Control
Shutdown
GND
7.3 Feature Description
7.3.1 Soft Start-Up
Soft-start circuitry is integrated into the IC to avoid high inrush current spike during start-up. After the device is
enabled, the GM amplifier output voltage ramps up very slowly, which ensures that the output voltage rises
slowly to reduce the input current. During this period, the switch current limit is set to 0.72 A. After around 6.5
ms, the switch current limit changes back to ILIM, and the FB pin voltage ramps up to the reference voltage
slowly. These features ensure the smooth start-up and minimize the inrush current. See Start-Up Dimming Duty
= 100% for a typical example.
7.3.2 Open LED Protection
Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS92360
monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the switch FET
and shuts down the IC when both of the following conditions persist for 3 switching cycles: (1) the SW voltage
exceeds the VOVP threshold, and (2) the FB voltage is less than 30 mV. As the result, the output voltage falls to
the level of the input supply. The device remains in shutdown mode until it is enabled by toggling the CTRL pin.
7.3.3 Shutdown
The TPS92360 enters shutdown mode when the CTRL voltage is logic low for more than 2.5 ms. During
shutdown, the input supply current for the device is less than 2 μA (max). Although the internal switch FET does
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not switch in shutdown, there is still a DC current path between the input and the LEDs through the inductor and
Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to
ensure that the LEDs remain off in shutdown.
7.3.4 Current Program
The FB voltage is regulated by a low 204-mV reference voltage. The LED current is programmed externally
using a current-sense resistor in series with the LED string(s). The value of the RSET is calculated using:
VFB
ILED
=
RSET
(1)
where
• ILED = total output current of LED string(s)
• VFB = regulated voltage of FB pin
• RSET = current sense resistor
The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.
7.3.5 LED Brightness Dimming
The TPS92360 receives PWM dimming signal at CTRL pin to control the total output current. When the CTRL
pin is constantly high, the FB voltage is regulated to 204 mV typically. When the duty cycle of the input PWM
signal is low, the regulation voltage at FB pin is reduced, and the total output current is reduced; therefore, it
achieves LED brightness dimming. The relationship between the duty cycle and FB regulation voltage is given
by:
VFB = Duty ì 204 mV
where
(2)
• Duty = Duty cycle of the PWM signal
• 204 mV = internal reference voltage
Thus, the user can easily control the WLED brightness by controlling the duty cycle of the PWM signal.
As shown in 图 7-1, the IC chops up the internal 204-mV reference voltage at the duty cycle of the PWM signal.
The pulse signal is then filtered by an internal low-pass filter. The output of the filter is connected to the GM
amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for
brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This
eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and
duty cycle of PWM control. Unlike other methods which filter the PWM signal for analog dimming, TPS92360
regulation voltage is independent of the PWM logic voltage level which often has large variations.
For optimum performance, use the PWM dimming frequency in the range of 5 kHz to 100 kHz. If the PWM
frequency is lower than 5 kHz, it is out of the low pass filter's filter range, the FB regulation voltage ripple
becomes large, causing large output ripple and may generate audible noise.
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VBG
204 mV
CTRL
VREF
EA Output
GM
Amplifier
FB
图7-1. Programmable FB Voltage Using PWM Signal
7.3.6 Undervoltage Lockout
An undervoltage lockout prevents operation of the device at input voltages below typical 2 V. When the input
voltage is below the undervoltage threshold, the device is shut down, and the internal switch FET is turned off. If
the input voltage rises by undervoltage lockout hysteresis, the IC restarts.
7.3.7 Thermal Foldback and Thermal Shutdown
When TPS92360 drives heavy load for large size panel applications, the power dissipation increases a lot and
the device junction temperature may reach a very high value, affecting the device function and reliability. In order
to lower the thermal stress, the TPS92360 features a thermal foldback function. When the junction temperature
is higher than 100°C, the switch current limit ILIM is reduced automatically as Current Limit vs Temperature
shows. This thermal foldback mechanism controls the power dissipation and keeps the junction temperature
from rising to a very high value. If the typical junction temperature of 160°C is exceeded, an internal thermal
shutdown turns off the device. The device is released from shutdown automatically when the junction
temperature decreases by 15°C.
7.4 Device Functional Modes
7.4.1 Operation with CTRL
The enable rising edge threshold voltage is 1.2 V. When the CTRL pin is held below that voltage the device is
disabled and switching is inhibited. The IC quiescent current is reduced in this state. When input voltage is
above the UVLO threshold, and the CTRL pin voltage is increased above the rising edge threshold, the device
becomes active. Switching enables and the soft-start sequence initiates.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS92360 device is a step-up DC-DC converter which can drive single or parallel LED strings for small- to
large-size panel backlighting. This section includes a design procedure (Detailed Design Procedure) to select
component values for the TPS92360 typical application (图8-1).
8.2 Typical Application
L
4.7 µH
2.7 V to 5.5 V
VBAT
D
10s1p
CIN
4.7 µF
COUT
1 µF
TPS92360
VIN
SW
FB
CTRL
GND
PWM DIMMING
CONTROL
RSET
10.2 ꢀ
图8-1. TPS92360 2.7-V to 5.5-V Input, 10 LEDs in Series Output Converter
8.2.1 Design Requirements
For this design example, use the parameters listed in 表8-1 as the input parameters.
表8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.7 V to 5.5 V
Output, LED number in a string
Output, LED string number
Output, LED current per string
10
1
20 mA
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor Selection
The selection of the inductor affects power efficiency, steady state operation as well as transient behavior and
loop stability. These factors make it the most important component in power regulator design. There are three
important inductor specifications, inductor value, DC resistance and saturation current. Considering inductor
value alone is not enough. The inductor value determines the inductor ripple current. Choose an inductor that
can handle the necessary peak current without saturating. Follow 方程式 3 to 方程式 4 to calculate the peak
current of the inductor. To calculate the current in the worst case, use the minimum input voltage, maximum
output voltage and maximum load current of application. In a boost regulator, the input DC current can be
calculated as 方程式3.
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VOUT ìIOUT
IL(DC)
=
V ì h
IN
(3)
where
• VOUT = boost output voltage
• IOUT = boost output current
• VIN = boost input voltage
• η= power conversion efficiency
The inductor current peak to peak ripple can be calculated as 方程式4.
1
DIL(P-P)
=
1
1
L ì(
+
)ìFS
VOUT - V
V
IN
IN
(4)
where
• ΔIL(PP) = inductor peak-to-peak ripple
• L = inductor value
• FS = boost switching frequency
• VOUT = boost output voltage
• VIN = boost input voltage
Therefore, the peak current IL(P) seen by the inductor is calculated with 方程式5.
DIL(P-P)
IL(P) = IL(DC)
+
2
(5)
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation
level, its inductance can decrease 20% to 35% from the 0-A value depending on how the inductor vendor
defines saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM when
the inductor current ramps down to zero before the end of each switching cycle. This reduces the boost
converter’s maximum output current, causes large input voltage ripple and reduces efficiency. Large
inductance value provides much more output current and higher conversion efficiency. For these reasons, a 4.7-
μH to 10-μH inductor value range is recommended, and 4.7-μH inductor is recommended for higher than 5-V
input voltage by considering inductor peak current and loop stability. 表 8-2 lists the recommended inductor for
the TPS92360.
表8-2. Recommended Inductors for TPS92360
SATURATION
CURRENT (A)
PART NUMBER
L (µH)
SIZE (L x W x H mm)
VENDOR
DCR MAX (mΩ)
LPS4018-472ML
LPS4018-103ML
PCMB051H-4R7M
PCMB051H-100M
4.7
10
125
200
85
1.9
1.3
4
4 × 4 × 1.8
4 × 4 × 1.8
Coilcraft
Coilcraft
Cyntec
Cyntec
4.7
10
5.4 × 5.2 × 1.8
5.4 × 5.2 × 1.8
155
3
8.2.2.2 Schottky Diode Selection
The TPS92360 demands a low forward voltage, high-speed and low capacitance Schottky diode for optimum
efficiency. Ensure that the diode average and peak current rating exceeds the average output current and peak
inductor current. In addition, the diode reverse breakdown voltage must exceed the open LED protection
voltage. ONSemi NSR0240 is recommended for the TPS92360.
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8.2.2.3 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirement for the output ripple and loop stability. This
ripple voltage is related to capacitor capacitance and its equivalent series resistance (ESR). Assuming a
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated with 方程式6:
(VOUT - V )ìIOUT
IN
COUT
=
VOUT ìFS ì V
ripple
(6)
where
• Vripple = peak-to-peak output ripple
The additional part of the ripple caused by ESR is calculated using: Vripple_ESR = IOUT × RESR
Due to its low ESR, Vripple_ESR could be neglected for ceramic capacitors, a 1-µF to 4.7-µF capacitor is
recommended for typical application.
8.2.2.4 LED Current Set Resistor
The LED current set resistor can be calculated by 方程式1.
8.2.2.5 Thermal Considerations
The allowable IC junction temperature must be considered under normal operating conditions. This restriction
limits the power dissipation of the TPS92360. The allowable power dissipation for the device can be determined
by 方程式7:
TJ - TA
PD =
RqJA
(7)
where
• TJ is allowable junction temperature given in recommended operating conditions
• TA is the ambient temperature for the application
• RθJA is the thermal resistance junction-to-ambient given in Power Dissipation Table
The TPS92360 device also features a thermal foldback function to reduce the thermal stress automatically.
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8.2.3 Application Curves
Typical application condition is as in 图 8-1, VIN = 3.6 V, RSET = 10.2 Ω, L = 4.7 µH, COUT = 1 µF, 10 LEDs in series (unless
otherwise specified).
100
90
80
70
60
50
100
90
80
70
60
50
10 LEDs in series
6 LEDs in series
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.0 V
0
10
20
30
40
50
60
Dimming Duty Cycle (%)
70
80
90 100
0
10
20
30
40
50
60
Dimming Duty Cycle (%)
70
80
90 100
D003
D004
10 LEDs in series
图8-2. Efficiency vs Dimming Duty Cycle
图8-3. Efficiency vs Dimming Duty Cycle
100
100
90
80
70
60
50
90
80
70
60
50
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.0 V
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.0 V
0
10
20
30
40
Dimming Duty Cycle (%)
50
60
70
80
90 100
0
10
20
30
40
Dimming Duty Cycle (%)
50
60
70
80
90 100
D005
D006
8 LEDs in series
6 LEDs in series
图8-4. Efficiency vs Dimming Duty Cycle
图8-5. Efficiency vs Dimming Duty Cycle
SW (20 V/DIV)
SW (20 V/DIV)
VOUT (100 mV/DIV, AC coupled)
IInductor (500 mA/DIV)
VOUT (100 mV/DIV, AC coupled)
IInductor (500 mA/DIV)
ILED (9 mA/DIV)
ILED (9 mA/DIV)
Time = 1 µs/DIV
Time = 1 µs/DIV
图8-6. Switching-Dimming Duty = 100%
图8-7. Switching-Dimming Duty = 50%
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SW (20 V/DIV)
PWM
(2 V/DIV)
VOUT (100 mV/DIV, AC coupled)
IInductor (500 mA/DIV)
IInductor
(300 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
ILED (5 mA/DIV)
Time = 2 µs/DIV
Time = 2 ms/DIV
图8-8. Switching-Dimming Duty = 10%
图8-9. Start-Up Dimming Duty = 100%
PWM (2 V/DIV)
PWM (2 V/DIV)
IInductor (300 mA/DIV)
IInductor
(300 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
Time = 2 ms/DIV
Time = 2 ms/DIV
图8-10. Start-Up Dimming Duty = 50%
图8-11. Shutdown Dimming Duty = 100%
PWM (2 V/DIV)
PWM (2 V/DIV)
VOUT (5 V/DIV, AC coupled)
IInductor (300 mA/DIV)
IInductor (300 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
ILED (9 mA/DIV)
Time = 2 ms/DIV
Duty = 50%
Time = 5 ms/DIV
Duty = 1%-100%-1%
图8-12. Shutdown Dimming
图8-13. Dimming Transient-Dimming
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VFB (200 mV/DIV)
VOUT (20 V/DIV)
IInductor (600 mA/DIV)
ILED (9 mA/DIV)
Time = 50 µs/DIV
图8-14. Open LED Protection
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.7 V and 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the TPS92360 device,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those high frequency and high current ones, layout is an important
design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.
Therefore, use wide and short traces for high current paths. The input capacitor CIN must be close to VIN pin
and GND pin in order to reduce the input ripple seen by the device. If possible, choose higher capacitance value
for it. The SW pin carries high current with fast rising and falling edge; therefore, the connection between the SW
pin to the inductor must be kept as short and wide as possible. The output capacitor COUT must be put close to
VOUT pin. It is also beneficial to have the ground of COUT close to the GND pin because there is large ground
return current flowing between them. FB resistor must be put close to FB pin. When laying out signal ground, TI
recommends using short traces separated from power ground traces and connecting them together at a single
point close to the GND pin.
10.2 Layout Example
Bottom
GND
GND
Plane
VIN
GND
VOUT
图10-1. TPS92360 Board Layout
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11 Device and Documentation Support
11.1 Device Support
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92360DCKR
ACTIVE
SC70
DCK
5
3000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
1IX
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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